A large-scale coherent signal generation system and method

Abstract

This invention discloses a large-scale coherent signal generation system and method. The system includes M local signal source modules, a global synchronization module, M-1 cascaded control switches, and a control module; M is an integer greater than 1. The local signal source modules are equipped with a synchronization input port group, a synchronization output port group, a reference port group, a control port, and a radio frequency output port group. The global synchronization module is equipped with a synchronization input port group and M synchronization output port groups. The control module is data-connected to the control ports of the M local signal source modules and the M-1 cascaded control switches, respectively, for acquiring test information and, based on the test information, controlling the on / off state of the M-1 cascaded control switches, and controlling the M local signal source modules to generate several coherent signal groups. This invention can flexibly generate coherent signal groups for different scale test scenarios, supports large-scale multi-scenario parallel testing, and effectively improves the utilization rate of signal source hardware resources.

Description

Technical Field

[0001] This invention belongs to the field of coherent signal generation, specifically a large-scale coherent signal generation system and method. Background Technology

[0002] In the fields of modern communications, radar detection, and wireless communication testing, multi-channel coherent signal sources serve as core testing equipment, widely used in critical scenarios such as phased array radar beamforming verification, satellite communication link performance testing, and channel simulation of large-scale MIMO (Multiple-Input Multiple-Output) systems. The performance verification of these systems highly depends on the coherence of the multi-channel signals—that is, the output signals of each channel must maintain a definite and stable correlation in frequency and phase to simulate the coherent characteristics of signals arriving at different receiving channels in a real electromagnetic environment. Therefore, the performance of the multi-channel coherent signal source directly determines the accuracy and reliability of the related system tests.

[0003] To achieve coherence between channels, current mainstream multi-channel coherent signal generators generally adopt a "hard-bonded RF channel" design: each RF channel achieves coherence by sharing a single frequency reference source, clock source, and phase control module. While this architecture ensures high coherence accuracy between channels, it has significant functional limitations. Specifically, because the frequency generation and phase control logic of all channels are deeply coupled to the same hardware unit, independent frequency configuration between channels is not possible. This results in all channels only being able to output signals at a single frequency or fixed frequency intervals, and they cannot be physically or logically separated into multiple independently operating signal generators. This "inseparable bonded" characteristic severely limits the application scenarios of the equipment: when small-scale testing is required (e.g., only 2-4 independent signal generators are needed), it is impossible to use some channels of existing large-scale multi-channel equipment for independent testing. Dedicated small signal generators must be configured separately, leading to equipment idleness and resource waste.

[0004] In large-scale system testing scenarios, the shortcomings of the existing architecture become even more prominent. Testing systems such as phased array radar, satellite communication ground stations, and large-scale MIMO base stations often requires 32, 64, 128, or even more channels of coherent signal sources. Existing centralized multi-channel coherent signal sources require integrating all channel modules into a single rack or a few closely connected racks to ensure stable transmission of frequency references and clock signals. This centralized cabling scheme leads to an exponential increase in the number of RF and control cables across racks: for example, a 128-channel system requires hundreds of RF coaxial cables and control signal lines, increasing the complexity of cabling both inside and between racks. Furthermore, the following problems exist: First, the risk of electromagnetic interference between cables is significantly increased, potentially leading to increased phase noise in the coherent signals and affecting test accuracy; second, the installation process requires professional personnel to check the connections line by line, resulting in low installation efficiency and often requiring several days or even weeks to complete system setup; third, subsequent maintenance is difficult, as a single cable failure can cause the entire channel group to fail, requiring troubleshooting hundreds of cables one by one, greatly increasing maintenance costs and downtime.

[0005] To address the shortcomings of existing technologies, there is an urgent need for a novel multi-channel coherent signal source architecture that can overcome the limitation of "inseparable bonded" channels in traditional architectures, enabling flexible switching between application scenarios, improving equipment reuse rate and reducing costs; it can also adapt to large-scale testing needs, reduce the number of cross-rack cables, reduce system complexity, and improve installation and maintenance efficiency, thereby providing strong support for efficient testing of systems such as phased array radar, satellite communication, and large-scale MIMO. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide a large-scale coherent signal generation system and method that can support large-scale multi-scenario parallel testing and reduce the complexity of the testing system.

[0007] To address the aforementioned technical problems, a first aspect of this invention discloses a large-scale coherent signal generation system, the system comprising M local signal source modules, a global synchronization module, M-1 cascaded control switches, and a control module; where M is an integer greater than 1.

[0008] The local signal source module is provided with a synchronous input port group, a synchronous output port group, a reference port group, a control port, and a radio frequency output port group;

[0009] The synchronization input port group includes a trigger input port, a first local oscillator input port, and a second local oscillator input port; the synchronization output port group includes a trigger output port, a first local oscillator output port, and a second local oscillator output port; the reference port group includes a reference input port and a reference output port; the radio frequency output port group includes N radio frequency output ports; N is an integer greater than 1.

[0010] The global synchronization module includes the synchronization input port group and M synchronization output port groups;

[0011] The M synchronization output port groups of the global synchronization module are respectively connected to the synchronization input port groups of the M local signal source modules;

[0012] The synchronization output port group of the first local signal source module is connected to the synchronization input port group of the global synchronization module; The synchronous output port group of the local signal source module is left floating; Integers from 2 to M;

[0013] The reference input port of the first local signal source module is left floating; The reference output port of the local signal source module is connected to the first... The input port of the cascaded control switch; the reference output port of the Mth local signal source module is left floating; Integers from 1 to M-1;

[0014] The control module is connected to the control ports of the M local signal source modules and the M-1 cascaded control switches respectively, for acquiring test information, and controlling the on / off state of the M-1 cascaded control switches based on the test information, and controlling the M local signal source modules to generate several coherent signal groups; the coherent signal group includes several coherent and synchronously output radio frequency signals.

[0015] As an optional implementation, in the first aspect of the present invention, the control module includes an information acquisition unit, a cascaded computing unit, and a data transmission unit;

[0016] The information acquisition unit is data-connected to the cascaded computing unit and the data sending unit, and is used to acquire test information;

[0017] The test information includes RF requirement information and RF configuration information;

[0018] The radio frequency demand information includes a first demand number PA and a second demand number sequence; the second demand number sequence includes NB second demand numbers; PA is an integer from 1 to M×N; the second demand number is an integer from 1 to N; PA and NB satisfy the following constraints:

[0019]

[0020] The radio frequency configuration information includes a first configuration information and a second configuration information sequence; the second configuration information sequence includes NB second configuration information; both the first configuration information and the second configuration information include a switch state sequence and a baseband parameter set.

[0021] The switch state sequence includes L switch state values; each switch state value is 0 or 1; L is an integer greater than 1.

[0022] The cascaded computing unit is data-connected to the data transmission unit and is used to process the radio frequency demand information to obtain the number of cascaded groups Q and the cascaded control sequence.

[0023] The cascaded control sequence includes Q+NB cascaded control values; the cascaded control values ​​are either 0 or 1.

[0024] The data transmission unit is used to forward the radio frequency configuration information and the cascade control sequence to the local signal source module based on the number of cascade groups.

[0025] As an optional implementation, in the first aspect of the present invention, the local signal source module includes a local synchronization unit, a local switch, and N signal source units;

[0026] The local synchronization unit is provided with the synchronization input port group and N synchronization output port groups;

[0027] The signal source unit includes the synchronization input port group, the synchronization output port group, the reference port group, the control port, and the radio frequency output port.

[0028] The N synchronization output port groups of the local synchronization unit are respectively connected to the synchronization input port groups of the N signal source units;

[0029] The synchronization output port group of the first signal source unit is connected to the synchronization input port group of the local synchronization unit, and also serves as the synchronization output port group of the local signal source module.

[0030] The reference input port of the first signal source unit serves as the reference input port of the local signal source module; the reference output port of the nth signal source unit is connected to the reference input port of the (n+1)th signal source unit; the reference output port of the Nth signal source unit serves as the reference output port of the local signal source module; n is an integer from 1 to N-1;

[0031] The control ports of the N local signal source modules are all connected to the control ports of the local signal source modules through the local switch;

[0032] The radio frequency output ports of the N signal source units are respectively used as the N radio frequency output ports of the local signal source module.

[0033] As an optional implementation, in the first aspect of the present invention, the global synchronization module includes a first driver, a first amplifier, a first power divider, a second amplifier, and a second power divider;

[0034] The input port of the first driver serves as the trigger input port of the global synchronization module; the output port of the first driver serves as the trigger output port of the global synchronization module.

[0035] The input port of the first amplifier serves as the first local oscillator input port of the global synchronization module; the output port of the first amplifier is connected to the input port of the first power divider; the M output ports of the first power divider serve as the M first local oscillator output ports of the global synchronization module, respectively.

[0036] The input port of the second amplifier serves as the second local oscillator input port of the global synchronization module; the output port of the second amplifier is connected to the input port of the second power divider; the M output ports of the second power divider serve as the M second local oscillator output ports of the global synchronization module, respectively.

[0037] As an optional implementation, in the first aspect of the present invention, the local synchronization unit includes a second driver, a third amplifier, a third power divider, a fourth amplifier, and a fourth power divider;

[0038] The input port of the second driver serves as the trigger input port of the local synchronization unit; the output port of the second driver serves as the trigger output port of the local synchronization unit.

[0039] The input port of the third amplifier serves as the first local oscillator input port of the local synchronization unit; the output port of the third amplifier is connected to the input port of the third power divider; the N output ports of the third power divider serve as the N first local oscillator output ports of the local synchronization unit, respectively.

[0040] The input port of the fourth amplifier serves as the second local oscillator input port of the local synchronization unit; the output port of the fourth amplifier is connected to the input port of the fourth power divider; and the N output ports of the fourth power divider serve as the N second local oscillator output ports of the local synchronization unit.

[0041] As an optional implementation, in the first aspect of the present invention, the signal source unit includes a state control subunit, a local oscillator selection subunit, a signal generation subunit, and a clock subunit;

[0042] The input port of the state control subunit serves as the control port of the signal source unit; the first output port of the state control subunit is connected to the control port of the clock subunit; the second output port of the state control subunit is connected to the control port of the local oscillator selection subunit; and the third output port of the state control subunit is connected to the control port of the signal generation subunit.

[0043] The value of L is 7; the state control subunit is used to output the first switch state value of the received switch state sequence to the first output port of the state control subunit, output the last 6 switch state values ​​of the received switch state sequence to the second output port of the state control subunit, and output the received baseband parameter set to the third output port of the state control subunit.

[0044] The first input port of the local oscillator selection subunit serves as the first local oscillator input port of the signal source module; the second input port of the local oscillator selection subunit serves as the second local oscillator input port of the signal source module.

[0045] The first output port of the local oscillator selection subunit serves as the first local oscillator output port of the signal source module; the second output port of the local oscillator selection subunit serves as the second local oscillator output port of the signal source module.

[0046] The third output port of the local oscillator selection subunit is connected to the second input port of the signal generation subunit; the fourth output port of the local oscillator selection subunit is connected to the third input port of the signal generation subunit.

[0047] The first input port of the signal generation subunit serves as the trigger input port of the signal source unit;

[0048] The first output port of the signal generation subunit serves as the trigger output port of the signal source unit;

[0049] The second output port of the signal generation subunit serves as the radio frequency output port of the signal source unit;

[0050] The input port of the clock subunit serves as the reference input port of the signal source unit; the first output port of the clock subunit serves as the reference output port of the signal source unit; the second output port of the clock subunit is connected to the fourth input port of the signal generation subunit; the third output port of the clock subunit is connected to the third input port of the local oscillator selection subunit; and the fourth output port of the clock subunit is connected to the fourth input port of the local oscillator selection subunit.

[0051] As an optional implementation, in the first aspect of the present invention, the local oscillator selection subunit includes a first output selection switch, a second output selection switch, a third output selection switch, a fourth output selection switch, a first input selection switch, a second input selection switch, a first local oscillator source, a second local oscillator source, and a control signal distributor;

[0052] The input port of the first output selection switch serves as the first input port of the local oscillator selection subunit; the first output port of the first output selection switch is connected to the first input port of the first input selection switch; the second output port of the first output selection switch is in the off state.

[0053] The input port of the second output selection switch serves as the second input port of the local oscillator selection subunit; the first output port of the second output selection switch is connected to the first input port of the second input selection switch; the second output port of the second output selection switch is in the off state.

[0054] The input port of the first local oscillator source serves as the third input port of the local oscillator selection subunit; the output port of the first local oscillator source is connected to the input port of the third output selection switch; the first output port of the third output selection switch is connected to the second input port of the first input selection switch; the second output port of the third output selection switch serves as the first output port of the local oscillator selection subunit.

[0055] The input port of the second local oscillator source serves as the fourth input port of the local oscillator selection subunit; the output port of the second local oscillator source is connected to the input port of the fourth output selection switch; the first output port of the fourth output selection switch is connected to the second input port of the second input selection switch; the second output port of the fourth output selection switch serves as the second output port of the local oscillator selection subunit.

[0056] The output port of the first input selection switch serves as the third output port of the local oscillator selection subunit; the output port of the second input selection switch serves as the fourth output port of the local oscillator selection subunit.

[0057] The input port of the control signal distributor serves as the control port of the local oscillator selection subunit; the control signal distributor is used to send the received six switch state values ​​to the control ports of the first output selection switch, the second output selection switch, the third output selection switch, the fourth output selection switch, the first input selection switch, and the second input selection switch, respectively.

[0058] When the control ports of the first output selection switch, the second output selection switch, the third output selection switch and the fourth output selection switch receive a switch state value of 1, the signal received by the corresponding input port is forwarded to the corresponding first output port.

[0059] When the control ports of the first output selection switch, the second output selection switch, the third output selection switch and the fourth output selection switch receive a switch state value of 0, the signal received by the corresponding input port is forwarded to the corresponding second output port.

[0060] When the control port of the first input selection switch and the second input selection switch receives a switch state value of 1, the signal received by the corresponding first input port is forwarded to the corresponding output port.

[0061] When the control port of the first input selection switch and the second input selection switch receives a switch state value of 0, the signal received by the corresponding second input port is forwarded to the corresponding output port.

[0062] As an optional implementation, in the first aspect of the present invention, the signal generation subunit includes an FPGA, a digital-to-analog converter, and a frequency converter;

[0063] The first input port of the FPGA serves as the control port of the signal generation subunit.

[0064] The second input port of the FPGA serves as the first input port of the signal generation subunit.

[0065] The third input port of the FPGA serves as the second input port of the signal generation subunit;

[0066] The first output port of the FPGA serves as the first output port of the signal generation subunit.

[0067] The second output port of the FPGA is connected to the input port of the digital-to-analog converter;

[0068] The output port of the digital-to-analog converter is connected to the first input port of the frequency converter;

[0069] The second input port of the frequency converter serves as the third input port of the signal generation subunit; the third input port of the frequency converter serves as the fourth input port of the signal generation subunit; and the output port of the frequency converter serves as the second output port of the signal generation subunit.

[0070] As an optional implementation, in the first aspect of the present invention, the clock subunit includes a clock amplifier, a reference clock generator, a clock selection switch, and a clock power divider;

[0071] The input port of the clock amplifier serves as the input port of the clock subunit; the output port of the clock amplifier is connected to the first input port of the clock selection switch.

[0072] The output port of the reference clock generator is connected to the second input port of the clock selection switch;

[0073] The control port of the clock selection switch serves as the control port of the clock subunit.

[0074] When the control port of the clock selection switch receives the switch state value of 1, the signal received by the first input port of the clock selection switch is forwarded to the output port of the clock selection switch.

[0075] When the control port of the clock selection switch receives a switch state value of 0, the signal received by the second input port of the clock selection switch is forwarded to the output port of the clock selection switch.

[0076] The output port of the clock selection switch is connected to the input port of the clock power divider.

[0077] The first output port of the clock power divider serves as the first output port of the clock subunit; the second output port of the clock power divider serves as the second output port of the clock subunit; the third output port of the clock power divider serves as the third output port of the clock subunit; and the fourth output port of the clock power divider serves as the fourth output port of the clock subunit.

[0078] A second aspect of this invention discloses a method for generating large-scale coherent signals, the method comprising:

[0079] S1. Obtain test information using the control module;

[0080] S2. Using the control module, the first demand number PA in the test information is processed to obtain the cascade group number Q, expressed as:

[0081]

[0082] In the formula, This is the floor function operator;

[0083] S3. Using the control module, send a cascade control value of 1 to the 1st to Q-1th cascade control switches respectively;

[0084] Using the data transmission unit of the control module, a cascade control value of 0 is sent to each of the Q to M-1 cascade control switches;

[0085] S4. Using the control module, the first configuration information in the test information is sent to the first to Q local signal source modules;

[0086] The first phase coherent signal group is generated using the first to Q local signal source modules; the first phase coherent signal group includes PA radio frequency signals;

[0087] S5. Using the control module, the NB second configuration information in the test information are sent to the Q+1 to Q+NB local signal source modules respectively;

[0088] Using the Q+1 to Q+NB local signal source modules, the 2nd to NB+1th coherent signal groups are generated respectively; the kth coherent signal group includes The radio frequency signal; k is an integer from 2 to NB+1; It is the (k-1)th second demand number in the second demand number sequence in the test information.

[0089] Compared with the prior art, the embodiments of the present invention have the following beneficial effects:

[0090] The control module controls the cascaded structure of the global synchronization module and M local signal source modules, flexibly generating coherent signal groups for different scale test scenarios. This supports large-scale multi-scenario parallel testing, effectively improving the utilization rate of signal source hardware resources, while also effectively reducing the number of cables, lowering system complexity, and improving installation and maintenance efficiency. Attached Figure Description

[0091] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0092] Figure 1 This is a schematic diagram of the structure of a large-scale coherent signal generation system disclosed in an embodiment of the present invention.

[0093] Figure 2 This is a schematic diagram of the structure of the control module of a large-scale coherent signal generation system disclosed in an embodiment of the present invention.

[0094] Figure 3 This is a schematic diagram of the structure of a local signal source module of a large-scale coherent signal generation system disclosed in an embodiment of the present invention.

[0095] Figure 4 This is a schematic diagram of the structure of a global synchronization module of a large-scale coherent signal generation system disclosed in an embodiment of the present invention.

[0096] Figure 5 This is a schematic diagram of the structure of a local synchronization unit of a large-scale coherent signal generation system disclosed in an embodiment of the present invention.

[0097] Figure 6 This is a schematic diagram of the structure of the signal source unit of a large-scale coherent signal generation system disclosed in an embodiment of the present invention.

[0098] Figure 7 This is a schematic diagram of the local oscillator selection subunit of a large-scale coherent signal generation system disclosed in an embodiment of the present invention.

[0099] Figure 8 This is a schematic diagram of the structure of a signal generation subunit of a large-scale coherent signal generation system disclosed in an embodiment of the present invention.

[0100] Figure 9 This is a schematic diagram of the clock subunit of a large-scale coherent signal generation system disclosed in an embodiment of the present invention.

[0101] Figure 10This is a flowchart illustrating a method for generating large-scale coherent signals disclosed in an embodiment of the present invention. Detailed Implementation

[0102] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0103] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0104] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0105] Example 1

[0106] Please see Figure 1-9 . Figure 1 This is a schematic diagram of the structure of a large-scale coherent signal generation system disclosed in an embodiment of the present invention. Figure 2 This is a schematic diagram of the structure of the control module of a large-scale coherent signal generation system disclosed in an embodiment of the present invention. Figure 3 This is a schematic diagram of the structure of a local signal source module of a large-scale coherent signal generation system disclosed in an embodiment of the present invention. Figure 4 This is a schematic diagram of the structure of a global synchronization module of a large-scale coherent signal generation system disclosed in an embodiment of the present invention. Figure 5 This is a schematic diagram of the structure of a local synchronization unit of a large-scale coherent signal generation system disclosed in an embodiment of the present invention. Figure 6 This is a schematic diagram of the structure of the signal source unit of a large-scale coherent signal generation system disclosed in an embodiment of the present invention. Figure 7This is a schematic diagram of the local oscillator selection subunit of a large-scale coherent signal generation system disclosed in an embodiment of the present invention. Figure 8 This is a schematic diagram of the structure of a signal generation subunit of a large-scale coherent signal generation system disclosed in an embodiment of the present invention. Figure 9 This is a schematic diagram of the clock subunit of a large-scale coherent signal generation system disclosed in an embodiment of the present invention. Figure 1 The described large-scale coherent signal generation system is applied in the field of coherent signal generation, such as the generation of large-scale coherent signals in modern communication, radar detection, and wireless communication testing. The embodiments of this invention are not limited to this application. Figure 1 As shown, the system includes M local signal source modules, a global synchronization module, M-1 cascaded control switches and control modules; M is an integer greater than 1.

[0107] The aforementioned local signal source module is equipped with a synchronous input port group, a synchronous output port group, a reference port group, a control port, and a radio frequency output port group.

[0108] The aforementioned synchronization input port group includes a trigger input port, a first local oscillator input port, and a second local oscillator input port; the aforementioned synchronization output port group includes a trigger output port, a first local oscillator output port, and a second local oscillator output port; the aforementioned reference port group includes a reference input port and a reference output port; the aforementioned radio frequency output port group includes N radio frequency output ports; N is an integer greater than 1.

[0109] like Figure 1 As shown, the three ports on the left side of the local signal source module, from top to bottom, are the synchronization input port group, the control port, and the reference input port; the three ports on the right side of the local signal source module, from top to bottom, are the synchronization output port group, the radio frequency output port group, and the reference output port. The global synchronization module has a synchronization input port group on the left and M synchronization output port groups on the right side, from top to bottom.

[0110] The aforementioned global synchronization module has the aforementioned synchronization input port group and M of the aforementioned synchronization output port groups.

[0111] The M synchronization output port groups of the global synchronization module are respectively connected to the synchronization input port groups of the M local signal source modules.

[0112] The synchronization output port group of the first local signal source module is connected to the synchronization input port group of the global synchronization module; The aforementioned synchronous output port group of the aforementioned local signal source module is left floating. It is an integer from 2 to M.

[0113] It should be noted that the above-mentioned connection of the synchronous output port group to the synchronous input port group means connecting the trigger output port, the first local oscillator output port and the second local oscillator output port in the synchronous output port group to the trigger input port, the first local oscillator input port and the second local oscillator input port in the synchronous input port group, respectively.

[0114] The reference input port of the first aforementioned local signal source module is left floating; The aforementioned reference output port of the aforementioned local signal source module is connected to the first... The input ports of the aforementioned cascaded control switches; the reference output port of the Mth local signal source module is left floating; It is an integer from 1 to M-1.

[0115] The aforementioned control module is connected to the control ports of the M local signal source modules and the M-1 cascaded control switches respectively, for acquiring test information, and based on the test information, controlling the on / off state of the M-1 cascaded control switches, and controlling the M local signal source modules to generate several coherent signal groups; the coherent signal groups include several coherent and synchronously output radio frequency signals.

[0116] It should be noted that the aforementioned coherent signal groups are used as signal sources for different test scenarios; the radio frequency signals within the same coherent signal group are coherent and synchronized, while the radio frequency signals between different coherent signal groups are independent (non-coherent or asynchronous).

[0117] It should be noted that the aforementioned RF output port is used to output the aforementioned RF signal.

[0118] It should be noted that the trigger output ports of both the global synchronization module and the local signal source module are set to low level by default. When the global synchronization module and the local signal source module detect the rising edge of the input signal at their respective trigger input ports, they immediately pull up the output signal of their respective trigger output ports to generate a rising edge. Simultaneously, they immediately send the input signals from their first local oscillator input ports and second local oscillator input ports to their first local oscillator output ports and second local oscillator output ports, respectively, and output up to N RF signals from their respective RF output port groups. Furthermore, through the cascaded structure between the global synchronization module and the local signal source modules, synchronization of the RF signals output by the local signal source modules can be achieved with a relatively small number of cables.

[0119] As can be seen, the large-scale coherent signal generation system described in the embodiments of the present invention can flexibly generate multiple coherent signal groups for different scale test scenarios, support large-scale multi-scenario parallel testing, and effectively reduce the number of cables, reduce system complexity, and improve installation and maintenance efficiency.

[0120] In an optional embodiment, such as Figure 2 As shown, the control module includes an information acquisition unit, a cascaded computing unit, and a data transmission unit.

[0121] The aforementioned information acquisition unit is data-connected to the aforementioned cascaded computing unit and the aforementioned data sending unit, and is used to acquire test information.

[0122] The above test information includes RF requirements and RF configuration information.

[0123] The aforementioned radio frequency demand information includes a first demand number PA and a second demand number sequence; the second demand number sequence includes NB second demand numbers; PA is an integer from 1 to M×N; the second demand number is an integer from 1 to N; PA and NB satisfy the following constraints:

[0124]

[0125] The aforementioned radio frequency configuration information includes a sequence of first configuration information and a sequence of second configuration information; the aforementioned second configuration information sequence includes NB second configuration information; both the aforementioned first configuration information and the aforementioned second configuration information include a switch state sequence and a set of baseband parameters.

[0126] Optionally, the above set of baseband parameters includes signal baud rate, modulation method, polarity, level range, and clock frequency.

[0127] It should be noted that the above modulation method can be NRZ, RZ, Manchester, differential Manchester, etc., and the embodiments of the present invention are not limited thereto; the above polarity is unipolar or bipolar; the above level range is CMOS / LVTTL, LVDS, etc., and the embodiments of the present invention are not limited thereto.

[0128] The above switch state sequence includes L switch state values; the switch state values ​​are 0 or 1; L is an integer greater than 1.

[0129] The aforementioned cascaded computing unit is connected to the aforementioned data transmission unit and is used to process the aforementioned radio frequency demand information to obtain the number of cascaded groups Q and the cascaded control sequence.

[0130] The above cascaded control sequence includes Q+NB cascaded control values; the above cascaded control values ​​are 0 or 1.

[0131] It should be noted that when the control port of the aforementioned cascade control switch receives a cascade control value of 0, its input port and output port are in a disconnected state; when the control port of the aforementioned cascade control switch receives a cascade control value of 1, its input port and output port are in a directly connected state, and the signal received by its input port will be immediately transmitted to its own output port.

[0132] The aforementioned data transmission unit is used to forward the aforementioned radio frequency configuration information and the aforementioned cascade control sequence to the aforementioned local signal source module based on the aforementioned number of cascade groups.

[0133] In another alternative embodiment, such as Figure 3 As shown, the aforementioned local signal source module includes a local synchronization unit, a local switch, and N signal source units.

[0134] The aforementioned local synchronization unit is provided with the aforementioned synchronization input port group and N of the aforementioned synchronization output port groups.

[0135] The aforementioned signal source unit includes the aforementioned synchronous input port group, the aforementioned synchronous output port group, the aforementioned reference port group, the aforementioned control port, and the aforementioned radio frequency output port.

[0136] The N synchronization output port groups of the aforementioned local synchronization unit are respectively connected to the N synchronization input port groups of the aforementioned signal source units.

[0137] The synchronization output port group of the first signal source unit is connected to the synchronization input port group of the local synchronization unit, and also serves as the synchronization output port group of the local signal source module.

[0138] It should be noted that the synchronous output port groups of the other N-1 signal source units are in a floating state.

[0139] The reference input port of the first signal source unit serves as the reference input port of the local signal source module; the reference output port of the nth signal source unit is connected to the reference input port of the (n+1)th signal source unit; the reference output port of the Nth signal source unit serves as the reference output port of the local signal source module; n is an integer from 1 to N-1.

[0140] It should be noted that the reference input port of the first signal source unit is left floating.

[0141] The control ports of the N local signal source modules are all connected to the control ports of the local signal source modules through the local switch.

[0142] The radio frequency output ports of the N signal source units are respectively used as the N radio frequency output ports of the local signal source module.

[0143] like Figure 3As shown, the left side of the local synchronization unit is the synchronization input port group, and the right side, from top to bottom, consists of N synchronization output port groups; the three ports on the left side of the signal source unit, from top to bottom, are the synchronization input port group, the control port, and the reference input port; the three ports on the right side of the signal source unit, from top to bottom, are the synchronization output port group, the radio frequency output port, and the reference output port.

[0144] Preferably, the output port of the control module is connected to the local switch of any local signal source module, and the local switches of adjacent local signal source modules are connected for data connection, thereby realizing the data connection between the control module and all local signal source modules.

[0145] It is evident that the cascaded structure among the N signal source units within the local signal source module can effectively reduce the number of cables within the local signal source module, further reducing system complexity and improving installation and maintenance efficiency.

[0146] In yet another alternative embodiment, such as Figure 4 As shown, the global synchronization module includes a first driver, a first amplifier, a first power divider, a second amplifier, and a second power divider.

[0147] The input port of the first driver serves as the trigger input port of the global synchronization module; the output port of the first driver serves as the trigger output port of the global synchronization module.

[0148] It should be noted that the aforementioned first driver is used to send the input signal from its own input port to its own output port, thereby achieving isolation between the two.

[0149] The input port of the first amplifier serves as the first local oscillator input port of the global synchronization module; the output port of the first amplifier is connected to the input port of the first power divider; and the M output ports of the first power divider serve as the M first local oscillator output ports of the global synchronization module.

[0150] The input port of the second amplifier serves as the second local oscillator input port of the global synchronization module; the output port of the second amplifier is connected to the input port of the second power divider; and the M output ports of the second power divider serve as the M second local oscillator output ports of the global synchronization module.

[0151] It should be noted that the input signal at the first local oscillator input port of the global synchronization module is amplified by the first amplifier and then proportionally distributed by the first power divider, resulting in M ​​identical but isolated output signals at the M first local oscillator output ports of the global synchronization module; the input signal at the second local oscillator input port of the global synchronization module is amplified by the second amplifier and then proportionally distributed by the second power divider, resulting in M ​​identical but isolated output signals at the M second local oscillator output ports of the global synchronization module.

[0152] In yet another alternative embodiment, such as Figure 5 As shown, the aforementioned local synchronization unit includes a second driver, a third amplifier, a third power divider, a fourth amplifier, and a fourth power divider.

[0153] The input port of the second driver serves as the trigger input port of the local synchronization unit; the output port of the second driver serves as the trigger output port of the local synchronization unit.

[0154] The input port of the third amplifier serves as the first local oscillator input port of the local synchronization unit; the output port of the third amplifier is connected to the input port of the third power divider; and the N output ports of the third power divider serve as the N first local oscillator output ports of the local synchronization unit.

[0155] The input port of the fourth amplifier serves as the second local oscillator input port of the local synchronization unit; the output port of the fourth amplifier is connected to the input port of the fourth power divider; and the N output ports of the fourth power divider serve as the N second local oscillator output ports of the local synchronization unit.

[0156] It should be noted that the input signal at the first local oscillator input port of the local synchronization module is amplified by the third amplifier and then proportionally distributed by the third power divider, resulting in N identical but isolated output signals at the N first local oscillator output ports of the local synchronization module; the input signal at the second local oscillator input port of the local synchronization module is amplified by the fourth amplifier and then proportionally distributed by the fourth power divider, resulting in N identical but isolated output signals at the N second local oscillator output ports of the local synchronization module.

[0157] In yet another alternative embodiment, such as Figure 6 As shown, the above signal source unit includes a state control subunit, a local oscillator selection subunit, a signal generation subunit, and a clock subunit.

[0158] like Figure 6As shown, the left side of the state control subunit is the input port, and the right side, from top to bottom, consists of the first output port, the second output port, and the third output port.

[0159] The input port of the aforementioned state control subunit serves as the control port of the aforementioned signal source unit; the first output port of the aforementioned state control subunit is connected to the control port of the aforementioned clock subunit; the second output port of the aforementioned state control subunit is connected to the control port of the aforementioned local oscillator selection subunit; and the third output port of the aforementioned state control subunit is connected to the control port of the aforementioned signal generation subunit.

[0160] The value of L is 7; the aforementioned state control subunit is used to output the first switch state value of the received switch state sequence to the first output port of the aforementioned state control subunit, output the last 6 switch state values ​​of the received switch state sequence to the second output port of the aforementioned state control subunit, and output the received baseband parameter set to the third output port of the aforementioned state control subunit.

[0161] like Figure 6 As shown, the left side of the aforementioned local oscillator selection subunit, from top to bottom, consists of the first input port, the second input port, the third input port, the fourth input port, and the control port; the right side of the aforementioned local oscillator selection subunit, from top to bottom, consists of the first output port, the second output port, the third output port, and the fourth output port.

[0162] The first input port of the aforementioned local oscillator selection subunit serves as the first local oscillator input port of the aforementioned signal source module; the second input port of the aforementioned local oscillator selection subunit serves as the second local oscillator input port of the aforementioned signal source module.

[0163] The first output port of the aforementioned local oscillator selection subunit serves as the first local oscillator output port of the aforementioned signal source module; the second output port of the aforementioned local oscillator selection subunit serves as the second local oscillator output port of the aforementioned signal source module.

[0164] The third output port of the aforementioned local oscillator selection subunit is connected to the second input port of the aforementioned signal generation subunit; the fourth output port of the aforementioned local oscillator selection subunit is connected to the third input port of the aforementioned signal generation subunit.

[0165] like Figure 6 As shown, on the left side of the above signal generation subunit, from top to bottom, are the control port, the first input port, the second input port, the third input port, and the fourth input port; on the right side of the above signal generation subunit, from top to bottom, are the first output port and the second output port.

[0166] The first input port of the aforementioned signal generation subunit serves as the aforementioned trigger input port of the aforementioned signal source unit.

[0167] The first output port of the aforementioned signal generation subunit serves as the aforementioned trigger output port of the aforementioned signal source unit.

[0168] The second output port of the aforementioned signal generation subunit serves as the aforementioned radio frequency output port of the aforementioned signal source unit.

[0169] like Figure 6 As shown, on the left side of the clock subunit, from top to bottom, are the control port and the input port, respectively; on the right side, from top to bottom, are the first output port, the second output port, the third output port, and the fourth output port, respectively.

[0170] The input port of the aforementioned clock subunit serves as the reference input port of the aforementioned signal source unit; the first output port of the aforementioned clock subunit serves as the reference output port of the aforementioned signal source unit; the second output port of the aforementioned clock subunit is connected to the fourth input port of the aforementioned signal generation subunit; the third output port of the aforementioned clock subunit is connected to the third input port of the aforementioned local oscillator selection subunit; and the fourth output port of the aforementioned clock subunit is connected to the fourth input port of the aforementioned local oscillator selection subunit.

[0171] In yet another alternative embodiment, such as Figure 7 As shown, the aforementioned local oscillator selection subunit includes a first output selection switch, a second output selection switch, a third output selection switch, a fourth output selection switch, a first input selection switch, a second input selection switch, a first local oscillator source, a second local oscillator source, and a control signal distributor.

[0172] The input port of the first output selection switch is used as the first input port of the local oscillator selection subunit; the first output port of the first output selection switch is connected to the first input port of the first input selection switch; the second output port of the first output selection switch is in the off state.

[0173] The input port of the aforementioned second output selection switch serves as the second input port of the aforementioned local oscillator selection subunit; the first output port of the aforementioned second output selection switch is connected to the first input port of the aforementioned second input selection switch; the second output port of the aforementioned second output selection switch is in an off state.

[0174] The input port of the first local oscillator source is used as the third input port of the local oscillator selection subunit; the output port of the first local oscillator source is connected to the input port of the third output selection switch; the first output port of the third output selection switch is connected to the second input port of the first input selection switch; and the second output port of the third output selection switch is used as the first output port of the local oscillator selection subunit.

[0175] The input port of the second local oscillator source is used as the fourth input port of the local oscillator selection subunit; the output port of the second local oscillator source is connected to the input port of the fourth output selection switch; the first output port of the fourth output selection switch is connected to the second input port of the second input selection switch; and the second output port of the fourth output selection switch is used as the second output port of the local oscillator selection subunit.

[0176] The output port of the first input selection switch is used as the third output port of the local oscillator selection subunit; the output port of the second input selection switch is used as the fourth output port of the local oscillator selection subunit.

[0177] The input port of the aforementioned control signal distributor serves as the control port of the aforementioned local oscillator selection subunit; the aforementioned control signal distributor is used to send the received six aforementioned switch state values ​​to the control ports of the aforementioned first output selection switch, the aforementioned second output selection switch, the aforementioned third output selection switch, the aforementioned fourth output selection switch, the aforementioned first input selection switch, and the aforementioned second input selection switch, respectively.

[0178] When the control ports of the first output selection switch, the second output selection switch, the third output selection switch, and the fourth output selection switch receive a switch state value of 1, the signal received by the corresponding input port is forwarded to the corresponding first output port.

[0179] When the control ports of the first output selection switch, the second output selection switch, the third output selection switch, and the fourth output selection switch receive a switch state value of 0, the signal received by the corresponding input port is forwarded to the corresponding second output port.

[0180] When the control port of the first input selection switch and the second input selection switch receives a switch state value of 1, the signal received by the corresponding first input port is forwarded to the corresponding output port.

[0181] When the control port of the first input selection switch and the second input selection switch receives a switch state value of 0, the signal received by the corresponding second input port is forwarded to the corresponding output port.

[0182] In yet another alternative embodiment, such as Figure 8 As shown, the signal generation subunit includes an FPGA, a digital-to-analog converter, and a frequency converter.

[0183] The first input port of the FPGA serves as the control port of the signal generation subunit.

[0184] The second input port of the FPGA mentioned above serves as the first input port of the signal generation subunit.

[0185] The third input port of the FPGA mentioned above serves as the second input port of the signal generation subunit.

[0186] It should be noted that the signal input to the third input port of the FPGA is used as the clock signal to drive the FPGA.

[0187] The first output port of the FPGA is used as the first output port of the signal generation subunit.

[0188] It should be noted that the signal output from the first output port of the FPGA is low by default. When the FPGA detects the rising edge of the signal input to its second input port, it changes the signal output from its first output port from low to high, thus achieving synchronous triggering of the output signal of the FPGA's first output port and the input signal of the FPGA's second input port.

[0189] The second output port of the FPGA is connected to the input port of the digital-to-analog converter.

[0190] It should be noted that the FPGA generates a digital baseband signal based on the baseband parameter set received at its first input port, and outputs the digital baseband signal from its second output port when it detects the rising edge of the signal input at its second input port, thereby synchronizing the digital baseband signal with the input signal at the FPGA's second input port. The method of generating a digital baseband signal using a baseband parameter set is existing, and will not be elaborated further in this embodiment.

[0191] The output port of the aforementioned digital-to-analog converter is connected to the first input port of the aforementioned frequency converter.

[0192] It should be noted that the aforementioned digital-to-analog converter is used to convert the received digital baseband signal into an analog signal, which is then output from its own output port.

[0193] The second input port of the frequency converter serves as the third input port of the signal generation subunit; the third input port of the frequency converter serves as the fourth input port of the signal generation subunit; and the output port of the frequency converter serves as the second output port of the signal generation subunit.

[0194] It should be noted that the above-mentioned frequency converter first mixes the analog baseband signal received at its first input port with the signal received at its second input port to obtain a preliminary mixed signal. Then, it mixes the preliminary mixed signal with the signal received at its third input port to obtain a radio frequency signal, which is then output from its output port.

[0195] In yet another alternative embodiment, such as Figure 9 As shown, the aforementioned clock subunit includes a clock amplifier, a reference clock generator, a clock selection switch, and a clock power divider.

[0196] The input port of the aforementioned clock amplifier serves as the input port of the aforementioned clock subunit; the output port of the aforementioned clock amplifier is connected to the first input port of the aforementioned clock selection switch.

[0197] The output port of the aforementioned reference clock generator is connected to the second input port of the aforementioned clock selection switch.

[0198] It should be noted that the aforementioned reference clock generating device can be a clock signal generating device such as a crystal oscillator or a phase-locked loop, and the embodiments of the present invention are not limited thereto.

[0199] The control port of the aforementioned clock selection switch serves as the control port of the aforementioned clock subunit.

[0200] When the control port of the clock selection switch receives a switch state value of 1, the signal received by the first input port of the clock selection switch is forwarded to the output port of the clock selection switch.

[0201] When the control port of the clock selection switch receives a switch state value of 0, the signal received by the second input port of the clock selection switch is forwarded to the output port of the clock selection switch.

[0202] The output port of the aforementioned clock selection switch is connected to the input port of the aforementioned clock power divider.

[0203] The first output port of the aforementioned clock power divider serves as the first output port of the aforementioned clock subunit; the second output port of the aforementioned clock power divider serves as the second output port of the aforementioned clock subunit; the third output port of the aforementioned clock power divider serves as the third output port of the aforementioned clock subunit; and the fourth output port of the aforementioned clock power divider serves as the fourth output port of the aforementioned clock subunit.

[0204] The aforementioned power divider is used to divide the clock signal received at the input port into four equal parts based on energy, resulting in four synchronous clock signals.

[0205] As can be seen, by implementing the large-scale coherent signal generation system described in the embodiments of the present invention, coherent signal groups for different scale test scenarios can be flexibly generated, supporting large-scale multi-scenario parallel testing, effectively improving the utilization rate of signal source hardware resources, while effectively reducing the number of cables, reducing system complexity, and improving installation and maintenance efficiency.

[0206] Example 2

[0207] Please see Figure 10 , Figure 10 This is a flowchart illustrating a large-scale coherent signal generation method disclosed in an embodiment of the present invention. Figure 10 The described large-scale coherent signal generation method is applied in the field of coherent signal generation, such as the generation of large-scale coherent signals in modern communication, radar detection, and wireless communication testing. This invention does not limit the application of this method. Figure 10 As shown, this large-scale coherent signal generation method includes:

[0208] S1. Obtain test information using the information acquisition unit of the control module.

[0209] S2. Using the cascaded calculation unit of the control module, the first requirement number PA in the above test information is processed to obtain the cascade group number Q, expressed as:

[0210]

[0211] In the formula, This is the floor operator.

[0212] S3. Using the data transmission unit of the control module described above, send a cascade control value of 1 to the cascade control switches from the 1st to the Q-1th respectively.

[0213] Using the data transmission unit of the control module described above, a cascade control value of 0 is sent to each of the Q to M-1 cascade control switches.

[0214] It should be noted that after step S3 is executed, the first to Q local signal source modules form a cascaded structure, which is used to generate the first coherent signal group after step S4 is executed; the remaining local signal source modules are independent of each other, among which the Q+1 to Q+NB local signal source modules are used to generate the second to NB+1 coherent signal groups after step S5 is executed.

[0215] S4. Using the data transmission unit of the control module, the first configuration information in the test information is sent to the first to Q local signal source modules.

[0216] The first coherent signal group is generated using the first to Q local signal source modules; the first coherent signal group includes PA radio frequency signals.

[0217] It should be noted that the aforementioned PA radio frequency signals include the (Q-1)×N radio frequency signals output from the (Q-1)×N radio frequency output ports of the 1st to Q-1th local signal source modules, and the PA-(Q-1)×N radio frequency signals output from any PA-(Q-1)×N radio frequency output ports of the Qth local signal source module.

[0218] As can be seen, the first coherent signal group mentioned above can support test scenarios that require up to M×N coherent signal sources.

[0219] S5. Using the data transmission unit of the control module, the NB second configuration information in the test information is sent to the Q+1 to Q+NB local signal source modules respectively.

[0220] Using the Q+1 to Q+NB local signal source modules described above, the 2nd to NB+1th coherent signal groups are generated respectively; the kth coherent signal group includes... The above-mentioned radio frequency signals; k is an integer from 2 to NB+1; This refers to the (k-1)th second demand number in the second demand number sequence from the above test information.

[0221] It should be noted that the kth coherent signal group mentioned above... A radio frequency signal, which is any signal from the k-th local signal source module. Each RF output port outputs One radio frequency signal.

[0222] It can be seen that the above-mentioned 2nd to NB+1th coherent signal groups can each support test scenarios that require up to N coherent signal sources.

[0223] It should be noted that the above coherent signal groups are independent of each other, and therefore can be used for different test scenarios.

[0224] In summary, the large-scale coherent signal generation method described in the embodiments of the present invention can flexibly generate coherent signal groups for different scale test scenarios, support large-scale multi-scenario parallel testing, and effectively improve the utilization rate of signal source hardware resources.

[0225] The device embodiments described above are merely illustrative. The modules described as separate components may or may not be physically separate, and the components shown as modules may or may not be physical modules; that is, they may be located in one place or distributed across multiple network modules. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0226] Through the detailed description of the above embodiments, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, including read-only memory (ROM), random access memory (RAM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), one-time programmable read-only memory (OTPROM), electrically-erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, disk storage, magnetic tape storage, or any other computer-readable medium that can be used to carry or store data.

[0227] Finally, it should be noted that the large-scale coherent signal generation system and method disclosed in the embodiments of the present invention are merely preferred embodiments of the present invention, and are only used to illustrate the technical solutions of the present invention, not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A large-scale coherent signal generation system, characterized in that, It includes M local signal source modules, a global synchronization module, M-1 cascaded control switches and control modules; M is an integer greater than 1; The local signal source module is provided with a synchronous input port group, a synchronous output port group, a reference port group, a control port, and a radio frequency output port group; The synchronization input port group includes a trigger input port, a first local oscillator input port, and a second local oscillator input port; The synchronous output port group includes a trigger output port, a first local oscillator output port, and a second local oscillator output port; The reference port group includes a reference input port and a reference output port; The radio frequency output port group includes N radio frequency output ports; N is an integer greater than 1; The global synchronization module includes the synchronization input port group and M synchronization output port groups; The M synchronization output port groups of the global synchronization module are respectively connected to the synchronization input port groups of the M local signal source modules; The synchronization output port group of the first local signal source module is connected to the synchronization input port group of the global synchronization module; The synchronous output port group of the local signal source module is left floating; Integers from 2 to M; The reference input port of the first local signal source module is left floating; The reference output port of the local signal source module is connected to the first... The input port of the cascaded control switch; the reference output port of the Mth local signal source module is left floating; Integers from 1 to M-1; The control module is connected to the control ports of the M local signal source modules and the M-1 cascaded control switches respectively, for acquiring test information, and controlling the on / off state of the M-1 cascaded control switches based on the test information, and controlling the M local signal source modules to generate several coherent signal groups; the coherent signal group includes several coherent and synchronously output radio frequency signals.

2. The large-scale coherent signal generation system according to claim 1, characterized in that, The control module includes an information acquisition unit, a cascaded computing unit, and a data transmission unit; The information acquisition unit is data-connected to the cascaded computing unit and the data sending unit, and is used to acquire test information; The test information includes RF requirement information and RF configuration information; The radio frequency demand information includes a first demand number PA and a second demand number sequence; the second demand number sequence includes NB second demand numbers; PA is an integer from 1 to M×N; the second demand number is an integer from 1 to N; PA and NB satisfy the following constraints: The radio frequency configuration information includes a first configuration information and a second configuration information sequence; the second configuration information sequence includes NB second configuration information; both the first configuration information and the second configuration information include a switch state sequence and a baseband parameter set. The switch state sequence includes L switch state values; each switch state value is 0 or 1; and the value of L is 7. The cascaded computing unit, data-connected to the data transmission unit, processes the radio frequency demand information to obtain the number of cascade groups Q and the cascaded control sequence; the expression for the number of cascade groups Q is: In the formula, This is the floor function operator; ; The cascaded control sequence includes Q+NB cascaded control values; the cascaded control values ​​are either 0 or 1. The data transmission unit is used to forward the radio frequency configuration information and the cascade control sequence to the local signal source module based on the number of cascade groups.

3. The large-scale coherent signal generation system according to claim 2, characterized in that, The local signal source module includes a local synchronization unit, a local switch, and N signal source units; The local synchronization unit is provided with the synchronization input port group and N synchronization output port groups; The signal source unit includes the synchronization input port group, the synchronization output port group, the reference port group, the control port, and the radio frequency output port. The N synchronization output port groups of the local synchronization unit are respectively connected to the synchronization input port groups of the N signal source units; The synchronization output port group of the first signal source unit is connected to the synchronization input port group of the local synchronization unit, and also serves as the synchronization output port group of the local signal source module. The reference input port of the first signal source unit serves as the reference input port of the local signal source module; the reference output port of the nth signal source unit is connected to the reference input port of the (n+1)th signal source unit; the reference output port of the Nth signal source unit serves as the reference output port of the local signal source module; n is an integer from 1 to N-1; The control ports of the N local signal source modules are all connected to the control ports of the local signal source modules through the local switch; The radio frequency output ports of the N signal source units are respectively used as the N radio frequency output ports of the local signal source module.

4. The large-scale coherent signal generation system according to claim 3, characterized in that, The global synchronization module includes a first driver, a first amplifier, a first power divider, a second amplifier, and a second power divider; The input port of the first driver serves as the trigger input port of the global synchronization module; the output port of the first driver serves as the trigger output port of the global synchronization module. The input port of the first amplifier serves as the first local oscillator input port of the global synchronization module; the output port of the first amplifier is connected to the input port of the first power divider; the M output ports of the first power divider serve as the M first local oscillator output ports of the global synchronization module, and are connected one-to-one with the first local oscillator input ports of the M local signal source modules. The input port of the second amplifier serves as the second local oscillator input port of the global synchronization module; the output port of the second amplifier is connected to the input port of the second power divider; the M output ports of the second power divider serve as the M second local oscillator output ports of the global synchronization module, and are connected one-to-one with the second local oscillator input ports of the M local signal source modules.

5. The large-scale coherent signal generation system according to claim 4, characterized in that, The local synchronization unit includes a second driver, a third amplifier, a third power divider, a fourth amplifier, and a fourth power divider; The input port of the second driver serves as the trigger input port of the local synchronization unit; the output port of the second driver serves as the trigger output port of the local synchronization unit. The input port of the third amplifier serves as the first local oscillator input port of the local synchronization unit; the output port of the third amplifier is connected to the input port of the third power divider; the N output ports of the third power divider serve as the N first local oscillator output ports of the local synchronization unit, and are connected one-to-one with the first local oscillator input ports of the N signal source units. The input port of the fourth amplifier serves as the second local oscillator input port of the local synchronization unit; the output port of the fourth amplifier is connected to the input port of the fourth power divider; the N output ports of the fourth power divider serve as the N second local oscillator output ports of the local synchronization unit, and are connected one-to-one with the second local oscillator input ports of the N signal source units.

6. The large-scale coherent signal generation system according to claim 5, characterized in that, The signal source unit includes a state control subunit, a local oscillator selection subunit, a signal generation subunit, and a clock subunit; The input port of the state control subunit serves as the control port of the signal source unit; The first output port of the state control subunit is connected to the control port of the clock subunit; The second output port of the state control subunit is connected to the control port of the local oscillator selection subunit; The third output port of the state control subunit is connected to the control port of the signal generation subunit; The value of L is 7; the state control subunit is used to output the first switch state value of the received switch state sequence to the first output port of the state control subunit, output the last 6 switch state values ​​of the received switch state sequence to the second output port of the state control subunit, and output the received baseband parameter set to the third output port of the state control subunit. The first input port of the local oscillator selection subunit serves as the first local oscillator input port of the signal source module; the second input port of the local oscillator selection subunit serves as the second local oscillator input port of the signal source module. The first output port of the local oscillator selection subunit serves as the first local oscillator output port of the signal source module. The second output port of the local oscillator selection subunit serves as the second local oscillator output port of the signal source module; The third output port of the local oscillator selection subunit is connected to the second input port of the signal generation subunit; The fourth output port of the local oscillator selection subunit is connected to the third input port of the signal generation subunit; The first input port of the signal generation subunit serves as the trigger input port of the signal source unit; The first output port of the signal generation subunit serves as the trigger output port of the signal source unit; The second output port of the signal generation subunit serves as the radio frequency output port of the signal source unit; The input port of the clock subunit serves as the reference input port of the signal source unit; The first output port of the clock subunit serves as the reference output port of the signal source unit; The second output port of the clock subunit is connected to the fourth input port of the signal generation subunit; The third output port of the clock subunit is connected to the third input port of the local oscillator selection subunit; The fourth output port of the clock subunit is connected to the fourth input port of the local oscillator selection subunit.

7. The large-scale coherent signal generation system according to claim 6, characterized in that, The local oscillator selection subunit includes a first output selection switch, a second output selection switch, a third output selection switch, a fourth output selection switch, a first input selection switch, a second input selection switch, a first local oscillator source, a second local oscillator source, and a control signal distributor; The input port of the first output selection switch serves as the first input port of the local oscillator selection subunit; The first output port of the first output selection switch is connected to the first input port of the first input selection switch; The second output port of the first output selection switch is in the off state; The input port of the second output selection switch serves as the second input port of the local oscillator selection subunit; The first output port of the second output selection switch is connected to the first input port of the second input selection switch; The second output port of the second output selection switch is in the off state; The input port of the first local oscillator source serves as the third input port of the local oscillator selection subunit; the output port of the first local oscillator source is connected to the input port of the third output selection switch. The first output port of the third output selection switch is connected to the second input port of the first input selection switch. The second output port of the third output selection switch serves as the first output port of the local oscillator selection subunit; The input port of the second local oscillator source serves as the fourth input port of the local oscillator selection subunit; The output port of the second local oscillator is connected to the input port of the fourth output selection switch; The first output port of the fourth output selection switch is connected to the second input port of the second input selection switch. The second output port of the fourth output selection switch serves as the second output port of the local oscillator selection subunit. The output port of the first input selection switch serves as the third output port of the local oscillator selection subunit; The output port of the second input selection switch, and the fourth output port of the local oscillator selection subunit; The input port of the control signal distributor serves as the control port of the local oscillator selection subunit. The control signal distributor is used to send the received six switch state values ​​to the control ports of the first output selection switch, the second output selection switch, the third output selection switch, the fourth output selection switch, the first input selection switch, and the second input selection switch, respectively. When the control ports of the first output selection switch, the second output selection switch, the third output selection switch and the fourth output selection switch receive a switch state value of 1, the signal received by the corresponding input port is forwarded to the corresponding first output port. When the control ports of the first output selection switch, the second output selection switch, the third output selection switch and the fourth output selection switch receive a switch state value of 0, the signal received by the corresponding input port is forwarded to the corresponding second output port. When the control port of the first input selection switch and the second input selection switch receives a switch state value of 1, the signal received by the corresponding first input port is forwarded to the corresponding output port. When the control port of the first input selection switch and the second input selection switch receives a switch state value of 0, the signal received by the corresponding second input port is forwarded to the corresponding output port.

8. The large-scale coherent signal generation system according to claim 6, characterized in that, The signal generation subunit includes an FPGA, a digital-to-analog converter, and a frequency converter; The first input port of the FPGA serves as the control port of the signal generation subunit. The second input port of the FPGA serves as the first input port of the signal generation subunit. The third input port of the FPGA serves as the second input port of the signal generation subunit; The first output port of the FPGA serves as the first output port of the signal generation subunit. The second output port of the FPGA is connected to the input port of the digital-to-analog converter; The output port of the digital-to-analog converter is connected to the first input port of the frequency converter; The second input port of the frequency converter serves as the third input port of the signal generation subunit; the third input port of the frequency converter serves as the fourth input port of the signal generation subunit. The output port of the frequency converter serves as the second output port of the signal generation subunit.

9. The large-scale coherent signal generation system according to claim 6, characterized in that, The clock subunit includes a clock amplifier, a reference clock generator, a clock selection switch, and a clock power divider; The input port of the clock amplifier serves as the input port of the clock subunit; the output port of the clock amplifier is connected to the first input port of the clock selection switch. The output port of the reference clock generator is connected to the second input port of the clock selection switch; The control port of the clock selection switch serves as the control port of the clock subunit. When the control port of the clock selection switch receives the switch state value of 1, the signal received by the first input port of the clock selection switch is forwarded to the output port of the clock selection switch. When the control port of the clock selection switch receives a switch state value of 0, the signal received by the second input port of the clock selection switch is forwarded to the output port of the clock selection switch. The output port of the clock selection switch is connected to the input port of the clock power divider. The first output port of the clock power divider serves as the first output port of the clock subunit. The second output port of the clock power divider serves as the second output port of the clock subunit. The third output port of the clock power divider serves as the third output port of the clock subunit; The fourth output port of the clock power divider serves as the fourth output port of the clock subunit.

10. A method for generating large-scale coherent signals, characterized in that, Applied to the large-scale coherent signal generation system according to any one of claims 2 to 9, the method comprises: S1. Obtain test information using the control module; S2. Using the control module, the first demand number PA in the test information is processed to obtain the cascade group number Q, expressed as: In the formula, This is the floor function operator; S3. Using the control module, send a cascade control value of 1 to the 1st to Q-1th cascade control switches respectively; Using the data transmission unit of the control module, a cascade control value of 0 is sent to each of the Q to M-1 cascade control switches; S4. Using the control module, the first configuration information in the test information is sent to the first to Q local signal source modules; The first phase coherent signal group is generated using the first to Q local signal source modules; the first phase coherent signal group includes PA radio frequency signals; S5. Using the control module, the NB second configuration information in the test information are sent to the Q+1 to Q+NB local signal source modules respectively; Using the Q+1 to Q+NB local signal source modules, the 2nd to NB+1th coherent signal groups are generated respectively; the kth coherent signal group includes The radio frequency signal; k is an integer from 2 to NB+1; It is the (k-1)th second demand number in the second demand number sequence in the test information.

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