A schottky transistor implementing a metal-semiconductor tunneling schottky junction and a method of fabricating the same

Abstract

The application discloses a Schottky transistor realizing a metal-semiconductor tunneling Schottky junction and a preparation method thereof, and belongs to the technical field of semiconductor electronic devices. The application utilizes the characteristic that the width of a depletion layer is inversely proportional to the tunneling strength, constructs a Schottky contact and an ohmic contact between a metal and a semiconductor, limits the width of the depletion layer by using an external physical means to obtain a semiconductor material with an extremely thin physical thickness, and applies a gate voltage to modulate the width of a Schottky barrier of a metal-semiconductor Schottky junction generated by the Schottky contact, so as to realize the tunneling effect of electrons from the semiconductor material to the metal material. The width of the barrier of the metal-semiconductor interface is dynamically modulated by the gate voltage, so that the tunneling current is accurately controlled.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor electronic device technology, and in particular relates to a Schottky transistor that realizes a metal-semiconductor tunneling Schottky junction and its fabrication method. Background Technology

[0002] The Schottky barrier tunneling transistor (SMT) belongs to the field of semiconductor transistor physics and microelectronics. It is a novel type of transistor that uses gate voltage to precisely control the quantum tunneling process of electrons through a Schottky junction to achieve switching. The gate voltage can dynamically modulate the width and shape of the source Schottky barrier. When a positive gate voltage is applied, the depletion region on the semiconductor surface narrows, and the Schottky barrier becomes very thin. Electrons can efficiently tunnel from the metal source into the semiconductor channel, forming a large conduction current. When a negative gate voltage (or zero gate voltage) is applied, the depletion region widens, and the Schottky barrier becomes very thick. The probability of electron tunneling decays exponentially, and the tunneling current is effectively suppressed.

[0003] When a metal and a semiconductor come into contact, two types of contacts with drastically different properties are formed based on the difference in their work functions and the doping concentration on the semiconductor surface: one is the Schottky contact, which allows current to flow smoothly in one direction but significantly impedes it in the opposite direction; the other is the Ohmic contact, where, when a metal comes into contact with a heavily doped semiconductor, charge carriers can pass through an extremely thin barrier via quantum tunneling.

[0004] Heavy doping makes the depletion layer on the semiconductor surface extremely thin. According to quantum mechanics, electrons can tunnel directly through this extremely thin barrier instead of being thermally excited, creating a controllable and efficient quantum mechanical current transmission channel, thereby achieving transistor characteristics that cannot be achieved by classical thermionic emission theory.

[0005] In nanoscale transistors, contact resistance has become a dominant factor limiting transistor performance. Traditional heavy doping processes struggle to further reduce the barrier width. Achieving ultra-low resistance ohmic contacts is particularly difficult for low-dimensional materials and wide-bandgap semiconductors due to their inherent characteristics or the lack of effective doping processes. Summary of the Invention

[0006] To address the aforementioned problems, this invention provides a Schottky transistor that realizes a metal-semiconductor tunneling Schottky junction and its fabrication method. This invention utilizes the difference in work function between the metal and semiconductor to achieve a Schottky contact. By reducing the physical thickness of the semiconductor material, a sufficiently thin depletion layer is obtained, thereby utilizing the tunneling effect to replace hot electron emission. This transforms the metal-semiconductor contact from a rectifying Schottky contact to a non-rectifying ohmic contact. Furthermore, by applying a gate voltage to control the width of the Schottky barrier in the metal-semiconductor Schottky junction, the tunneling effect of electrons from the semiconductor to the metal is achieved.

[0007] To achieve the above-mentioned objectives, the present invention adopts the following technical solution:

[0008] In a first aspect, the present invention provides a Schottky transistor that realizes a metal-semiconductor tunneling Schottky junction, comprising, from bottom to top: an insulating substrate, a first metal electrode, an n-type semiconductor material, a second metal electrode, a top gate insulating layer material, and a top gate electrode; the first metal electrode forms a Schottky contact with the n-type semiconductor material; the second metal electrode forms an ohmic contact with the n-type semiconductor material; and the thickness of the n-type semiconductor material is in the nanometer or sub-nanometer range.

[0009] Furthermore, the thickness of the n-type semiconductor material is 1-9 nm.

[0010] Through extensive experiments, this invention has found that tunneling can occur when the thickness of the n-type semiconductor material used is 6.6 nm. If the feature size is less than 6.6 nm, the depletion region also meets the conditions for tunneling in this invention. Therefore, the thickness of the n-type semiconductor material is limited to 1-9 nm.

[0011] Furthermore, the work function of the first metal electrode is greater than the work function of the n-type semiconductor material.

[0012] Furthermore, the first metal electrode is selected from gold.

[0013] Furthermore, the n-type semiconductor material is MoS2.

[0014] Furthermore, the work function of the second metal electrode is less than the work function of the n-type semiconductor material.

[0015] Furthermore, the second metal electrode is selected from titanium.

[0016] This invention utilizes a physical method to obtain an ultrathin semiconductor structure in contact with a metal, which is equivalent to a heavily doped effect. Due to the limitation of physical thickness, the surface depletion layer shrinks at the nanoscale. By applying a gate voltage to control the width of the Schottky barrier at the metal-semiconductor Schottky junction, the tunneling effect of electrons from the semiconductor material to the metal material is achieved. By dynamically modulating the barrier width at the metal-semiconductor interface with the gate voltage, the tunneling current advantage can be precisely controlled. Theoretically, a subthreshold swing of less than 60 mV / decade can be achieved.

[0017] Secondly, the present invention provides a method for fabricating a Schottky transistor that realizes a metal-semiconductor tunneling Schottky junction, comprising the following steps: fabricating a first metal electrode pattern on a substrate A by a first photolithography process; depositing a first metal electrode material on the substrate A according to the first metal electrode pattern; stripping excess photoresist on the substrate A; and obtaining the first metal electrode after a first annealing process; stripping an n-type semiconductor material to obtain an n-type semiconductor material with a uniform thickness at the nanometer or sub-nanometer level on a substrate B; transferring the n-type semiconductor material onto the first metal electrode; and fabricating a second metal electrode on the n-type semiconductor material by a second photolithography process. The process involves: forming a second metal electrode pattern; depositing a second metal electrode material on the n-type semiconductor material according to the second metal electrode pattern; removing excess photoresist from substrate A; and obtaining the second metal electrode after a second annealing. The top gate insulating layer material is then removed, and a top gate insulating layer material of uniform thickness is formed on substrate C. The top gate insulating layer material is then transferred to substrate A. A top gate electrode pattern is prepared on the top gate insulating layer material using a third photolithography process. The top gate electrode material is deposited on the top gate insulating layer material according to the top gate electrode pattern. Excess photoresist on substrate A is removed, and after a third annealing, the Schottky transistor realizing a metal-semiconductor tunneling Schottky junction is obtained.

[0018] Furthermore, substrates A, B, and C are all silicon substrates and each has an insulating dielectric layer attached.

[0019] Furthermore, the temperature for the first annealing, the second annealing, and the third annealing are all 200℃, and the time is 15-20 minutes for each.

[0020] This invention involves fabricating a first metal electrode on an insulating substrate that can form a Schottky contact with a semiconductor; then transferring an n-type semiconductor material with a sufficiently thin physical thickness onto the first metal electrode to create a contact surface with an extremely thin barrier width; then fabricating a second metal electrode using a metal material that forms an ohmic contact with the n-type semiconductor material to form a circuit; then covering the contact surface with the Schottky contact with an h-BN top gate insulating layer material; and finally depositing a top gate electrode to complete the fabrication of the device.

[0021] Compared with the prior art, the present invention has the following advantages and technical effects:

[0022] This invention utilizes the inversely proportional relationship between depletion layer width and tunneling intensity. By constructing Schottky and Ohmic contacts between the metal and semiconductor, and using external physical means to obtain an extremely thin semiconductor material to limit the width of the depletion layer, a gate voltage is applied to modulate the width of the Schottky barrier at the metal-semiconductor Schottky junction where the Schottky contact occurs, thus achieving the tunneling effect of electrons from the semiconductor to the metal. By dynamically modulating the barrier width at the metal-semiconductor interface with the gate voltage, the tunneling current advantage can be precisely controlled. Theoretically, a subthreshold swing of less than 60 mV / decade can be achieved. The Schottky barrier tunneling transistor junction constructed in this invention exhibits extremely low contact resistance and precise control of the tunneling current. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of the structure of a Schottky transistor that realizes a metal-semiconductor tunneling Schottky junction provided by the present invention, wherein 1 is an insulating substrate, 2 is a first metal electrode, 3 is an n-type semiconductor material, 4 is a second metal electrode, 5 is a top gate insulating layer material, and 6 is a top gate electrode.

[0025] Figure 2 This is a schematic diagram of the fabrication scheme for a Schottky transistor realizing a metal-semiconductor tunneling Schottky junction in Example 1;

[0026] Figure 3 An optical microscope schematic diagram of the Schottky transistor realizing a metal-semiconductor tunneling Schottky junction prepared in Example 1;

[0027] Figure 4 The IV characteristic curve of the Schottky transistor realizing a metal-semiconductor tunneling Schottky junction prepared in Example 1;

[0028] Figure 5 The transfer curve of the Schottky transistor realizing a metal-semiconductor tunneling Schottky junction prepared in Example 1;

[0029] Figure 6 The IV characteristic curves of the Schottky transistor that realizes a metal-semiconductor tunneling Schottky junction prepared in Example 2 are shown.

[0030] Figure 7 The transfer curve of the Schottky transistor realizing a metal-semiconductor tunneling Schottky junction prepared for Example 2;

[0031] Figure 8 The IV characteristic curve of the Schottky transistor prepared for Comparative Example 1. Detailed Implementation

[0032] Various exemplary embodiments of the present invention will now be described in detail. This detailed description should not be considered as a limitation of the present invention, but rather as a more detailed description of certain aspects, features, and embodiments of the present invention.

[0033] It should be understood that the terminology used in this invention is merely for describing particular embodiments and is not intended to limit the invention. Furthermore, with respect to numerical ranges in this invention, it should be understood that each intermediate value between the upper and lower limits of the range is also specifically disclosed. Every smaller range between any stated value or intermediate value within a stated range, and any other stated value or intermediate value within said range, is also included in this invention. The upper and lower limits of these smaller ranges may be independently included or excluded from the range.

[0034] Unless otherwise stated, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. While only preferred methods and materials have been described herein, any methods and materials similar or equivalent to those described herein may be used in the implementation or testing of this invention. All references to this specification are incorporated by way of citation to disclose and describe methods and / or materials associated with those references. In the event of any conflict with any incorporated reference, the content of this specification shall prevail.

[0035] Various modifications and variations can be made to the specific embodiments described in this specification without departing from the scope or spirit of the invention, as will be apparent to those skilled in the art. Other embodiments derived from this specification will also be apparent to those skilled in the art. This specification and embodiments are merely exemplary.

[0036] The terms “include,” “including,” “have,” “contain,” etc., used in this article are all open-ended terms, meaning that they include but are not limited to.

[0037] This invention provides a Schottky transistor that realizes a metal-semiconductor tunneling Schottky junction. It is a Schottky barrier tunnel transistor that utilizes an ultra-thin physical thickness to limit the width of the depletion layer, enabling tunneling of the metal-semiconductor Schottky junction. Its structure is as follows: Figure 1 As shown, it includes: an insulating substrate 1, a first metal electrode 2 (forming a Schottky contact with an n-type semiconductor material), an n-type semiconductor material 3, a second metal electrode 4 (forming an ohmic contact with an n-type semiconductor material), a top gate insulating layer material 5, and a top gate electrode 6.

[0038] This invention utilizes a physical method to obtain an ultrathin semiconductor structure in contact with a metal, which is equivalent to a heavily doped effect. Due to the limitation of physical thickness, the surface depletion layer shrinks at the nanoscale, enabling the transistor to tunnel. The Schottky contact between the metal and semiconductor is achieved by utilizing the difference in work function between them. By reducing the physical thickness of the semiconductor material, a sufficiently thin depletion layer is obtained, thereby enabling carrier tunneling through the depletion layer. This device can simultaneously control the width of the Schottky barrier in the metal-semiconductor tunneling Schottky junction by applying a gate voltage, thus regulating the electron tunneling process from the semiconductor to the metal. The design concept of this invention can realize a metal-semiconductor tunneling Schottky junction, obtaining a Schottky barrier tunnel crystal with extremely low contact resistance and precisely controllable tunneling current.

[0039] This invention also provides a method for fabricating a Schottky transistor that realizes a metal-semiconductor tunneling Schottky junction, specifically including the following steps:

[0040] Step 1: A substrate A with a first layer of metal electrode pattern is obtained by photolithography and development. Metal electrodes are deposited on the obtained substrate A by evaporation, and then the photoresist on it is removed. After annealing, the first metal electrode that can make the required contact with the semiconductor material can be obtained.

[0041] Step 2: The n-type semiconductor material with a suitable work function is peeled off using a blue adhesive tape mechanical peeling method to obtain a uniform thickness of n-type semiconductor material at the nanometer or sub-nanometer level on a clean substrate B; the uniform thickness of n-type semiconductor material at the nanometer or sub-nanometer level on the obtained substrate B is transferred to the substrate A obtained in the first step to obtain a metal-semiconductor junction with the required contact.

[0042] Step 3: By photolithography and development, a desired second metal electrode pattern is obtained on substrate A obtained in step 2; metal electrodes are deposited on substrate A by evaporation, and then the photoresist on it is removed. After annealing, a second metal electrode that can make the desired contact with the semiconductor is obtained.

[0043] Step 4: The top gate insulating layer material h-BN is peeled off using blue adhesive tape to obtain a thin layer of h-BN material of uniform thickness on a clean substrate C; the obtained h-BN material is transferred to the substrate A obtained in Step 3 to obtain a metal-semiconductor junction covered with the top gate insulating material.

[0044] Step 5: By photolithography and development, a desired top gate electrode pattern is obtained on substrate A obtained in step 4; a metal electrode is deposited on substrate A, and then the photoresist on it is removed. After annealing, a top gate metal electrode with adjustable gate voltage is obtained, and a Schottky transistor that realizes a metal-semiconductor tunneling Schottky junction is fabricated.

[0045] In some preferred embodiments, substrates A, B, and C are all silicon substrates and each has an insulating dielectric layer attached.

[0046] In some preferred embodiments, positive photoresist is spin-coated onto substrate A before photolithography. The spin-coating time is 60s and the spin-coating speed is 4000 rpm. Then, it is heated at 105°C for 4min.

[0047] In some preferred embodiments, the required first metal electrode pattern, second metal electrode pattern, and top gate electrode pattern are all designed and drawn using specific drawing software.

[0048] In some preferred embodiments, the electrode pattern is designed based on the shape of the stripped semiconductor material and h-BN material. There is no fixed electrode pattern shape; the optimal electrode pattern shape is determined based on the actual material shape.

[0049] In some preferred embodiments, electron beam lithography is used to precisely position and expose the designed electrode pattern during photolithography. The scanning speed of the photolithography machine is 0.9 mm / s and the power is 27 mW.

[0050] In some preferred embodiments, after exposure, development is performed using a developer. After development, the designed photolithographic electrode pattern can be obtained on the insulating dielectric layer of the substrate. The developer is a 6 wt.% tetramethylammonium hydroxide aqueous solution, and the development time is 20-30 s.

[0051] In some preferred embodiments, after the evaporation is completed, the evaporated substrate is immersed in a specific solvent that can dissolve the photoresist (such as acetone) to remove the photoresist, and then the dissolved substrate is transferred to another solvent (such as isopropanol) for cleaning to remove residual acetone and metal debris.

[0052] In some preferred embodiments, after the photoresist is stripped, it needs to be annealed at 200°C for 15-20 minutes under N2 protection to promote the interface reaction and improve the metal contact performance.

[0053] To facilitate understanding, the following explanations will first address several technical terms:

[0054] The method of mechanically peeling off blue tape is one such method.

[0055] Electron beam lithography is a cutting-edge microfabrication technique that uses a focused electron beam to directly scan and write micro- and nano-patterns onto the surface of a substrate coated with an electron-sensitive resist (electron beam photoresist). It belongs to maskless direct-write lithography, and by controlling the deflection and on / off state of the electron beam via computer, it achieves nanometer-level resolution fabrication of complex two-dimensional patterns.

[0056] The n-type semiconductor material used in the embodiments and comparative examples of this invention is selected from MoS2; the metal with a work function greater than that of the n-type semiconductor material is selected from Au; the metal with a work function less than that of the n-type semiconductor material is selected from Ti; the top gate insulating layer material is h-BN (hexagonal boron nitride); the substrates A, B and C used in this embodiment are all silicon substrates, and each has an insulating dielectric layer attached thereon.

[0057] In the embodiments and comparative examples of this invention, a high vacuum environment refers to a vacuum level of less than 10. -6 Vacuum environments on the order of Pa.

[0058] Example 1: A method for fabricating a Schottky transistor that realizes a metal-semiconductor tunneling Schottky junction.

[0059] The fabrication process of the Schottky transistor realizing the metal-semiconductor tunneling Schottky junction in this embodiment is as follows: Figure 2 As shown, the specific preparation method includes the following steps:

[0060] 1) Cut substrate A into 10mm×10mm pieces and wash them in acetone, isopropanol and deionized water for 15 minutes in sequence to obtain a clean insulating substrate. Dry it with a nitrogen gun for later use.

[0061] 2) Perform the first photolithography process on substrate A obtained in step 1): Use a spin coater to spin-coat the clean substrate A with positive photoresist (spin coating time is 60s, spin coating speed is 4000 rpm), then heat at 105℃ for 4min, use electrode pattern drawing software to draw the required electrode pattern, and then use electron beam exposure technology to accurately position and expose the designed electrode pattern. The scanning speed of the photolithography machine is 0.9mm / s, and the power is 27mW. After exposure, develop with developer to obtain the first metal electrode pattern on the insulating dielectric layer of substrate A.

[0062] 3) The first metal electrode (a metal electrode that forms a Schottky contact with the n-type semiconductor material) is prepared by performing the first metal deposition on the substrate A obtained in step 2): The substrate A obtained in step 2) is placed in the vacuum chamber of an electron beam evaporator, the metal source material Au is placed in a crucible, and the vacuum environment is evacuated. The electron beam evaporator will emit a highly focused electron beam to bombard the metal source material Au. At this time, the kinetic energy of the electron beam is converted into thermal energy, causing the metal source material to melt and evaporate instantly. The evaporated metal atoms fly in a straight line and deposit upwards on the entire substrate surface, including the exposed substrate A area and the upper surface and sidewalls of the photoresist. The substrate after the first metal deposition is completed is immersed in acetone, and then the dissolved substrate is transferred to isopropanol for cleaning to remove residual acetone and metal debris. Then the substrate is gently dried with a nitrogen gun. After that, it is annealed under N2 protection (200°C, 15 min), which helps to improve the metal contact performance and form the first metal electrode.

[0063] 4) MoS2 was peeled off using a blue adhesive tape: it was repeatedly peeled off from the large semiconductor crystal to obtain ultrathin MoS2 fragments (6.6 nm thick), which were then attached to a clean substrate B to obtain MoS2 with a uniform thickness at the nanometer level; the substrate B was then placed on the sample stage of the transfer stage, and a PVA (polyvinyl alcohol) solution was spin-coated onto the PDMS (polydimethylsiloxane) film. After curing (55 °C, 5 min), a PVA film was obtained. The PVA film was then precisely aligned with the MoS2 on the substrate B in the transfer stage and transferred to obtain a PVA film loaded with ultrathin MoS2.

[0064] 5) Place the substrate A obtained in step 3) on the sample stage of the transfer stage, fix the glass slide with the ultrathin MoS2-loaded PVA film obtained in step 4) in the slot of the transfer stage, select the contact area under the microscope, apply pressure to the two gradually through the transfer platform to achieve tight bonding, and hot-press bond at 95°C for 1 min. Immerse the substrate in 55°C deionized water for 15 min to dissolve and remove the PVA support film, and then gently blow dry the substrate with a nitrogen gun to obtain a MoS2 / Au metal-semiconductor Schottky junction with Schottky contacts, where MoS2 is an n-type semiconductor material with an extremely thin physical thickness.

[0065] 6) Perform a second photolithography process on substrate A obtained in step 5); spin-coat the MoS2 / Au metal-semiconductor Schottky junction obtained in step 5) using a spin coater, then heat it at 105℃ for 4 min, draw the required electrode pattern using electrode pattern drawing software, and then use electron beam exposure technology to precisely position and expose the designed electrode pattern. The photolithography machine has a scanning speed of 0.9 mm / s and a power of 27 mW. After exposure, develop it with developer to obtain the second metal electrode pattern on the n-type semiconductor material with an extremely thin physical thickness.

[0066] 7) Perform a second metal deposition on the substrate A obtained in step 6) to prepare a second metal electrode (a metal electrode that makes ohmic contact with the n-type semiconductor material): Place the substrate A obtained in step 6) into the vacuum chamber of the electron beam evaporator, place the metal source material Ti in the crucible, and evacuate to a high vacuum environment. The electron beam evaporator will emit a highly focused electron beam to bombard the metal source material Ti. At this time, the kinetic energy of the electron beam is converted into thermal energy, causing the metal to melt and evaporate instantly. The evaporated metal atoms fly in a straight line and deposit upwards on the entire substrate surface, including the exposed substrate area and the upper surface and sidewalls of the photoresist.

[0067] Substrate A is then immersed in acetone, and the dissolved substrate is transferred to isopropanol for cleaning to remove residual acetone and metal debris. The substrate is then gently dried with a nitrogen gun and annealed under N2 protection (200°C, 15 min) to promote the interfacial reaction between the metal and semiconductor, improve the metal contact performance, and form the second metal electrode.

[0068] 8) The h-BN material is peeled off by mechanical peeling with blue tape; the material is repeatedly peeled off from the bulk h-BN crystal to obtain a thin layer of h-BN fragments of 10 nm, which are then attached to a clean substrate C to obtain h-BN material with uniform thickness at the nanometer level.

[0069] 9) Prepare top gate insulating layer material on substrate A obtained in step 7): Place substrate A obtained in step 7) on the sample stage of the transfer stage, spin-coat PVA solution on PDMS film, and obtain PVA film after curing (55℃, 5min). Precisely align it with substrate C obtained in step 8) in the transfer stage and complete the transfer to finally obtain PVA film loaded with h-BN material.

[0070] 10) Place the substrate A obtained in step 7) on the sample stage of the transfer stage, fix the glass slide with the h-BN material PVA film obtained in step 9) in the slot of the transfer stage, observe the overlapping part through the microscope of the transfer stage, select a suitable contact area, apply pressure to the two gradually through the transfer platform to achieve tight adhesion, and hot press bond at 95°C for 1 min, immerse the substrate in 55°C deionized water for 15 min to dissolve and remove the PVA carrier film, and then gently blow dry the substrate with a nitrogen gun to obtain a metal-semiconductor Schottky junction covered with the top gate insulating material h-BN;

[0071] 11) Perform a third photolithography process on the metal-semiconductor Schottky junction covered with top gate insulating material h-BN in step 10): Spin coat the metal-semiconductor Schottky junction covered with top gate insulating material h-BN in step 10) using a spin coater, then heat it at 105℃ for 4 min, draw the required electrode pattern using electrode pattern drawing software, and then use electron beam exposure technology to accurately position and expose the designed electrode pattern. The photolithography machine scanning speed is 0.9 mm / s and the power is 27 mW. After exposure, develop it with developer to obtain the top gate electrode pattern on the top gate insulating material h-BN.

[0072] 12) A third metal deposition is performed on substrate A obtained in step 11) to prepare the top gate electrode: Substrate A obtained in step 11) is placed in the vacuum chamber of an electron beam evaporator. High-purity metal source material (Au) is placed in a crucible and the vacuum environment is evacuated. The electron beam evaporator will emit a highly focused electron beam to bombard the metal source. At this time, the kinetic energy of the electron beam is converted into thermal energy, causing the metal to melt and evaporate instantly. The evaporated metal atoms fly in a straight line and deposit upwards on the entire substrate surface, including the exposed substrate area and the upper surface and sidewalls of the photoresist. The obtained substrate A is immersed in acetone solvent. The dissolved substrate A is transferred to isopropanol for cleaning to remove residual acetone and metal debris. Then, the substrate is gently dried with a nitrogen gun. After that, it is annealed under N2 protection (200℃, 15min) to promote the interfacial reaction between the top gate electrode and the top gate insulating material h-BN to obtain a top gate metal electrode with adjustable gate voltage. A Schottky transistor that realizes a metal-semiconductor tunneling Schottky junction is thus prepared.

[0073] Figure 2 This is a schematic diagram of the fabrication scheme of the Schottky transistor realizing the metal-semiconductor tunneling Schottky junction prepared in Example 1.

[0074] Figure 3 This is a schematic diagram of an optical microscope showing the Schottky transistor that realizes a metal-semiconductor tunneling Schottky junction prepared in Example 1.

[0075] Example 2

[0076] Same as Example 1, except that the thickness of the MoS2 fragment in step 4) is 8.9 nm.

[0077] Performance testing:

[0078] The performance of the Schottky transistors realizing metal-semiconductor tunneling Schottky junctions prepared in Examples 1-2 was tested using a probe station and a dual-channel digital source meter. The results are as follows: Figures 4-7 As shown, Figure 4 The image shows the IV characteristic curves of the Schottky transistor that realizes a metal-semiconductor tunneling Schottky junction prepared in Example 1. Figure 5 The transfer curve of the Schottky transistor realizing a metal-semiconductor tunneling Schottky junction prepared in Example 1; Figure 6 The image shows the IV characteristic curves of the Schottky transistor that realizes a metal-semiconductor tunneling Schottky junction prepared in Example 2. Figure 7 The transfer curve is shown for the Schottky transistor that realizes a metal-semiconductor tunneling Schottky junction prepared in Example 2.

[0079] Depend on Figure 4 As can be seen, the curve to the right represents the typical rectified IV characteristic curve of a Schottky transistor, while the curve to the left represents the IV characteristic curve of a Schottky tunneling transistor exhibiting the tunneling effect. Figure 5 It can be seen that the Schottky transistor that realizes a metal-semiconductor tunneling Schottky junction prepared in Example 1 exhibits V d Under gate voltage regulation of 2V, the change was orders of magnitude, and a negative transconductance (NTR) phenomenon appeared on the right side of the curve, that is, as the gate voltage V... gs Increase, drain current I ds Instead, it decreases, indicating that it is a tunneled metal-semiconductor Schottky junction. According to... Figure 5 Based on the subthreshold swing calculation formula, it can be seen that within the range of Vgs = -2 to -1V, there is a small change in the gate voltage (dV). gs This can cause a change in drain current of one order of magnitude (ten times), and the SS of this Schottky transistor can be calculated as 43mV / decade.

[0080] The formula for calculating the subthreshold swing is as follows:

[0081] .

[0082] Depend on Figure 6 As can be seen, the curve to the right is the typical rectified IV characteristic curve of a Schottky transistor, while the curve to the left is the IV characteristic curve of a Schottky tunneling transistor that has undergone tunneling.

[0083] Depend on Figure 7It can be seen that the Schottky transistor that realizes a metal-semiconductor tunneling Schottky junction prepared in Example 2 exhibits V d Under gate voltage regulation of 3V, the change was orders of magnitude, and a negative transconductance (NTR) phenomenon appeared on the right side of the curve, that is, as the gate voltage V... gs Increase, drain current I ds Instead, it decreases, indicating that it is a tunneled metal-semiconductor Schottky junction. According to... Figure 7 Based on the subthreshold swing calculation formula, it can be seen that within the range of Vgs = 2~3V, there is a slight change in the gate voltage (dV). gs This can cause a change in drain current by an order of magnitude (tenfold), and the SS of this Schottky transistor can be calculated as 40mV / decade.

[0084] Comparative Example 1: A method for fabricating a Schottky transistor

[0085] Same as Example 1, except that in step 4), the thickness of the MoS2 fragments is 14.8 nm, and they are adhered to a clean substrate to obtain a uniform thickness of MoS2.

[0086] The transistors fabricated in Comparative Example 1 were used for performance testing using a probe station and a dual-channel digital source meter. The results are shown below. Figure 8 , Figure 8 The IV characteristic curves of the Schottky transistor fabricated for Comparative Example 1 are shown. Figure 8 It can be seen that when the physical thickness of the semiconductor material does not reach the ultra-thin thickness required by this invention, the transistor does not exhibit the tunneling effect and presents the typical rectification IV characteristic curve of a Schottky transistor.

[0087] The above are merely preferred embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A Schottky transistor implementing a metal-semiconductor tunneling Schottky junction, characterized in that, From bottom to top, sequentially include: insulating substrate, first metal electrode, n-type semiconductor material, second metal electrode, top gate insulating layer material and top gate electrode; The first metal electrode forms a Schottky contact with the n-type semiconductor material; the second metal electrode forms an ohmic contact with the n-type semiconductor material; the thickness of the n-type semiconductor material is nanometer or sub-nanometer level; The thickness of the n-type semiconductor material is 6.6nm; The metal work function of the first metal electrode is greater than the work function of the n-type semiconductor material; The metal work function of the second metal electrode is less than the work function of the n-type semiconductor material; The first metal electrode is selected from gold; The n-type semiconductor material is MoS2; The second metal electrode is selected from titanium; The preparation method of the Schottky transistor realizing metal-semiconductor tunneling Schottky junction comprises the following steps: preparing a first metal electrode pattern on a substrate A by a first photolithography process, depositing a first metal electrode material on the substrate A according to the first metal electrode pattern, peeling off the excess photoresist on the substrate A, obtaining the first metal electrode after the first annealing; peeling off the n-type semiconductor material, obtaining the n-type semiconductor material with uniform thickness of nanometer or sub-nanometer level on a substrate B, transferring the n-type semiconductor material to the first metal electrode; preparing a second metal electrode pattern on the n-type semiconductor material by a second photolithography process; depositing a second metal electrode material on the n-type semiconductor material according to the second metal electrode pattern, peeling off the excess photoresist on the substrate A, obtaining the second metal electrode after the second annealing; peeling off the top gate insulating layer material, obtaining the top gate insulating layer material with uniform thickness on a substrate C, transferring the top gate insulating layer material to the substrate A; preparing a top gate electrode pattern on the top gate insulating layer material by a third photolithography process, depositing a top gate electrode material on the top gate insulating layer material according to the top gate electrode pattern, peeling off the excess photoresist on the substrate A, obtaining the Schottky transistor realizing metal-semiconductor tunneling Schottky junction after the third annealing.

2. The Schottky transistor implementing a metal-semiconductor tunneling Schottky junction according to claim 1, wherein, The substrate A, substrate B and substrate C are all silicon substrates, and all have an insulating dielectric layer.

3. The Schottky transistor implementing a metal-semiconductor tunneling Schottky junction of claim 1, wherein, The temperature of the first annealing, the second annealing and the third annealing is all 200℃, and the time is all 15-20min.

Images