Memory data read error correction method and device based on logic operations

Abstract

This application discloses a memory data read error correction method and apparatus based on logical operations. The method includes: performing anomaly detection on each memory cell in the memory array to determine the number and location information of the data read error based on the detection results; XORing all read data bits according to the encoding rules of the ECC encoder to obtain the encoding formula corresponding to each bit in the ECC value; extracting the encoding formula including the erroneous data bit from the encoding formula corresponding to each bit in the ECC value based on the number and location information of the data read error; establishing a system of linear equations using a pre-obtained correct ECC value and the extracted encoding formula including the erroneous data bit, and solving the system of equations to obtain the correct value of the erroneous bit; replacing the correct data in the corresponding position according to the location information to perform error correction; thereby achieving arbitrary bit error correction and reducing the required ECC bits and memory array area.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a memory data read error correction method and a memory data read error correction device based on logic operations. Background Technology

[0002] In related technologies, memory data read error correction is generally based on the ECC algorithm. Taking 32-bit data as an example, correcting a 1-bit error requires adding 6 ECC bits, correcting a 2-bit error requires adding 12 ECC bits, and correcting a 3-bit error requires adding 18 ECC bits. In the 32-bit ECC scheme that corrects 2 bits, although 12 ECC bits are required, it can only correct a maximum of 2 bits of error in the 32-bit data. When a 3-bit error occurs, even if the error location is known, it is impossible to correct the error. Summary of the Invention

[0003] This application aims to at least partially solve one of the technical problems in the aforementioned technologies. To this end, one objective of this application is to propose a memory data read error correction method based on logical operations. This method utilizes the inverse reasoning principle of the ECC encoding algorithm, using known ECC values ​​to deduce the correct value of the erroneous bit, thereby achieving arbitrary bit error correction and reducing the required ECC bits and memory array area.

[0004] The second objective of this application is to propose a memory data read error correction device based on logical operations.

[0005] To achieve the above objectives, the first aspect of this application proposes a memory data read error correction method based on logical operations, comprising the following steps: performing anomaly detection on each memory cell in the memory array to determine the number and location information of data read errors based on the detection results; performing XOR on all read data bits according to the encoding rules of the ECC encoder to obtain the encoding formula corresponding to each bit in the ECC value; extracting the encoding formula including the erroneous data bits from the encoding formula corresponding to each bit in the ECC value based on the number and location information of the data read errors; establishing a system of linear equations using a pre-acquired correct ECC value and the extracted encoding formula including the erroneous data bits to solve the system of equations to obtain the correct value of the erroneous bit; and replacing the correct data in the corresponding position according to the location information to perform error correction.

[0006] The memory data read error correction method based on logical operations according to the embodiments of this application has the following advantages: based on the reverse reasoning principle of ECC encoding algorithm, the correct value of the error bit is deduced by using the known ECC value, thereby realizing arbitrary bit error correction and reducing the required ECC bits and memory array area.

[0007] In addition, the memory data read error correction method based on logical operations proposed in the above embodiments of this application may also have the following additional technical features:

[0008] Optionally, anomaly detection is performed on each storage cell in the storage array, including: using an error detection module to detect the cell current on each word line in the storage array; comparing the cell current on each word line with a preset reference current to determine whether the data read by the corresponding cell is abnormal.

[0009] Optionally, the data of the correct data bits can be kept unchanged when solving the system of equations.

[0010] Optionally, the correct ECC value is obtained by XORing the correct data written using the encoding rules of the ECC encoder.

[0011] To achieve the above objectives, a memory data read error correction device based on logical operations is proposed in the second aspect of this application, comprising: an error detection module for performing anomaly detection on each memory cell in the memory array to determine the number of bits and location information of data read errors based on the detection results; an error correction module for performing XOR operation on all read data bits according to the encoding rules of the ECC encoder to obtain the encoding formula corresponding to each bit in the ECC value; extracting the encoding formula including the erroneous data bits from the encoding formula corresponding to each bit in the ECC value according to the number of bits and location information of data read errors; establishing a system of linear equations using a pre-acquired correct ECC value and the extracted encoding formula including the erroneous data bits to solve the system of equations to obtain the correct value of the erroneous bit; and replacing the correct data in the corresponding position according to the location information to perform error correction.

[0012] In addition, the memory data read error correction device based on logic operations proposed in the above embodiments of this application may also have the following additional technical features:

[0013] Optionally, the error detection module is also used to detect the cell current on each word line in the memory array; and compare the cell current on each word line with a preset reference current to determine whether the data read by the corresponding cell is abnormal.

[0014] Optionally, the data of the correct data bits can be kept unchanged when solving the system of equations.

[0015] Optionally, the correct ECC value is obtained by XORing the correct data written using the encoding rules of the ECC encoder. Attached Figure Description

[0016] Figure 1This is a flowchart illustrating a memory data read error correction method based on logical operations according to an embodiment of this application;

[0017] Figure 2 This is a schematic diagram illustrating data error correction according to an embodiment of this application;

[0018] Figure 3 This is a schematic diagram of a memory data read error correction circuit based on logic operations according to an embodiment of this application. Detailed Implementation

[0019] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application.

[0020] To better understand the above technical solutions, exemplary embodiments of this application will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of this application are shown in the drawings, it should be understood that this application can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of this application and to fully convey the scope of this application to those skilled in the art.

[0021] To better understand the above technical solutions, the following will provide a detailed explanation of the technical solutions in conjunction with the accompanying drawings and specific implementation methods.

[0022] Please see Figure 1 , Figure 1 This is a flowchart illustrating a memory data read error correction method based on logical operations according to an embodiment of this application, as shown below. Figure 1 As shown, the memory data read error correction method based on logic operations includes the following steps:

[0023] S101 performs anomaly detection on each storage cell in the storage array to determine the number of bits and location information of data read errors based on the detection results.

[0024] As one embodiment, anomaly detection is performed on each storage cell in the storage array, including: using an error detection module to detect the cell current on each word line in the storage array; comparing the cell current on each word line with a preset reference current to determine whether the data read by the corresponding cell is abnormal.

[0025] As a specific example, such as Figure 3As shown, if the cell current on the word line is greater than the preset reference current and the difference is greater than the first threshold, the read data is judged to be normal, and the normal data is output as 1; if the cell current on the word line is less than the preset reference current and the difference exceeds the first threshold, the read data is judged to be normal, and the normal data is output as 0; if the cell current on the word line is approximately equal to the preset reference current, that is, the cell current on the word line is close to the preset reference current, the read data is judged to be abnormal, and the abnormal data location information is output; thus, the number of bits read incorrectly is counted based on the number of abnormal data location information.

[0026] S102, XOR all read data bits according to the encoding rules of the ECC encoder to obtain the encoding formula corresponding to each bit in the ECC value.

[0027] As a specific example, such as Figure 2 As shown, taking 32-bit error correction 3bite as an example, assuming that the error detection module (SA) detects that the last 3 bits of the 32-bit data are wrong, that is, it is clear that the error is concentrated in a specific position of the 32-bit data as the last 3 bits: data[0], data[1], data[2]), and the remaining 29 bits of data (data[3]~data

[31] ) are all correct (assuming that all the correct data are 0 for the time being).

[0028] The existing ECC encoding rule is: each bit of ECC is generated by the XOR operation (^) of multiple data bits (such as ecc[0] = data

[30] ^data

[29] ^...^data[0], ecc[1] = data

[31] ^data

[30] ^...^data[1] etc.).

[0029] S103, based on the number and location information of the erroneous bits read from the data, extract the encoding formula including the erroneous data bits from the encoding formula corresponding to each bit in the ECC value.

[0030] As a specific implementation, according to the ECC encoding rules, the ECC bit formula containing error bits data[0], data[1], and data[2] is selected. For example:

[0031] ecc[0]: contains data[0] and data[2];

[0032] ecc[1]: contains data[1];

[0033] ecc[2]: contains data[2].

[0034] Since the remaining 29 bits data[3]~data

[31] are all 0, 0 can be ignored in the XOR operation, so the formula can be simplified to a form containing only the error bit.

[0035] S104. A system of linear equations is established using the pre-obtained correct ECC value and the extracted coding formula including the error data bits, and the correct value of the error bits is obtained by solving the system of equations.

[0036] As an example, the correct ECC value is obtained by XORing the correct data written with the encoding rules of the ECC encoder.

[0037] Assuming the 12-bit correct ECC value corresponding to the 32-bit data is 12'b1110_1001_0110, that is, ecc[0]=0, ecc[1]=1, ecc[2]=1, the simplified formula is transformed into an equation:

[0038] Equation 1: 0 = data[2]^data[0];

[0039] Equation 2: 1 = data[1];

[0040] Equation 3: 1 = data[2].

[0041] Solve the above equation using logical operations:

[0042] From equation 2, we can directly deduce that data[1]=1;

[0043] From equation 3, we can directly deduce that data[2]=1;

[0044] Substitute data[2]=1 into equation 1: 0 =1^data[0]→data[0]=1 (because 1^1=0).

[0045] The correct values ​​for the final error bits are: data[0]=1, data[1]=1, data[2]=1.

[0046] It should be noted that the more error bits there are, the more equations are needed to solve the problem, but the number of equations cannot exceed the number of bits in the ECC.

[0047] S105, Replace the correct data with the corresponding position based on the location information to correct the error.

[0048] As an example, replace the incorrect 3'bxxx with the correct 3'b111.

[0049] In summary, since the error location is known, this application utilizes the reverse process of ECC encoding to deduce the correct value of the error bit from the known ECC value and encoding rules. Relying on the linearity of XOR operation, it has the advantages of fast operation speed, no need for additional storage, efficient correction of multi-bit errors, and no increase in the number of ECC bits.

[0050] To implement the above embodiments, this application also proposes a memory data read error correction device based on logical operations, such as... Figure 3 As shown, it includes: an error detection module 10 and an error correction module 20.

[0051] The error detection module 10 is used to perform anomaly detection on each storage cell in the storage array to determine the number and location information of data read errors based on the detection results. The error correction module 20 is used to XOR all read data bits according to the encoding rules of the ECC encoder to obtain the encoding formula corresponding to each bit in the ECC value; extract the encoding formula including the erroneous data bits from the encoding formula corresponding to each bit in the ECC value according to the number and location information of data read errors; establish a system of linear equations using the pre-acquired correct ECC value and the extracted encoding formula including the erroneous data bits to solve the system of equations to obtain the correct value of the erroneous bit; and replace the correct data in the corresponding position according to the location information to perform error correction.

[0052] Furthermore, the error detection module 10 is also used to detect the cell current on each word line in the memory array; and compare the cell current on each word line with a preset reference current to determine whether the data read by the corresponding cell is abnormal.

[0053] Furthermore, the data of the correct data bits is kept unchanged when solving the system of equations.

[0054] Furthermore, the correct ECC value is obtained by XORing the correct data written using the ECC encoder's encoding rules.

[0055] It should be noted that the above description of the memory data read error correction method based on logic operations also applies to the memory data read error correction device based on logic operations, and will not be repeated here.

[0056] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0057] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0058] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0059] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0060] It should be noted that any reference signs placed between parentheses in the claims should not be construed as limiting the claims. The word "comprising" does not exclude the presence of components or steps not listed in the claims. The word "a" or "an" preceding a component does not exclude the presence of a plurality of such components. This application can be implemented by means of hardware comprising several different components and by means of a suitably programmed computer. In a unit claim enumerating several means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third, etc., does not indicate any order. These words can be interpreted as names.

[0061] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0062] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

[0063] In the description of this application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0064] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0065] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0066] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification should not be construed as necessarily referring to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0067] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A memory data read error correction method based on logical operations, characterized in that, The method includes: Anomaly detection is performed on each storage cell in the storage array to determine the number of bits and location of data read errors based on the detection results; According to the encoding rules of the ECC encoder, all read data bits are XORed to obtain the encoding formula corresponding to each bit in the ECC value; Based on the data, read the number and location of the erroneous bits, and extract the encoding formula including the erroneous data bits from the encoding formula corresponding to each bit in the ECC value; A system of linear equations is established using the pre-obtained correct ECC value and the extracted encoding formula including the erroneous data bits, and the correct value of the erroneous bits is obtained by solving the system of equations. The correct value is replaced with the corresponding position based on the location information to correct the error. This includes anomaly detection for each storage cell in the storage array, including: An error detection module is used to detect the cell current on each word line in the memory array; The cell current on each word line is compared with the preset reference current to determine whether the data read by the corresponding cell is abnormal. The correct ECC value is obtained by XORing the written correct data according to the encoding rules of the ECC encoder.

2. The memory data read error correction method based on logical operations according to claim 1, characterized in that, When solving a system of equations, the data in the correct data bits is kept unchanged.

3. A memory data read error correction device based on logical operations, characterized in that, include: The error detection module is used to perform anomaly detection on each storage cell in the storage array, so as to determine the number of bits and location information of data read errors based on the detection results; The error correction module is used to XOR all read data bits according to the encoding rules of the ECC encoder to obtain the encoding formula corresponding to each bit in the ECC value; extract the encoding formula including the erroneous data bits from the encoding formula corresponding to each bit in the ECC value according to the number and location information of the erroneous bits read from the data; establish a system of linear equations using the pre-acquired correct ECC value and the extracted encoding formula including the erroneous data bits, and solve the system of equations to obtain the correct value of the erroneous bit; The correct value is replaced with the corresponding position based on the location information to correct the error. The error detection module is also used to detect the cell current on each word line in the memory array; and to compare the cell current on each word line with a preset reference current to determine whether the data read from the corresponding cell is abnormal. The correct ECC value is obtained by XORing the written correct data according to the encoding rules of the ECC encoder.

4. The memory data read error correction device based on logical operations according to claim 3, characterized in that, When solving a system of equations, the data in the correct data bits is kept unchanged.

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