A high-speed analog-to-digital converter input drive circuit with overvoltage protection

Abstract

This invention provides a high-speed analog-to-digital converter (ADC) input drive circuit with overvoltage protection, belonging to the technical field of ADC drive circuits. It includes a power-on overvoltage protection circuit, a boost circuit, and a voltage buffer main circuit. The voltage buffer main circuit enhances the broadband signal performance of the ADC. The power-on overvoltage protection circuit is connected to multiple nodes in the voltage buffer main circuit to provide power-on and power-off overvoltage protection for the voltage buffer. The boost circuit is connected to the input signal terminal of the voltage buffer main circuit, ensuring that the gate voltage of the MOSFETs in the voltage buffer main circuit follows the input signal, and no clock is set at the boost circuit. Power-on and power-off of the power-on overvoltage protection circuit and multiple nodes in the voltage buffer main circuit are performed according to a timing sequence to ensure that the voltage across the voltage buffer main circuit does not exceed its withstand voltage. This invention achieves low power consumption while improving performance, and provides complete power-on and power-off overvoltage protection.

Description

Technical Field

[0001] This invention relates to the field of analog-to-digital converter (ADC) driver circuit technology, and more specifically, to a high-speed ADC input driver circuit with overvoltage protection. Background Technology

[0002] An analog-to-digital converter (ADC) is a component used in electronic applications to convert analog input signals into digital output signals so that further digital signal processing or storage can be achieved.

[0003] Analog-to-digital converters (ADCs) are widely used in communication systems, transmitter systems, and receiver systems. Various application scenarios have different requirements regarding performance, power consumption, cost, and size. With the development of electronic technology, the bandwidth of systems such as radar and communication is constantly increasing, signal bandwidth is continuously improving, and modulation modes are becoming more complex, placing higher demands on the speed and accuracy of ADCs. The input drive circuit, as a crucial component of the ADC, is a prerequisite for ensuring the broadband signal performance of the ADC. The performance of the input drive circuit directly determines the upper limit of the ADC's performance. In addition, the input drive circuit also provides isolation between the ADC and external circuits, avoiding oscillations during sampling caused by parasitics introduced by packaging, etc. Existing technologies generally reduce nonlinear distortion caused by channel modulation effects and substrate bias effects by increasing gm. However, SFDR deteriorates sharply under high-frequency input signals. If existing technologies were to counteract this effect, it would increase system complexity and consume signal swing space, making it unsuitable for ADCs with large input swings. Furthermore, there is the problem of electrical components being easily damaged by overvoltage during power-on and power-off.

[0004] Therefore, it is urgent to optimize the input drive circuit to achieve low power consumption while improving performance, and at the same time provide complete power-on and power-off overvoltage protection functions. Summary of the Invention

[0005] The purpose of this invention is to provide a high-speed analog-to-digital converter input drive circuit with overvoltage protection, which can maintain low power consumption while improving performance, and at the same time provide complete power-on and power-off overvoltage protection functions.

[0006] This invention is achieved through the following technical solution:

[0007] A high-speed analog-to-digital converter input drive circuit with overvoltage protection includes a power-on overvoltage protection circuit, a boost circuit, and a voltage buffer main circuit.

[0008] The voltage buffer main circuit is used to improve the broadband signal performance of the analog-to-digital converter.

[0009] The power-on overvoltage protection circuit is connected to multiple nodes in the main circuit of the voltage buffer to realize power-on and power-off overvoltage protection for the voltage buffer.

[0010] The boost circuit is connected to the input signal terminal of the main circuit of the voltage buffer, so that the gate voltage of the MOSFET in the main circuit of the voltage buffer follows the input signal, and no clock is set at the boost circuit.

[0011] The power-on overvoltage protection circuit and multiple nodes of the main circuit of the voltage buffer are powered on and off in a sequential manner to ensure that the voltage borne by the main circuit of the voltage buffer does not exceed the withstand voltage.

[0012] Preferably, the main circuit of the voltage buffer includes multiple MOSFETs;

[0013] The source of the second MOSFET is connected to the power-on overvoltage protection circuit, the drain of the second MOSFET is connected to the drain of the third MOSFET, and the gate of the second MOSFET is connected to the power-on overvoltage protection circuit.

[0014] The source of the third MOSFET is connected to the drain of the fourth MOSFET and serves as the output signal terminal, while the gate of the third MOSFET serves as the input signal terminal.

[0015] The source of the fourth MOSFET is connected to the drain of the fifth MOSFET, and the gate of the fourth MOSFET is connected to the power-on overvoltage protection circuit and connected to the first power supply through the first current source.

[0016] The gate of the fifth MOSFET is connected to the power-on overvoltage protection circuit, and the source of the fifth MOSFET is grounded.

[0017] Preferably, in the main circuit of the voltage buffer, the second MOSFET is a PMOS and the other MOSFETs are NMOS.

[0018] Preferably, the power-on overvoltage protection circuit includes multiple MOSFETs;

[0019] The source of the first MOSFET is connected to the first power supply, and the drain of the first MOSFET is connected to the source of the second MOSFET.

[0020] The gate of the second MOSFET is connected to the drain of the sixth MOSFET, the source of the sixth MOSFET is connected to the second bias voltage node, and the gate of the sixth MOSFET is connected to the gate of the ninth MOSFET.

[0021] The drain of the seventh MOSFET is connected to the common-mode voltage, the source of the seventh MOSFET is connected to the first terminal of the second resistor, the second terminal of the second resistor is connected to the gate of the third MOSFET and the first terminal of the second capacitor, and the second terminal of the second capacitor is connected to the gate of the twelfth MOSFET.

[0022] The source of the eighth MOSFET is connected to the drain of the second MOSFET, and the drain of the eighth MOSFET is connected to the second bias voltage node.

[0023] The source of the ninth MOSFET is connected to the source of the third MOSFET, the gate of the ninth MOSFET is connected to the gate of the eighth MOSFET, and the drain of the ninth MOSFET is connected to the second bias voltage node.

[0024] The drain of the tenth MOSFET is connected to the gate of the fourth MOSFET, and the source of the tenth MOSFET is connected to the second power supply.

[0025] The source of the eleventh MOSFET is connected to the source of the fourth MOSFET, and the drain of the eleventh MOSFET is connected to the fourth bias voltage node.

[0026] The drain of the twelfth MOSFET is connected to the gate of the fourth MOSFET, the source of the twelfth MOSFET is grounded, and the gate of the twelfth MOSFET is connected to the source of the fourth MOSFET.

[0027] The source of the thirteenth MOSFET and the drain of the fifteenth MOSFET are connected to the gate of the fifth MOSFET. The drain of the thirteenth MOSFET is connected to the gate and drain of the fourteenth MOSFET. The source of the fourteenth MOSFET and the source of the fifteenth MOSFET are grounded. The gate of the fifteenth MOSFET is connected to the gate of the eighth MOSFET. The drain of the fourteenth MOSFET is connected to the gate of the sixth power-on overvoltage protection circuit and is connected to the first power supply through the second current source.

[0028] Preferably, in the power-on overvoltage protection circuit, the first MOSFET is a PMOS and the other MOSFETs are NMOS.

[0029] Preferably, the voltage of the first power supply is greater than the voltage of the second power supply, and the voltage of the second power supply is the withstand voltage limit of the MOSFET in the main circuit of the voltage buffer.

[0030] Preferably, when multiple nodes are powered on and off in sequence, the multiple nodes include the gate of the eighth MOSFET, the gate of the thirteenth MOSFET, the gate of the first MOSFET, and the gate of the eleventh MOSFET, and are sequentially referred to as the first power-on / off node, the second power-on / off node, the third power-on / off node, and the fourth power-on / off node.

[0031] Preferably, the method for powering on and off multiple nodes according to a timing sequence is as follows:

[0032] The first power-on / off node alternates between power-on and power-off according to a period T, and the third power-on / off node alternates between power-on and power-off according to a period T with a delay t relative to the first power-on / off node.

[0033] The second power-on / off node alternates between power-on and power-off according to a period T, and the fourth power-on / off node alternates between power-on and power-off according to a period T with a delay t relative to the second power-on / off node.

[0034] The power-on and power-off actions of the first and second power-on / off nodes are opposite.

[0035] Preferably, the boost circuit includes a first resistor and a first capacitor;

[0036] The first end of the first resistor is connected to the first bias voltage node, the second end of the first resistor is connected to the first end of the first capacitor and the gate of the second MOSFET, and the second end of the first capacitor is connected to the gate of the third MOSFET.

[0037] The technical solution of the present invention has at least the following advantages and beneficial effects:

[0038] This invention incorporates a power-on overvoltage protection circuit, which ensures that the voltage of electrical components in the main circuit of the voltage buffer does not exceed the specified range during power-on and power-off processes. This ensures circuit safety, helps improve circuit lifespan and reliability, and enables more stable and high-quality operation.

[0039] This invention ensures that the voltage during the power-on process does not exceed the withstand voltage of the electrical components in the main circuit of the voltage buffer by using the power-on and power-off sequence of multiple nodes. Compared with the traditional solution, it changes from passive protection to active prevention, which has higher reliability.

[0040] The boost circuit of this invention features an electrical component in the main circuit of a voltage buffer whose voltage follows the input signal. Compared with traditional switched capacitor boost circuits, this circuit does not require a clock, which reduces the complexity of the circuit.

[0041] This invention, by setting up a voltage buffer main circuit in conjunction with a boost circuit and a power-on overvoltage protection circuit, can ensure high-speed operation while suppressing signal distortion under low power consumption, thereby improving the linearity and signal fidelity of the analog-to-digital converter in high-bandwidth, high-speed input scenarios. Attached Figure Description

[0042] Figure 1 A schematic diagram of the circuit structure of the input drive circuit of the high-speed analog-to-digital converter with overvoltage protection provided in an embodiment of the present invention;

[0043] Figure 2 A timing diagram illustrating power-on and power-off provided for embodiments of the present invention;

[0044] Icons: 1-First MOSFET, 2-Second MOSFET, 3-Third MOSFET, 4-Fourth MOSFET, 5-Fifth MOSFET, 6-Sixth MOSFET, 7-Seventh MOSFET, 8-Eighth MOSFET, 9-Ninth MOSFET, 10-Tenth MOSFET, 11-Eleventh MOSFET, 12-Twelfth MOSFET, 13-Thirteenth MOSFET, 14-Fourteenth MOSFET, 15-Fifteenth MOSFET, 16-First Resistor, 17-First Capacitor, 18-Second Resistor, 19-Second Capacitor, 20-First Current Source, 21-Second Current Source, 31-First Power-On / Off Node, 32-Second Power-On / Off Node, 33-Third Power-On / Off Node, 34-Fourth Power-On / Off Node, VB1-First Bias Voltage Node, VB2-Second Bias Voltage Node, VB4-Fourth Bias Voltage Node, VDD1-First Power Supply, VDD2-Second Power Supply, VIN-Input Signal Terminal, VOUT-Output Signal Terminal, VCM-Common Mode Voltage. Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0046] Example

[0047] This embodiment provides a high-speed analog-to-digital converter input drive circuit with overvoltage protection. (See attached document.) Figure 1 It includes a power-on overvoltage protection circuit, a boost circuit, and a voltage buffer main circuit.

[0048] The voltage buffer main circuit is used to improve the broadband signal performance of the analog-to-digital converter.

[0049] In this embodiment, the main circuit of the voltage buffer includes multiple MOSFETs; in this embodiment, the main circuit of the voltage buffer is formed by connecting multiple MOSFETs in series.

[0050] The source of the second MOSFET 2 is connected to the power-on overvoltage protection circuit, the drain of the second MOSFET 2 is connected to the drain of the third MOSFET 3, and the gate of the second MOSFET 2 is connected to the power-on overvoltage protection circuit.

[0051] The source of the third MOSFET 3 is connected to the drain of the fourth MOSFET 4 and is the output signal terminal VOUT. The gate of the third MOSFET 3 is the input signal terminal VIN.

[0052] The source of the fourth MOSFET 4 is connected to the drain of the fifth MOSFET 5, and the gate of the fourth MOSFET 4 is connected to the power-on overvoltage protection circuit and connected to the first power supply VDD1 through the first current source 21.

[0053] The gate of the fifth MOSFET 5 is connected to the power-on overvoltage protection circuit, and the source of the fifth MOSFET 5 is grounded.

[0054] With the above structure, the various MOSFETs work together to achieve a stable output between the input and output terminals. During power-on and power-off processes, the overvoltage protection circuit ensures the safe operation of the devices, effectively avoiding overvoltage damage and significantly improving the safety and reliability of the circuit.

[0055] As a further embodiment, in the main circuit of the voltage buffer, the second MOSFET 2 is a PMOS, and the other MOSFETs are NMOS.

[0056] The power-on overvoltage protection circuit is connected to multiple nodes in the main circuit of the voltage buffer to provide power-on and power-off overvoltage protection for the voltage buffer.

[0057] As a preferred embodiment, the power-on overvoltage protection circuit includes multiple MOSFETs;

[0058] The source of the first MOSFET 1 is connected to the first power supply VDD1, and the drain of the first MOSFET 1 is connected to the source of the second MOSFET 2.

[0059] The gate of the second MOSFET 2 is connected to the drain of the sixth MOSFET 6, the source of the sixth MOSFET 6 is connected to the second bias voltage node VB2, and the gate of the sixth MOSFET 6 is connected to the gate of the ninth MOSFET 9.

[0060] The drain of the seventh MOSFET 7 is connected to the common-mode voltage VCM, the source of the seventh MOSFET 7 is connected to the first terminal of the second resistor 18, the second terminal of the second resistor 18 is connected to the gate of the third MOSFET 3 and the first terminal of the second capacitor 19, and the second terminal of the second capacitor 19 is connected to the gate of the twelfth MOSFET 12.

[0061] The source of the eighth MOSFET 8 is connected to the drain of the second MOSFET 2, and the drain of the eighth MOSFET 8 is connected to the second bias voltage node VB2.

[0062] The source of the ninth MOSFET 9 is connected to the source of the third MOSFET 3, the gate of the ninth MOSFET 9 is connected to the gate of the eighth MOSFET 8, and the drain of the ninth MOSFET 9 is connected to the second bias voltage node VB2.

[0063] The drain of the tenth MOSFET 10 is connected to the gate of the fourth MOSFET 4, and the source of the tenth MOSFET 10 is connected to the second power supply VDD2.

[0064] The source of the eleventh MOSFET 11 is connected to the source of the fourth MOSFET 4, and the drain of the eleventh MOSFET 11 is connected to the fourth bias voltage node VB4.

[0065] The drain of the twelfth MOSFET 12 is connected to the gate of the fourth MOSFET 4, the source of the twelfth MOSFET 12 is grounded, and the gate of the twelfth MOSFET 12 is connected to the source of the fourth MOSFET 4.

[0066] The source of the thirteenth MOSFET 13 and the drain of the fifteenth MOSFET 15 are connected to the gate of the fifth MOSFET 5. The drain of the thirteenth MOSFET 13 is connected to the gate and drain of the fourteenth MOSFET 14. The source of the fourteenth MOSFET 14 and the source of the fifteenth MOSFET 15 are grounded. The gate of the fifteenth MOSFET 15 is connected to the gate of the eighth MOSFET 8. The drain of the fourteenth MOSFET 14 is connected to the gate of the sixth power-on overvoltage protection circuit and is connected to the first power supply VDD1 through the second current source 21.

[0067] The gate of the seventh MOSFET 7 is connected to a power-on indicator signal. Upon completion of power-on, the connection between the second resistor 18 and the common-mode voltage VCM is severed. Subsequently, the sixth MOSFET 6, the eighth MOSFET 8 through the fifteenth MOSFET 15 are sequentially turned off through the four-way power-on sequence on nodes 31-34. The sixth MOSFET 6 through the fifteenth MOSFET 15 act as a protection circuit for the second MOSFET 2 through the fifth MOSFET 5, ensuring that the voltage of the second MOSFET 2 through the fifth MOSFET 5 does not exceed the withstand voltage during power-on.

[0068] Based on this, in the power-on overvoltage protection circuit, the first MOSFET 1 is a PMOS, and the other MOSFETs are NMOS.

[0069] On the other hand, the boost circuit is connected to the input signal terminal VIN of the main circuit of the voltage buffer, so that the gate voltage of the MOSFET in the main circuit of the voltage buffer follows the input signal, and no clock is set at the boost circuit.

[0070] The boost circuit preferably includes a first resistor 16 and a first capacitor 17;

[0071] The first end of the first resistor 16 is connected to the first bias voltage node VB1, the second end of the first resistor 16 is connected to the first end of the first capacitor 17 and the gate of the second MOSFET 2, and the second end of the first capacitor 17 is connected to the gate of the third MOSFET 3.

[0072] Compared with the traditional switched capacitor boost circuit, the boost circuit in this embodiment does not require clock input, which reduces circuit complexity and ensures that the gate voltage of the second MOSFET 2 follows the input signal.

[0073] The power-on overvoltage protection circuit and multiple nodes of the main circuit of the voltage buffer are powered on and off in a sequential manner to ensure that the voltage borne by the main circuit of the voltage buffer does not exceed the withstand voltage.

[0074] Specifically, see Figure 2 The method for powering on and off multiple nodes according to a timing sequence is as follows:

[0075] Multiple nodes include the gate of the eighth MOSFET 8, the gate of the thirteenth MOSFET 13, the gate of the first MOSFET 1, and the gate of the eleventh MOSFET 11, and are sequentially referred to as the first power-on / off node 31, the second power-on / off node 32, the third power-on / off node 33, and the fourth power-on / off node 34.

[0076] The first power-on / off node 31 alternates between power-on and power-off according to a period T, and the third power-on / off node 33 alternates between power-on and power-off according to a period T, with a delay t relative to the first power-on / off node 31.

[0077] The second power-on / off node 32 alternates between power-on and power-off according to a period T, and the fourth power-on / off node 34 alternates between power-on and power-off according to a period T, with a delay t relative to the second power-on / off node 32.

[0078] The power-on and power-off actions of the first power-on / off node 31 and the second power-on / off node 32 are opposite.

[0079] It should be noted that in this embodiment, the voltage of the first power supply VDD1 is greater than the voltage of the second power supply VDD2, and the voltage of the second power supply VDD2 is the withstand voltage limit of the MOSFET in the main circuit of the voltage buffer. During the power-on process of the first power supply VDD1, which is a high-voltage power supply, the MOSFET in the main circuit of the voltage buffer may be damaged. In order to ensure the normal operation of the above circuit, multiple MOSFETs are used as a power-on overvoltage protection circuit, and the power-on timing of multiple nodes is used to ensure that the MOSFET in the main circuit of the voltage buffer does not exceed its withstand voltage during the power-on process.

[0080] Based on the solution of this embodiment, the second capacitor 19 and... Figure 1 The load driven by node 38 is kept consistent to improve linearity. On one hand, the AC current generated by the input signal through the second capacitor 19 directly charges the output node 38 via the fourth MOSFET 4, thus partially offsetting the AC current variation of the input transistor and helping the third MOSFET 3 maintain a stable gm. On the other hand, the twelfth MOSFET 12 acts as a feedback transistor to stabilize the voltage of the feedforward capacitor, i.e., the second capacitor 19, ensuring a linear relationship between the generated input AC current and the output AC current. The first resistor 16 and the first capacitor 17 form another AC path connected to the input port. Depending on their resistance and capacitance values, the gate voltage of the second MOSFET 2 can follow the input signal at a certain frequency, reducing the voltage variation range of the third MOSFET 3 and improving the linearity of the output signal.

[0081] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A high-speed analog-to-digital converter input drive circuit with overvoltage protection, characterized in that, Includes power-on overvoltage protection circuit, boost circuit and voltage buffer main circuit; The voltage buffer main circuit is used to improve the broadband signal performance of the analog-to-digital converter. The power-on overvoltage protection circuit is connected to multiple nodes in the main circuit of the voltage buffer to realize power-on and power-off overvoltage protection for the voltage buffer. The boost circuit is connected to the input signal terminal of the main circuit of the voltage buffer, so that the gate voltage of the MOSFET in the main circuit of the voltage buffer follows the input signal, and no clock is set at the boost circuit. The power-on overvoltage protection circuit and multiple nodes of the main circuit of the voltage buffer are powered on and off in a timing sequence to ensure that the voltage borne by the main circuit of the voltage buffer does not exceed the withstand voltage. The main circuit of the voltage buffer includes multiple MOSFETs; The source of the second MOSFET is connected to the power-on overvoltage protection circuit, the drain of the second MOSFET is connected to the drain of the third MOSFET, and the gate of the second MOSFET is connected to the power-on overvoltage protection circuit. The source of the third MOSFET is connected to the drain of the fourth MOSFET and serves as the output signal terminal, while the gate of the third MOSFET serves as the input signal terminal. The source of the fourth MOSFET is connected to the drain of the fifth MOSFET, and the gate of the fourth MOSFET is connected to the power-on overvoltage protection circuit and connected to the first power supply through the first current source. The gate of the fifth MOSFET is connected to the power-on overvoltage protection circuit, and the source of the fifth MOSFET is grounded. The power-on overvoltage protection circuit includes multiple MOSFETs; The source of the first MOSFET is connected to the first power supply, and the drain of the first MOSFET is connected to the source of the second MOSFET. The gate of the second MOSFET is connected to the drain of the sixth MOSFET, the source of the sixth MOSFET is connected to the second bias voltage node, and the gate of the sixth MOSFET is connected to the gate of the ninth MOSFET. The drain of the seventh MOSFET is connected to the common-mode voltage, the source of the seventh MOSFET is connected to the first terminal of the second resistor, the second terminal of the second resistor is connected to the gate of the third MOSFET and the first terminal of the second capacitor, and the second terminal of the second capacitor is connected to the gate of the twelfth MOSFET. The source of the eighth MOSFET is connected to the drain of the second MOSFET, and the drain of the eighth MOSFET is connected to the second bias voltage node. The source of the ninth MOSFET is connected to the source of the third MOSFET, the gate of the ninth MOSFET is connected to the gate of the eighth MOSFET, and the drain of the ninth MOSFET is connected to the second bias voltage node. The drain of the tenth MOSFET is connected to the gate of the fourth MOSFET, and the source of the tenth MOSFET is connected to the second power supply. The source of the eleventh MOSFET is connected to the source of the fourth MOSFET, and the drain of the eleventh MOSFET is connected to the fourth bias voltage node. The drain of the twelfth MOSFET is connected to the gate of the fourth MOSFET, the source of the twelfth MOSFET is grounded, and the gate of the twelfth MOSFET is connected to the source of the fourth MOSFET. The source of the thirteenth MOSFET and the drain of the fifteenth MOSFET are connected to the gate of the fifth MOSFET. The drain of the thirteenth MOSFET is connected to the gate and drain of the fourteenth MOSFET. The source of the fourteenth MOSFET and the source of the fifteenth MOSFET are grounded. The gate of the fifteenth MOSFET is connected to the gate of the eighth MOSFET. The drain of the fourteenth MOSFET is connected to the gate of the fourteenth MOSFET and is connected to the first power supply through the second current source. When multiple nodes are powered on and off in sequence, the multiple nodes include the gate of the eighth MOSFET, the gate of the thirteenth MOSFET, the gate of the first MOSFET, and the gate of the eleventh MOSFET, and are sequentially referred to as the first power-on / off node, the second power-on / off node, the third power-on / off node, and the fourth power-on / off node. The method for powering on and off multiple nodes according to a timing sequence is as follows: The first power-on / off node alternates between power-on and power-off according to a period T, and the third power-on / off node alternates between power-on and power-off according to a period T with a delay t relative to the first power-on / off node. The second power-on / off node alternates between power-on and power-off according to a period T, and the fourth power-on / off node alternates between power-on and power-off according to a period T with a delay t relative to the second power-on / off node. The power-on and power-off actions of the first and second power-on / off nodes are opposite.

2. The high-speed analog-to-digital converter input drive circuit with overvoltage protection according to claim 1, characterized in that, In the main circuit of the voltage buffer, the second MOSFET is a PMOS, and the other MOSFETs are NMOS.

3. The high-speed analog-to-digital converter input drive circuit with overvoltage protection according to claim 1, characterized in that, In the power-on overvoltage protection circuit, the first MOSFET is a PMOS, and the other MOSFETs are NMOS.

4. The high-speed analog-to-digital converter input drive circuit with overvoltage protection according to claim 1, characterized in that, The voltage of the first power supply is greater than the voltage of the second power supply, and the voltage of the second power supply is the withstand voltage limit of the MOSFET in the main circuit of the voltage buffer.

5. The high-speed analog-to-digital converter input drive circuit with overvoltage protection according to claim 1, characterized in that, The boost circuit includes a first resistor and a first capacitor; The first end of the first resistor is connected to the first bias voltage node, the second end of the first resistor is connected to the first end of the first capacitor and the gate of the second MOSFET, and the second end of the first capacitor is connected to the gate of the third MOSFET.

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