Core layer multi-layer wiring embedded substrate and manufacturing method thereof

Abstract

The invention provides a core layer multi-layer wiring embedded substrate and a manufacturing method. Specifically, a barrier layer is formed while a first circuit layer is formed on a core layer, and then a second dielectric layer covering the first circuit layer is formed on the core layer, so that a blind slot with the barrier layer as the bottom can be formed on the second dielectric layer through opening, and then a component can be embedded in the blind slot without additionally manufacturing an embedded frame. And the alignment error problem of the embedded frame and the core plate is avoided. In addition, a second circuit layer can be arranged on the second dielectric layer, the wiring density in the direction perpendicular to the embedded substrate is increased, and the overall wiring density of the embedded substrate can be further improved.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor packaging, and particularly relates to a core layer multi-layer wiring embedded substrate and a manufacturing method. BACKGROUND

[0002] The embedded substrate technology realizes high integration of system-level packaging by integrating passive components and active devices inside the substrate, so that the device volume can be significantly reduced. With the rapid development of the artificial intelligence (AI), 5G communication, intelligent terminal, new energy vehicle and other industries, the market demand for high-density and high-performance integrated circuits is showing explosive growth, which further highlights the strategic value of the embedded substrate technology. In the related art, the embedded substrate still has deficiencies in helping electronic devices to continuously evolve towards miniaturization, high performance and high reliability. SUMMARY

[0003] Therefore, the purpose of the present disclosure is to provide a core layer multi-layer wiring embedded substrate and a manufacturing method.

[0004] To achieve the above purpose, in a first aspect, the present disclosure provides a manufacturing method of a core layer multi-layer wiring embedded substrate, comprising: (a) providing a core layer; wherein the core layer comprises a first dielectric layer; (b) forming a first wiring layer on the first dielectric layer; wherein the first wiring layer comprises a barrier layer; (c) forming a second dielectric layer and a second wiring layer on the first dielectric layer; wherein the second dielectric layer covers the first wiring layer; (d) forming a blind groove in the second dielectric layer with the barrier layer as the bottom; (e) pressing an uncured third dielectric layer on the second dielectric layer, so that the third dielectric layer is pressed to fill the blind groove of the second dielectric layer; (f) attaching a component on the surface of the third dielectric layer; (g) pressing the component into the blind groove; (h) pressing a fourth dielectric layer on the surface of the third dielectric layer, and curing or semi-curing the third dielectric layer and the fourth dielectric layer; (i) forming a through hole penetrating through the first dielectric layer, the second dielectric layer, the third dielectric layer and the fourth dielectric layer, and forming a blind hole exposing the terminal of the component by windowing on the fourth dielectric layer; (j) electroplating the through hole and the blind hole to form a through hole column and a terminal pad, and forming a third circuit layer on the fourth dielectric layer; wherein the third circuit layer is in conductive connection with the terminal of the component; the through hole column is in conductive connection with the third circuit layer on both sides of the first dielectric layer.

[0005] In some embodiments, further comprising: (k) forming an outer dielectric layer on the fourth dielectric layer, covering the third circuit layer; (l) forming an outer circuit layer on the outer dielectric layer; wherein the outer circuit layer is in conductive connection with its closest third circuit layer, respectively.

[0006] In some embodiments, the material of the first dielectric layer and the second dielectric layer is a resin material containing glass fiber; and / or the material of the third dielectric layer and the fourth dielectric layer is a resin material not containing glass fiber; and / or the third dielectric layer is a resin material with adhesion; and / or the material of the third dielectric layer and the fourth dielectric layer is the same or different.

[0007] In some embodiments, the thickness of the second dielectric layer is not less than the thickness of the component; or the total thickness of the second dielectric layer and the third dielectric layer is not less than the thickness of the component.

[0008] In some embodiments, step (g) uses a vacuum hot pressing process.

[0009] In some embodiments, step (c) comprises: (c1) applying a second dielectric layer and a copper foil on the first dielectric layer; wherein the second dielectric layer covers the first circuit layer; (c2) etching the copper foil to obtain the second circuit layer.

[0010] In some embodiments, the second circuit layer includes a target; before step (f), further comprising: laser irradiating the third dielectric layer to expose the target.

[0011] In a second aspect, the embodiments of the present disclosure further provide a core layer multi-layer wiring embedded substrate, comprising: a core layer, a fourth dielectric layer on the upper and lower surfaces of the core layer, and a third circuit layer on the fourth dielectric layer; wherein, The core layer comprises: a first dielectric layer; a first circuit layer on the upper and lower surfaces of the first dielectric layer, the first circuit layer comprising a barrier layer; a second dielectric layer on the first circuit layer, the second dielectric layer having a blind groove with the barrier layer as the bottom; a third dielectric layer on the second dielectric layer; a component embedded in the blind groove, wherein the gap between the component and the second dielectric layer is filled with the third dielectric layer, wherein the back surface of the component is not in direct contact with the barrier layer, and the terminals of the component face upward; The fourth dielectric layer is located on the third dielectric layer, and the third circuit layer is conductively connected to the terminals of the component. The embedded substrate further comprises a via pillar penetrating through the first dielectric layer, the second dielectric layer, the third dielectric layer, and the fourth dielectric layer, wherein the via pillar is conductively connected to the third circuit layers located on both sides of the first dielectric layer.

[0012] In some embodiments, an outer dielectric layer and an outer circuit layer are further included on the third circuit layer; wherein, The outer dielectric layer and the outer circuit layer are respectively symmetrically arranged with respect to the core layer; wherein, each of the outer circuit layers is respectively conductively connected to the closest third circuit layer.

[0013] In some embodiments, the thickness of the second dielectric layer is not less than the thickness of the component; or The total thickness of the second dielectric layer and the third dielectric layer is not less than the thickness of the component.

[0014] In some embodiments, the materials of the first dielectric layer and the second dielectric layer are resin materials containing glass fibers; and / or The materials of the third dielectric layer and the fourth dielectric layer are resin materials not containing glass fibers; and / or The third dielectric layer is a resin material with adhesion; and / or The materials of the third dielectric layer and the fourth dielectric layer are the same or different.

[0015] In some embodiments, the second circuit layer comprises a target.

[0016] As can be seen from the above, the core layer multilayer wiring embedded substrate and manufacturing method provided by the embodiments of the present disclosure form the blocking layer at the same time of forming the first circuit layer on the core layer, then form the second dielectric layer covering the first circuit layer on the core layer, so that the blind groove with the blocking layer as the bottom can be formed on the second dielectric layer through the opening, and then the components and devices can be embedded in the blind groove, without the need of additionally manufacturing the embedding frame, avoiding the alignment error problem of the embedding frame and the core plate. In addition, the second circuit layer can be arranged on the second dielectric layer, increasing the wiring density in the vertical embedded substrate direction, which is helpful to further improve the overall wiring density of the embedded substrate. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the present disclosure or the related art, the drawings needed to be used in the embodiments or the related art description will be briefly introduced. Obviously, the drawings in the following description are only embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0018] Figure 1 A structure schematic diagram of an embedded substrate provided by the related art is shown. FIG. 2(a) to FIG. 2(r) show cross-sectional schematic diagrams of intermediate structures of each step of a manufacturing method of an embedded substrate provided by the embodiments of the present disclosure. Figure 3 A structure schematic diagram of an embedded substrate provided by the embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical solutions and advantages of the present disclosure more clear, the present disclosure will be further described in detail below in combination with specific embodiments and with reference to the drawings.

[0020] It should be noted that the technical terms or scientific terms used in the embodiments of the present disclosure should be understood as the general meaning understood by those skilled in the art to which the embodiments of the present disclosure belong, unless otherwise defined. The terms "first", "second", and similar terms used in the embodiments of the present disclosure do not represent any order, number, or importance, but are only used to distinguish different components. The terms "include", "contain", and similar terms mean that the elements or objects before the terms cover the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects. The terms "connect" or "connected" and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms "upper", "lower", "left", "right", and the like only represent relative positional relationships, which can change accordingly when the absolute position of the described object changes. In the drawings, the thickness and shape of some layers and regions can be exaggerated for better understanding and ease of description.

[0021] Figure 1 A structure diagram of an embedded substrate provided by the related art is shown. As shown in Figure 1 The core layer 800' includes an embedded frame 401'. No wiring layer is arranged in the embedded frame 401', which leads to insufficient utilization of vertical wiring and is not conducive to high-density integration. In addition, the embedded frame 401' needs to be accurately aligned with the core layer 100', which is difficult to manufacture.

[0022] Therefore, the embodiments of the present disclosure provide a core layer multi-layer wiring embedded substrate and a manufacturing method. The first wiring layer and the barrier layer are formed on the core layer at the same time, and then the second dielectric layer covering the first wiring layer is formed on the core layer, so that the blind groove with the barrier layer as the bottom can be formed on the second dielectric layer by opening, and then the components can be embedded in the blind groove, without the need for additional manufacturing of the embedded frame, avoiding the alignment error problem of the embedded frame and the core plate. In addition, the second wiring layer can be arranged on the second dielectric layer, which increases the wiring density in the vertical direction of the embedded substrate, which helps to further improve the overall wiring density of the embedded substrate.

[0023] In a first aspect, the embodiments of the present disclosure provide a manufacturing method of a core layer multi-layer wiring embedded substrate. FIGS. 2(a)-2(l) show cross-sectional schematic diagrams of intermediate structures of each step of the manufacturing method of the embedded substrate provided by the embodiments of the present disclosure. As shown in FIGS. 2(a)-2(l), the manufacturing method includes: First, a core layer 100 is provided - step (a), as shown in FIG. 2(a).

[0024] Optionally, the core layer 100 includes a first dielectric layer 101 and first copper foils 102a, 102b. It should be understood that the first dielectric layer 101 can include a first surface A and a second surface B oppositely arranged. Exemplarily, the first surface A is attached with the copper foil 102a; the second surface B is attached with the copper foil 102b.

[0025] Optionally, the material of the first dielectric layer 101 is a resin material containing glass fiber, for example, selected from one of the group consisting of liquid crystal polymer, BT (bismaleimide triazine) resin, Prepreg, ABF (Ajinomoto Build-up) film, epoxy resin, and polyimide resin, without limitation to the present disclosure.

[0026] It should be noted that, without special instructions, the structures and components with the letter "a" in the reference signs are located on the first surface A; the structures and components with the letter "b" are located on the second surface B.

[0027] Next, the first dielectric layer 101 is formed on the first circuit layer 103a, 103b—step (b), as shown in FIG. 2(b). It should be noted that the first copper foils 102a, 102b can be used as seed layers for the manufacture of the first circuit layer 103a, 103b, which will not be described in detail.

[0028] In some embodiments, the first circuit layer 103a, 103b includes a barrier layer 1031a, 1031b.

[0029] Then, the second dielectric layer 201a, 201b and the second circuit layer 202a, 202b are formed on the first dielectric layer 101, and the second dielectric layer 201a, 201b covers the first circuit layer 103a, 103b—step (c), as shown in FIG. 2(c). Here, the second dielectric layer 201a, 201b can completely cover the surface of the first dielectric layer 101.

[0030] Optionally, the material of the second dielectric layer 201a, 201b is a resin material containing glass fiber. For the specific type of the resin material containing glass fiber, refer to the aforementioned first dielectric layer 101, which will not be described again.

[0031] In some embodiments, the thickness of the second dielectric layer 201a, 201b is not less than the thickness of the following components 401a, 401b.

[0032] In some embodiments, step (c) can include: (c1) applying a second dielectric layer 201a, 201b and a second copper foil on the first dielectric layer 101; wherein the second dielectric layer 201a, 201b covers the first circuit layer 103a, 103b; (c2) etching the second copper foil to obtain a second circuit layer 202a, 202b.

[0033] Such technical solutions directly utilize the second copper foil to form the second circuit layer 202a, 202b, omit the steps of forming a seed layer and electroplating thickening, and the process is simple.

[0034] Compared with the technical solutions in the related art in which the embedded frame cannot be provided with a circuit layer, the second circuit layer 202a, 202b is provided on the second dielectric layer 201a, 201b, so that the two sides of the second dielectric layer 201a, 201b can be provided with a circuit layer, which helps to improve the wiring density of the embedded substrate as a whole.

[0035] In some embodiments, referring to FIG. 2(f), the second circuit layer 202a, 202b includes a target 204a, 204b. Here, the target 204a, 204b can be used for component alignment.

[0036] Next, a blind groove 203a, 203b is formed in the second dielectric layer 201a, 201b with the barrier layer 1031a, 1031b as the bottom—step (d), as shown in FIG. 2(d).

[0037] Here, the blind groove 203a, 203b can be formed by laser drilling, at this time, the barrier layer 1031a, 1031b can block the laser energy to avoid damaging the first dielectric layer 101.

[0038] Then, the uncured third dielectric layer 301a is pressed on the second dielectric layer 201a, so that the third dielectric layer 301a is squeezed to fill the blind groove 203a of the second dielectric layer 201a—step (e), as shown in FIG. 2(e). It should be noted that at this time, the third dielectric layer 301a still remains in an uncured state.

[0039] Optionally, the material of the third dielectric layer 301a is a resin material with viscosity. Optionally, the material of the third dielectric layer 301a is a resin material without glass fiber.

[0040] In some embodiments, as shown in FIG. 2(f), the target 204a is exposed by laser irradiation of the third dielectric layer 301a.

[0041] Then, the component 401a is attached to the surface of the third dielectric layer 301a—step (f), as shown in FIG. 2(g).

[0042] It is to be noted that the component 401a, 401b can be an active component (e.g. transistor, IC chip, logic circuit component, power amplifier), a passive component (capacitor, inductor, resistor), or a combination thereof. The number of components attached is not limited to one, and the present disclosure does not limit the number of components attached.

[0043] In some alternative embodiments, the thickness of the second dielectric layer 201a can be less than the thickness of the component 401a; in this case, the total thickness of the second dielectric layer 201a and the third dielectric layer 301a is not less than the thickness of the component 401a.

[0044] Next, the component 401a is pressed into the blind slot 203a - step (g), as shown in FIG. 2(h).

[0045] For example, the component 401a is pressed into the blind slot 203a by vacuum hot pressing. The specific conditions for vacuum hot pressing can be selected as needed, and the present disclosure does not limit the specific conditions for vacuum hot pressing.

[0046] In this way, the blind slot 203a is formed without separately manufacturing an embedded frame and aligning the embedded frame and the core layer 100, thereby effectively avoiding the problem of alignment error between the embedded frame and the core layer 100, and enabling the components on both sides of the first dielectric layer 101 to be in a better symmetrical position.

[0047] Then, the fourth dielectric layer 501a is pressed onto the surface of the third dielectric layer 301a, and the third dielectric layer 301a and the fourth dielectric layer 501a are cured or semi-cured - step (h), as shown in FIG. 2(i).

[0048] In some embodiments, the material of the fourth dielectric layer 501a is a resin material without glass fiber. Here, the resin material can be selected from one of the group consisting of liquid crystal high molecular polymer, BT (bismaleimide triazine) resin, semi-cured prepreg, ABF (Ajinomoto Build-up) film, epoxy resin, and polyimide resin, and the present disclosure does not limit the material of the fourth dielectric layer 501a.

[0049] Optionally, the material of the fourth dielectric layer 501a is the same as or different from the material of the third dielectric layer 301a.

[0050] Next, the semi-cured third dielectric layer 301b is pressed onto the second dielectric layer 201b, so that the third dielectric layer 301b is squeezed to fill the blind slot 203b of the second dielectric layer 201b - step (e'), as shown in FIG. 2(j). It is to be noted that the third dielectric layer 301b is still in an uncured state at this time.

[0051] It should be noted that the third dielectric layer 301b has similar material as the third dielectric layer 301a, and thus will not be repeated.

[0052] In some embodiments, the laser exposes the target 204b through the third dielectric layer 301b, as shown in FIG. 2(k).

[0053] Then, the component 401b is attached to the surface of the third dielectric layer 301b, as shown in FIG. 2(l).

[0054] In some alternative embodiments, the thickness of the second dielectric layer 201b can be smaller than the thickness of the component 401b; in this case, the total thickness of the second dielectric layer 201b and the third dielectric layer 301b is not smaller than the thickness of the component 401b.

[0055] Next, the component 401b is pressed into the blind slot 203b, as shown in FIG. 2(m). The way of pressing the component 401b can be the same as that of pressing the component 401a, and thus will not be repeated.

[0056] Then, the fourth dielectric layer 501b is attached to the surface of the third dielectric layer 301b, and the third dielectric layer 301b and the fourth dielectric layer 501b are cured or semi-cured, as shown in FIG. 2(n). The material of the fourth dielectric layer 501b can be the same as that of the fourth dielectric layer 501a, and thus will not be repeated.

[0057] Optionally, the material of the fourth dielectric layer 501b can be the same as or different from that of the third dielectric layer 301b.

[0058] It should be noted that in the above embodiments, the steps (e)-(h) are performed on the first surface A side first, and then the steps (e')-(h') are performed on the second surface B side.

[0059] In some alternative embodiments, the steps (e)-(h) can be performed on the first surface A and the second surface B simultaneously, and thus will not be repeated.

[0060] Next, a through hole 502 is formed through the first dielectric layer 101, the second dielectric layers 201a, 201b, the third dielectric layers 301a, 301b, and the fourth dielectric layers 501a, 501b, and a first blind hole 503a, 503b is formed on the fourth dielectric layer 501a, 501b to expose the terminal of the component 401a, 401b, as shown in FIG. 2(o).

[0061] It should be noted that the process of making the through hole 502 and the first blind hole 503a, 503b can be mechanical drilling or laser drilling. For example, the through hole 502 is made by mechanical drilling, and the blind hole 503a, 503b is made by laser drilling.

[0062] Then, the through hole 502 and the first blind hole 503a, 503b are electroplated to form a through hole column and a terminal pad, and a third line layer 701a, 701b is formed on the fourth dielectric layer 501a, 501b; wherein the third line layer 701a, 701b is connected to the terminal of the component 401a, 401b; the through hole column is connected to the third line layer 701a, 701b on both sides of the first dielectric layer 101—step (j), as shown in FIG. 2 (p).

[0063] It should be noted that the through hole column can realize the interconnection between the first line layer 103a, 103b, the second line layer 202a, 202b, the third line layer 701a, 701b and the component 401a, 401b.

[0064] As shown in FIG. 2 (p), the core layer 600 can include components 401a, 401b, a first dielectric layer 101, a second dielectric layer 201a, 201b, a third dielectric layer 301a, 301b, and a line layer located therebetween, such as a first line layer 103a, 103b, a second line layer 202a, 202b.

[0065] Next, an outer dielectric layer 801a, 801b covering the third line layer 701a, 701b is formed on the fourth dielectric layer 501a, 501b—step (k), as shown in FIG. 2 (q).

[0066] Optionally, the material of the outer dielectric layer 801a, 801b can be a resin material, such as ABF.

[0067] Here, the outer dielectric layer 801a, 801b can be windowed to form a second blind hole 802a, 802b exposing the third line layer 701a, 701b.

[0068] Finally, an outer line layer 901a, 901b is formed on the outer dielectric layer 801a, 801b; wherein the outer line layer 901a, 901b is connected to the third line layer 701a, 701b—step (l), as shown in FIG. 2 (r).

[0069] It should be noted that according to the needs of the product, repeating steps (k) and (l) can continue to increase the layer and realize the conduction between different layers of lines. This disclosure will not be repeated here.

[0070] Further, each of the aforementioned layers can be respectively arranged symmetrically relative to the first dielectric layer 101, thereby preventing the substrate from being bent due to the difference in the thermal expansion coefficient of each layer.

[0071] In a second aspect, the embodiments of the present disclosure further provide a core layer multi-layer wiring embedded substrate. Figure 3 A structure schematic diagram of an embedded substrate provided by the embodiments of the present disclosure is shown. As shown in Figure 3 The embedded substrate includes: a core layer 600, fourth dielectric layers 501a, 501b on the upper and lower surfaces of the core layer 600, and third wiring layers 701a, 701b on the fourth dielectric layers 501a, 501b; wherein, The core layer 600 includes: a first dielectric layer 101; first wiring layers 103a, 103b on the upper and lower surfaces of the first dielectric layer 101, the first wiring layers 103a, 103b including barrier layers 1031a, 1031b; second dielectric layers 201a, 201b on the first wiring layers 103a, 103b, the second dielectric layers 201a, 201b having blind slots with the barrier layers 1031a, 1031b as the bottom; third dielectric layers 301a, 301b on the second dielectric layers 201a, 201b; and components 401a, 401b embedded in the blind slots, wherein the gap between the components 401a, 401b and the second dielectric layers 201a, 201b is filled with the third dielectric layers 301a, 301b; The fourth dielectric layers 501a, 501b are located on the third dielectric layers 301a, 301b, and the third wiring layers 701a, 701b are connected to the terminals of the components 401a, 401b in a conductive manner. The embedded substrate further includes a via column penetrating through the first dielectric layer 101, the second dielectric layers 201a, 201b, the third dielectric layers 301a, 301b, and the fourth dielectric layers 501a, 501b, wherein the via column is connected to the third wiring layers 701a, 701b located on both sides of the first dielectric layer 101 in a conductive manner.

[0072] Such a technical solution sets the second wiring layers 202a, 202b on the second dielectric layers 201a, 201b, so that wiring layers can be arranged on both sides of the second dielectric layers 201a, 201b, which helps to improve the wiring density of the embedded substrate as a whole. At the same time, the components 401a, 401b are embedded in the formed blind slots 203a, 203b, and there is no need to separately manufacture an embedding frame and then align the embedding frame with the core layer 100, thereby effectively avoiding the problem of alignment error between the embedding frame and the core layer 100, and making the components 401a, 401b located on both sides of the first dielectric layer 101 in a better symmetrical position.

[0073] In some embodiments, further comprising outer layer dielectric layers 801a, 801b and outer layer circuit layers 901a, 901b on the third circuit layers 701a, 701b; wherein the outer layer dielectric layers 801a, 801b and the outer layer circuit layers 901a, 901b are symmetrically arranged with respect to the core layer 600 respectively; wherein each of the outer layer circuit layers 901a, 901b is conductive to connect the closest third circuit layer 701a, 701b respectively.

[0074] In some embodiments, the thickness of the second dielectric layers 201a, 201b is not less than the thickness of the components 401a, 401b.

[0075] In some alternative embodiments, the total thickness of the second dielectric layers 201a, 201b and the third dielectric layers 301a, 301b is not less than the thickness of the components 401a, 401b.

[0076] In some embodiments, the material of the first dielectric layer 101 and the second dielectric layers 201a, 201b is resin material containing glass fiber. In some embodiments, the material of the third dielectric layers 301a, 301b and the fourth dielectric layers 501a, 501b is resin material not containing glass fiber.

[0077] In some embodiments, the third dielectric layers 301a, 301b are resin material with viscosity. In some embodiments, the material of the third dielectric layers 301a, 301b and the fourth dielectric layers 501a, 501b is the same or different.

[0078] In some embodiments, the second circuit layers 202a, 202b comprise targets 204a, 204b.

[0079] It should be understood by those of ordinary skill in the art that the above discussion of any embodiment is merely exemplary and is not intended to suggest the scope of the disclosure (including the claims) is limited to these examples; the embodiments above or technical features among different embodiments can also be combined, and the steps can be implemented in any order, and there are many other changes to the aspects of the embodiments of the disclosure as described above, which are not provided in detail for the sake of brevity.

[0080] The embodiments of the disclosure are intended to cover all such alternatives, modifications, and variations as fall within the broad scope of the appended claims. Accordingly, any one of the above-mentioned embodiments or technical features among different embodiments can be combined, and the steps can be implemented in any order, and any omission, modification, equivalent replacement, improvement, etc. made within the spirit and principle of the embodiments of the disclosure shall be included in the protection scope of the disclosure.

Claims

1. A method for fabricating a core layer multilayer wiring embedded substrate, characterized in that, include: (a) A core layer is provided; wherein the core layer includes a first dielectric layer; (b) A first circuit layer is formed on the first dielectric layer; wherein the first circuit layer includes a barrier layer; (c) A second dielectric layer and a second circuit layer are formed on the first dielectric layer; wherein the second dielectric layer covers the first circuit layer; (d) Using the barrier layer as a base, a blind trench is formed in the second dielectric layer; (e) Pressing an uncured third medium layer onto the second medium layer, such that the third medium layer is squeezed to fill the blind groove of the second medium layer; (f) Attaching the components to the surface of the third dielectric layer; (g) Press the component into the blind slot; (h) Press a fourth medium layer onto the surface of the third medium layer, and cure or semi-cure the third medium layer and the fourth medium layer; (i) A through-hole is formed through the first dielectric layer, the second dielectric layer, the third dielectric layer and the fourth dielectric layer, and a blind hole is formed in the fourth dielectric layer to expose the terminals of the component; (j) Electroplating is performed on the through holes and the blind holes to form through hole pillars and terminal pads, and then a third circuit layer is formed on the fourth dielectric layer; wherein the third circuit layer is conductively connected to the terminals of the component; the through hole pillars are conductively connected to the third circuit layers located on both sides of the first dielectric layer.

2. The manufacturing method according to claim 1, characterized in that, Also includes: (k) An outer dielectric layer covering the third circuit layer is formed on the fourth dielectric layer; (l) An outer circuit layer is formed on the outer dielectric layer; wherein the outer circuit layer is connected to the nearest third circuit layer.

3. The manufacturing method according to claim 1, characterized in that, The first dielectric layer and the second dielectric layer are made of glass fiber-containing resin materials; and / or The third dielectric layer and the fourth dielectric layer are made of a resin material that does not contain glass fiber; and / or The third medium layer is a viscous resin material; and / or The third dielectric layer and the fourth dielectric layer may be made of the same or different materials.

4. The manufacturing method according to claim 1, characterized in that, The thickness of the second dielectric layer is not less than the thickness of the component; or The total thickness of the second dielectric layer and the third dielectric layer is not less than the thickness of the component.

5. The manufacturing method according to claim 1, characterized in that, Step (g) employs a vacuum hot pressing process.

6. The manufacturing method according to claim 1, characterized in that, Step (c) includes: (c1) Apply a second dielectric layer and copper foil on the first dielectric layer; wherein the second dielectric layer covers the first circuit layer; (c2) Etch the copper foil to obtain the second circuit layer.

7. The manufacturing method according to claim 1, characterized in that, The second circuit layer includes a target; prior to step (f), the third dielectric layer is laser-exposed to expose the target.

8. A core layer multilayer wiring embedded substrate, characterized in that, include: A core layer, a fourth dielectric layer on the upper and lower surfaces of the core layer, and a third circuit layer on the fourth dielectric layer; wherein... The core layer includes: a first dielectric layer; a first circuit layer on the upper and lower surfaces of the first dielectric layer, the first circuit layer including a barrier layer; a second dielectric layer on the first circuit layer, the second dielectric layer having a blind slot with the barrier layer as its bottom; a third dielectric layer on the second dielectric layer; and a component embedded in the blind slot, wherein the gap between the component and the second dielectric layer is filled by the third dielectric layer, wherein the back side of the component is not in direct contact with the barrier layer, and the terminals of the component face upwards; The fourth dielectric layer is located on the third dielectric layer, and the third circuit layer is connected to the terminals of the component. The embedded substrate further includes through-hole posts penetrating the first dielectric layer, the second dielectric layer, the third dielectric layer, and the fourth dielectric layer, wherein the through-hole posts are conductively connected to the third circuit layers located on both sides of the first dielectric layer.

9. The core layer multilayer wiring embedded substrate according to claim 8, characterized in that, It also includes an outer dielectric layer and an outer circuit layer on the third circuit layer; wherein, The outer dielectric layer and the outer circuit layer are arranged symmetrically with respect to the core layer; wherein each of the outer circuit layers is connected to its nearest third circuit layer.

10. The core layer multilayer wiring embedded substrate according to claim 8, characterized in that, The thickness of the second dielectric layer is not less than the thickness of the component; or The total thickness of the second dielectric layer and the third dielectric layer is not less than the thickness of the component.

11. The core layer multilayer wiring embedded substrate according to claim 8, characterized in that, The first dielectric layer and the second dielectric layer are made of glass fiber-containing resin materials; and / or The third dielectric layer and the fourth dielectric layer are made of a resin material that does not contain glass fiber; and / or The third medium layer is a viscous resin material; and / or The third dielectric layer and the fourth dielectric layer may be made of the same or different materials.

12. The core layer multilayer wiring embedded substrate according to claim 8, characterized in that, The second circuit layer includes a target.

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