Infrared detector column-level buffer and control method thereof
By designing an infrared detector column-level buffer and its control method, the problems of IR drop and rapid build-up of parasitic capacitance in long column lines of infrared detectors are solved, and the circuit area and power consumption are optimized. It is suitable for high linearity and low power consumption signal output and is applicable to high-speed infrared detectors with large-scale arrays.
Patent Information
- Application Number
- CN202511603787.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-05
- Publication Date
- 2026-03-03
AI Technical Summary
Existing infrared detectors suffer from problems such as long column line IR drop and rapid build-up of parasitic capacitance. PING-PANG sampling increases circuit area and power consumption complexity, while cell column buffers are difficult to design with high linearity and low power consumption.
By adopting a control method compatible with both PING-PANG sampling and continuous sampling, and through the design of column-level buffer input stage, acquisition stage and drive stage circuits, high-speed, low-power, and high-performance signal output is achieved. Signal processing is performed using an analog-to-digital converter, and signal readout is optimized by controlling timing and drive mode.
It reduces circuit area and power consumption, solves the problems of long column line IR drop and rapid build-up of parasitic capacitance, and achieves high linearity and low power consumption signal output, making it suitable for high-speed infrared detectors with large-scale arrays.
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Figure CN121603003A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of infrared focal plane detector technology, and in particular to an infrared detector column-level buffer and its control method. Background Technology
[0002] Infrared detection technology is a passive imaging technology for detecting targets. It achieves detection and identification based on the difference in infrared radiation caused by the difference in temperature and emissivity between the target and the background. It has the characteristics of wide coverage, good concealment, strong anti-interference ability, and all-weather operation. It has been widely used in many fields such as industry, medicine, and astronomy.
[0003] The development trends of infrared detection technology mainly include high resolution, high sensitivity, large dynamic range, high frame rate, multispectral processing, and intelligent detection. Based on their working principles, infrared detectors are mainly divided into two categories: photonic detectors and thermal detectors. Currently, high-performance infrared detectors are dominated by cooled photonic HgCdTe infrared detectors. The infrared focal plane array (IRFPA) is the core component of an infrared detection system responsible for converting infrared radiation light signals into electrical signals and outputting them. It mainly consists of two parts: the infrared detector's sensitive element array and the readout integrated circuit (ROIC).
[0004] The infrared detector's sensing elements and readout circuit are interconnected via indium pillars using flip-flops. The sensing element array is primarily responsible for converting incident infrared radiation into photocurrent, which then flows through the interconnected indium pillars into the readout circuit. The digital readout circuit's signal processing path typically integrates injection-level pixel circuitry, signal processing circuitry, data output circuitry, and digital control circuitry.
[0005] Under the existing technology, the following problems mainly exist: (1) In large-scale arrays, the length of the pixel signal trace increases, and the parasitic resistance and parasitic capacitance increase linearly with the array size, resulting in a large IR drop in the pixel output signal and limited signal settling speed; (2) To achieve fast signal establishment, the cell column buffer usually adopts the PING-PANG sampling method, which is actually a space-for-time design method. It usually requires two identical driver stage designs, which increases the circuit area and power consumption. At the same time, due to the column size limitation, the layout complexity also increases. In addition, the PING-PANG acquisition method cannot make full use of the oversampling and noise reduction function of the subsequent analog-to-digital converter.
[0006] (3) In order to increase the dynamic range of the detector, the signal swing within the pixel should be designed to be as large as possible. The pixel column buffer usually drives the ADC capacitor load. Under large signals, it is a difficult design to ensure both high linearity and low power consumption of the buffer. Summary of the Invention
[0007] This application provides an infrared detector column-level buffer and its control method, which solves the problems of rapid establishment of long column line IRDrop and parasitic capacitance, as well as the design problems of circuit area and power consumption complexity caused by PING-PANG sampling.
[0008] This application provides an infrared detector column-level buffer, including: The pixel signal output stage and column-level buffer bias circuit are respectively connected to the column-level buffer input stage circuit; The column-level buffer input stage circuit is connected to the column-level buffer PING-PANG acquisition circuit. The column-level buffer PING-PANG acquisition circuit outputs to the column-level buffer driver stage circuit. A column-level buffer driver stage circuit is connected to the analog-to-digital converter (ADC) to utilize the ADC output.
[0009] This application provides a control method for an infrared detector column-level buffer, including: After the internal signal of a pixel is integrated, the column output line is reset. After the reset, the row selection switch of the pixel array is turned on row by row. The pixel output stage is connected to the buffer input stage circuit. The column signal operates through current and voltage respectively, and passes through the level-shift NMOS transistor M of the column buffer input stage circuit. N8 To achieve linearity restoration, in order to complete the readout of the pixel column signal; Configure V shift The signal's operating timing controls the switching of the column-level buffer PING-PANG acquisition circuit on V. shift The signal is acquired and filtered, and the acquisition control is performed based on the column-level buffer PING-PANG acquisition circuit. The Vshift signal is acquired and held. Based on the amplitude of the acquired and held signal, the switching of the column-level buffer driver circuit is controlled to change the open-loop and closed-loop modes of the column-level buffer driver circuit, so as to achieve signal output.
[0010] This application proposes a control method compatible with both PING-PANG sampling and continuous sampling, which eliminates the need for two identical driver stage circuits, reduces area and power consumption, solves the problems of rapid IR drop and parasitic capacitance build-up on long column lines, and addresses the design complexity issues related to circuit area and power consumption caused by PING-PANG sampling.
[0011] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description
[0012] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings: Figure 1 This is a schematic diagram of the architecture of the infrared detector column-level buffer in an embodiment of this application; Figure 2 This is a schematic diagram of the circuit structure of the infrared detector column-level buffer in an embodiment of this application; Figure 3 This is a control timing diagram of an infrared detector column-level buffer control method according to an embodiment of this application; Figure 4 This is a schematic diagram of another control timing for the infrared detector column-level buffer control method according to an embodiment of this application. Detailed Implementation
[0013] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
[0014] This invention proposes an infrared detector column-level buffer and its control method to solve at least some of the problems in the prior art, including solving the problems of long column line IR drop and rapid build-up of parasitic capacitance; addressing the circuit area and power consumption complexity caused by PING-PANG sampling, while also considering continuous signal sampling to reduce noise; and achieving high linearity and low power consumption in the buffer design under large signal conditions. Specifically, this application provides an infrared detector column-level buffer, such as... Figure 1 As shown, it includes: Pixel signal output stage 1 and column-level buffer bias circuit 2 are respectively connected to column-level buffer input stage circuit 3; The column-level buffer input stage circuit 3 is connected to the column-level buffer PING-PANG acquisition circuit 4. The output of the column-level buffer PING-PANG acquisition circuit 4 is connected to the column-level buffer driver circuit 5. The column-level buffer driver stage circuit 5 is connected to the analog-to-digital converter (ADC) to utilize the ADC output.
[0015] This application proposes a control method compatible with both PING-PANG sampling and continuous sampling, which eliminates the need for two identical driver stage circuits, reduces area and power consumption, and helps reduce noise in applications.
[0016] In some embodiments, the gate of the pixel signal output stage is connected to the pixel internal integral signal, drives the long column lines through the pixel internal source follower, and is then connected to the input terminal of the signal buffer input stage circuit for outputting pixel signals line by line.
[0017] In some embodiments, such as Figure 2 As shown, the column-level buffer bias circuit includes: A current generating tube M P0 It is used to receive external bias voltage and generate basic bias unit current; A set of NMOS CASCODE current mirrors M N0 / M N1 / M N2 / M N3 , used to generate the basic bias voltage of NMOS; A current generating tube M P1 This is used to generate the basic bias voltage of the PMOS inside the buffer. Two PowerDown control tubes M PPD and M NPD It is used to control the enable of the buffer circuit.
[0018] In some embodiments, such as Figure 2 As shown, the column-level buffer input stage circuit includes: PMOS current mirror M P2 NMOS tail current transistor M N4 / M N5 Column line reset NMOS transistor M N6 / M N7 and level-shift NMOS transistor M N8 ,in: The NMOS current mirror and PMOS current mirror are used to generate the bias current of the two branches, respectively. Column-line reset NMOS transistor M N6 / M N7 Used to reset column signals; A level-shift NMOS transistor is used for column signal mirroring.
[0019] In some embodiments, such as Figure 2As shown, the column-level buffer ping-pang acquisition circuit includes: Switches S1 / S2 / S3 / S4 are used to implement PING-PANG sampling and continuous sampling. Capacitors C1 and C2 are used for signal sampling and filtering; The transfer capacitor C3 is used to maintain the phase of the received column signal and to prevent kickback when the ADC acquisition buffer output stage signal is generated.
[0020] In some embodiments, such as Figure 2 As shown, the column-level buffer driver stage circuit includes: Five switches S5 / S6 / S7 / S8 / S9 are used to implement open-loop drive and closed-loop drive control of the buffer; PMOS current mirror M P3 and NMOS current mirror M N9 / M N10 / M N11 These are used to generate the bias current for the three branches respectively; NMOS SF input transistor M N12 / M N13 , serving as the main driving transistor in the output stage of the buffer; Resistor R0 is an adjustable resistor used to provide a relatively constant voltage V to the output drive transistor of the buffer. ds .
[0021] The infrared detector column buffer of this application, through the aforementioned constituent units 2-5 and the pixel signal output stage 1, realizes high-speed, low-power, and high-performance establishment of pixel column signals, which is especially suitable for column-level digital infrared detectors.
[0022] The buffer driver stage circuit of this application can solve the problem of high-speed, high-linearity setup of large-swing pixel signals, achieving SNDR>70dB with a 1.6V output swing, and supporting the driving of high-speed oversampling column-level analog-to-digital converters. The infrared detector column-level buffer circuit proposed in this application, through the design of the buffer's signal operating timing and the driver stage's driving mode, enables high-speed, low-power, and high-performance driving of the ADC load of the column-level analog-to-digital converter by the pixel column signals.
[0023] This application also proposes a control method for the infrared detector column-level buffer as described above. The infrared detector column-level buffer control method proposed in this application is applicable to signal processing using a column-level analog-to-digital converter (ADC). The column-level ADC can be a Nyquist ADC or an incremental SDM ADC, with the incremental SDM ADC showing better performance. The use of an incremental SDM ADC in this embodiment is described as follows: Step S1: After the internal signal integration of the pixel is completed, the column output line is reset. After the reset, the row selection switch of the pixel array is turned on row by row. The pixel output stage is connected to the buffer input stage circuit. The column signal operates through current and voltage respectively, and passes through the level-shift NMOS transistor M of the column buffer input stage circuit. N8 To achieve linearity restoration, in order to complete the readout of the pixel column signal; Step S2, Configure V shift The signal's operating timing controls the switching of the column-level buffer PING-PANG acquisition circuit on V. shift The signal is acquired and filtered, and the acquisition control is performed based on the column-level buffer PING-PANG acquisition circuit. Step S3: Acquire and hold the Vshift signal. Based on the amplitude of the acquired and held signal, control the switching of the column-level buffer driver circuit to change the open-loop and closed-loop modes of the column-level buffer driver circuit, so as to achieve signal output.
[0024] In some embodiments, the switch of the control column-level buffer PING-PANG acquisition circuit controls V shift Signal acquisition and filtering include PING-PANG acquisition and continuous acquisition, with PING-PANG acquisition and continuous acquisition each configured with different V values. shift Signal operating timing; Step S21, PING-PANG acquisition control includes: according to the configured V shift Signal timing, such as V shift The signal is in accordance with the attached Figure 3 Works according to the timing, based on F S1 and F S2 Alternately control switches S1 and S2 of the column-level buffer PING-PANG acquisition circuit to control V. shift Signal acquisition, and alternating control of switches S3 and S4 to F S1 and F S2 The acquired signal is held, and the idle time of the control switches S1 and S2 generates C. RST The column readout lines are reset, and the on-times of switches S1 and S2, and switches S3 and S4 overlap by 6*TMC, i.e., F. H1 and F S1 F H2 and F S2 The opening times overlap by 6*T MC TMC is the master clock cycle, and through the overlapping design, the buffer output stage does not need to be copied twice.
[0025] Step S22, continuous acquisition control includes: according to the configured V shiftThe signal operating sequence is as follows: control switches S1 and S3 are always open, connecting capacitors C1 and C3 to supply voltage to V. shift Signal filtering, control switches S2 and S3 are always off, and the idle time between the row strobe control signals generates C. RST The column read lines are reset, and the buffer output stage outputs continuously.
[0026] In steps S21 and S22, V has been processed in two different ways. shift The signal is acquired and held. Based on the amplitude of the acquired and held signal, the switching of the column-level buffer driver circuit is controlled to change the open-loop and closed-loop modes of the column-level buffer driver circuit, including: When the signal swing is large, switches S5, S7, and S9 are turned on by control circuit M1 of the column-level buffer driver stage, and switches S6 and S8 are turned off by control circuit M0, so that the buffer driver stage operates in closed-loop mode. Resistor R0 drives the output driver transistor M. N12 / M N13 Provides a relatively constant drain-source voltage V ds This improves the linearity of large-swing output signals and reduces output impedance to accelerate signal establishment.
[0027] When the signal swing is small, switches S5, S7, and S9 are turned off by control circuit M1 of the column-level buffer driver stage, and switches S6 and S8 are turned on by control circuit M0, so that the buffer driver stage operates in open-loop mode. Resistor R0 drives the output driver transistor M. N12 / M N13 Provides a relatively constant drain-source voltage V ds This improves the linearity of the output signal and reduces the power consumption of the buffer.
[0028] This application employs a column-level buffer input stage circuit with dual column lines and a reset switch, which can effectively solve the problem of high-speed pixel column signal readout in large-area arrays and reduce the impact of column line voltage drop and parasitic capacitance on signal establishment.
[0029] Based on the PING-PANG sampling control timing and circuitry of this application, the driver stage circuitry can be reduced by half, thereby reducing circuit area and power consumption, which is beneficial for column-level layout within size constraints. Furthermore, this PING-PANG sampling control timing and circuitry can be switched to continuous sampling mode, which is beneficial for continuous acquisition of signals within pixels, further reducing circuit noise.
[0030] The infrared detector column-level buffer control method proposed in this application can realize four pixel column signal driving modes: PING-PANG closed-loop driving, continuous closed-loop driving, PING-PANG open-loop driving, and continuous open-loop driving, solving the problem of high-speed, low-power, and high-performance column-level output in the design of large-scale column-level digital infrared detectors.
[0031] This application further proposes an implementation example of an infrared detector column-level buffer and its control method. In this example, according to... Figure 3 The control timing shown includes the following steps: (1) Pixel column signal readout row by row: The buffer bias circuit is set with a reasonable bias voltage to generate the correct operating current, ensuring the normal operation of the circuit; such as Figure 2 Each column line shown in the diagram simultaneously connects to N rows of cells in the array. First, the column line is reset between row-to-row gating signals; in this embodiment, it is reset to ground. Then, the row gating switches are opened row by row. Cells in the same column are connected to the buffer input stage circuit via dual column lines, and in0 is connected to M via current. N4 in1 is connected to M via voltage. N5 After M N8 After in1 superimposed V GS8 The Vshift signal was obtained, and the pixel integral signal was restored with high linearity.
[0032] (2) Acquisition of column signal PING-PANG: such as Figure 3 The control timing shown is F in this embodiment. S1 and F S2 With twice the line processing time of 256*T MC The period is 123*T, and the pulse width is 123*T. MC Alternately control switches S1 and S2 to acquire the Vshift signal; F S1 and F S2 The idle time between them generates C RST The period is 128*T MC The period is 3*T, and the pulse width is 3*T. MC Reset the column readout lines; F H1 and F H2 With twice the line processing time of 256*T MC The period is 127*T, and the pulse width is 127*T. MC Alternately control switches S3 and S4 to control F S1 and F S2 The acquired signal is held; where F H1 and F S1 F H2 and F S2 The opening times overlap by 6*T MC T MCUsing the master clock cycle, the buffer can output continuously through an overlapping design, reducing area and power consumption.
[0033] (3) Pixel column signal closed-loop drive ADC: Configure M1 high through the register to enable S5, S7 and S9, configure M0 low to disable switches S6 and S8, and set the current of R0 and the feedback branch to supply power to the output drive transistor M N12 / M N13 It provides a relatively constant drain-source voltage Vds, enabling the buffer driver stage to operate in closed-loop mode, and reduces the equivalent output impedance of the buffer, thereby accelerating signal establishment and improving the linearity of large-swing signals.
[0034] (4) Pixel column signal open-loop drive ADC: By configuring M1 to low in the register, S5, S7 and S9 are turned off, and by configuring M0 to high, switches S6 and S8 are turned on. The bias current is provided by the buffer bias circuit. R0 and the feedback branch are shielded, so that the buffer drive stage works in open-loop mode. The linearity of small signal swing is improved and the power consumption is reduced by shorting the substrate source.
[0035] (5) ADC acquires quantization buffer signal: In steps (2) and (3 or 4), the pixel column signal has been acquired and driven by PING-PANG method. The period of the ADC NRST_AD signal is 128*T. MC The pulse width is 12*T MC During the initial reset and signal establishment phase of the column buffer, the ADC internals are reset, which also serves to synchronize the quantization code value of the previous row's pixel signal. After the reset is complete, the signal is sampled and quantized M times to obtain the quantization code for the current row.
[0036] According to the control method of this embodiment, voltage readout is used to reduce the impact of column line voltage drop differences, column line reset control is used to reduce the impact of column line parasitic capacitance on signal establishment, PING-PANG acquisition control method is used to increase readout time without adding additional circuitry and power consumption, and closed-loop drive of the output stage is used to achieve high-speed, high-linearity establishment of large signals. In summary, the control method of this embodiment can effectively solve the problem of reading out and acquiring pixel column signals of large-array high-speed, high-linearity infrared detectors.
[0037] This application further proposes an implementation example of an infrared detector column-level buffer and its control method. In this example, according to... Figure 4 The control timing shown is consistent with... Figure 3 The difference in the control example shown is that in step (2), the column signal is set to continuous acquisition instead of PING-PANG acquisition. Therefore, the remaining steps will not be repeated. Only the continuous acquisition method of the column signal in step (2) will be described: (2) Continuous acquisition of column signals: such as Figure 4 The control timing shown is FS1 and F H1 Switches S1 and S3 are kept on continuously, and capacitors C1 and C3 are connected together to filter the Vshift signal; F S2 and F H2 The S2 and S4 switches are kept off; the idle time between the row strobe control signals generates CRST to reset the column readout lines; the ADC's NRST_AD resets the ADC internally during the column line reset and the initial stage of signal establishment, while synchronizing the quantization code value of the previous row of pixel signals, and the buffer output stage outputs continuously.
[0038] According to control method two, noise can be further reduced by continuously acquiring pixel column signals and combining this with incremental ADC to suppress oversampling of signal noise. In summary, both methods can achieve both ultra-high-speed PING-PANG acquisition and low-noise continuous acquisition without increasing additional circuit area and power consumption.
[0039] The control method proposed in this application, which is compatible with both PING-PANG sampling and continuous sampling, eliminates the need for two identical driver stage circuits, reducing area and power consumption, and also helps to reduce noise in applications.
[0040] It should be noted that, in the embodiments of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.
[0041] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.
[0042] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of this application.
[0043] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims. All of these forms are within the protection scope of this application.
Claims
1. An infrared detector column-level buffer, characterized in that, include: The pixel signal output stage and column-level buffer bias circuit are respectively connected to the column-level buffer input stage circuit; The column-level buffer input stage circuit is connected to the column-level buffer PING-PANG acquisition circuit. The column-level buffer PING-PANG acquisition circuit outputs to the column-level buffer driver stage circuit. A column-level buffer driver stage circuit is connected to the analog-to-digital converter (ADC) to utilize the ADC output.
2. The infrared detector column-level buffer as described in claim 1, characterized in that, The gate of the pixel signal output stage is connected to the internal integral signal of the pixel, drives the long column lines through the internal source follower of the pixel, and then connects to the input terminal of the signal buffer input stage circuit for outputting the pixel signal line by line.
3. The infrared detector column-level buffer as described in claim 2, characterized in that, The column-level buffer bias circuit includes: Current generating tube M P0 It is used to receive external bias voltage and generate basic bias unit current; A set of NMOS CASCODE current mirrors M N0 / M N1 / M N2 / M N3 , used to generate the basic bias voltage of NMOS; Current generating tube M P1 This is used to generate the basic bias voltage of the PMOS inside the buffer. PowerDown control tube M PPD and M NPD It is used to control the enable of the buffer circuit.
4. The infrared detector column-level buffer as described in claim 3, characterized in that, The column-level buffer input stage circuit includes: PMOS current mirror M P2 NMOS tail current transistor M N4 / M N5 Column line reset NMOS transistor M N6 / M N7 and level-shift NMOS transistor M N8 ,in: The NMOS current mirror and PMOS current mirror are used to generate the bias current of the two branches, respectively. Column-line reset NMOS transistor M N6 / M N7 Used to reset column signals; A level-shift NMOS transistor is used for column signal mirroring.
5. The infrared detector column-level buffer as described in claim 4, characterized in that, The column-level buffer ping-pang acquisition circuit includes: Switches S1 / S2 / S3 / S4 are used to implement PING-PANG sampling and continuous sampling. Capacitors C1 and C2 are used for signal acquisition and filtering; The transfer capacitor C3 is used to maintain the phase of the received column signal and to prevent kickback when the ADC acquisition buffer output stage signal is generated.
6. The infrared detector column-level buffer as described in claim 5, characterized in that, The column-level buffer driver stage circuit includes: Switches S5 / S6 / S7 / S8 / S9 are used to implement open-loop and closed-loop drive control of the buffer. PMOS current mirror M P3 and NMOS current mirror M N9 / M N10 / M N11 These are used to generate the bias current for the three branches respectively; NMOS SF input transistor M N12 / M N13 , serving as the main driving transistor in the output stage of the buffer; Resistor R0 is used to provide voltage V to the output drive transistor of the buffer. ds .
7. The control method for the infrared detector column-level buffer as described in any one of claims 1-6, characterized in that, include: After the internal signal of a pixel is integrated, the column output line is reset. After the reset, the row selection switch of the pixel array is turned on row by row. The pixel output stage is connected to the buffer input stage circuit. The column signal operates through current and voltage respectively, and passes through the level-shift NMOS transistor M of the column buffer input stage circuit. N8 To achieve linearity restoration, in order to complete the readout of the pixel column signal; Configure V shift The signal's operating timing controls the switching of the column-level buffer PING-PANG acquisition circuit on V. shift The signal is acquired and filtered, and the acquisition control is performed based on the column-level buffer PING-PANG acquisition circuit. The Vshift signal is acquired and held. Based on the amplitude of the acquired and held signal, the switching of the column-level buffer driver circuit is controlled to change the open-loop and closed-loop modes of the column-level buffer driver circuit, so as to achieve signal output.
8. The control method for the infrared detector column-level buffer as described in claim 7, characterized in that, The switch of the control column-level buffer PING-PANG acquisition circuit to V shift Signal acquisition and filtering include PING-PANG acquisition and continuous acquisition, with PING-PANG acquisition and continuous acquisition each configured with different V values. shift Signal operating timing; PING-PANG acquisition control includes: based on the configured V shift The signal operating timing alternately controls switches S1 and S2 of the column-level buffer PING-PANG acquisition circuit to control V. shift The signal is acquired, and the sampled signal is held by alternately controlling switches S3 and S4. The idle time of switches S1 and S2 generates C. RST The column readout lines are reset, and the on-times of switches S1 and S2, and switches S3 and S4 overlap by 6*TMC, T. MC Master clock cycle; Continuous acquisition control includes: based on the configured V shift The signal operating sequence is as follows: control switches S1 and S3 are always open, connecting capacitors C1 and C3 to supply voltage to V. shift Signal filtering, control switches S2 and S3 are always off, and the idle time between the row strobe control signals generates C. RST Reset the column readout lines.
9. The control method for the infrared detector column-level buffer as described in claim 7, characterized in that, Based on the amplitude of the acquired and held signal, the open-loop and closed-loop modes of the column-level buffer driver circuit are changed by controlling the switching of the column-level buffer driver circuit, including: When the signal swing is large, switches S5, S7, and S9 are turned on by control circuit M1 of the column-level buffer driver stage, and switches S6 and S8 are turned off by control circuit M0, so that the buffer driver stage operates in closed-loop mode. Resistor R0 drives the output driver transistor M. N12 / M N13 Provides a relatively constant drain-source voltage V ds This improves the linearity of large-amplitude output signals; When the signal swing is small, switches S5, S7, and S9 are turned off by control circuit M1 of the column-level buffer driver stage, and switches S6 and S8 are turned on by control circuit M0, so that the buffer driver stage operates in open-loop mode. Resistor R0 drives the output driver transistor M. N12 / M N13 Provides a relatively constant drain-source voltage V ds This improves the linearity of the output signal.