Photoetching test pattern generation method and computer equipment

Abstract

The invention provides a photoetching test pattern generation method and computer equipment. The generation method of the photoetching test pattern comprises the following steps: constructing an initial test pattern; training a de-noising diffusion probability model by using the initial test pattern; combining the trained de-noising diffusion probability model with random noise to obtain a generated test pattern; and screening the generated test pattern to obtain a target test pattern. According to the scheme provided by the invention, simple and multivariate test patterns can be automatically generated, excessive dependence on artificial experience is avoided, the test period is shortened, the consistency and stability of a photoetching process are improved, and the photoetching yield is improved; according to the method, pattern exploration is carried out in a design space specified by a process design suite of a current process node, the boundary of a known pattern space is expanded, features in various design spaces are covered as far as possible, the coverage rate is increased, and generation of a photoetching test pattern is accelerated.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for generating photolithographic test patterns and a computer device. Background Technology

[0002] Test patterns are specific design patterns used in photolithography to verify and evaluate the performance of the photolithography process. These patterns are used to test and optimize multiple parameters in the photolithography process to ensure that the final semiconductor device design layout meets the design manufacturability specifications. Test patterns have three main applications: First, in the early development stages of chip design process nodes, when design manufacturability rules are not yet fully established, artificially constructed test patterns are needed to explore the design space with yield constraints and establish complete design process rules; second, during the product manufacturing monitoring stage, test patterns are used periodically to monitor the consistency and stability of the photolithography process; and third, they are used for photolithography equipment calibration to ensure that the equipment operates under optimal conditions.

[0003] However, as process nodes shrink further, manufacturing processes become more complex, and test pattern design should cover as many sizes and shapes as possible in practical applications. Traditional test pattern generation relies mainly on human experience and test patterns migrated from mature nodes. These methods are susceptible to human interference and risk insufficient coverage. Therefore, there is a need to establish an automated, batch test pattern generation method that enhances design space exploration and expands the boundaries of the known pattern space, capable of covering patterns for all manufacturable process conditions as much as possible.

[0004] Existing test pattern generation schemes generally include the following three types: First, using parametric pattern arrays. This includes linewidth test patterns (creating a set of lines with different widths), spacing test patterns (using lines or graphics with different spacings), circular and square patterns (taking polygons of different sizes to evaluate the shape and outline of the pattern in lithography), and testing patterns with different fill rates, etc. Second, drawing test patterns based on manual experience, selecting key feature patterns from accumulated cases, including migrating test patterns from mature process nodes to newly developed process nodes. Third, selecting key patterns from existing design layouts as the test pattern set.

[0005] However, the above three test pattern generation schemes have the following technical problems: parametric patterns do not cover the design and manufacturing space of advanced process nodes, the provided test patterns are not rich enough, and there is a risk of process defects; manually designed test patterns rely on the experience accumulation of engineers, and human interference factors are too strong; for newly developed process nodes, there may be a lack of existing design layouts as input. Summary of the Invention

[0006] One objective of this invention is to avoid over-reliance on human experience, reduce testing cycles, improve the consistency and stability of the photolithography process, and increase the yield of photolithography.

[0007] A further objective of this invention is to expand the boundaries of the known pattern space, improve coverage, and accelerate the generation of lithographic test patterns.

[0008] Specifically, the present invention provides a method for generating a photolithographic test pattern, comprising: constructing an initial test pattern; training a denoising diffusion probability model using the initial test pattern; obtaining a generated test pattern by combining the trained denoising diffusion probability model with random noise; and performing a screening process on the generated test pattern to obtain a target test pattern.

[0009] Optionally, the steps for constructing the initial test pattern include: sampling and extracting the standard cell design layout provided by the process design suite of the current process node, and using the obtained local pattern as the initial test pattern.

[0010] Optionally, the denoising diffusion probability model adopts the U-Net architecture, which is a symmetrical layout of input, downsampling, intermediate layer, upsampling, and output.

[0011] Optionally, the U-Net architecture employs a temporal embedding training noise diffusion process, and the intermediate layers use a self-attention mechanism layer to improve the ability of the generated test pattern to retain typical features of the initial test pattern.

[0012] Optionally, the steps of training the denoising diffusion probability model using the initial test pattern include: randomly sampling time steps from a set of time series, assigning time steps to the initial test pattern, wherein the number of time steps is less than a time step threshold; adding real noise of corresponding intensity to the initial test pattern according to the time step, and calculating the pattern after adding real noise; inputting the pattern after adding real noise into the denoising diffusion probability model to obtain the predicted noise; and calculating the gradient of the loss function based on the real noise and the predicted noise, and updating the parameters of the U-Net architecture based on the gradient.

[0013] Optionally, the step of obtaining the generated test pattern by combining the trained denoising diffusion probability model with random noise includes: continuously predicting the added noise corresponding to each time step in the random noise using the denoising diffusion probability model, updating the current state based on the predicted added noise, and obtaining the generated test pattern after iteratively completing the back diffusion.

[0014] Optionally, the step of screening the generated test patterns includes: performing a design rule check on the generated test patterns according to the design rule file provided by the process design kit, and filtering out generated test patterns that do not meet the design rule check; and filtering out duplicate patterns among the generated test patterns that pass the design rule check.

[0015] Optionally, the step of filtering out duplicate patterns in the generated test patterns that pass the design rule check includes: performing a fast Fourier transform on the generated test patterns that pass the design rule check; and using a density-based spatial clustering algorithm in the Fourier space to cluster the patterns and select representative patterns from each cluster.

[0016] Optionally, after the step of training the denoising diffusion probability model using the initial test pattern, the method further includes: selecting a key test pattern from the initial test pattern; adding noise to the key test pattern by a certain number of steps; inputting the key test pattern with added noise into the trained denoising diffusion probability model; obtaining variant test patterns of the key test pattern through back diffusion using the denoising diffusion probability model; and filtering the variant test patterns to obtain the target test pattern.

[0017] According to another aspect of the present invention, a computer device is also provided, including a memory, a processor, and a computer program stored in the memory and running on the processor, wherein the processor executes the computer program to implement the method for generating a photolithographic test pattern as described above.

[0018] The method for generating photolithography test patterns of the present invention constructs an initial test pattern, trains a denoising diffusion probability model using the initial test pattern, obtains a generated test pattern by combining the trained denoising diffusion probability model with random noise, and performs screening processing on the generated test pattern to obtain a target test pattern. This method can automatically generate concise but diverse test patterns, avoids excessive reliance on human experience, reduces the test cycle, improves the consistency and stability of the photolithography process, and increases the yield of photolithography.

[0019] Furthermore, the method for generating lithographic test patterns of the present invention can explore patterns within the design space specified by the process design kit of the current process node with minimal human intervention, expand the boundary of the known pattern space, cover features in multiple design spaces as much as possible, improve coverage, and accelerate the generation of lithographic test patterns.

[0020] The above and other objects, advantages and features of the present invention will become more apparent to those skilled in the art from the following detailed description of specific embodiments of the invention in conjunction with the accompanying drawings. Attached Figure Description

[0021] The following sections will describe some specific embodiments of the invention in detail by way of example and not limitation, with reference to the accompanying drawings. The same reference numerals in the drawings denote the same or similar parts or portions. Those skilled in the art should understand that these drawings are not necessarily drawn to scale. In the drawings: Figure 1This is a schematic diagram of a method for generating a photolithographic test pattern according to an embodiment of the present invention; Figure 2 This is a schematic diagram illustrating the generation of multiple variant test patterns from a key test pattern in a photolithographic test pattern generation method according to an embodiment of the present invention. Figure 3 This is a detailed flowchart of a method for generating a photolithographic test pattern according to an embodiment of the present invention; Figure 4 This is a schematic diagram of the training and prediction process of the denoising diffusion probability model in the method for generating photolithographic test patterns according to an embodiment of the present invention. Figure 5 This is a schematic diagram of fast Fourier transform and density-based spatial clustering in a method for generating photolithographic test patterns according to an embodiment of the present invention. Figure 6 This is a schematic diagram of a computer program product according to an embodiment of the present invention; Figure 7 This is a schematic diagram of a computer-readable storage medium according to an embodiment of the present invention; and Figure 8 This is a schematic diagram of a computer device according to an embodiment of the present invention. Detailed Implementation

[0022] This embodiment provides a method for generating photolithography test patterns, which can automatically generate simplified but diverse test patterns, avoid over-reliance on human experience, reduce the test cycle, improve the consistency and stability of the photolithography process, and increase the yield of photolithography. Figure 1 This is a schematic diagram of a method for generating a photolithographic test pattern according to an embodiment of the present invention. Figure 1 As shown, the method for generating the photolithographic test pattern in this embodiment generally includes: Step S102: Construct the initial test pattern; Step S104: Train the denoising diffusion probability model using the initial test pattern; Step S106: The generated test pattern is obtained by combining the trained denoised diffusion probability model with random noise; Step S108: Filter the generated test pattern to obtain the target test pattern.

[0023] In the above steps, step S102, constructing the initial test pattern, may specifically include: sampling and extracting the standard cell design layout provided by the Process Design Kit (PDK) of the current process node, and using the obtained local pattern as the initial test pattern. In a specific embodiment, the Denoising Diffusion Probabilistic Model (DDPM) in step S104 adopts a U-Net architecture, which is a symmetrical layout of input, downsampling, intermediate layers, upsampling, and output. In a preferred embodiment, the U-Net architecture uses temporal embedding to train the noise diffusion process, and the intermediate layers use a self-attention mechanism layer to improve the ability of the generated test pattern to retain the typical features of the initial test pattern.

[0024] The advantages of the denoising diffusion probability model lie in its ability to balance high fidelity and diversity of generated results. It can accurately restore data details through multi-step iterations, cover a wide range of data distributions, and possess strong functional adaptability, flexibly adapting to complex tasks such as repair and interpolation. The training process is stable, and it can be optimized to meet industrial-grade accuracy and efficiency requirements. The denoising diffusion probability model was chosen because, on the one hand, its "stepwise noise addition-reverse denoising" mechanism solves problems in traditional test pattern generation such as insufficient coverage, reliance on experience, and lack of existing layout input for new nodes, automatically generating patterns that conform to process rules in batches. On the other hand, it combines the mathematical solvability and physical rationality of Gaussian noise with the U-Net architecture and self-attention mechanism, enabling efficient learning of data features. Through design rule checks and clustering filtering, it obtains a concise and representative pattern set, supporting design space exploration and yield improvement in lithography processes.

[0025] In one specific embodiment, step S104, which trains the denoising diffusion probability model using the initial test pattern, may include: randomly sampling time steps from a set of time series, allocating time steps to the initial test pattern, wherein the number of time steps is less than a time step threshold; adding real noise of corresponding intensity to the initial test pattern according to the time step, and calculating the pattern after adding real noise; inputting the pattern after adding real noise into the denoising diffusion probability model to obtain the predicted noise; and calculating the gradient of the loss function based on the real noise and the predicted noise, and updating the parameters of the U-Net architecture based on the gradient.

[0026] Step S106, which combines the trained denoising diffusion probability model with random noise to generate a test pattern, may specifically include: continuously predicting the added noise corresponding to each time step in the random noise using the denoising diffusion probability model, updating the current state based on the predicted added noise, and obtaining the generated test pattern after iteratively completing the back diffusion.

[0027] The screening process for the generated test patterns in step S108 may specifically include: performing design rule checking on the generated test patterns according to the design rule file provided by the process design kit, and screening out the generated test patterns that do not meet the design rule checking; and screening out duplicate patterns in the generated test patterns that pass the design rule checking.

[0028] In a preferred embodiment, the steps for removing repetitiveness from the generated test patterns that pass the design rule checking include: performing a fast Fourier transform on the generated test patterns that pass the design rule checking; and performing clustering using a density-based spatial clustering algorithm in the Fourier space, and selecting representative patterns from each cluster.

[0029] In a preferred embodiment, after training the denoising diffusion probability model using the initial test patterns in step S104, it may further include: selecting key test patterns from the initial test patterns; adding noise for a certain number of steps to the key test patterns, inputting the key test patterns with added noise into the trained denoising diffusion probability model, obtaining variant test patterns of the key test patterns through reverse diffusion by the denoising diffusion probability model, and performing screening processing on the variant test patterns to obtain target test patterns.

[0030] Figure 2 It is a schematic diagram of generating multiple variant test patterns from key test patterns in the method for generating lithography test patterns according to an embodiment of the present invention. Key test patterns can be selected from the initial test patterns, and the denoising diffusion probability model is used to generate more variant test patterns, improving the coverage rate of this type of pattern in the test design space. As Figure 2 shown by the red arrow in, add noise for a certain number of steps to the selected key test patterns, and variant test patterns of the key test patterns can be obtained using the denoising diffusion probability model. It should be noted that the noise for a certain number of steps t < T, where T is the time step threshold. The closer t is to 0, the closer the generated variant test pattern is to the original key test pattern, and vice versa, it is less similar to the original key test pattern. After obtaining the variant test patterns, screening processing can be performed on them to obtain target test patterns. The screening processing includes screening through design rule checking and removing duplicate patterns.

[0031] The method for generating lithography test patterns in this embodiment can automatically generate concise but diverse test patterns. It can explore patterns within the design space specified by the PDK with minimal human intervention, expand the boundaries of the known pattern space, and cover features in multiple design spaces as much as possible. This will effectively accelerate the generation of lithography test patterns, avoid over-reliance on manual experience, reduce the test cycle, help improve the consistency and stability of the lithography process, and increase the yield of lithography.

[0032] In some alternative embodiments, higher technical effects can be achieved by further optimizing and configuring the above steps. The following describes the method for generating photolithographic test patterns in this embodiment in detail with reference to an optional execution flow of this embodiment. This embodiment is only an example of the execution flow. In specific implementation, the execution order and running conditions of some steps can be modified according to specific implementation requirements. Figure 3 This is a detailed flowchart of a method for generating a photolithographic test pattern according to an embodiment of the present invention. The method for generating the photolithographic test pattern includes the following steps: Step S302: Sample and extract the standard cell design layout provided by the process design kit of the current process node, and use the obtained local pattern as the initial test pattern. Step S304: Randomly sample time steps from a set of time series and assign time steps to the initial test pattern; Step S306: Add real noise of corresponding intensity to the initial test pattern according to the time step, and calculate the pattern after adding real noise; Step S308: Input the pattern with added real noise into the denoising diffusion probability model to obtain the predicted noise; Step S310: Calculate the gradient of the loss function based on the real noise and the predicted noise, and update the parameters of the U-Net architecture based on the gradient; Step S312: The noise added at each time step in the random noise is continuously predicted by the denoising diffusion probability model, and the current state is updated based on the predicted noise added. After the back diffusion is completed iteratively, the generated test pattern is obtained. Step S314: Perform a design rule check on the generated test pattern according to the design rule file provided by the process design kit, and filter out the generated test patterns that do not meet the design rule check. Step S316: Remove duplicate patterns from the generated test patterns that have passed the design rule check; Step S318: Obtain the target test pattern.

[0033] In the above steps, the initial test pattern in step S302 can be extracted from standard cell design layouts or from other sources. In a specific embodiment, the initial test pattern mainly comes from two parts. The first part is a test pattern obtained by screening test patterns derived from human experience, basic parametric test patterns, test patterns from mature nodes, or patterns from existing designs. The second part comes from the standard cell design files provided by the process design suite of the current process node, by sampling and extracting the standard cell design layout to obtain a series of local patterns. These two parts of patterns constitute the initial test pattern and are used for training the denoising diffusion probability model in the next step.

[0034] Figure 4 It is a schematic diagram of the training and prediction process of the denoising diffusion probability model in the method for generating a lithography test pattern according to an embodiment of the present invention. In a specific embodiment, the main body of the denoising diffusion probability model in step S308 adopts a classic U-Net architecture, that is, a symmetric layout of input-downsampling-middle layer-upsampling-output, and uses time embedding to train the noise diffusion process. At the same time, a self-attention mechanism layer (selfattention) is adopted in the middle layer to improve the consistency of the typical features of the generated test pattern and the initial test pattern.

[0035] The noise in this embodiment can all be Gaussian noise. From a mathematical perspective, Gaussian noise has excellent properties, enabling the derivation of a closed-form solution for the noise distribution at any time step in the forward diffusion process of DDPM, without recursive calculation. When performing reverse diffusion, the conditional distribution is still Gaussian, simplifying parameter learning and loss function calculation, and reducing the difficulty of engineering implementation. From a physical perspective, Gaussian noise conforms to the true noise characteristics of natural data and can simulate the progressive process of physical diffusion, enabling the model to more realistically learn the laws of data generation and degradation. At the same time, its characteristics are adapted to model training. The smooth transition of the forward process can be controlled by scheduling the noise weight, ensuring the restoration of details in reverse generation. It can also cooperate efficiently with network architectures such as U-Net, ultimately guaranteeing the high fidelity and diversity of the generation results, which is the key design for DDPM to achieve stable and high-quality generation.

[0036] Figure 4 In (a), it is the forward diffusion process, continuously adding Gaussian noise to the initial test pattern pattern. Based on this forward diffusion process, the training process of the U-Net architecture is as follows: For a batch of patterns, randomly sample the number of time steps t < T from a set of time series, where T is the time step threshold and can be set to 1000, and calculate the pattern after adding real noise. Use the model to predict the noise, calculate the gradient of the loss function based on the real noise and the predicted noise, and update the parameters of the U-Net architecture according to the gradient. Specifically, gradually inject Gaussian noise into the initial test pattern pattern, making the initial test pattern gradually change from a clear state to pure noise. X0 refers to the initial state, corresponding to the clear initial test pattern. X1, X2,... refer to the intermediate states, adding Gaussian noise to the current pattern at each step, and the pattern gradually becomes blurred and the gray level increases. Finally, Xt becomes pure noise noise, which is a uniform gray texture without pattern features.

[0037] Figure 4(b) in the diagram represents the reverse diffusion process, which generates a new test pattern from the noise. Specifically, from a set of random Gaussian noise, the process continuously predicts the added noise at time t, updates the current state based on the predicted added noise, and ultimately obtains a new test pattern. Specifically, the denoising diffusion probability model starts from pure noise, gradually updates the state through learned patterns, and pattern features gradually emerge from the blurred texture, restoring a clear new test pattern. The initial state is pure noise, and... Figure 4 The final state in (a) is consistent. Xt-1, Xt-2, ... refer to intermediate states. The denoising diffusion probability model updates the state step by step through the learned rules. Finally, the new generated test pattern corresponding to X0 is obtained, which is a striped pattern with a black background and white lines.

[0038] The generated test pattern obtained by the denoising diffusion probability model must meet the design rules in the process design kit in order to be used for photolithography manufacturing. Therefore, step S314 needs to be executed to check the generated test pattern according to the design rule file provided by the process design kit, filter out the generated test patterns that do not meet the design rule check, and retain the generated test patterns that pass the design rule check.

[0039] Because of the translation and rotation of the pattern, the repeated pattern does not expand the design space coverage of the test pattern. Therefore, step S316 needs to be performed to filter out the repeated patterns in the generated test pattern that have passed the design rule check. Figure 5 This is a schematic diagram illustrating Fast Fourier Transform and density-based spatial clustering in a method for generating photolithographic test patterns according to an embodiment of the present invention. Figure 5 As shown, the generated test patterns that pass the design rule check can be subjected to a Fast Fourier Transform, and then a Density-Based Spatial Clustering of Applications with Noise (DBSCAN) algorithm can be used in the Fourier space to cluster the generated test patterns. Representative patterns are selected from each cluster, and finally a simplified and duplicate-removed target test pattern set is obtained.

[0040] Figure 5 (a) shows a comparison between the generated test patterns and the simulated imaging results under photolithography. The top row shows five different generated test patterns, all of which are geometric shapes with black backgrounds and white lines, such as U-shapes, stepped shapes, striped shapes, and discrete dot shapes, reflecting the diversity of generated test patterns. The bottom row corresponds to the photolithography simulation results of each generated test pattern in the top row, presented as grayscale striped / textured images. This simulates the actual imaging effect of the pattern after photolithography exposure, development, and other processes, reflecting the pattern's performance in real-world processes, such as line blurring and contrast changes.

[0041] Figure 5 (b) shows the cluster analysis results of the generated test patterns. This part is a classification / cluster statistics and distribution visualization of a large number of generated test patterns. The left side shows the cluster statistics, listing the number of samples in 8 clusters (Cluster0 to Cluster7). Cluster0 has 559 patterns, Cluster1 has 280 patterns, which is a large proportion, while Cluster4 to Cluster7 have very few samples, only 1 to 3, reflecting the differences in the number of generated patterns of different types.

[0042] The bottom and right sides show example clustering diagrams, illustrating typical patterns of some clusters. Specifically, Cluster0 is characterized by a combination of discrete points / short lines; Cluster3 includes simple geometric shapes such as T-shapes and L-shapes; Cluster1 / 2 are characterized by a combination of multiple stripes, with different numbers and arrangements of lines; and Cluster6 is a grid-like pattern of dense points / small squares.

[0043] The dimensionality-reduced visualization scatter plot in the middle maps all generated test patterns to a two-dimensional space using dimensionality reduction algorithms such as t-SNE. Different colored points represent different clusters, and the distribution of points reflects the similarity of the generated test patterns. Generated test patterns of the same type are clustered in space with the same color, while generated test patterns of different types are dispersed, intuitively demonstrating the rationality of the clustering.

[0044] The method for generating photolithography test patterns in this embodiment is based on a denoising diffusion probability model. It utilizes the design rule information and standard cell design in the original process design kit to automatically and batch generate test patterns that meet the design rules. Then, through fast Fourier transform, it uses a density-based spatial clustering algorithm to classify and filter the generated test patterns, ultimately obtaining a concise but representative set of target test patterns.

[0045] This embodiment also provides a computer program product, a computer-readable storage medium, and a computer device. Figure 6 This is a schematic diagram of a computer program product 500 according to an embodiment of the present invention. Figure 7 This is a schematic diagram of a computer-readable storage medium 300 according to an embodiment of the present invention. Figure 8 This is a schematic diagram of a computer device 400 according to an embodiment of the present invention.

[0046] Computer program product 500 includes computer program 310, which, when executed by processor 410, implements any of the aforementioned methods for generating photolithographic test patterns. Computer-readable storage medium 300 stores the aforementioned computer program 310 thereon, which, when executed by processor 410, implements any of the aforementioned methods for generating photolithographic test patterns. Computer device 400 may include memory 420, processor 410, and computer program 310 stored in memory 420 and running on processor 410, wherein processor 410, when executing computer program 310, implements any of the aforementioned methods for generating photolithographic test patterns.

[0047] The computer program 310 used to perform the operations of the present invention may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, status setting data, integrated circuit configuration data, or source code or object code written in any combination of one or more programming languages ​​and procedural programming languages.

[0048] Computer program 310 may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0049] In some embodiments, in order to perform aspects of the present invention, electronic circuits including, for example, programmable logic circuits, field-programmable gate arrays (FPGAs) or programmable logic arrays (PLAs) can execute computer-readable program instructions to personalize the electronic circuits by utilizing state information of computer-readable program instructions.

[0050] For the purposes of this embodiment, computer program product 500 is a related product containing computer program 310. For the purposes of this embodiment, computer-readable storage medium 300 is a tangible device capable of holding and storing computer program 310, and can be any device capable of containing, storing, communicating, propagating or transmitting computer program 310 for use by or in conjunction with an instruction execution system, apparatus or device.

[0051] More specific examples (a non-exhaustive list) of computer-readable storage media 300 include the following: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable optical disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices, and any suitable combination of the foregoing.

[0052] It should be noted that the logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be specifically implemented in any machine-readable storage medium for use by, or in conjunction with, instruction execution systems, apparatuses or devices (such as computer-based systems, processor-based systems or other systems that can fetch and execute instructions from, or instruction execution systems, apparatuses or devices).

[0053] It should be understood that various parts of the present invention can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in memory and executed by a suitable instruction execution system.

[0054] Computer device 400 can be, for example, a server, desktop computer, laptop computer, tablet computer, or smartphone. In some examples, computer device 400 can be a cloud computing node. Computer device 400 can be described in the general context of computer system executable instructions (such as program modules) executed by a computer system. Typically, program modules can include routines, programs, object programs, components, logic, data structures, etc., that perform specific tasks or implement specific abstract data types. Computer device 400 can be implemented in a distributed cloud computing environment where tasks are performed by remote processing devices linked through a communication network. In a distributed cloud computing environment, program modules can reside on local or remote computing system storage media, including storage devices.

[0055] Computer device 400 may include a processor 410 adapted to execute stored instructions and a memory 420 that provides temporary storage space for the operation of instructions during operation. The processor 410 may be a single-core processor, a multi-core processor, a computing cluster, or any other configuration. The memory 420 may include random access memory (RAM), read-only memory, flash memory, or any other suitable storage system.

[0056] The processor 410 can be connected via a system interconnect (e.g., PCI, PCI-Express, etc.) to an I / O interface (input / output interface) suitable for connecting the computer device 400 to one or more I / O devices (input / output devices). I / O devices may include, for example, a keyboard and indicating devices, where indicating devices may include a touchpad or touchscreen, etc. I / O devices may be built into the computer device 400 or may be external devices connected to the computing device.

[0057] The processor 410 may also be linked via a system interconnect to a display interface suitable for connecting the computer device 400 to a display device. The display device may include a display screen as a built-in component of the computer device 400. The display device may also include an external computer monitor, television, or projector connected to the computer device 400. Furthermore, a network interface controller (NIC) may be adapted to connect the computer device 400 to a network via a system interconnect. In some embodiments, the NIC may use any suitable interface or protocol (such as an Internet Minicomputer System Interface) to transmit data. The network may be a cellular network, a radio network, a wide area network (WAN), a local area network (LAN), or the Internet, etc. Remote devices may connect to the computing device via the network.

[0058] Therefore, those skilled in the art should recognize that although numerous exemplary embodiments of the present invention have been shown and described in detail herein, many other variations or modifications conforming to the principles of the present invention can be directly determined or derived from the disclosure of the present invention without departing from the spirit and scope of the invention. Thus, the scope of the present invention should be understood and construed as covering all such other variations or modifications.

Claims

1. A method for generating lithography test patterns, comprising: constructing an initial test pattern; training a denoising diffusion probability model using the initial test pattern; generating a test pattern by combining random noise with the trained denoising diffusion probability model; and filtering the generated test pattern to obtain a target test pattern.

2. The method of claim 1, wherein the step of constructing an initial test pattern comprises: sampling and extracting a standard cell design layout provided by a process design kit of a current technology node, and taking a local pattern obtained as the initial test pattern.

3. The method of claim 1, wherein the denoising diffusion probability model adopts a U-Net architecture, and the U-Net architecture has a symmetrical layout of input, down-sampling, intermediate layer, up-sampling, and output.

4. The method of claim 3, wherein the U-Net architecture adopts a time embedding to train a noise diffusion process, and the intermediate layer adopts a self-attention mechanism layer to improve the ability of the generated test pattern to retain typical features of the initial test pattern.

5. The method of claim 3, wherein the step of training a denoising diffusion probability model using the initial test pattern comprises: randomly sampling a number of time steps from a set of time series, and assigning the number of time steps to the initial test pattern, wherein the number of time steps is less than a threshold number of time steps; adding real noise of a corresponding intensity to the initial test pattern according to the number of time steps, and calculating a pattern after adding the real noise; inputting the pattern after adding the real noise into the denoising diffusion probability model to obtain predicted noise; and calculating a gradient of a loss function according to the real noise and the predicted noise, and updating parameters of the U-Net architecture according to the gradient.

6. The method of claim 5, wherein the step of generating a test pattern by combining random noise with the trained denoising diffusion probability model comprises: continuously predicting added noise corresponding to each time step in the random noise by the denoising diffusion probability model, and updating a current state based on the predicted added noise, and obtaining the generated test pattern after iterative completion of reverse diffusion.

7. The method of claim 2, wherein the step of filtering the generated test pattern comprises: performing design rule checking on the generated test pattern according to a design rule file provided by the process design kit, and filtering out the generated test pattern that does not pass the design rule checking; and filtering out repeated patterns in the generated test pattern that passes the design rule checking.

8. The method of claim 7, wherein the step of filtering out repeated patterns in the generated test pattern that passes the design rule checking comprises: performing fast Fourier transform on the generated test pattern that passes the design rule checking; and using a density-based spatial clustering algorithm in Fourier space to perform clustering, and selecting a representative pattern from each cluster.

9. The method of claim 1, further comprising, after the step of training a denoising diffusion probability model using the initial test pattern: ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ selecting a key test pattern in the initial test pattern; adding a step of noise to the key test pattern, inputting the key test pattern after adding noise into the trained denoising diffusion probability model, and obtaining a variant test pattern of the key test pattern through reverse diffusion of the denoising diffusion probability model, and performing screening processing on the variant test pattern to obtain the target test pattern. 10.A computer device, comprising a memory, a processor, and a computer program stored in the memory and running on the processor, and when the processor executes the computer program, a photolithography test pattern generation method according to any one of claims 1 to 9 is implemented.

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