Micropore and microgroove front etching method based on chemical etching

Abstract

The invention discloses a micropore microgroove front etching method based on chemical etching, and the method comprises the steps: sequentially depositing a Si3N4 layer, a SiO2 layer and a SiOxNy layer on the surface of a silicon substrate, and enabling the Si3N4 layer, the SiO2 layer and the SiOxNy layer to serve as a micropore microgroove substrate; an inductive coupling plasma etching technology is adopted, the bias power is set to be 100-240 W, etching gas is introduced, and HMO etching is carried out on the microporous microgroove substrate; when the etching depth reaches 70%-90%, the bias power is adjusted to be 50-100 W, OE etching continues to be conducted on the micropore and microgroove substrate, and the micropore and microgroove patterned layer is obtained. According to the method, through layered deposition and two-step ICP etching, the etching morphology is remarkably improved, damage caused by physical bombardment is reduced, controllable forming of the microstructure with the high aspect ratio is achieved, and the problems that in existing ICP etching, the angle of the side wall is low, and necking or chamfering is prone to occurring are thoroughly solved.

Description

Technical Field

[0001] This invention belongs to the field of advanced packaging technology and relates to a method for front-side etching of micro-holes and micro-grooves based on chemical etching. Background Technology

[0002] With the continuous miniaturization of semiconductor devices and the rapid development of 3D integration technology, the morphology control of metal interconnect structures has become increasingly critical. In advanced packaging, microvia and microgroove processes are widely used in the manufacturing of copper interconnects, capacitor electrodes, and high aspect ratio microvia and microgroove structures due to their ability to effectively form metal wiring structures with high fill density and low defect rate. One of the key steps in microvia and microgroove processes is the etching of the dielectric layer, whose morphology directly determines the quality of subsequent metal filling and chemical mechanical polishing (CMP). To obtain a groove structure with high verticality, a flat bottom, and no residual damage, the selection and control of the etching process are particularly important.

[0003] In traditional reactive ion etching (RIE) or capacitively coupled plasma (CCP) etching methods, ion bombardment energy is high, but chemical reactivity is limited. The etched morphology is easily affected by ion orientation and residual polymers on the surface, leading to tilting, bending, or "bowing" phenomena on the trench sidewalls. Furthermore, in high aspect ratio microgrooves and micropore structures, ion energy is significantly lost at the bottom of the trench, resulting in a reduced etching rate and insufficient sidewall protection, thus affecting the final trench verticality. As feature sizes further decrease, this physical bombardment-based etching mechanism is insufficient to meet the requirements for morphological accuracy and surface quality. Inductively Coupled Plasma (ICP) systems, due to their ability to independently control radio frequency power and bias power, thereby achieving separate regulation of ion energy and plasma density, have been widely used in the field of micro- and nano-etching.

[0004] Traditional front-side etching processes are physically driven. ICP equipment has low sidewall angles for etching micro-holes and micro-grooves on the front side. When processing insulating media such as SiO2, Si3N4, and Al2O3, problems such as poor controllability of etching morphology, insufficient perpendicularity, uneven polymer accumulation, and bottom morphology defects are often caused by ion bombardment. Summary of the Invention

[0005] The purpose of this invention is to provide a method for etching the front side of micro-holes and micro-grooves based on chemical etching, which solves the problem of low sidewall angles when etching the front side of micro-holes and micro-grooves in existing ICP equipment.

[0006] To achieve the above objectives, the present invention employs the following technical solution: A method for front-side etching of micropores and microgrooves based on chemical etching, comprising: Si3N4, SiO2, and SiO2 layers were sequentially deposited on the surface of a silicon substrate.x N y The layer serves as a microporous and microgroove substrate; Inductively coupled plasma etching technology was used, with a bias power of 100~240W and etching gas introduced to perform HMO etching on the micro-hole and micro-groove substrate. When the etching depth reaches 70%~90%, the bias power is adjusted to 50~100W, and OE etching is continued on the micro-hole and micro-groove substrate to obtain the micro-hole and micro-groove patterned layer.

[0007] Furthermore, the Si3N4 layer, SiO2, and SiO x N y The layer was deposited using the PECVD deposition process.

[0008] Furthermore, the etching gases include CF4, CHF3, C4F8, C4F6, and auxiliary gases.

[0009] Furthermore, the auxiliary gases include O2 and Ar.

[0010] Furthermore, during the HMO etching process, the power is 1800~3000W and the pressure inside the chamber is 20~40mT.

[0011] Furthermore, during the HMO etching process, the etching gas flow rates are as follows: CF4 gas flow rate is 115~173 sccm, Ar gas flow rate is 200~300 sccm, and O2 gas flow rate is 30~50 sccm.

[0012] Furthermore, the single-step time for HMO etching is 280~420s.

[0013] Furthermore, during the OE etching process, the power is 2000~2800W and the pressure inside the chamber is 10~20mT.

[0014] Furthermore, during the OE etching process, the etching gas flow rates are as follows: CF4 gas flow rate is 150~220 sccm, O2 flow rate is 20~40 sccm, and Ar flow rate is 100~200 sccm.

[0015] Furthermore, the OE etching single-step time is 60~150s.

[0016] Compared with the prior art, the present invention has the following beneficial effects: This invention provides a method for front-side etching of micropores and microgrooves based on chemical etching, which involves sequentially depositing Si3N4, SiO2, and SiO2 layers on the surface of a silicon substrate. x N yA layer is used as the substrate for microporous microgrooves; then, inductively coupled plasma etching (ICP-E) is employed with a bias power of 100–240 W, and etching gas is introduced to perform HMO etching on the microporous microgrooves substrate. The low bias power of 100–240 W used in the HMO etching stage significantly reduces the physical sputtering effect of ion bombardment, making the etching primarily driven by F radical chemical reactions, while simultaneously... x F y Free radicals form a uniform fluorocarbon polymer layer, effectively protecting the sidewalls from lateral etching. When the etching depth reaches 70%~90%, the bias power is adjusted to 50~100W, and OE etching continues on the microporous and microgrooved substrate to obtain a patterned microporous and microgrooved layer. During the OE etching stage, the bias power is further reduced (50~100W) to precisely control the sidewall angle, ensuring a smooth transition in etching rate and avoiding abrupt changes in depth. This invention employs a layered deposition + two-step ICP etching process, which is simple and requires no additional rework or auxiliary processes, significantly improving etching efficiency compared to traditional multi-step etching. Using an ICP process primarily based on chemical etching, the concentration of free radicals and the formation rate of the sidewall polymer layer are controlled by optimizing the etching gas ratio and chamber pressure. An appropriate amount of fluorocarbon free radicals can form a self-limiting polymer protective layer on the sidewalls, inhibiting lateral etching. Meanwhile, oxygen free radicals can moderately remove excess polymer layers, maintaining the continuity of bottom etching. By reducing the bias power and making the ion energy moderate, the etching process relies more on chemical reactions, resulting in trench structures with high verticality and smooth sidewalls. Furthermore, the high-frequency excitation provided by the inductively coupled coil in the ICP system significantly increases plasma density, allowing for more complete chemical reactions and maintaining a high etching rate even at lower bias voltages. This invention not only significantly improves the etching morphology and reduces damage from physical bombardment, but also enables controllable shaping of high aspect ratio microstructures, completely solving the problems of low sidewall angles and easy necking or chamfering in existing ICP etching, meeting the high-precision structural requirements of 3D integration, microchannels, and other scenarios. Simultaneously, it significantly improves the electrical performance and long-term reliability of devices, with strong process versatility and controllable cost, providing an efficient and reliable industrial solution for wafer-level front-side micro-hole and micro-groove etching, meeting the requirements of next-generation chip manufacturing processes such as power devices, MEMS, and 3D integration, and possessing significant industrial application value and technological promotion significance. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1This is an etching effect diagram of Embodiment 1 of the present invention, wherein the SiO2 layer deposition temperature is 180°C.

[0019] Figure 2 This is an etching effect diagram of Embodiment 1 of the present invention, wherein the SiO2 layer deposition temperature is 400°C. Detailed Implementation

[0020] To enable those skilled in the art to understand the features and effects of the present invention, the terms and expressions used in the specification and claims are explained and defined in general below. Unless otherwise specified, all technical and scientific terms used herein have the ordinary meaning understood by those skilled in the art regarding the present invention, and in case of conflict, the definitions in this specification shall prevail.

[0021] The theories or mechanisms described and disclosed herein, whether right or wrong, should not in any way limit the scope of the invention, that is, the contents of the invention can be implemented without being limited by any particular theory or mechanism.

[0022] In this document, all features defined by numerical ranges or percentage ranges, such as numerical values, quantities, contents, and concentrations, are for the sake of brevity and convenience only. Accordingly, descriptions of numerical ranges or percentage ranges should be considered as covering and specifically disclosing all possible sub-ranges and individual numerical values ​​(including integers and fractions) within those ranges.

[0023] In this article, unless otherwise specified, “contains,” “includes,” “containing,” “has,” or similar terms cover the meanings of “composed of” and “mainly composed of,” for example, “A contains a” covers the meanings of “A contains a and others” and “A contains only a.”

[0024] For the sake of brevity, not all possible combinations of the technical features in each implementation scheme or embodiment are described herein. Therefore, as long as there is no contradiction in the combination of these technical features, the technical features in each implementation scheme or embodiment can be combined arbitrarily, and all possible combinations should be considered within the scope of this specification.

[0025] The present invention will be further illustrated below with reference to specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. Furthermore, it should be understood that after reading the teachings of this invention, those skilled in the art can make various alterations or modifications to the invention, and these equivalent forms also fall within the scope defined by the appended claims.

[0026] The following examples use instruments and equipment conventional in the art. Experimental methods in the following examples, unless otherwise specified, are generally performed under conventional conditions or as recommended by the manufacturer. All raw materials used in the following examples are conventional commercially available products with specifications conventional in the art. In this specification and the following examples, unless otherwise specified, "%" refers to weight percentage, "parts" refers to parts by weight, and "ratio" refers to weight proportion.

[0027] The present invention will now be described in further detail with reference to the accompanying drawings: This invention provides a method for front-side etching of micro-holes and micro-grooves based on chemical etching. It employs inductively coupled plasma etching (ICP Etching) technology, using low bias power to reduce particle bombardment energy and achieve etching primarily through F-radical chemical reactions. Combined with dynamic parameter adjustment, it achieves high verticality etching of the sidewalls of the front-side micro-holes and micro-grooves. Specifically, it includes the following steps: S1: Microporous and microgroove substrate deposition A Si3N4 layer is deposited on the silicon substrate as a stop layer to halt etching at the Si3N4 layer, which has a very stable chemical structure. Commonly used etching gases include fluorine-containing gases such as CF4, CHF3, C4F8, and C4F6 (used for SiO2 etching), as well as O2 and Ar auxiliary gases. These gases exhibit high etching rates for SiO2 but show almost no reaction with Si3N4, thus achieving etching cessation. A SiO2 layer is then deposited on the Si3N4 layer as a micro-via / micro-groove patterning layer to transfer patterns from the photoresist onto the SiO2 layer. A SiO2 layer is then deposited on the SiO2 layer surface. x N y As a dielectric anti-reflective coating (DARC), its function is to suppress reflection interference during the photolithography process, improve pattern resolution and etching consistency. At the same time, the DARC layer can also serve as an etching barrier layer to prevent the photoresist from reacting directly with the plasma, suppress the excessive etching of the underlying medium by etching gases such as O2 and CF4, and maintain the sidewall morphology of micro-holes or micro-grooves.

[0028] S2: Front-side micro-hole and micro-groove HMO etching Inductively Coupled Plasma (ICP) etching technology is employed. The ICP system generates an alternating magnetic field through an upper electrode coil, inducing a high-density electron pool, thereby effectively exciting the etching gas to form plasma. During ICP etching, the power is set to 1800–3000 W, the bias power to 100–240 W, and the chamber pressure to 20–40 mT. Etching gases are introduced at flow rates of 115–173 sccm for CF4, 200–300 sccm for Ar, and 30–50 sccm for O2, with a single step time of 280–420 s for HMO etching. When the bias power is set lower, the ion energy is controlled, significantly reducing ion bombardment energy, and the etching reaction shifts from physical sputtering to a chemical reaction primarily involving free radicals. At this point, a large number of reactive neutral particles (such as F and CF2) generated in the plasma react chemically with the material surface to produce volatile products, achieving material removal. Simultaneously, C… x F y Free radicals form a fluorocarbon polymer layer to protect the sidewalls. This chemically-driven etching method not only significantly reduces damage from physical bombardment but also enhances the isotropy and morphology controllability of the etching process, making it suitable for etching highly vertical micro-hole and micro-groove structures.

[0029] S3: Front-side microgroove and micro-via OE etching During the etching process of micro-holes and micro-grooves on the front side, the deep hole angle needs to be controlled by adjusting the power, bias power, single-step time, and gas flow rate when the etching depth reaches 70%~90%. In this step, the power is adjusted to 2000~2800W, the bias power to 50~100W, the chamber pressure to 10~20mT, the O2 flow rate to 20~40sccm, the Ar flow rate to 100~200sccm, the CF4 flow rate to 150~220sccm, and the single-step time to 60~150s. The power affects the plasma energy, the gas flow rate determines the etching rate, the bias power affects the ion bombardment direction and intensity, determining anisotropy, and the single-step time determines the etching depth of each step. Using the adjusted parameters, OE etching is continued on the micro-hole and micro-grooves substrate to obtain a patterned layer of micro-holes and micro-grooves.

[0030] This invention utilizes inductively coupled plasma etching (ICP) technology, combining high chemical etching with low physical bombardment, and dynamically adjusts power, bias power, and gas flow rate to achieve high verticality in the front-side etching of micro-holes and micro-grooves. The core principle lies in the fact that, under low bias power, the physical bombardment effect of Ar is significantly lower than the reactive etching effect of F radicals. The ratio and concentration of C and F radicals within the chamber are controlled by process parameters such as gas flow rate and power. Through the synergistic effect of this mechanism, this invention solves the problem of low sidewall angles in front-side micro-hole and micro-groove etching using existing ICP equipment, providing an efficient and reliable angle control solution for wafer-level front-side micro-hole and micro-groove etching.

[0031] This invention achieves a highly vertical front-side etching process for micro-holes and micro-grooves, primarily using chemical etching, by continuously reducing bias power and dynamically adjusting process parameters. The optimized sidewall angle improves the uniformity of the PVD-deposited seed layer, reduces thin areas or voids at the bottom of the holes or lower sidewalls, and enhances the density of subsequent electroplating. The uniform seed layer and dense electroplated copper fill reduce signal transmission delay and power consumption, improving the long-term reliability of the 3D integrated system.

[0032] The technical solution of the present invention will be further described in detail below through specific embodiments: Example 1: S1: A 150nm thick Si3N4 layer is deposited on the front side of the wafer as a stop layer to stop the etching process. A 2μm thick SiO2 layer is deposited on the surface of the Si3N4 layer as a micro-hole / micro-groove patterning layer to transfer the pattern from the photoresist onto the SiO2 layer. An 80nm thick SiO2 layer is then deposited on the surface of the SiO2 layer. x N y As a dielectric antireflective layer for DARC.

[0033] S2: Inductively Coupled Plasma (ICP) etching is performed with a power of 2800W, a bias power of 200W, and a chamber pressure of 35mT. Etching gases are introduced at a flow rate of 160 sccm for CF4, 280 sccm for Ar, and 45 sccm for O2, with a single step time of 400s for HMO etching.

[0034] S3: The SiO2 patterned layer etching depth reaches 70% of the target total depth, and a preliminary fluorocarbon polymer layer is formed on the sidewalls for protection, with no obvious physical bombardment damage. The power is adjusted to 2600W, the bias power to 80W, the chamber pressure to 18mT, the O2 flow rate to 35sccm, the Ar flow rate to 180sccm, the CF4 flow rate to 200sccm, and the single-step time to 60s. Using the adjusted parameters, OE etching is continued on the micro-hole and micro-groove substrate to obtain the micro-hole and micro-groove patterned layer.

[0035] Example 2: S1: A 120nm thick Si3N4 layer is deposited on the front side of the wafer as a stop layer to stop the etching process. A 1.5μm thick SiO2 layer is deposited on the surface of the Si3N4 layer as a micro-hole / micro-groove patterning layer to transfer the pattern from the photoresist onto the SiO2 layer. A 60nm thick SiO2 layer is deposited on the surface of the SiO2 layer. x N y As a dielectric antireflective layer for DARC.

[0036] S2: Inductively Coupled Plasma (ICP) etching is performed with a power of 2200W, a bias power of 150W, and a chamber pressure of 28mT. Etching gases are introduced at a flow rate of 140 sccm for CF4, 240 sccm for Ar, and 38 sccm for O2, with a single step time of 350s for HMO etching.

[0037] S3: The SiO2 patterned layer etching depth reaches 80% of the target total depth. The power is adjusted to 2400W, the bias power to 60W, the cavity pressure to 15mT, the O2 flow rate to 30sccm, the Ar flow rate to 150sccm, the CF4 flow rate to 180sccm, and the single-step time to 100s. Using the adjusted parameters, OE etching is continued on the micro-hole and micro-groove substrate to obtain the micro-hole and micro-groove patterned layer.

[0038] Example 3: S1: A 180nm thick Si3N4 layer is deposited on the front side of the wafer as a stop layer to stop the etching process. A 2.5μm thick SiO2 layer is deposited on the surface of the Si3N4 layer as a micro-hole / micro-groove patterning layer to transfer the pattern from the photoresist onto the SiO2 layer. A 90nm thick SiO2 layer is deposited on the surface of the SiO2 layer. x N y As a dielectric antireflective layer for DARC.

[0039] S2: Inductively Coupled Plasma (ICP) etching is performed with a power of 1900W, a bias power of 120W, and a chamber pressure of 22mT. Etching gases are introduced at a flow rate of 120 sccm for CF4, 210 sccm for Ar, and 32 sccm for O2, with a single step time of 400s for HMO etching.

[0040] S3: The SiO2 patterned layer etching depth reaches 90% of the target total depth. The power is adjusted to 2000W, the bias power to 50W, the cavity pressure to 12mT, the O2 flow rate to 25sccm, the Ar flow rate to 120sccm, the CF4 flow rate to 150sccm, and the single-step time to 150s. Using the adjusted parameters, OE etching is continued on the micro-hole and micro-groove substrate to obtain the micro-hole and micro-groove patterned layer.

[0041] Example 4: S1: A 160nm thick Si3N4 layer is deposited on the front side of the wafer as a stop layer to stop the etching process. A 1.8μm thick SiO2 layer is deposited on the surface of the Si3N4 layer as a micro-hole / micro-groove patterning layer to transfer the pattern from the photoresist onto the SiO2 layer. A 70nm thick SiO2 layer is deposited on the surface of the SiO2 layer. x N y As a dielectric antireflective layer for DARC.

[0042] S2: Inductively Coupled Plasma (ICP) etching is performed with a power of 3000W, a bias power of 240W, and a chamber pressure of 40mT. Etching gases are introduced: CF4 gas flow rate of 173sccm, Ar gas flow rate of 300sccm, and O2 gas flow rate of 50sccm. The single-step time is 420s for HMO etching.

[0043] S3: The SiO2 patterned layer etching depth reaches 75% of the target total depth. The power is adjusted to 2800W, the bias power to 100W, the cavity pressure to 20mT, the O2 flow rate to 40sccm, the Ar flow rate to 200sccm, the CF4 flow rate to 220sccm, and the single-step time to 120s. Using the adjusted parameters, OE etching is continued on the micro-hole and micro-groove substrate to obtain the micro-hole and micro-groove patterned layer.

[0044] Example 5: S1: A 140nm thick Si3N4 layer is deposited on the front side of the wafer as a stop layer to stop the etching process. A 2.2μm thick SiO2 layer is deposited on the surface of the Si3N4 layer as a micro-hole / micro-groove patterning layer to transfer the pattern from the photoresist onto the SiO2 layer. An 85nm thick SiO2 layer is deposited on the surface of the SiO2 layer. x N y As a dielectric antireflective layer for DARC.

[0045] S2: Inductively Coupled Plasma (ICP) etching is performed with a power of 2500W, a bias power of 180W, and a chamber pressure of 30mT. Etching gases are introduced at a flow rate of 150 sccm for CF4, 250 sccm for Ar, and 40 sccm for O2, with a single step time of 380s for HMO etching.

[0046] S3: The SiO2 patterned layer etching depth reaches 85% of the target total depth. The power is adjusted to 2500W, the bias power to 70W, the cavity pressure to 16mT, the O2 flow rate to 32sccm, the Ar flow rate to 160sccm, the CF4 flow rate to 170sccm, and the single-step time to 90s. Using the adjusted parameters, OE etching is continued on the micro-hole and micro-groove substrate to obtain the micro-hole and micro-groove patterned layer.

[0047] Example 6: S1: A 110nm thick Si3N4 layer is deposited on the front side of the wafer as a stop layer to stop the etching process. A 1.2μm thick SiO2 layer is deposited on the surface of the Si3N4 layer as a micro-hole / micro-groove patterning layer to transfer the pattern from the photoresist onto the SiO2 layer. A 55nm thick SiO2 layer is deposited on the surface of the SiO2 layer. x N y As a dielectric antireflective layer for DARC.

[0048] S2: Inductively Coupled Plasma (ICP) etching is performed with a power of 1800W, a bias power of 100W, and a chamber pressure of 20mT. Etching gases are introduced at a flow rate of 115 sccm for CF4, 200 sccm for Ar, and 30 sccm for O2, with a single step time of 280s for HMO etching.

[0049] S3: The SiO2 patterned layer etching depth reaches 70% of the target total depth. The power is adjusted to 2100W, the bias power to 55W, the cavity pressure to 10mT, the O2 flow rate to 20sccm, the Ar flow rate to 110sccm, the CF4 flow rate to 160sccm, and the single-step time to 115s. Using the adjusted parameters, OE etching is continued on the micro-hole and micro-groove substrate to obtain the micro-hole and micro-groove patterned layer.

[0050] Example 7: S1: A 130nm thick Si3N4 layer is deposited on the front side of the wafer as a stop layer to stop the etching process. A 1.6μm thick SiO2 layer is deposited on the surface of the Si3N4 layer as a micro-hole / micro-groove patterning layer to transfer the pattern from the photoresist onto the SiO2 layer. A 65nm thick SiO2 layer is deposited on the surface of the SiO2 layer. x N y As a dielectric antireflective layer for DARC.

[0051] S2: Inductively Coupled Plasma (ICP) etching is performed with a power of 2100W, a bias power of 160W, and a chamber pressure of 25mT. Etching gases are introduced at a flow rate of 130 sccm for CF4, 220 sccm for Ar, and 35 sccm for O2, with a single step time of 310 s for HMO etching.

[0052] S3: The SiO2 patterned layer etching depth reaches 72% of the target total depth. The power is adjusted to 2300W, the bias power to 75W, the cavity pressure to 14mT, the O2 flow rate to 28sccm, the Ar flow rate to 140sccm, the CF4 flow rate to 175sccm, and the single-step time to 130s. Using the adjusted parameters, OE etching is continued on the micro-hole and micro-groove substrate to obtain the micro-hole and micro-groove patterned layer.

[0053] Example 8: S1: A 170nm thick Si3N4 layer is deposited on the front side of the wafer as a stop layer to stop the etching process. A 2.1μm thick SiO2 layer is deposited on the surface of the Si3N4 layer as a micro-hole / micro-groove patterning layer to transfer the pattern from the photoresist onto the SiO2 layer. An 82nm thick SiO2 layer is deposited on the surface of the SiO2 layer. x N y As a dielectric antireflective layer for DARC.

[0054] S2: Inductively Coupled Plasma (ICP) etching is performed with a power of 2700W, a bias power of 210W, and a chamber pressure of 32mT. Etching gases are introduced at a flow rate of 155 sccm for CF4, 270 sccm for Ar, and 42 sccm for O2, with a single step time of 390s for HMO etching.

[0055] S3: The SiO2 patterned layer etching depth reaches 88% of the target total depth. The power is adjusted to 2600W, the bias power to 90W, the cavity pressure to 17mT, the O2 flow rate to 36sccm, the Ar flow rate to 180sccm, the CF4 flow rate to 195sccm, and the single-step time to 145s. Using the adjusted parameters, OE etching is continued on the micro-hole and micro-groove substrate to obtain the micro-hole and micro-groove patterned layer.

[0056] like Figure 1 and Figure 2 As shown, the oxide layer was etched using Example 1 of the present invention, wherein the deposition temperature of the SiO2 layer was 180℃ and 400℃ respectively. It can be seen that under different deposition temperature conditions, the front etching process of micropores and microgrooves based on chemical etching can obtain good etching morphology, which proves that the etching method of the present invention has good versatility.

[0057] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for front etching of micro-holes and micro-slots based on chemical etching, characterized in that, The method comprises the following steps: Depositing Si3N4 layer, SiO2 and SiO on the surface of silicon substrate in sequence x N y layer as microporous microgroove substrate An inductively coupled plasma etching technology is adopted, a bias power of 100-240 W is set, etching gas is introduced, and HMO etching is performed on the microporous microgroove substrate; When the etching depth reaches 70%-90%, the bias power is adjusted to 50-100 W, OE etching is continuously performed on the microporous microgroove substrate, and a microporous microgroove patterned layer is obtained.

2. The method according to claim 1, wherein the method is a chemical etching-based micro-hole and micro-groove front etching method, characterized in that, Si3N4 layer, SiO2 and SiO x N y Layers are deposited using a PECVD deposition process.

3. The method according to claim 1, wherein the method is a chemical etching based micro-hole and micro-groove front etching method, characterized in that, The etching gas comprises CF4, CHF3, C4F8, C4F6 and auxiliary gas.

4. The method according to claim 3, wherein the method is a chemical etching-based micro-hole and micro-groove front etching method. The auxiliary gas comprises O2 and Ar.

5. The method according to claim 1, wherein the method is a chemical etching based micro-hole and micro-groove front etching method, characterized in that, During the HMO etching process, the power is 1800-3000 W, and the cavity pressure is 20-40 mT.

6. The method according to claim 1, wherein the method is a chemical etching based micro-hole and micro-groove front etching method. During the HMO etching process, the etching gas flow rate is as follows: the CF4 gas flow rate is 115-173 sccm, the Ar gas flow rate is 200-300 sccm, and the O2 gas flow rate is 30-50 sccm.

7. The method according to claim 1, wherein the method is a chemical etching based micro-hole and micro-groove front etching method. The single-step time of the HMO etching is 280-420 s.

8. The method according to claim 1, wherein the method is a chemical etching based micro-hole and micro-groove front etching method. During the OE etching process, the power is 2000-2800 W, and the cavity pressure is 10-20 mT.

9. The method according to claim 1, wherein the method is a chemical etching based micro-hole and micro-groove front etching method. During the OE etching process, the etching gas flow rate is as follows: the CF4 gas flow rate is 150-220 sccm, the O2 flow rate is 20-40 sccm, and the Ar flow rate is 100-200 sccm.

10. The method according to claim 1, wherein the method is a chemical etching-based micro-hole and micro-groove front etching method. The single-step time of the OE etching is 60-150 s.

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