Unblocking control method and related device

Abstract

The invention provides a deblocking control method and a related device, and relates to the field of inverter overcurrent protection. According to the method and the device, after the wave sealing operation of the inverter is executed, if the unsealing working condition exists, the wave sealing state of the inverter is released at the unsealing moment in the first time period. The first time period is a time period in which the switching tube frequency of the inverter is equal to a specified switching tube frequency after the wave sealing state is removed, and the specified switching tube frequency is greater than or equal to the original switching tube frequency of the inverter and is less than or equal to the maximum switching frequency tolerable by a switching tube in the inverter; when the wave sealing state is removed according to a deblocking moment in the first time period, the switching frequency of the switching tube can be within the tolerable switching frequency of the switching tube, the high switching frequency of the switching tube is avoided, and the problem of switching tube failure caused by the fact that the thermal stress of the device exceeds the standard is further avoided.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of inverter over-current protection, and more particularly, to a method for controlling unblocking and related devices. BACKGROUND

[0002] In the field of photovoltaic systems or photovoltaic storage systems, an inverter over-current protection strategy is configured. When it is detected that the current exceeds the set protection threshold, a blocking event is triggered. After blocking, when the current does not exceed the set protection threshold, an unblocking event is triggered.

[0003] When the blocking event or the unblocking event is executed, the switching tube is controlled to be forced off or turned on. If the blocking event and the unblocking event are executed multiple times, the switching frequency of the switching tube is high, which may cause the thermal stress of the device to exceed the standard and cause the switching tube to fail. SUMMARY

[0004] Therefore, the present application provides a method for controlling unblocking and related devices to solve the problem that if the blocking event and the unblocking event are executed multiple times, the switching frequency of the switching tube is high, which may cause the thermal stress of the device to exceed the standard and cause the switching tube to fail.

[0005] To solve the above technical problems, the present application adopts the following technical solutions:

[0006] In a first aspect, the present application discloses a method for controlling unblocking, comprising:

[0007] performing a blocking action of an inverter;

[0008] in response to an unblocking condition of the inverter, releasing the blocking state of the inverter at an unblocking time within a first time period; the first time period is a time period in which the switching frequency of the inverter is equal to a specified switching frequency after the blocking state is released, the specified switching frequency is greater than or equal to the original switching frequency of the inverter, and less than or equal to the maximum switching frequency that the switching tube in the inverter can tolerate.

[0009] Optionally, the releasing of the blocking state of the inverter at the unblocking time within the first time period comprises:

[0010] determining an unblocking time within the first time period;

[0011] releasing the blocking state of the inverter at the unblocking time.

[0012] Optionally, the determining of the unblocking time within the first time period comprises:

[0013] determining the first time period;

[0014] determining a time within the first time period as the unblocking time.

[0015] Optionally, the specified switching tube frequency is an original switching tube frequency, and the determining the first time period comprises:

[0016] taking a switching tube off time period after the unblocking condition of the inverter occurs as the first time period.

[0017] Optionally, the determining the first time period comprises:

[0018] acquiring a second time period; the second time period is a delay unblocking time period after the unblocking condition occurs;

[0019] calculating a sum of the unblocking condition occurrence time and the second time period to obtain the first time period.

[0020] Optionally, the specified switching tube frequency is n times of the original switching tube frequency, the n times of the original switching tube frequency is less than or equal to a maximum switching frequency that a switching tube in the inverter can tolerate, and n is a positive integer greater than 1.

[0021] The determining the unblocking time point in the first time period comprises:

[0022] in a case where the n times is two, taking an earliest time point of a zero-crossing point and a vertex point of a carrier signal of the switching tube in the inverter as the unblocking time point in the first time period; the zero-crossing point and the vertex point are located after the unblocking condition of the inverter.

[0023] Optionally, the determining the unblocking time point in the first time period further comprises:

[0024] in a case where the n times is a value other than two, taking one of a zero-crossing point and a vertex point of a frequency multiplication signal of the carrier signal of the switching tube in the inverter, or an earliest time point of the zero-crossing point and the vertex point as the unblocking time point in the first time period; the zero-crossing point and the vertex point are located after the unblocking condition of the inverter.

[0025] Optionally, before taking the zero-crossing point and the vertex point of the carrier signal of the switching tube in the inverter as the unblocking time point in the first time period, the unblocking control method further comprises:

[0026] in a case where a total switching off number of the switching tube in the inverter is less than a total switching off number threshold of the switching tube, taking the zero-crossing point and the vertex point of the carrier signal of the switching tube in the inverter as the unblocking time point in the first time period.

[0027] In a second aspect, the application discloses an inverter for performing the above-mentioned unblocking control method.

[0028] In a third aspect, the application discloses a light storage system comprising the above-mentioned inverter.

[0029] Optionally, the DC side of the inverter is connected with a photovoltaic module and an energy storage battery, and the AC side of the inverter is connected with a power grid and / or a load.

[0030] In a fourth aspect, the application discloses a photovoltaic system comprising the above-mentioned inverter.

[0031] The application provides an unblocking control method and related devices. In the application, after performing a blocking action of an inverter, if there is an unblocking condition, the blocking state of the inverter is released at an unblocking time in a first time period. The first time period is a time period during which the switching tube frequency of the inverter is equal to a specified switching tube frequency after the blocking state is released. The specified switching tube frequency is greater than or equal to the original switching tube frequency of the inverter and less than or equal to the maximum switching frequency that the switching tube can tolerate. When the blocking state is released at the unblocking time in the first time period, the switching frequency of the switching tube can be within the switching frequency that the switching tube can tolerate, avoiding a high switching frequency of the switching tube, and thus avoiding a switching tube failure problem caused by excessive thermal stress of the device. BRIEF DESCRIPTION OF DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the application or the related art, the following will briefly introduce the drawings needed to be used in the embodiment or the related art description. Obviously, the drawings in the following description are only embodiments of the application, and for those skilled in the art, other drawings can also be obtained without creative labor based on the provided drawings.

[0033] Figure 1 A flowchart of an unblocking control method provided by an embodiment of the application;

[0034] Figure 2 A waveform schematic diagram of an unblocking control method provided by an embodiment of the application;

[0035] Figure 3 A waveform schematic diagram of another unblocking control method provided by an embodiment of the application;

[0036] Figure 4 A waveform schematic diagram of still another unblocking control method provided by an embodiment of the application;

[0037] Figure 5 A waveform schematic diagram of yet another unblocking control method provided by an embodiment of the application;

[0038] Figure 6 A waveform diagram of a fifth unblocking control method provided for an embodiment of the present application is shown in FIG. 6.

[0039] Figure 7 A waveform diagram of a sixth unblocking control method provided for an embodiment of the present application is shown in FIG. 7.

[0040] Figure 8 A flow chart of another unblocking control method provided for an embodiment of the present application is shown in FIG. 8.

[0041] Figure 9 A schematic diagram of a light storage system provided for an embodiment of the present application is shown in FIG. 9. DETAILED DESCRIPTION

[0042] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0043] In the field of photovoltaic systems or light storage systems, an inverter overcurrent protection strategy is configured. When the current is detected to exceed the set protection threshold, a blocking or shutdown event is triggered.

[0044] Specifically, the inverter overcurrent protection strategy in the current photovoltaic or light storage system usually uses a double protection design of hardware + software. For the hardware protection mode, the hardware circuit sets multiple current protection points for blocking operation or shutdown operation. In an embodiment, the typical number of stages is 2, and when the current reaches the 1st protection point, a blocking event is triggered, at which time the IGBT (Insulate-Gate Bipolar Transistor) / MOS (Metal-Oxide-Semiconductor Field-Effect Transistor) switch stops wave, and when the current drops below the 1st protection point, an unblocking event is triggered to release the blocking. If the current reaches the 2nd protection point, a shutdown event is triggered, and the device is shut down. For the software protection mode, the software protection logic can also set multiple current protection points, and when the current is detected to exceed the set protection threshold, a blocking or shutdown event is triggered.

[0045] After triggering the clamping event, the switch tube is controlled to be forced to be turned off, and after the current drops to the first protection point, the switch tube is controlled to be forced to be turned on. Generally, the switch frequency of the normal operating device switch tube is a pre-set frequency (also referred to as an original switch tube frequency), for example, 16 kHz (62.5 us), so that the switch tube performs one turn-on and one turn-off within one switching cycle (62.5 us). However, if the clamping event is triggered, the hardware circuit or the software algorithm controls the switch tube to be forced to be turned off or turned on, which breaks the set switch tube switching frequency, and in a serious case, causes the device thermal stress to exceed the standard, and causes the switch tube to fail.

[0046] To this end, in the embodiments of the present application, a kind of unclamping control method and related device are provided, and in the present application, after executing the clamping action of inverter, if there is unclamping condition, the clamping state of the inverter is released at one unclamping time in the first time period.The first time period is: after executing the release of clamping state, the switching frequency of the inverter is equal to the specified switching frequency of the switching tube, the specified switching frequency is greater than or equal to the original switching frequency of the inverter, and less than or equal to the maximum switching frequency of the switching tube in the inverter, then according to the first time period, the switching frequency of the switching tube can be released in the clamping state at one unclamping time, so that the switching frequency of the switching tube is within the switching frequency that the switching tube can withstand, to avoid the switching frequency of the switching tube being too high, and to avoid the switching tube failure problem caused by the device thermal stress exceeding the standard.

[0047] On the basis of the above, an embodiment of the present application provides a kind of unclamping control method, the execution subject can be inverter, which can be inverter in photovoltaic system or light storage system. Figure 1 , unclamping control method can include:

[0048] S11, execute the clamping action of inverter.

[0049] In actual scenario, in the overcurrent protection strategy of inverter, whether it is hardware protection mode or software protection mode, after current reaches current threshold, such as first protection point, clamping event is triggered, and at this time, the clamping action of inverter is executed.When executing clamping action, control IGBT / MOS, etc. Switch tube stops wave, and current value drops to protect equipment safety.In one clamping scenario, after current reaches first protection point, inverter will detect wave-by-wave clamping signal, and switch tube will be clamped immediately, and when clamping, the timing of inner and outer tube clamping is considered, for example, I type NPC (Neutral Point Clamped, Neutral Point Clamped) circuit, at this time, outer tube can be clamped first, and then inner tube is clamped.

[0050] S12, in response to the unclamping condition of the inverter, the clamping state of the inverter is released at one unclamping time in the first time period.

[0051] In this embodiment, if the current does not drop below the first protection point, the inverter does not detect the unblocking signal, and the blocking state is maintained. When the current drops below the first protection point, i.e. the current value is less than the current threshold, the inverter detects the unblocking signal, and the inverter is in the unblocking working condition. At this time, the unblocking operation is not performed immediately, but is delayed. The delay unblocking refers to delaying a period of time before the inverter is in the unblocking working condition. The specific delay time can be configured according to actual conditions. During the delay unblocking time period, the inverter is still in the blocking state.

[0052] In an embodiment, when the unblocking is delayed, a unblocking time point needs to be selected. The unblocking time point in this embodiment is a unblocking time point in the first time period.

[0053] The first time period is a time period during which the switching tube frequency of the inverter is equal to the specified switching tube frequency after the blocking state is released. The specified switching tube frequency is greater than or equal to the original switching tube frequency of the inverter, and less than or equal to the maximum switching frequency that the switching tube can withstand in the inverter.

[0054] Specifically, when the unblocking is delayed, a minimum blocking time can be set. After the switching tube operates once, it will not operate again for a short time to avoid frequent operation of the switching tube. For example, after the switching tube is turned off, it is not allowed to be turned on within 5us to avoid the problem of switching tube function failure caused by high switching frequency of the switching tube.

[0055] The implementation schematic diagram is as shown in Figure 2 The abscissa is time T, and the ordinate is the level signal. Figure 2

[0056] In the normal output driving process, the switching frequency is determined by a carrier signal, such as a PWM (Pulse width modulation, pulse width modulation) carrier signal (which can be a triangular carrier signal). The switching tube can be configured to be turned on in high level or low level. In actual implementation, the PWM carrier signal can be compared with a fixed comparison value CMP used for driving control. If the signal value of the PWM carrier signal is greater than the comparison value CMP, a high level is output, otherwise a low level is output. Alternatively, if the signal value of the PWM carrier signal is less than the comparison value CMP, a high level is output, otherwise a low level is output. In this embodiment, the high level and the low level constitute a PWM driving signal, which is used to control the switching tube to perform corresponding actions.

[0057] ​Taking the high-level conduction mode of the switch tube as an example, in the process of outputting the PWM drive signal in the above-mentioned manner, if the actual current Iac is greater than the first level protection point Ith, at this time the switch tube will immediately be blocked, the PWM drive signal output is low to realize the blocking operation, and during the blocking period, the PWM drive signal always remains low, at this time the inverter is always in the blocking state, the switch tube stops emitting waves, and until Iac is less than Ith, the blocking release operation is performed, the PWM drive signal is converted to high level, and the switch tube is turned on. The current blocking and unblocking waveform of the specific PWM drive signal refers to the "hardware wave-by-wave signal" in Figure 2 , and the PWM drive signal is low when the switch tube is blocked. When Iac is less than Ith, the blocking release operation is performed. At this time, the PWM drive signal is adjusted from the "normal output drive (i.e. no blocking and unblocking operation)" PWM drive waveform to the PWM drive waveform in the "wave-by-wave output drive signal (blocking and unblocking operation exists)".

[0058] On this basis, in order to avoid the switch tube from acting too fast, the wave-by-wave blocking minimum time can be limited, and the delay unblocking operation is performed. Even if the unblocking signal is received within the wave-by-wave blocking minimum time, the unblocking operation is not performed, and until the wave-by-wave blocking minimum time is reached, the PWM drive signal is adjusted to high level, at this time the unblocking operation is performed, and the PWM drive signal is adjusted from the "normal output drive (i.e. no blocking and unblocking operation)" PWM drive waveform to the "wave-by-wave signal considering delay unblocking (blocking and unblocking operation exists, and delay unblocking)" PWM drive waveform. The PWM drive signal waveform of all periods refers to the "output drive considering delay unblocking" in Figure 2 .

[0059] Figure 2 In the above-mentioned manner, T0 is the start time of a switching period, T1 is the time when the actual current Iac is greater than the first level protection point Ith, T2 is the time when the actual current Iac is less than the first level protection point Ith, T3 is the unblocking time of the delay unblocking, T4 is the time when the PWM drive signal is converted from high level to low level, and T5 is the end time of the switching period.

[0060] Although the above-mentioned manner limits the switch tube action by limiting the wave-by-wave blocking minimum time, setting the wave-by-wave blocking minimum time only avoids the switch tube from acting too fast, and when the blocking and unblocking processing is performed according to the wave-by-wave blocking minimum time, there are still a large number of switch tube action times in a switching period, which may cause the device thermal stress to exceed the standard and cause failure problems. For example, Figure 2As shown, the output drive signal after the delay unblocking is considered, in which the PWM drive signal waveform has two high levels and two low levels, if the switch tube only supports one off + one on in a switching period, the switch tube failure problem caused by high off frequency still exists.

[0061] Therefore, in the embodiments of the present application, a specified switch tube frequency is set, which is greater than or equal to the original switch tube frequency of the inverter and less than or equal to the maximum switch tube frequency that the switch tube can tolerate in the inverter. Then a first time period is determined, in which the switch tube frequency of the inverter is equal to the specified switch tube frequency after the unblocking state is executed. The unblocking operation is performed at the unblocking time in the first time period.

[0062] Specifically, the switch tube is analyzed from a switching period, and it is found that the switch tube mainly has two switching frequencies. One is the maximum switching frequency, which considers the maximum number of actions when the heat stress does not exceed the standard due to the heat generated by the loss of switch tube turn-on and turn-off. Each switch tube can set a corresponding maximum switching frequency according to the actual heat stress bearing capacity, and the maximum switching frequencies of the switch tubes can be the same or different. The other is the switching frequency determined based on the performance requirement, which can be called the required switching frequency. In actual scenarios, during the switch tube blocking process, the current value decreases, and the longer the blocking time, the more the current decreases. If it is subsequently turned on, the current rising range is also large, that is, when the blocking time is long, the current rising and falling change amplitude is large, resulting in large ripple, and there is a problem of current control performance degradation caused by blocking. At this time, if the switch tube device thermal stress or temperature rise and other indicators still have margin, the switching frequency of the switch tube during the short time heat or other factors can be considered to be accelerated to ensure the safety of the switch tube to avoid low current control performance. The required switching frequency is a reasonable switching frequency set considering the performance requirements of the switch tube.

[0063] Therefore, in the embodiments of the present application, the minimum value of the maximum switching frequency and the required switching frequency of the switch tube can be obtained, and the minimum value is used as the specified switch tube frequency. In actual scenarios, if the required switching frequency is less than the maximum switching frequency, it means that the thermal stress limit of the switch tube will not be reached according to the required switching frequency, and the switch tube can be operated according to the required switching frequency at this time. If the required switching frequency is greater than the maximum switching frequency, it means that the thermal stress limit of the switch tube will be reached according to the required switching frequency, and in order to protect the switch tube, the switch tube is only allowed to operate according to the maximum switching frequency.

[0064] In one implementation, if both the required switching frequency and the maximum switching frequency are constant, the minimum value of the two is also constant, and the minimum value only needs to be determined once to obtain the specified switching tube frequency. If at least one of the required switching frequency and the maximum switching frequency changes, the minimum value of the two also changes, and the minimum value needs to be determined once when the frequency changes to obtain the specified switching tube frequency. When the subsequent two frequencies do not change, the determined specified switching tube frequency is used to determine the unblocking time.

[0065] In this embodiment, the minimum value of the maximum switching frequency and the required switching frequency is used to determine the unblocking time, which can consider both performance requirements and thermal stress requirements, and achieve performance requirements on the basis of ensuring the safety of the switching tube.

[0066] The specified switching tube frequency in this embodiment is greater than or equal to the original switching tube frequency of the inverter and less than or equal to the maximum switching frequency that the switching tube in the inverter can tolerate. That is, the specified switching tube frequency is at least the original switching tube frequency and at most the maximum switching frequency. Based on the specified switching tube frequency, one unblocking time in the first time period is determined, so that the blocking state of the inverter is released at the unblocking time.

[0067] In another implementation of the present application, the unblocking state of the inverter at the one unblocking time in the first time period includes:

[0068] One unblocking time in the first time period is determined, and the blocking state of the inverter is released at the unblocking time.

[0069] Specifically, in the embodiment of the present application, one unblocking time in the first time period is determined first, and then the blocking unblocking operation is performed when the current time is the unblocking time, the switching tube is unblocked, and thereafter the inverter normally performs the wave emission operation.

[0070] In this embodiment, after the blocking action of the inverter is performed, if there is an unblocking working condition, the blocking state of the inverter is released at one unblocking time in the first time period. The first time period is a time period in which the switching tube frequency of the inverter is equal to the specified switching tube frequency after the blocking state is released. The specified switching tube frequency is greater than or equal to the original switching tube frequency of the inverter and less than or equal to the maximum switching frequency that the switching tube in the inverter can tolerate. Therefore, when the blocking state is released at one unblocking time in the first time period, the switching frequency of the switching tube can be within the switching frequency that the switching tube can tolerate, avoiding high switching frequency of the switching tube, and thereby avoiding the switching tube failure problem caused by excessive device thermal stress.

[0071] In the above embodiments, the blocking state of the inverter needs to be released at an unblocking moment in the first time period. When determining the unblocking moment, there are two implementation manners. One manner is to first determine the first time period and then determine the unblocking moment in the first time period. The other manner is to directly determine an unblocking moment in the first time period. The two manners will be introduced respectively.

[0072] 1. The first implementation manner.

[0073] The first time period is determined, and a moment in the first time period is taken as the unblocking moment.

[0074] Specifically, the first time period is a time period in which the switch tube frequency of the inverter can be equal to the specified switch tube frequency after the blocking state is released. At this time, at any moment in the first time period, the switch tube frequency of the inverter can be equal to the specified switch tube frequency. Therefore, after the first time period is determined, any moment in the first time period can be taken as the unblocking moment.

[0075] The determination of the first time period also has various manners, which will be introduced respectively. The determination of the first time period in the embodiments of the present application can not only be implemented by the following two embodiments, but also can be implemented by other manners, which are within the protection scope of the embodiments of the present application.

[0076] First embodiment:

[0077] The determination of the first time period is related to the specified switch tube frequency. When the specified switch tube frequency is different, the determined first time period is different. When the specified switch tube frequency is the original switch tube frequency, the determination of the first time period includes the following steps.

[0078] The switch tube off time period after the unblocking working condition of the inverter appears is taken as the first time period.

[0079] The switch tube off time period is the nearest switch tube off time period to the unblocking working condition.

[0080] Specifically, when the original switch tube frequency is 16 kHz (62.5 us), the switch tube can only be turned on once and turned off once in one period.

[0081] When the original switch tube frequency is 16 kHz (62.5 us), the switch tube can only be turned on once and turned off once in one period. Figure 3For example, T0-T5 is one switching cycle, during which only one turn-on and one turn-off are allowed. Analyzing the PWM drive signal during the T3-T5 time period (i.e., the waveform during the T3-T5 time period in normal output drive) reveals that the PWM drive signal is low during this period, controlling the switch to turn off; therefore, the T3-T5 time period is the switch-off time period. If the de-sealment time is set within the T3-T5 time period, even if the switch is allowed to de-seal at this time, it will not turn on due to the low PWM signal. Analyzing the output waveform considering the delay reveals that within the entire preset frequency, there is only one turn-on and one turn-off, satisfying the frequency requirement of the specified switch frequency.

[0082] In the above implementation, within the time period T3-T5, T3 is the first moment when the PWM carrier signal and the comparison value are the same, and T5 is the second moment when the PWM carrier signal and the comparison value are the same. Any moment within the time period T3-T5 is the unsealing moment in this embodiment. When the current moment is the unsealing moment, the unsealing operation is performed. At this time, since the PWM drive signal is low, the switch remains on until after moment T5, when the PWM drive signal becomes high, and the switch turns on.

[0083] In practical scenarios, the PWM carrier signal changes rapidly. Monitoring points other than the zero-crossing and peak of the PWM carrier signal results in low accuracy due to the rapid signal changes. However, monitoring the zero-crossing and peak (also called periodic points, specifically the highest point of the PWM carrier signal) yields relatively high accuracy. Therefore, in one implementation of this application, to stabilize the switching frequency during wave-by-wave blocking, the deblocking action can be performed only at the time of the carrier's zero-crossing or peak. This ensures that the IGBT / MOS switching frequency does not exceed the set frequency, avoiding excessive thermal stress. The deblocking time includes the time of the zero-crossing or peak during the switching transistor's turn-off period, specifically, the wave blocking and deblocking operation is performed at the time of the zero-crossing or peak within the T3-T5 time period. Specifically, there are two implementation methods: deblocking at the zero-crossing time and deblocking at the peak time. The choice of method depends on the actual configuration.

[0084] Figure 3 This is a diagram illustrating the lifting of restrictions at the moment of midnight. Figure 3 As shown in the bottom diagram, when the unsealing occurs at the first zero-crossing point after the unsealing condition, the PWM drive signal has only one high level and one low level within the T0-T5 cycle. At this time, the switching transistor will only turn on and off once, which meets the frequency requirements corresponding to the original switching transistor frequency.

[0085] It should be noted that,Figure 3 The “wave-by-wave signal considering carrier unblocking” refers to the schematic diagram of the PWM drive signal unblocking at the zero-crossing point of the carrier during this wave blocking and unblocking operation. The PWM drive signal for all control cycles can be referred to as “output drive after wave-by-wave considering carrier”. Figure 3 For the remaining level signal diagrams and explanations of T0-T5, please refer to the corresponding descriptions above.

[0086] Figure 4 This is a schematic diagram illustrating the unsealing at the current vertex. Figure 4 In the process, when the comparison value is greater than the carrier value in the PWM carrier signal, the PWM drive signal is high; otherwise, it is low. When the unsealing condition of Iac being less than Ith is met, unsealing does not occur at this time, but rather waits until the moment of the first vertex after the unsealing condition. Figure 4 As shown in the bottom diagram, when the capping occurs at the vertex, the PWM drive signal has only one high level and one low level within the T0-T5 cycle. At this time, the switching transistor will only turn on and off once, which meets the frequency requirement corresponding to the original switching transistor frequency.

[0087] It should be noted that, Figure 4 The diagrams of each signal level and the explanations of T0-T5 are provided. Figure 3 Similarly, please refer to the corresponding instructions above.

[0088] In this embodiment, when using the PWM carrier signal for wave-by-wave deblocking control, the time of the zero-crossing point or the time of the peak is taken as the deblocking time. Deblocking can only be performed when the time of the zero-crossing point or the peak of the PWM carrier signal is detected, ensuring that the switching frequency of the switching transistor is the original switching frequency. After deblocking, normal operation is restored, so that there is only one turn-off and turn-on in one switching cycle, which meets the actual requirements of the switching frequency of the switching transistor.

[0089] Second embodiment:

[0090] Determining the first time period includes:

[0091] Obtain a second time period, which is the delayed unsealing period after the unsealing condition occurs. Calculate the sum of the time when the unsealing condition occurs and the time of the second time period to obtain a first time period.

[0092] Specifically, the above embodiment determines the first time period by using the signal value of the PWM carrier signal. Alternatively, the first time period can also be determined using software timing.

[0093] When using software timing, the de-sealing delay time after the de-sealing condition corresponding to a specified switching frequency can be pre-configured. This de-sealing delay time is called the second time period. The second time period can be half a switching cycle, one or several switching cycles, or it can be a set value unrelated to the switching cycle. The de-sealing delay time can be, for example, 1 minute, 3 minutes, 5 minutes, etc., which can be configured according to the actual scenario. In this case, the second time period is decoupled from the PWM cycle.

[0094] Under normal circumstances, such as Figure 3 As shown, when the switching transistor turn-off period is taken as the first time period, the inverter's switching transistor frequency can be made to be the original switching transistor frequency. Therefore, when the de-blocking control is implemented through software control, the first time period can also be the switching transistor turn-off period. In this case, the starting point of the second time period is the difference between the starting point of the first time period and the time when the de-blocking condition occurs, and the ending point of the second time period is the difference between the ending point of the first time period and the time when the de-blocking condition occurs.

[0095] In one embodiment, the two differences mentioned above can be obtained through a large number of experiments. Through experiments, the two differences corresponding to any time when the unsealing time is arbitrary can be determined, thereby obtaining the second time period.

[0096] After determining the second time period, add the start point of the second time period to the time when the lockdown is lifted to obtain the start point of the first time period. Add the end point of the second time period to the time when the lockdown is lifted to obtain the end point of the first time period, thus determining the first time period. Any time within the first time period is the time when the lockdown is lifted.

[0097] In practical implementation, after the hardware triggers the blocking event, it directly latches the blocking signal and maintains the blocking signal. After there is a deblocking condition that satisfies Iac less than Ith, the software starts timing. When the timing reaches the deblocking time, the deblocking operation is performed to release the blocking state of the inverter.

[0098] It should be noted that if the specified switching frequency is greater than the original switching frequency, a corresponding second time period can be configured according to the requirements, thereby obtaining a first time period that makes the specified switching frequency greater than the original switching frequency, and the unsealing operation is performed at the unsealing time in the first time period.

[0099] In this embodiment, the unsealing time no longer depends on the PWM period, zero-crossing point, or vertex signal, but relies on software timing to control the unsealing time, which has greater flexibility and can realize wave-by-wave of different durations to meet actual frequency requirements.

[0100] 2. The second implementation method.

[0101] In this embodiment, instead of determining the first time period first and then determining the unsealing time within the first time period, we directly determine one unsealing time within the first time period. In this case, the first time period only includes one or more times.

[0102] In one scenario, when the specified switching frequency is n times the original switching frequency, and the n times original switching frequency is less than or equal to the maximum switching frequency that the switching transistors in the inverter can withstand, where n is a positive integer greater than 1, a method is adopted to directly determine a desealing time within a first time period. The above embodiment describes the process of achieving the inverter's switching frequency being the original switching frequency, while this invention describes the process of achieving the inverter's switching frequency being n times the original switching frequency. This invention also has several embodiments, which are described separately below.

[0103] First embodiment:

[0104] Determining a specific time for lifting the lockdown within the first time period includes:

[0105] When n is twice the value, the earliest of the zero-crossing point and the peak point of the carrier signal of the switching transistor in the inverter is taken as a desealing point within the first time period.

[0106] The zero-crossing point and the vertex are located after the inverter's unsealing operation.

[0107] In this embodiment, when n is doubled, the specified switching frequency is 32kHz (31.25us), meaning the switching transistor needs to perform two turn-on and two turn-off operations within one switching cycle. In this case, since the unsealing time is either the zero-crossing point or the periodic point, and the switching transistor needs to perform one turn-on and one turn-off operation within one switching cycle, if unsealing can be performed at both the zero-crossing point and the peak point, it can be guaranteed that the switching transistor performs two turn-on and two turn-off operations within one switching cycle, thus meeting the switching frequency requirement.

[0108] In practical implementation, the earliest of the times of the zero-crossing point and the vertex is taken as the unsealing time within the first time period. That is, whichever time arrives first, the unsealing operation is performed at that time. Specifically, after the occurrence of the unsealing condition, the earliest of the times of the first zero-crossing point and the first vertex is the unsealing time. Figure 5 As shown, after a release condition exists where Iac is less than Ith, the time of the zero-crossing occurs first. Therefore, the time of the zero-crossing, i.e., time T3, is used as the release time. Figure 5As shown in the bottom diagram, when desealing can be performed at both the zero-crossing point and the vertex point, the PWM drive signal has two high levels and two low levels within the T0-T5 cycle. At this time, the switching transistor will turn on and off twice, satisfying the frequency requirement corresponding to twice the original switching transistor frequency.

[0109] It should be noted that, Figure 5 The diagrams of each signal level and the explanations of T0-T5 are provided. Figure 3 Similarly, please refer to the corresponding instructions above.

[0110] Furthermore, in this embodiment, the earliest of the zero-crossing point and the peak point is used as the unsealing time within the first time period, instead of any two times within a time period. This is because the PWM drive signal change requires waiting for the next comparison value to equalize with the PWM carrier signal, ensuring that the PWM drive signal turn-off time is necessarily later than the earliest zero-crossing point or peak point. Therefore, there is no possibility of premature unsealing before the zero-crossing point / peak point. Simultaneously, to ensure that the switching transistor can perform two turn-on and two turn-off operations within the period corresponding to twice the original switching transistor frequency, unsealing is required before the next comparison value is loaded. Therefore, only the zero-crossing point and the peak point can be used as the unsealing time.

[0111] If the switching frequency is controlled at twice the original switching frequency, the switching frequency will double, meaning the switching transistor will operate twice within one switching cycle. This increases the thermal stress on the switching transistor. To ensure effective operation, reducing the number of wave-by-wave cycles can reduce thermal stress. Therefore, in another implementation of this application, if the total number of switching transistor cycles in the inverter is less than the threshold value, the earliest of the zero-crossing point and the peak point of the carrier signal of the switching transistor in the inverter is used as an unsealing point within the first time period.

[0112] The total number of interruptions can be the sum of all interruptions since the switch began operation. The threshold for the total number of interruptions is the maximum total number of interruptions the switch can withstand. If the total number of interruptions is not greater than the threshold, it means the switch can continue to perform interruption operations, and the unsealing operation can be performed at the unsealing point (i.e., the earliest of the zero-crossing time and the peak time). If it is greater than the threshold, it means the switch has reached its maximum wave-by-wave count. If the switch is unsealed further, there is a risk of switch failure due to thermal stress. In this case, unsealing is prohibited to ensure the switch's safety. A prompt message can then be output to allow maintenance personnel to determine whether the switch should continue operation or be replaced.

[0113] Second embodiment:

[0114] Determining a specific time for lifting the lockdown within the first time period also includes:

[0115] When n is any value other than twice, one of the zero-crossing time and the peak time in the frequency multiplication signal of the carrier signal of the switching transistor in the inverter, or the earliest of the zero-crossing time and the peak time, is taken as a desealing time in the first time period; the zero-crossing time and the peak time are located after the desealing condition of the inverter.

[0116] The above embodiment specifies a switching frequency of twice the original switching frequency. In addition, the specified switching frequency can also be three times, four times, five times, etc. When n times is any value other than twice, if only the earliest of the zero-crossing point and the periodic point is used as the unsealing time, only twice the original switching frequency can be achieved. If a higher switching frequency is required, a frequency multiplier signal of the carrier signal needs to be introduced.

[0117] The frequency-multiplied signal of the carrier signal is also a triangular carrier signal, used for deblocking control. See the example below. Figure 6 and Figure 7 The example of the frequency multiplier signal is shown below. The frequency of the frequency multiplier signal is a specified multiple of the frequency of the PWM carrier signal. This specified multiple is an adjustable coefficient, which can be an integer, such as 2, 3, 4, 5, etc., or a non-integer, such as 1.5, 2.3, etc., depending on the actual configuration. Figure 6 and 7 In this configuration, the frequency of the multiplier signal is three times the frequency of the PWM carrier signal; that is, the multiplier signal is a triple carrier signal. Alternatively, it can be implemented as a 2x, 4x, or 5x multiplier, depending on the specified switching transistor frequency. For example, if the specified switching transistor frequency is three times the original switching transistor frequency, the multiplier signal can be a triple carrier signal. If the specified switching transistor frequency is four times the original switching transistor frequency, the multiplier signal can be a quadruple carrier signal.

[0118] When determining an unsealing time within the first time period based on the frequency multiplication signal, at least one of the zero-crossing point and the peak point of the frequency multiplication signal of the carrier signal of the switching transistor in the inverter can be used as the unsealing time within the first time period.

[0119] In one implementation, the time of the first zero-crossing point in the frequency-doubled signal after the occurrence of the unsealing condition is taken as the unsealing time, or the time of the first vertex in the frequency-doubled signal after the occurrence of the unsealing condition is taken as the unsealing time.

[0120] For example, if the specified switching frequency is three times the original switching frequency, and the multiplier signal is a third-multiplier carrier signal, using the zero-crossing point or the peak point as the deblocking time ensures that only three turn-on cycles and three turn-off cycles are allowed within one switching cycle. The same applies to other specified switching frequencies.

[0121] In one implementation, the earliest of the two times in the frequency-doubled signal—the time of the peak after the occurrence of the unsealing condition and the time of the zero-crossing point—is taken as the unsealing time.

[0122] For example, if the specified switching frequency is six times the original switching frequency, and the multiplier signal is a third-harmonic carrier signal, if both the zero-crossing point and the peak point are used as the deblocking time, using the earliest of the two times for the deblocking operation can ensure that only six turn-on operations and six turn-off operations are allowed within one switching cycle. The same applies to other specified switching frequencies.

[0123] For the specific implementation of the three implementation methods in this application embodiment, please refer to the corresponding descriptions above.

[0124] Figure 6 In this context, the frequency-doubled signal is a third-harmonic carrier signal, set to be desealed at the zero-crossing point. After a desealing condition exists where Iac is less than Ith, the time of the first zero-crossing point (e.g., ...) will be... Figure 6 The unsealing operation is performed at the zero-crossing point of the frequency doubling carrier. Figure 6 The PWM drive signal in the last diagram is the switching control signal that satisfies the specified switching frequency.

[0125] Figure 7 In this context, the frequency-harmonic signal is a third-harmonic carrier signal, set to be unsealed at the time of the vertex. After there exists an unsealing condition satisfying Iac less than Ith, the time of the first vertex (e.g., Figure 7 The desealing operation is performed on the frequency doubling carrier vertex in the middle. Figure 7 The PWM drive signal in the last diagram is the switching control signal that satisfies the specified switching frequency.

[0126] It should be noted that, it should be noted that, Figure 6 and 7 The diagrams of each signal level and the explanations of T0-T5 are provided. Figure 3 Similarly, please refer to the corresponding instructions above.

[0127] Furthermore, in this embodiment, only the zero-crossing point and / or the vertex are used as the unsealing time, rather than any time within a time period. This is because the change in the PWM level signal requires waiting for the next comparison value to equalize with the PWM carrier signal. Since the frequency of the multiplier signal is higher than that of the PWM carrier signal, the change in the PWM level signal will inevitably be later than the earliest occurrence of the multiplier signal's zero-crossing point and / or vertex. Therefore, there is no possibility of unsealing before the zero-crossing point and / or vertex. Simultaneously, to ensure that the switching transistor can perform multiple turn-on and multiple turn-off operations within the period corresponding to the multiplier signal, unsealing is required before the next comparison value is loaded. Therefore, only the time of the zero-crossing point and / or the time of the vertex can be used as the unsealing time.

[0128] In this embodiment, the frequency multiplier of the PWM carrier signal is used to control the switching frequency of the switching transistor during wave-by-wave operation. This avoids the problem of rapid switching frequency changes caused by wave-by-wave blocking, meets the actual switching frequency requirements of the switching transistor, reduces the risk of excessive thermal stress, prevents switching transistor failure, and improves the reliability of continuous device operation. Furthermore, this application also considers the performance-required switching frequency when setting the switching frequency of the switching transistor to meet current performance requirements.

[0129] In another implementation of this application, the sealing and unsealing process is introduced by taking the time of zero crossing or the time of vertex as the unsealing time. The implementation process of other unsealing times is similar.

[0130] The first step is to immediately block the wave upon receiving the wave-by-wave blocking signal. Considering the blocking timing of the inner and outer tubes, for example, in a typical type I NPC circuit, the outer tube can be blocked first and then the inner tube.

[0131] The second step involves maintaining the blocked state if no unblocking signal is detected. If an unblocking signal is detected, the state will not be immediately unblocked; proceed to the third step.

[0132] The third step is to unblock the system when a zero-crossing carrier signal or a periodic signal is detected, and then resume normal operation.

[0133] This application also provides an inverter for performing the above-described unsealing control method.

[0134] This application also provides a photovoltaic energy storage system, including the inverter described above.

[0135] In one implementation, the DC side of the inverter is connected to photovoltaic modules and energy storage batteries, and the AC side of the inverter is connected to the power grid and / or load.

[0136] Reference Figure 9 , Figure 9This is a schematic diagram of a photovoltaic-storage system. The system includes at least one photovoltaic module and at least one inverter, such as a PCS (Power Conversion System, energy storage inverter), which is connected to the power grid and optional loads (such as diesel generators). The device for implementing the aforementioned deblocking control method can be located within the inverter and contains electronic equipment capable of storing programs, variables, and supporting information interaction.

[0137] The photovoltaic modules on the DC side are connected to the DC side of the inverter via PV+ and PV-, and the energy storage batteries are connected to the DC side of the inverter via BAT+ and BAT-. The grid, load, and diesel generator connected to the AC side of the inverter are in an AND / OR relationship, meaning they can coexist or not.

[0138] This application also provides a photovoltaic system, including the inverter described above.

[0139] The difference between a photovoltaic (PV) system and a solar-storage system is that a PV system does not have a storage battery. The rest of the structure is the same as that of a solar-storage system, and the desealing control process is also the same.

[0140] This application also provides a computer program product including computer-readable instructions, which, when executed on an electronic device, cause the electronic device to implement any of the unblocking control methods provided in this application.

[0141] This application also provides a computer-readable storage medium that carries one or more computer programs. When the one or more computer programs are executed by an electronic device, the electronic device can implement any of the unblocking control methods provided in this application.

[0142] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for controlling unsealing, characterized in that, include: Perform the wave blocking action of the inverter; In response to the unblocking condition of the inverter, the blocking state of the inverter is released at an unblocking moment within a first time period; the first time period is: the time period after the unblocking state is released, during which the switching frequency of the inverter is equal to a specified switching frequency, wherein the specified switching frequency is greater than or equal to the original switching frequency of the inverter and less than or equal to the maximum switching frequency that the switching transistor in the inverter can withstand.

2. The unsealing control method according to claim 1, characterized in that, The process of releasing the inverter from its blocking state at a specific time point within the first time period includes: Determine a specific time for lifting the lockdown within the first time period; The inverter's wave blocking state is lifted at the specified unblocking time.

3. The unsealing control method according to claim 2, characterized in that, Determining a specific time for lifting the lockdown within the first time period includes: Determine the first time period; One moment in the first time period is taken as the unsealing moment.

4. The unsealing control method according to claim 3, characterized in that, The specified switching frequency is the original switching frequency, and determining the first time period includes: The time period after the inverter is de-sealed is defined as the first time period.

5. The unsealing control method according to claim 3, characterized in that, Determining the first time period includes: Obtain the second time period; the second time period is the delayed unsealing period after the unsealing condition occurs; The first time period is obtained by summing the time of the unsealing condition and the time of the second time period.

6. The unsealing control method according to claim 2, characterized in that, The specified switching frequency is n times the original switching frequency, and the n times the original switching frequency is less than or equal to the maximum switching frequency that the switching transistors in the inverter can withstand, where n is a positive integer greater than 1. Determining a specific time for lifting the lockdown within the first time period includes: When n is twice the value, the earliest of the zero-crossing point and the peak point of the carrier signal of the switching transistor in the inverter is taken as a desealing point within the first time period; the zero-crossing point and the peak point are located after the desealing condition of the inverter.

7. The unsealing control method according to claim 6, characterized in that, Determining a specific time for lifting the lockdown within the first time period also includes: When n is any value other than twice, one of the zero-crossing time and the peak time in the frequency multiplication signal of the carrier signal of the switching transistor in the inverter, or the earliest of the zero-crossing time and the peak time, is taken as a desealing time in the first time period; the zero-crossing time and the peak time are located after the desealing condition of the inverter.

8. The unsealing control method according to claim 6, characterized in that, Before using the zero-crossing point and peak point of the carrier signal of the switching transistor in the inverter as an unsealing point within the first time period, the unsealing control method further includes: If the total number of switching transistors in the inverter is less than the threshold of the total number of switching transistors, the zero-crossing point and the peak point of the carrier signal of the switching transistors in the inverter are taken as a desealing point within the first time period.

9. An inverter, characterized in that, Used to perform the unsealing control method as described in any one of claims 1 to 8.

10. A photovoltaic energy storage system, characterized in that, Including the inverter as described in claim 9.

11. The photovoltaic energy storage system according to claim 10, characterized in that, The DC side of the inverter is connected to the photovoltaic modules and the energy storage battery, and the AC side of the inverter is connected to the power grid and / or the load.

12. A photovoltaic system, characterized in that, Including the inverter as described in claim 9.

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