Electronic device

Abstract

An electronic device includes: a first body including a circuit portion; and a second main body mounted on the first main body and including a sub-circuit portion. The first body also has a plurality of electrode pads. The second body also includes a plurality of terminals. The plurality of electrode pads includes a first electrode pad and a second electrode pad. The plurality of terminals includes a first terminal connected to the first electrode pad and a second terminal connected to the second electrode pad. The circuit portion is connected with the first electrode pad. The sub-circuit portion is connected to the second terminal. A center-to-center distance between the first electrode pad and the second electrode pad is greater than a center-to-center distance between the first terminal and the second terminal.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to an electronic device having a main body and a mounting device mounted on the main body. BACKGROUND

[0002] As one of electronic devices used in a wireless communication system, there are filters such as a low-pass filter, a high-pass filter, and a band-pass filter. These filters are configured using a plurality of resonators. As resonators used in these filters, for example, there are known LC resonators configured using an inductor and a capacitor, and elastic wave resonators configured using an elastic wave element. The elastic wave element refers to an element that utilizes an elastic wave. The elastic wave element includes an elastic surface wave element that utilizes an elastic surface wave, and a bulk elastic wave element that utilizes a bulk elastic wave.

[0003] As a filter device, in addition to a filter device configured using only LC resonators or only elastic wave resonators, there is known a filter device configured using both LC resonators and elastic wave resonators. In such a filter device, for example, a second main body including an elastic wave resonator is mounted on a first main body including an LC resonator.

[0004] A technique of mounting an electronic device including an elastic surface wave element on a wiring substrate is disclosed in Japanese Patent Application Publication No. 2013-33947. In Patent Document 1, a terminal of the electronic device and a pad electrode of the wiring substrate are electrically and mechanically connected by a bonding material such as solder.

[0005] In recent years, the market demands miniaturization and space saving of small mobile communication devices, and also demands miniaturization of a wave splitter used in the communication devices. In the electronic device in which the second main body is mounted on the first main body as in the technique disclosed in Japanese Patent Application Publication No. 2013-33947, a plurality of electrode pads of the first main body and a plurality of terminals of the second main body are connected by a bonding material. If the electronic device is miniaturized, not only the intervals between a plurality of elements of the electronic device become small, but also the intervals between a plurality of electrode pads of the first main body and the intervals between a plurality of terminals of the second main body become small. As a result, there are cases where unexpected coupling and parasitic capacitance occur, and desired characteristics cannot be obtained.

[0006] In order to suppress unexpected coupling and parasitic capacitance, not only improvements are required for the shapes and arrangements of a plurality of elements, but also certain improvements are required for a plurality of electrode pads and a plurality of terminals. However, improvements for a plurality of electrode pads and a plurality of terminals have not been sufficiently studied in the past.

[0007] The above-described problems are not limited to the case where the second main body includes an elastic wave resonator, and are also applicable to the case where the second main body includes an element other than an elastic wave resonator. SUMMARY

[0008] (One) Technical Problem to be Solved

[0009] One of the objects of the present disclosure is to provide an electronic device in which the electronic device can be downsized and desired characteristics can be achieved in an electronic device having a main body and a mounted device mounted on the main body.

[0010] (Two) Technical Solution

[0011] The electronic device of one embodiment of the present disclosure includes a first main body including a plurality of dielectric layers stacked and a circuit portion, a second main body mounted on the first main body and including a sub-circuit portion, and a first filter including at least one of the circuit portion and the sub-circuit portion and selectively passing a signal of a frequency within a first passband. The first main body further includes a first surface and a second surface at both ends in a stacking direction of the plurality of dielectric layers, and includes a plurality of electrode pads provided on the first surface. The second main body further includes a plurality of terminals provided on an outer surface of the second main body. The plurality of electrode pads include a first electrode pad and a second electrode pad. The plurality of terminals include a first terminal connected to the first electrode pad and a second terminal connected to the second electrode pad. The circuit portion is connected to the first electrode pad, and the sub-circuit portion is connected to the second terminal. A distance between centers of the first electrode pad and the second electrode pad is larger than a distance between centers of the first terminal and the second terminal.

[0012] (Three) Advantageous Effects

[0013] In the electronic device of the present disclosure, the distance between centers of the first electrode pad and the second electrode pad is larger than the distance between centers of the first terminal and the second terminal. Thus, according to the present disclosure, the electronic device can be downsized and desired characteristics can be achieved.

[0014] Other objects, features, and advantages of the present disclosure will become more fully understood from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 is a block diagram showing the structure of an electronic device of an exemplary embodiment of the present disclosure.

[0016] Figure 2 is a perspective view showing an electronic device of an exemplary embodiment of the present disclosure.

[0017] Figure 3 is a perspective view showing a first main body in an exemplary embodiment of the present disclosure.

[0018] Figure 4 is a top view showing the first main body in an exemplary embodiment of the present disclosure.

[0019] Figure 5is a plan view showing a portion of the inside of the first body in the exemplary embodiment of the present disclosure.

[0020] Figure 6 is a perspective view showing a portion of the inside of the first body in the exemplary embodiment of the present disclosure.

[0021] Figure 7 is a plan view showing the first to fourth electrode pads and the first to fourth terminals in the exemplary embodiment of the present disclosure.

[0022] Figure 8 is a circuit diagram showing a circuit structure in a model of the example used in the simulation.

[0023] Figure 9 is a plan view showing the first to fourth electrode pads and the first to fourth terminals in the electronic device of the comparative example.

[0024] Figure 10 is a characteristic diagram showing frequency characteristics of the isolation degree of each model calculated by the simulation.

[0025] Figure 11 is a plan view showing the first to fourth electrode pads and the first to fourth terminals in the first modification example.

[0026] Figure 12 is a plan view showing the first to fourth electrode pads and the first to fourth terminals in the second modification example. DETAILED DESCRIPTION

[0027] Hereinafter, embodiments of the present application will be explained in detail with reference to the attached drawings. First, the general structure of an electronic device 100 of an exemplary embodiment of the present disclosure will be explained with reference to FIG. 1. Figure 1 The general structure of the electronic device 100 of the exemplary embodiment of the present disclosure will be explained. Figure 1 is a block diagram showing the structure of the electronic device 100.

[0028] The electronic device 100 of the exemplary embodiment is a wave splitter (a triplexer) provided with a first filter 4, a second filter 5, and a third filter 6. The first filter 4 is configured to selectively pass a first signal of a frequency within a first passband. The second filter 5 is configured to selectively pass a second signal of a frequency within a second passband different from the first passband. The third filter 6 is configured to selectively pass a third signal of a frequency within a third passband different from the first passband and the second passband. In the exemplary embodiment, in particular, the second passband is a higher frequency band than the first passband, and the third passband is a lower frequency band than the first passband.

[0029] The first filter 4 includes a first circuit portion 10. The second filter 5 includes a second circuit portion 20. The third filter 6 includes a third circuit portion 30. The first circuit portion 10, the second circuit portion 20, and the third circuit portion 30 are LC circuits each including at least one inductor and at least one capacitor.

[0030] The first filter 4 further includes a first sub-circuit portion 41. The second filter 5 further includes a second sub-circuit portion 42. The first circuit portion 10 is connected to the first sub-circuit portion 41. The second circuit portion 20 is connected to the second sub-circuit portion 42. The first sub-circuit portion 41 and the second sub-circuit portion 42 are electrically separated from each other. In addition, the first sub-circuit portion 41 and the second sub-circuit portion 42 are each configured using at least one elastic wave element. The elastic wave element can be, for example, a bulk acoustic wave element or an elastic surface wave element. The first sub-circuit portion 41 and the second sub-circuit portion 42 can each be an elastic wave resonator.

[0031] The first circuit portion 10 and the first sub-circuit portion 41 constitute one filter circuit (the first filter 4). The second circuit portion 20 and the second sub-circuit portion 42 constitute another filter circuit (the second filter 5).

[0032] The electronic device 100 further includes a common terminal la, a first signal terminal lb, a second signal terminal lc, and a third signal terminal Id. The first filter 4 is connected to the first signal terminal lb and is disposed between the common terminal la and the first signal terminal lb in a circuit structure. The second filter 5 is connected to the second signal terminal lc and is disposed between the common terminal la and the second signal terminal lc in the circuit structure. The third filter 6 is connected to the third signal terminal Id and is disposed between the common terminal la and the third signal terminal Id in the circuit structure. In addition, in the present application, the expression "in a circuit structure" is used to refer to a configuration on a circuit diagram, not a configuration in a physical structure.

[0033] Next, the structure of the electronic device 100 will be described with reference to Figures 1 to 3 to FIG. 1. Figure 2 is a perspective view of the electronic device 100. Figure 3 is a perspective view of the first main body in the example embodiment. As Figure 2 indicated in FIG. 1, the electronic device 100 includes a first main body 1, a second main body 2 mounted on the first main body 1, and a sealing portion 3 that seals the first main body 1 and the second main body 2. The sealing portion 3 is made of, for example, resin.

[0034] The first main body 1 includes Figure 1The first circuit portion 10, the second circuit portion 20, and the third circuit portion 30 are shown. In addition, the first main body 1 includes a laminate 50. The laminate 50 includes a plurality of dielectric layers that are laminated, and a plurality of conductor layers and a plurality of vias that are formed in the plurality of dielectric layers. The LC circuits of the first circuit portion 10, the second circuit portion 20, and the third circuit portion 30 are each configured using the plurality of dielectric layers, the plurality of conductor layers, and the plurality of vias.

[0035] The plurality of vias are each formed by filling a via hole with a conductor paste. The plurality of vias are each connected to an electrode, a conductor layer, or another via.

[0036] The laminate 50 has a first face 50A and a second face 50B that are located at both ends in the lamination direction of the plurality of dielectric layers, and four side faces 50C to 50F that connect the first face 50A and the second face 50B. The side faces 50C and 50D face opposite directions from each other, and the side faces 50E and 50F also face opposite directions from each other. The side faces 50C to 50F are perpendicular with respect to the first face 50A and the second face 50B.

[0037] Here, as shown in Figure 2 and Figure 3 The X direction, the Y direction, and the Z direction are defined. The X direction, the Y direction, and the Z direction are orthogonal to each other. In the example embodiment, one direction parallel with the lamination direction is the Z direction. The Z direction is also one direction parallel with the direction in which the first main body 1 and the second main body 2 are arranged. In addition, the direction opposite to the X direction is the -X direction, the direction opposite to the Y direction is the -Y direction, and the direction opposite to the Z direction is the -Z direction. In addition, the expression "when viewed from a prescribed direction (for example, the lamination direction)" means that the object is viewed from a separate position along the prescribed direction or one direction parallel with the prescribed direction.

[0038] As shown in Figure 3 The first face 50A is located at the end in the Z direction in the laminate 50. The first face 50A is a part of the outer surface of the first main body 1 on which the second main body 2 is mounted, and is also the upper surface of the laminate 50. The second face 50B is located at the end in the -Z direction in the laminate 50. The second face 50B is the face on the side opposite to the first face 50A, and is also the bottom surface of the laminate 50. The side face 50C is located at the end in the -X direction in the laminate 50. The side face 50D is located at the end in the X direction in the laminate 50. The side face 50E is located at the end in the -Y direction in the laminate 50. The side face 50F is located at the end in the Y direction in the laminate 50.

[0039] The first body 1 further includes a plurality of electrodes 111, 112, 113, 114, 115, 116, 117, 118, and 119 disposed on the second surface 50B of the laminate 50. Electrode 111 is disposed near the corner where the second surface 50B, side surface 50C, and side surface 50E intersect. Electrode 113 is disposed near the corner where the second surface 50B, side surface 50D, and side surface 50E intersect. Electrode 115 is disposed near the corner where the second surface 50B, side surface 50D, and side surface 50F intersect. Electrode 117 is disposed near the corner where the second surface 50B, side surface 50C, and side surface 50F intersect.

[0040] Electrode 112 is disposed between electrode 111 and electrode 113. Electrode 114 is disposed between electrode 113 and electrode 115. Electrode 116 is disposed between electrode 115 and electrode 117. Electrode 118 is disposed between electrode 111 and electrode 117. Electrode 119 is disposed at the center or approximately the center of the second surface 50B.

[0041] The first subject 1 also includes Figure 1 The diagram shows a common terminal 1a, a first signal terminal 1b, a second signal terminal 1c, and a third signal terminal 1d. Electrode 111 corresponds to the third signal terminal 1d, electrode 113 corresponds to the common terminal 1a, electrode 115 corresponds to the second signal terminal 1c, and electrode 117 corresponds to the first signal terminal 1b. Therefore, the common terminal 1a and the first signal terminals 1b to the third signal terminals 1d are disposed on the second surface 50B of the laminate 50. Electrodes 112, 114, 116, 118, and 119 are respectively connected to a grounding element.

[0042] The first body 1 further includes a plurality of electrode pads disposed on a first surface 50A of the laminate 50. In an exemplary embodiment, the plurality of electrode pads includes a first electrode pad 121, a second electrode pad 122, a third electrode pad 123, and a fourth electrode pad 124. The first electrode pads 121 to 124 may be disposed near the center of the first surface 50A. The first electrode pads 121 and 122 are arranged in this order in the -Y direction. The third electrode pads 123 and 124 are arranged in this order in the Y direction at a position closer to the X direction than the first electrode pads 121 and 122.

[0043] The second main body 2 includes a first sub-circuit section 41 and a second sub-circuit section 42. Furthermore, the second main body 2 has: a third surface 2A and a fourth surface 2B located at opposite ends in a direction parallel to the Z direction; and four side surfaces 2C to 2F connecting the third surface 2A and the fourth surface 2B. Side surfaces 2C and 2D face opposite directions, as do side surfaces 2E and 2F. Side surfaces 2C to 2F are perpendicular to the third surface 2A and the fourth surface 2B.

[0044] like Figure 2 As shown, the third surface 2A is located at the Z-direction end of the second body 2. The third surface 2A is also the upper surface of the second body 2. The fourth surface 2B is located at the -Z-direction end of the second body 2. The fourth surface 2B is the surface opposite to the first body 1 and is also the bottom surface of the second body 2. Side surface 2C is located at the -X-direction end of the second body 2. Side surface 2D is located at the X-direction end of the second body 2. Side surface 2E is located at the -Y-direction end of the second body 2. Side surface 2F is located at the Y-direction end of the second body 2.

[0045] The second body 2 further includes a plurality of terminals disposed on a fourth surface 2B of the second body 2. In an exemplary embodiment, the plurality of terminals include a first terminal 2a, a second terminal 2b, a third terminal 2c, and a fourth terminal 2d. The first terminal 2a is disposed near a corner at the intersection of the fourth surface 2B, side surface 2C, and side surface 2F. The second terminal 2b is disposed near a corner at the intersection of the fourth surface 2B, side surface 2C, and side surface 2E. The third terminal 2c is disposed near a corner at the intersection of the fourth surface 2B, side surface 2D, and side surface 2E. The fourth terminal 2d is disposed near a corner at the intersection of the fourth surface 2B, side surface 2D, and side surface 2F.

[0046] The first auxiliary circuit section 41 is disposed between the first terminal 2a and the second terminal 2b in the circuit structure, and is connected to the first terminal 2a and the second terminal 2b. The second auxiliary circuit section 42 is disposed between the third terminal 2c and the fourth terminal 2d in the circuit structure, and is connected to the third terminal 2c and the fourth terminal 2d.

[0047] With the second body 2 mounted on the first body 1, the first to fourth terminals 2a, 2b, 2c, and 2d of the second body 2 are respectively opposed to the first to fourth electrode pads 121, 122, 123, and 124 of the first body 1. The first to fourth terminals 2a, 2b, 2c, and 2d are respectively connected to the first to fourth electrode pads 121, 122, 123, and 124 via conductive bonding materials. In an exemplary embodiment, specifically, the first to fourth terminals 2a, 2b, 2c, and 2d are electrically and physically connected to the first to fourth electrode pads 121, 122, 123, and 124, for example, via solder bumps 7.

[0048] The first electrode pad 121, the second electrode pad 122, the first terminal 2a, and the second terminal 2b are connected to the first signal terminal 1b. The third electrode pad 123, the fourth electrode pad 124, the third terminal 2c, and the fourth terminal 2d are connected to the second signal terminal 1c.

[0049] Next, refer to Figures 4 to 6 The first subject 1 will be described in more detail. Figure 4 This is a top view representing the first main body 1. Figure 5 It is a top view showing a portion of the interior of the first main body 1. Figure 6 It is a three-dimensional view representing a part of the interior of the first main body 1.

[0050] The first main body 1 further includes a first structure 8 and a second structure 9, which are respectively connected to a grounding element. Viewed from the Z direction, the second structure 9 is disposed between the first electrode pad 121 and the fourth electrode pad 124, and between the second electrode pad 122 and the third electrode pad 123. Viewed from the Z direction, the first electrode pad 121 and the second electrode pad 122 are positioned in front of the second structure 9 in the -X direction. Viewed from the Z direction, the third electrode pad 123 and the fourth electrode pad 124 are positioned in front of the second structure 9 in the X direction. The first structure 8 is disposed between the second structure 9 and the side surface 50F.

[0051] Here, refer to Figure 4 The three-dimensional region within the stacked body 50 defined by the first structure 8, the second structure 9, and the boundary surface P is described. The boundary surface P is an imaginary plane parallel to the XZ plane, located between the first structure 8 and the second structure 9 and the side surface 50E. The boundary surface P can be located closer to the second structure 9 than the side surface 50E.

[0052] The laminate 50 includes a first region R1, a second region R2, and a third region R3. The first region R1 is surrounded by the first structure 8 and the second structure 9, sides 50C and 50F, and boundary surface P. The second region R2 is surrounded by the first structure 8 and the second structure 9, sides 50D and 50F, and boundary surface P. The third region R3 is surrounded by sides 50C, 50D, 50E, and boundary surface P. Figure 4 In the diagram, the area enclosed by the dashed line marked with reference numeral R1 represents the first region R1, the area enclosed by the dashed line marked with reference numeral R2 represents the second region R2, and the area enclosed by the dashed line marked with reference numeral R3 represents the third region R3. The first structure 8 and the second structure 9 are used as partitions to separate the first region R1 from the second region R2.

[0053] The first region R1 is a region that includes at least a portion of the first circuit portion 10 but does not include the second circuit portion 20. The second region R2 is a region that includes at least a portion of the second circuit portion 20 but does not include the first circuit portion 10. The third region R3 is a region that includes the third circuit portion 30. The third region R3 may include another portion of the first circuit portion 10 and another portion of the second circuit portion 20, or it may not include any of them.

[0054] Next, refer to Figure 5 as well as Figure 6 The structures of the first structure 8 and the second structure 9 will be described. The first structure 8 includes a plurality of first through-holes 71 and a plurality of first conductor layers 61 electrically connected to the plurality of first through-holes 71. The plurality of first conductor layers 61 are arranged at different positions in the stacking direction, i.e., in a direction parallel to the Z-direction. The second structure 9 includes a plurality of second through-holes 72 and a plurality of second conductor layers 62 electrically connected to the plurality of second through-holes 72. The plurality of second conductor layers 62 are arranged at different positions in the stacking direction, i.e., in a direction parallel to the Z-direction.

[0055] Each of the plurality of first conductor layers 61 and the plurality of second conductor layers 62 includes portions extending in the same direction orthogonal to the stacking direction. In an exemplary embodiment, in particular, the entire plurality of first conductor layers 61 and the plurality of second conductor layers 62 extend in a direction parallel to the Y direction.

[0056] Furthermore, the plurality of first conductor layers 61 are identical in shape to each other. The arrangement of the plurality of first conductor layers 61 is identical to each other except for their position in the stacking direction. Two first conductor layers 61 that are spaced apart and adjacent in the stacking direction are interconnected through at least one first through-hole 71. Figure 5 as well as Figure 6In the example shown, the two first conductor layers 61 are interconnected through three first through holes 71.

[0057] Furthermore, the plurality of second conductor layers 62 are identical in shape to each other. The arrangement of the plurality of second conductor layers 62 is identical to each other except for their position in the stacking direction. Two second conductor layers 62 that are spaced apart and adjacent in the stacking direction are interconnected through at least one second through-hole 72. Figure 5 as well as Figure 6 In the example shown, the two second conductor layers 62 are interconnected through three second through holes 72.

[0058] The plurality of first conductor layers 61 include a specific first conductor layer 61. The specific first conductor layer 61 may, for example, be the conductor layer closest to the first surface 50A among the plurality of first conductor layers 61. Since the plurality of first conductor layers 61 are constituent elements of the first structure 8, it can also be said that the first structure 8 includes a specific first conductor layer 61. Figure 5 In the figure, reference numeral 61 indicates a specific first conductor layer 61.

[0059] The plurality of second conductor layers 62 includes a specific second conductor layer 62. The specific second conductor layer 62 may, for example, be the conductor layer closest to the first surface 50A among the plurality of second conductor layers 62. Since the plurality of second conductor layers 62 are constituent elements of the second structure 9, it can also be said that the second structure 9 includes a specific second conductor layer 62. Figure 5 In the figure, reference numeral 62 indicates a specific second conductor layer 62.

[0060] When viewed from the stacking direction (parallel to the Z direction), a specific first conductor layer 61 and a specific second conductor layer 62 are located between the first region R1 and the second region R2, and between the first circuit portion 10 and the second circuit portion 20. For example... Figure 5 As shown, the specific first conductor layer 61 is not directly connected to the specific second conductor layer 62.

[0061] In the exemplary embodiment, in particular, the description of the specific first conductor layer 61 described above also applies to first conductor layers 61 other than the specific first conductor layer 61. Similarly, the description of the specific second conductor layer 62 described above also applies to second conductor layers 62 other than the specific second conductor layer 62. The first conductor layer 61 is not directly connected to the second conductor layer 62 located at the same position in the stacking direction.

[0062] Next, refer to Figures 4 to 6Features related to the first structure 8, the second structure 9, the first circuit portion 10, and the second circuit portion 20 will be described. The first circuit portion 10 and the second circuit portion 20 each include at least one inductor and at least one capacitor. In an exemplary embodiment, the first circuit portion 10 includes inductors L1 and L2 and capacitor C1. The second circuit portion 20 includes inductors L3 and L4 and capacitor C2.

[0063] Inductors L1 and L2 are disposed in the first region R1. Inductor L2 is disposed between the second structure 9 and the side surface 50C. Inductor L1 is disposed between inductor L2 and the side surface 50F, and is also disposed between the first structure 8 and the side surface 50C.

[0064] Inductors L3 and L4 are disposed in the second region R2. Inductor L3 is disposed between the second structure 9 and the side surface 50D. Inductor L4 is disposed between inductor L3 and the side surface 50F, and is also disposed between the first structure 8 and the side surface 50D.

[0065] When viewed from the Z-direction, the first structure 8 is positioned between inductors L1 and L4. When viewed from the Z-direction, the second structure 9 is positioned between inductors L2 and L3.

[0066] Capacitor C1 is positioned between inductor L1 and the second surface 50B. Capacitor C2 is positioned between inductor L4 and the second surface 50B.

[0067] The first body 1 further includes a grounding conductor layer 91 connected to a grounding element. The grounding conductor layer 91 is electrically connected to at least one of electrodes 112, 114, 116, 118, and 119, which are connected to the grounding element.

[0068] The first structure 8 and the second structure 9 are connected to the grounding conductor layer 91. In an exemplary embodiment, in particular, at least one of the plurality of first through holes 71 and at least one of the plurality of second through holes 72 are connected to the grounding conductor layer 91.

[0069] When viewed from the Z direction, the grounding conductor layer 91 overlaps with at least a portion of at least one of the first circuit portion 10 and the second circuit portion 20. In an exemplary embodiment, in particular, when viewed from the Z direction, the grounding conductor layer 91 overlaps entirely with each of the inductors L1 to L4.

[0070] The first body 1 further includes capacitor conductor layers 92 and 93 disposed within the laminate 50. The capacitor conductor layers 92 and 93 are respectively opposed to the ground conductor layer 91 via at least one dielectric layer. The capacitor C1 is composed of the ground conductor layer 91, the capacitor conductor layer 92, and at least one dielectric layer between the ground conductor layer 91 and the capacitor conductor layer 92. The capacitor C2 is composed of the ground conductor layer 91, the capacitor conductor layer 93, and at least one dielectric layer between the ground conductor layer 91 and the capacitor conductor layer 93. The capacitor conductor layer 92 is disposed between the inductor L1 and the ground conductor layer 91. The capacitor conductor layer 93 is disposed between the inductor L4 and the ground conductor layer 91.

[0071] The first body 1 may further include: a third structure (not shown) that separates a portion of the first circuit portion 10 from a portion of the third circuit portion 30; and a fourth structure (not shown) that separates a portion of the second circuit portion 20 from another portion of the third circuit portion 30. The third and fourth structures may be directly or indirectly connected to the grounding conductor layer 91. Furthermore, the third and fourth structures may be directly connected to each other or not directly connected to each other.

[0072] Next, refer to Figures 2 to 5 Features related to the first structure 8, the second structure 9, and the second body 2 will be described. As described above, the first to fourth terminals 2a, 2b, 2c, and 2d of the second body 2 are connected to the first to fourth electrode pads 121, 122, 123, and 124 of the first body 1 via conductive bonding materials. Furthermore, when viewed from the Z direction, the second structure 9 is disposed between the first electrode pad 121 and the fourth electrode pad 124, and between the second electrode pad 122 and the third electrode pad 123. Therefore, when viewed from the Z direction, the second structure 9 is disposed between the first terminal 2a and the fourth terminal 2d, and between the second terminal 2b and the third terminal 2c.

[0073] Furthermore, when viewed from the Z direction, the first electrode pad 121 and the second electrode pad 122 are positioned in front of the second structure 9 in the -X direction. Therefore, when viewed from the Z direction, the first terminal 2a and the second terminal 2b are positioned in front of the second structure 9 in the -X direction.

[0074] Furthermore, when viewed from the Z direction, the third electrode pad 123 and the fourth electrode pad 124 are positioned in front of the second structure 9 in the X direction. Therefore, when viewed from the Z direction, the third terminal 2c and the fourth terminal 2d are positioned in front of the second structure 9 in the X direction.

[0075] As described above, the first auxiliary circuit portion 41 is disposed between the first terminal 2a and the second terminal 2b in the circuit structure. Although not shown in the figure, when viewed from the Z direction, at least a portion of the first auxiliary circuit portion 41 is positioned in front of the second structure 9 in the -X direction.

[0076] Furthermore, as described above, the second auxiliary circuit portion 42 is disposed between the third terminal 2c and the fourth terminal 2d in the circuit structure. Although not shown in the figure, when viewed from the Z direction, at least a portion of the second auxiliary circuit portion 42 is positioned in front of the second structure 9 in the X direction.

[0077] exist Figure 4 In the figure, the rectangular area marked with reference numeral R20 represents the region located between the first sub-circuit portion 41 and the second sub-circuit portion 42 in the second body 2. Region R20 can be a three-dimensional region or a planar region. Furthermore, region R20 can be located between a portion of the first sub-circuit portion 41 and a portion of the second sub-circuit portion 42. When viewed from the Z direction, a specific second conductor layer 62 of the second structure 9 overlaps with region R20.

[0078] like Figure 4 As shown, when viewed from the Z direction, the second structure 9 can extend to the outside of the second main body 2, that is, the Y-direction side of the second main body 2 and the -Y-direction side of the second main body 2.

[0079] When viewed from the Z-direction, a specific first conductor layer 61 of the first structure 8 does not overlap with region R20. Furthermore, provided the condition that the specific first conductor layer 61 does not overlap with region R20 is met, when viewed from the Z-direction, the first structure 8 may or may not overlap with the second main body 2. Figure 4 As shown, in an exemplary embodiment, when viewed from the Z direction, a specific first conductor layer 61 of the first structure 8 does not overlap with the second body 2.

[0080] Next, refer to Figure 5 as well as Figure 6 Features related to inductors L1 to L4 will be described. Inductor L1 includes at least one inductor conductor layer, which is wound around an axis extending in a direction parallel to the lamination direction to form an opening surrounded by inductor L1. Hereinafter, the opening surrounded by inductor L1 or at least one inductor conductor layer of inductor L1 will be referred to as the opening of inductor L1. The opening of inductor L1 faces the first surface 50A of the laminate 50. Furthermore, the opening of inductor L1 is entirely present in the first region R1. Hereinafter, for inductors other than inductor L1, the opening surrounded by that inductor or at least one inductor conductor layer of that inductor will also be referred to as the opening of that inductor.

[0081] Similarly, inductors L2, L3, and L4 each include at least one conductor layer for inductance, which is wound around an axis extending in a direction parallel to the stacking direction to form an opening surrounded by inductors L2, L3, and L4 respectively. The openings of inductors L2, L3, and L4 each face the first surface 50A of the laminate 50. The opening of inductor L2 is entirely located in the first region R1. The openings of inductors L3 and L4 are entirely located in the second region R2.

[0082] The inductor L1 comprises at least one inductor conductor layer 81 arranged at predetermined intervals in the stacking direction. The plurality of inductor conductor layers 81 are wound around an axis extending in a direction parallel to the stacking direction to surround an opening of the inductor L1. The first body 1 further comprises: a conductor layer 85 connected to a first specific inductor conductor layer 81 closest to the first surface 50A among the plurality of inductor conductor layers 81; and a through-hole T1 connecting the conductor layer 85 to a first electrode pad 121. Figure 5 In the diagram, the boundary between the first specific inductor conductor layer 81 and conductor layer 85 is indicated by a dashed line.

[0083] Inductor L1 may or may not be connected to capacitor C1. When inductor L1 is connected to capacitor C1, the first body 1 may also include a through-hole (not shown) that connects a second specific inductor conductor layer 81 closest to the second surface 50B among a plurality of inductor conductor layers 81 to a capacitor conductor layer 92.

[0084] The inductor L2 comprises at least one inductor conductor layer 82 arranged at predetermined intervals in the stacking direction. The plurality of inductor conductor layers 82 are each wound around an axis extending in a direction parallel to the stacking direction to surround an opening of the inductor L2. The first body 1 further comprises: a conductor layer 86 connected to a first specific inductor conductor layer 82 closest to the first surface 50A among the plurality of inductor conductor layers 82; and a through-hole T2 connecting the conductor layer 86 to a second electrode pad 122. Figure 5 In the diagram, the boundary between conductor layer 82 and conductor layer 86 for inductors is indicated by a dashed line.

[0085] The inductor L2 may or may not be connected to the grounding element. When the inductor L2 is connected to the grounding element, the first body 1 may also include a plurality of through holes (not shown) that connect the second specific inductor conductor layer 82 closest to the second surface 50B among the plurality of inductor conductor layers 82 to the grounding conductor layer 91.

[0086] The inductor L3 comprises at least one inductor conductor layer 83 arranged at predetermined intervals in the stacking direction. The plurality of inductor conductor layers 83 are each wound around an axis extending in a direction parallel to the stacking direction to surround an opening of the inductor L3. The first body 1 further comprises: a conductor layer 87 connected to a first specific inductor conductor layer 83 closest to the first surface 50A among the plurality of inductor conductor layers 83; and a through-hole T3 connecting the conductor layer 87 to a third electrode pad 123. Figure 5 In the diagram, the boundary between conductor layer 83 and conductor layer 87 for inductors is indicated by a dashed line.

[0087] Inductor L3 may or may not be connected to a grounding element. When inductor L3 is connected to a grounding element, the first body 1 may also include a plurality of through holes (not shown) that connect the second specific inductor conductor layer 83 closest to the second surface 50B among the plurality of inductor conductor layers 83 to the grounding conductor layer 91.

[0088] The inductor L4 comprises at least one inductor conductor layer 84 arranged at predetermined intervals in the stacking direction. The plurality of inductor conductor layers 84 are each wound around an axis extending in a direction parallel to the stacking direction to surround an opening of the inductor L4. The first body 1 further comprises: a conductor layer 88 connected to a first specific inductor conductor layer 84 closest to the first surface 50A among the plurality of inductor conductor layers 84; and a through-hole T4 connecting the conductor layer 88 to a fourth electrode pad 124. Figure 5 In the diagram, the boundary between conductor layer 84 and conductor layer 88 for inductors is indicated by a dashed line.

[0089] Inductor L4 may or may not be connected to capacitor C2. When inductor L4 is connected to capacitor C2, the first body 1 may also include a through-hole (not shown) that connects a second specific inductor conductor layer 84 closest to the second surface 50B among a plurality of inductor conductor layers 84 to a capacitor conductor layer 93.

[0090] Inductor L1 is connected to the first sub-circuit portion 41 of the second main body 2 via conductor layer 85, through-hole T1, first electrode pad 121, and first terminal 2a. Inductor L2 is connected to the first sub-circuit portion 41 of the second main body 2 via conductor layer 86, through-hole T2, second electrode pad 122, and second terminal 2b. Inductor L3 is connected to the second sub-circuit portion 42 of the second main body 2 via conductor layer 87, through-hole T3, third electrode pad 123, and third terminal 2c. Inductor L4 is connected to the second sub-circuit portion 42 of the second main body 2 via conductor layer 88, through-hole T4, fourth electrode pad 124, and fourth terminal 2d.

[0091] The plurality of inductor conductor layers 81 of inductor L1, the specific first conductor layer 61, and the plurality of inductor conductor layers 84 of inductor L4 are arranged in this order along a first direction orthogonal to the stacking direction. In an exemplary embodiment, in particular, the plurality of inductor conductor layers 81, the specific first conductor layer 61, and the plurality of inductor conductor layers 84 are arranged in this order along the X direction. The size of the specific first conductor layer 61 in a second direction (Y direction) orthogonal to both the stacking direction and the first direction (X direction) can be larger than the size of the second direction (Y direction) of the openings surrounded by the plurality of inductor conductor layers 81 and the size of the second direction (Y direction) of the openings surrounded by the plurality of inductor conductor layers 84.

[0092] Additionally, the plurality of inductor conductor layers 82 of inductor L2, the specific second conductor layer 62, and the plurality of inductor conductor layers 83 of inductor L3 may also be arranged in this order along a first direction orthogonal to the stacking direction. In an exemplary embodiment, in particular, the plurality of inductor conductor layers 82, the specific second conductor layer 62, and the plurality of inductor conductor layers 83 are arranged in this order along the X direction. The size of the specific second conductor layer 62 in the second direction (Y direction) orthogonal to both the stacking direction and the first direction (X direction) may be larger than the size of the opening in the second direction (Y direction) of the opening surrounded by the plurality of inductor conductor layers 82 and the size of the opening in the second direction (Y direction) of the opening surrounded by the plurality of inductor conductor layers 83.

[0093] Next, refer to Figure 7 Features related to the first electrode pads 121 to 124 of the first body 1 and the first terminals 2a to 2d of the second body 2 will be described. Figure 7 This is a top view showing the first electrode pad 121 to the fourth electrode pad 124 and the first terminal 2a to the fourth terminal 2d.

[0094] exist Figure 7 In the attached figure, reference numeral c11 indicates the shape of the first electrode pad 121 when viewed from the stacking direction (a direction parallel to the Z direction), i.e., the center of the planar shape of the first electrode pad 121. The center c11 of the planar shape of the first electrode pad 121 can be the center of the circumcenter of the planar shape of the first electrode pad 121, the center of the incenter of the planar shape of the first electrode pad 121, or the centroid of the planar shape of the first electrode pad 121.

[0095] Below, the center of the circumcircle of the planar shape of the first electrode pad 121 is taken as the center c11 of the planar shape of the first electrode pad 121. Figure 7 In the example shown, the planar shape of the first electrode pad 121 is circular. Therefore, the center c11 coincides with the center of the planar shape of the first electrode pad 121 (the center of the circle). In the following description, for convenience, the center c11 will be referred to as the center of the first electrode pad 121. Similarly, for the second electrode pads 122 to the fourth electrode pads 124 and the first terminals 2a to the fourth terminals 2d, the center of the circumcircle of the shape when viewed from the stacking direction, i.e., the planar shape, will also be simply referred to as the center.

[0096] Reference numeral c12 indicates the center of the second electrode pad 122, reference numeral c13 indicates the center of the third electrode pad 123, and reference numeral c14 indicates the center of the fourth electrode pad 124. Additionally, reference numeral c21 indicates the center of the first terminal 2a, reference numeral c22 indicates the center of the second terminal 2b, reference numeral c23 indicates the center of the third terminal 2c, and reference numeral c24 indicates the center of the fourth terminal 2d.

[0097] Additionally, the symbol D1 represents the distance between the centers of any two electrode pads from the first electrode pad 121 to the fourth electrode pad 124. Figure 7 In the diagram, the symbol D1 represents the distance between center c11 and center c14, and the distance between center c12 and center c13. Figure 7 The example shown is that the distances between center c11 and center c14 and the distances between center c12 and center c13 are equal.

[0098] Additionally, the symbol D2 represents the distance between the centers of any two terminals from the first terminal 2a to the fourth terminal 2d. Figure 7 In the diagram, the symbol D2 represents the distance between center c21 and center c24, and the distance between center c22 and center c23. Figure 7 The example shown is that the distances between center c21 and center c24 and the distances between center c22 and center c23 are equal.

[0099] Here, we focus on any two adjacent electrode pads (first electrode pads 121 to fourth electrode pads 124) that are spaced apart, and two terminals (first terminals 2a to fourth terminals 2d), which are respectively connected to the two electrode pads mentioned above. The center-to-center distance D1 between the two electrode pads is greater than the center-to-center distance D2 between the two terminals mentioned above.

[0100] As described above, the first electrode pad 121, the second electrode pad 122, the first terminal 2a, and the second terminal 2b are connected to the first signal terminal 1b. The third electrode pad 123, the fourth electrode pad 124, the third terminal 2c, and the fourth terminal 2d are connected to the second signal terminal 1c. The length of the path from the first signal terminal 1b to the second signal terminal 1c is greater than the path length when the center-to-center distance D1 between the two electrode pads and the center-to-center distance D2 between the two terminals are the same.

[0101] In an exemplary embodiment, specifically, all combinations of two electrode pads from the first electrode pad 121 to the fourth electrode pad 124 satisfy the condition that the center-to-center distance D1 between the two electrode pads is greater than the center-to-center distance D2 between the two terminals respectively connected to these two electrode pads. That is, the distance D1 between the center c11 of the first electrode pad 121 and the center c12 of the second electrode pad 122 is greater than the distance D2 between the center c21 of the first terminal 2a and the center c22 of the second terminal 2b. The distance D1 between the center c12 of the second electrode pad 122 and the center c13 of the third electrode pad 123 is greater than the distance D2 between the center c22 of the second terminal 2b and the center c23 of the third terminal 2c. The distance D1 between the center c13 of the third electrode pad 123 and the center c14 of the fourth electrode pad 124 is greater than the distance D2 between the center c23 of the third terminal 2c and the center c24 of the fourth terminal 2d. The distance D1 between the center c14 of the fourth electrode pad 124 and the center c11 of the first electrode pad 121 is greater than the distance D2 between the center c24 of the fourth terminal 2d and the center c21 of the first terminal 2a.

[0102] Furthermore, the distance D1 between the center c11 of the first electrode pad 121 and the center c13 of the third electrode pad 123 is greater than the distance D2 between the center c21 of the first terminal 2a and the center c23 of the third terminal 2c. The distance D1 between the center c12 of the second electrode pad 122 and the center c14 of the fourth electrode pad 124 is greater than the distance D2 between the center c22 of the second terminal 2b and the center c24 of the fourth terminal 2d.

[0103] The length of the path from the first signal terminal 1b to the second signal terminal 1c is greater than the path length when the center-to-center distance D1 between the first electrode pad 121 and the second electrode pad 122 and the center-to-center distance D2 between the first terminal 2a and the second terminal 2b are the same, and the center-to-center distance D1 between the third electrode pad 123 and the fourth electrode pad 124 and the center-to-center distance D2 between the third terminal 2c and the fourth terminal 2d are the same.

[0104] Next, refer to Figure 7The planar shapes (shapes when viewed from the stacking direction) of the first electrode pads 121 to 124 and the first terminals 2a to 2d will be described. The planar shape of each of the first electrode pads 121 to 124 may be similar to, or may not be similar to, the planar shapes of the first terminals 2a to 2d. In an exemplary embodiment, specifically, the shapes of each of the first electrode pads 121 to 124 are different from the planar shapes of the first terminals 2a to 2d. Specifically, the planar shape of each of the first electrode pads 121 to 124 is circular, and the planar shape of the first terminal 2a is polygonal (in...). Figure 8 (The example shown is a pentagon), and the planar shapes of the second terminal 2b to the fourth terminal 2d are each rectangular.

[0105] Furthermore, the planar shapes of the first terminal 2a to the fourth terminal 2d may be similar to each other or may not be similar to each other. In an exemplary embodiment, in particular, the planar shapes (rectangular) of the second terminal 2b to the fourth terminal 2d are different from the planar shape (polygonal) of the first terminal 2a. The first terminal 2a can be used as a marker to confirm the orientation of the second body 2.

[0106] Next, the operation and effects of the electronic device 100 according to an exemplary embodiment will be described. The electronic device 100 according to the exemplary embodiment includes: a first body 1, which includes a first circuit portion 10 and a second circuit portion 20; and a second body 2, which includes a first sub-circuit portion 41 and a second sub-circuit portion 42 mounted on the first body 1. The first body 1 further includes first electrode pads 121 to fourth electrode pads 124. The second body 2 further includes first terminals 2a to fourth terminals 2d. The first circuit portion 10 is connected to the first electrode pads 121 and 122. The second circuit portion 20 is connected to the third electrode pads 123 and 124. The first sub-circuit portion 41 is connected to the first terminal 2a and the second terminal 2b. The second sub-circuit portion 42 is connected to the third terminal 2c and the fourth terminal 2d.

[0107] In an exemplary embodiment, as described above, the center-to-center distance D1 between the two electrode pads is greater than the center-to-center distance D2 between the two terminals connected to the two electrode pads respectively. Therefore, according to the exemplary embodiment, unexpected coupling and parasitic capacitance can be suppressed, resulting in miniaturization of the electronic device 100 and the achievement of desired characteristics.

[0108] The effects of the electronic device 100 according to the exemplary embodiment will now be described in more detail. First, the first electrode pad 121, the second electrode pad 122, the first terminal 2a, and the second terminal 2b will be described. In the exemplary embodiment, the distance D1 between the center c11 of the first electrode pad 121 and the center c12 of the second electrode pad 122 is greater than the distance D2 between the center c21 of the first terminal 2a and the center c22 of the second terminal 2b. If we compare this to a case where the distance D2 between the centers c21 and c22 is the same, according to the exemplary embodiment, the spacing between the via T1 connected to the first electrode pad 121 and the via T2 connected to the second electrode pad 122 can be increased compared to a case where the distance D1 between the centers c11 and c12 and the distance D2 between the centers c21 and c22 are the same. As a result, according to the exemplary embodiment, parasitic capacitance generated between the via T1 and the via T2 can be suppressed.

[0109] Specifically, when the first sub-circuit portion 41 connected to the first terminal 2a and the second terminal 2b is an elastic wave resonator, self-resonance occurs due to the parasitic capacitance generated between the through-hole T1 and the through-hole T2. According to the exemplary embodiment, the generation of self-resonance can be suppressed by suppressing the parasitic capacitance as described above. Thus, according to the exemplary embodiment, the desired characteristics can be achieved.

[0110] Furthermore, if the distance D2 between centers c21 and c22 is set to be the same for comparison, according to the exemplary embodiment, compared to the case where the distance D1 between centers c11 and c12 and the distance D2 between centers c21 and c22 are the same, the path length from the first signal terminal 1b to the second signal terminal 1c can be increased. Therefore, according to the exemplary embodiment, the deterioration of the isolation characteristics between the first filter 4 and the second filter 5 can be suppressed.

[0111] The description of the first electrode pad 121, the second electrode pad 122, the first terminal 2a, and the second terminal 2b also applies to the third electrode pad 123, the fourth electrode pad 124, the third terminal 2c, and the fourth terminal 2d. That is, according to the exemplary embodiment, the spacing between the via T3 connected to the third electrode pad 123 and the via T4 connected to the fourth electrode pad 124 can be increased. As a result, according to the exemplary embodiment, parasitic capacitance generated between via T3 and via T4 can be suppressed. Furthermore, according to the exemplary embodiment, the path length from the first signal terminal 1b to the second signal terminal 1c can be increased, suppressing the deterioration of the isolation characteristics between the first filter 4 and the second filter 5.

[0112] Next, the first electrode pad 121, the fourth electrode pad 124, the first terminal 2a, and the fourth terminal 2d will be described. In an exemplary embodiment, the distance D1 between the center c11 of the first electrode pad 121 and the center c14 of the fourth electrode pad 124 is greater than the distance D2 between the center c21 of the first terminal 2a and the center c24 of the fourth terminal 2d. If we compare this to a case where the distance D2 between the centers c21 and c24 is the same, according to the exemplary embodiment, compared to the case where the distances D1 and D2 between the centers c11 and c14 are the same, the spacing between the via T1 connected to the first electrode pad 121 and the via T4 connected to the fourth electrode pad 124 can be increased. As a result, according to the exemplary embodiment, parasitic capacitance generated between via T1 and via T4 can be suppressed, and coupling between via T1 and via T4 can be suppressed. Therefore, according to the exemplary embodiment, coupling between the first sub-circuit portion 41 and the second sub-circuit portion 42 via vias T1, T4 or elements connected to vias T1, T4 can be suppressed. Therefore, according to the exemplary embodiment, deterioration of the isolation characteristics between the first filter 4 and the second filter 5 can be suppressed.

[0113] The above description of the first electrode pad 121, the fourth electrode pad 124, the first terminal 2a, and the fourth terminal 2d also applies to the group of the second electrode pad 122, the third electrode pad 123, the second terminal 2b, and the third terminal 2c; the group of the first electrode pad 121, the third electrode pad 123, the first terminal 2a, and the third terminal 2c; and the group of the second electrode pad 122, the fourth electrode pad 124, the second terminal 2b, and the fourth terminal 2d. That is, according to the exemplary embodiment, the spacing between the via T2 connected to the second electrode pad 122 and the via T3 connected to the third electrode pad 123 can be increased. As a result, according to the exemplary embodiment, parasitic capacitance generated between via T2 and via T3 can be suppressed, and coupling between via T2 and via T3 can be suppressed. Therefore, according to the exemplary embodiment, coupling between the first sub-circuit portion 41 and the second sub-circuit portion 42 via via T2, T3, or elements connected to via T2, T3 can be suppressed. Similarly, according to the exemplary embodiment, coupling between the first sub-circuit portion 41 and the second sub-circuit portion 42 via vias T1, T3 or elements connected to vias T1, T3, and coupling between the first sub-circuit portion 41 and the second sub-circuit portion 42 via vias T2, T4 or elements connected to vias T2, T4, can be suppressed. Thus, according to the exemplary embodiment, deterioration of the isolation characteristics between the first filter 4 and the second filter 5 can be suppressed.

[0114] Next, the isolation characteristics of the electronic device 100 according to the exemplary embodiment will be explained based on the simulation results after investigation. First, the model of the embodiment used in the simulation will be explained. The model of the embodiment is a model of the electronic device 100 according to the exemplary embodiment. In the simulation, the first circuit section 10 and the first sub-circuit section 41 of the first filter 4, the second circuit section 20 and the second sub-circuit section 42 of the second filter 5, and the third circuit section 30 of the third filter 6 were designed with the model of the embodiment as the demultiplexer operation. In addition, in the simulation, the first filter 4 to the third filter 6 were designed such that the passband of the first filter 4 is 3.300 to 5.000 GHz, the passband of the second filter 5 is 5.150 to 7.125 GHz, and the passband of the third filter 6 is 0.698 to 2.690 GHz.

[0115] Figure 8 This is a circuit diagram illustrating the circuit structure of the model in the embodiment. In addition to the first filter 4 to the third filter 6, the model in the embodiment also includes an inductor L41 and a capacitor C41. One end of the inductor L41 is connected to a common terminal 1a. One end of the third filter 6 and one end of the capacitor C41 are each connected to the other end of the inductor L41. The other end of the third filter 6 is connected to the third signal terminal 1d.

[0116] One end of the first filter 4 and the second filter 5 are each connected to the other end of the capacitor C41. The other end of the first filter 4 is connected to the first signal terminal 1b. The other end of the second filter 5 is connected to the second signal terminal 1c.

[0117] The third circuit section 30 of the third filter 6 includes inductors L31 and L32 and capacitors C31, C32, and C33. One end of inductor L31 is connected to the other end of inductor L41. One end of inductor L32 is connected to the other end of inductor L31. The other end of inductor L32 is connected to the third signal terminal 1d.

[0118] Capacitor C31 is connected in parallel with inductor L32. One end of capacitor C32 is connected to the junction of inductors L31 and L32. One end of capacitor C33 is connected to the other end of inductor L32. The other ends of capacitors C32 and C33 are each connected to ground.

[0119] The first circuit section 10 of the first filter 4 includes inductors L11, L12, L13, L14, L15, L16 and capacitors C11, C12, C13, C14. The first secondary circuit section 41 of the first filter 4 includes four elastic wave elements 411, 412, 413, 414.

[0120] One end of inductor L11 is connected to the other end of capacitor C41. One end of inductor L12 is connected to the other end of inductor L11. One end of capacitor C11 is connected to the other end of inductor L12. The other end of capacitor C11 is connected to the first terminal 2a of the second body 2.

[0121] One end of inductor L13 is connected to the junction of inductors L11 and L12. One end of capacitor C12 is connected to the other end of inductor L13. The other end of capacitor C12 is connected to ground.

[0122] One end of inductor L14 is connected to the other end of capacitor C11 and the first terminal 2a of the second body 2. One end of capacitor C13 is connected to the other end of inductor L14. The other end of capacitor C13 is connected to ground.

[0123] One end of each of the elastic wave elements 411 and 413 is connected to the first terminal 2a. One end of the elastic wave element 412 is connected to the other end of the elastic wave element 411. One end of the elastic wave element 414 is connected to the other end of the elastic wave element 413. The other end of each of the elastic wave elements 412 and 414 is connected to the second terminal 2b of the second body 2.

[0124] One end of each of inductors L15 and L16 is connected to the second terminal 2b. The other end of inductor L15 is connected to the first signal terminal 1b. The other end of inductor L16 is connected to the grounding component.

[0125] One end of capacitor C14 is connected to one end of inductor L15. The other end of capacitor C14 is connected to ground.

[0126] The second circuit section 20 of the second filter 5 includes inductors L21, L22, L23 and capacitors C21, C22, C23, C24, C25, C26. The second auxiliary circuit section 42 of the second filter 5 includes four elastic wave elements 421, 422, 423, 424.

[0127] One end of capacitor C21 is connected to the other end of capacitor C41. The other end of capacitor C21 and one end of inductor L21 are connected to the third terminal 2c of the second body 2. One end of capacitor C22 is connected to the other end of inductor L21. The other end of capacitor C22 is connected to the grounding component.

[0128] One end of each of the elastic wave elements 421 and 423 is connected to the third terminal 2c. One end of the elastic wave element 422 is connected to the other end of the elastic wave element 421. One end of the elastic wave element 424 is connected to the other end of the elastic wave element 423. The other end of each of the elastic wave elements 422 and 424 is connected to the fourth terminal 2d of the second body 2.

[0129] One end of capacitor C23 and one end of inductor L23 are connected to the fourth terminal 2d. One end of inductor L22 is connected to the other end of capacitor C23. The other end of inductor L22 is connected to the second signal terminal 1c. Capacitor C24 is connected in parallel with inductor L22.

[0130] One end of capacitor C25 is connected to the other end of inductor L23. The other end of capacitor C25 is connected to ground.

[0131] One end of capacitor C26 is connected to the other end of inductor L22. The other end of capacitor C26 is connected to ground.

[0132] Figure 5 The multiple inductors and multiple capacitors shown are constructed using multiple dielectric layers, multiple conductor layers and multiple vias of the laminate 50.

[0133] In addition, inductors L14 and L16 can be respectively connected to Figure 6 as well as Figure 5 The diagram shows "Inductor L1" and "Inductor L2". In this case, capacitor C13 can be used with... Figure 6 as well as Figure 5 The "capacitor C1" shown corresponds to this.

[0134] In addition, inductors L21 and L23 can be respectively connected to Figure 6 as well as Figure 5 The diagram shows "Inductor L3" and "Inductor L4". In this case, capacitor C25 can be used with... Figure 6 as well as Figure 8 The "capacitor C2" shown corresponds to this.

[0135] Next, the comparative example model used in the simulation will be explained. The comparative example model is a model of the electronic device used in the comparative example. The circuit structure of the electronic device model used in the comparative example is similar to... Figure 9 The circuit structure of the model shown in the embodiment is the same. Additionally, the electronic device of the comparative example includes a first body 101 instead of the first body 1 in the exemplary embodiment. The structure of the first body 101 is substantially the same as that of the first body 1 in the exemplary embodiment. However, in the model of the electronic device of the comparative example, the arrangement of the first electrode pads 121 to the fourth electrode pads 124 differs from that of the model in the embodiment.

[0136] Figure 10This is a top view showing the first electrode pads 121 to 124 and the first terminals 2a to 2d in the electronic device of the comparative example. In the model of the electronic device of the comparative example, the distance D1 between the centers of any two adjacent electrode pads 121 to 124 that are spaced apart is the same as the distance D2 between the centers of two terminals 2a to 2d, and these two terminals are respectively connected to the two electrode pads mentioned above.

[0137] In addition, in the comparative example model, the plurality of first conductor layers 61 of the first structure 8 are directly connected to the plurality of second conductor layers 62 of the second structure 9.

[0138] Next, the simulation results will be explained. In the simulation, the frequency characteristics of the isolation between the first filter 4 and the second filter 5 were determined for both the model of the embodiment and the model of the comparative example. Furthermore, the definition of isolation in the simulation is as follows. When a high-frequency signal with power P1 is input to the first signal terminal 1b, the power of the signal output from the second signal terminal 1c is set to P2. Isolation I is defined by the following equation (1).

[0139] I=10log(P2 / P1)…(1)

[0140] Figure 10 This is a characteristic graph representing the frequency response of the isolation. In Figure 10 In the graph, the horizontal axis represents frequency, and the vertical axis represents isolation. Additionally, in... Figure 10 In the figures, the curve labeled 301 represents the frequency response of the isolation in the embodiment model. The curve labeled 302 represents the frequency response of the isolation in the comparative example model. Based on the simulation results, it can be understood that the embodiment model (curve 301) has sufficient isolation characteristics in practical applications. Furthermore, as... Figure 11 As shown, in the model of the embodiment (curve 301), the absolute value of the isolation degree is larger compared with the model of the comparative example (curve 302).

[0141] [Variation Example]

[0142] Next, a first and a second modification of the exemplary embodiment of the electronic device 100 will be described. First, referring to... Figure 11 The first variation will be explained. Figure 11This is a top view showing the first electrode pads 121 to 124 and the first terminals 2a to 2d in the first modified example. In the first modified example, the shape (planar shape) of each of the first electrode pads 121 to 124 when viewed from the stacking direction (the direction parallel to the Z direction) is rectangular. In particular, in the first modified example, the planar shape of each of the second electrode pads 122 to 124 is similar to the planar shape of each of the second terminals 2b to 2d.

[0143] In the first variation, when viewed from the Z direction, a portion of the outer edge of the planar shape of the first terminal 2a may coincide with or substantially coincide with a portion of the outer edge of the planar shape of the first electrode pad 121. Similarly, when viewed from the Z direction, a portion of the outer edge of the planar shape of the second terminal 2b may coincide with or substantially coincide with a portion of the outer edge of the planar shape of the second electrode pad 122. When viewed from the Z direction, a portion of the outer edge of the planar shape of the third terminal 2c may coincide with or substantially coincide with a portion of the outer edge of the planar shape of the third electrode pad 123. When viewed from the Z direction, a portion of the outer edge of the planar shape of the fourth terminal 2d may coincide with or substantially coincide with a portion of the outer edge of the planar shape of the fourth electrode pad 124.

[0144] In addition, Figure 12 In the example shown, the planar shape of the first electrode pad 121 is not similar to the planar shape of the first terminal 2a. However, the planar shape of the first electrode pad 121 can also be similar to the planar shape of the first terminal 2a.

[0145] Next, refer to Figure 12 The second variation will be explained. Figure 11 This is a top view showing the first electrode pads 121 to 124 and the first terminals 2a to 2d in the second variation. In the second variation, the shapes (planar shapes) of the first terminals 2a to 2d when viewed from the stacking direction (the direction parallel to the Z direction) are each circular. The planar shapes of the first electrode pads 121 to 124 are similar to the planar shapes of the first terminals 2a to 2d.

[0146] In addition, with ​ Similarly, in the first variant shown, the planar shape of the first electrode pad 121 may not be similar to the planar shape of the first terminal 2a.

[0147] Furthermore, this disclosure is not limited to the exemplary embodiments described above, and various modifications are possible. For example, the electronic device of this disclosure may be a duplexer with two filters, or a bandpass filter with multiple filters.

[0148] Alternatively, a subset of all combinations of two electrode pads from the first electrode pad 121 to the fourth electrode pad 124 may satisfy the following condition: the center-to-center distance D1 between the two electrode pads is greater than the center-to-center distance D2 between the two terminals connected to each of the two electrode pads. For example, only the combination of the first electrode pad 121 and the second electrode pad 122 or the combination of the third electrode pad 123 and the fourth electrode pad 124 may satisfy the above condition. Alternatively, the combination of the first electrode pad 121 and the second electrode pad 122 and the combination of the third electrode pad 123 and the fourth electrode pad 124 may satisfy the above condition, while other combinations may not. Alternatively, the combination of the first electrode pad 121 and the fourth electrode pad 124 and the combination of the second electrode pad 122 and the third electrode pad 123 may satisfy the above condition, while other combinations may not.

[0149] In addition, when the planar shape of each of the first electrode pads 121 to the fourth electrode pads 124 is the shape of the first modified example, the planar shape of each of the first terminals 2a to the fourth terminals 2d can also be the shape in the second modified example.

[0150] As described above, an electronic device according to one embodiment of this disclosure includes: a first body comprising a plurality of stacked dielectric layers and a circuit portion; a second body mounted on the first body and comprising a sub-circuit portion; and a first filter comprising at least one of the circuit portion and the sub-circuit portion, and selectively allowing signals of a frequency within a first passband to pass through. The first body further has a first surface and a second surface located at both ends of the stacking direction of the plurality of dielectric layers, and includes a plurality of electrode pads disposed on the first surface. The second body further includes a plurality of terminals disposed on the outer surface of the second body. The plurality of electrode pads includes a first electrode pad and a second electrode pad. The plurality of terminals includes a first terminal connected to the first electrode pad and a second terminal connected to the second electrode pad. The circuit portion is connected to the first electrode pad, and the sub-circuit portion is connected to the second terminal. The center-to-center distance between the first electrode pad and the second electrode pad is greater than the center-to-center distance between the first terminal and the second terminal.

[0151] In one embodiment of the electronic device disclosed herein, the first body may further include a first signal terminal and a second signal terminal. The plurality of electrode pads may further include a third electrode pad and a fourth electrode pad. The plurality of terminals may further include a third terminal connected to the third electrode pad and a fourth terminal connected to the fourth electrode pad. The first electrode pad, the second electrode pad, the first terminal, and the second terminal may be connected to the first signal terminal. The third electrode pad, the fourth electrode pad, the third terminal, and the fourth terminal may be connected to the second signal terminal.

[0152] In addition, in an electronic device according to one embodiment of the present disclosure, the center-to-center distance between any two adjacent electrode pads that are spaced apart among a plurality of electrode pads can be greater than the center-to-center distance between two terminals that are respectively connected to any two electrode pads among a plurality of terminals.

[0153] Additionally, the electronic device in one embodiment of this disclosure may further include a second filter that selectively allows signals with frequencies within a second passband different from the first passband to pass through. The first filter may include a circuit section and a sub-circuit section. The first filter may be connected to a first signal terminal, and the second filter may be connected to a second signal terminal.

[0154] Furthermore, in an electronic device according to one embodiment of this disclosure, the length of the path from the first signal terminal to the second signal terminal is greater than the length of the path when the center-to-center distance between the first electrode pad and the second electrode pad is the same as the center-to-center distance between the first terminal and the second terminal.

[0155] In addition, in one embodiment of the electronic device disclosed herein, the shape of each of the multiple electrode pads when viewed from the stacking direction may also be circular.

[0156] In addition, in an electronic device according to one embodiment of the present disclosure, the shape of each of the plurality of electrode pads when viewed from the stacking direction can be similar to the shape of each of the plurality of terminals when viewed from the stacking direction.

[0157] In addition, in one embodiment of the electronic device disclosed herein, the first body may further include a plurality of through holes. The plurality of through holes may be connected to a plurality of electrode pads respectively.

[0158] Based on the foregoing description, it is evident that various methods and variations of this disclosure can be implemented. Therefore, within the scope equivalent to the claims, this disclosure may also be implemented in ways other than the exemplary embodiments described above.

Claims

1. An electronic device, characterized in that, have: The first body comprises multiple stacked dielectric layers and circuit components; The second main body is mounted on the first main body and includes a secondary circuit section; A first filter includes at least one of the said circuit portion and the said secondary circuit portion, and selectively allows signals of frequencies within a first passband to pass through. The first body further has a first surface and a second surface located at both ends of the stacking direction of the plurality of dielectric layers, and includes a plurality of electrode pads disposed on the first surface. The second body also includes a plurality of terminals disposed on the outer surface of the second body. The plurality of electrode pads includes a first electrode pad and a second electrode pad. The plurality of terminals includes a first terminal connected to the first electrode pad and a second terminal connected to the second electrode pad. The circuit portion is connected to the first electrode pad. The secondary circuit section is connected to the second terminal. The center-to-center distance between the first electrode pad and the second electrode pad is greater than the center-to-center distance between the first terminal and the second terminal.

2. The electronic device according to claim 1, characterized in that, The first body also includes a first signal terminal and a second signal terminal. The plurality of electrode pads further includes a third electrode pad and a fourth electrode pad. The plurality of terminals further includes a third terminal connected to the third electrode pad and a fourth terminal connected to the fourth electrode pad. The first electrode pad, the second electrode pad, the first terminal, and the second terminal are connected to the first signal terminal. The third electrode pad, the fourth electrode pad, the third terminal, and the fourth terminal are connected to the second signal terminal.

3. The electronic device according to claim 2, characterized in that, The center-to-center distance between any two adjacent electrode pads that are spaced apart is greater than the center-to-center distance between two terminals that are respectively connected to the two electrode pads.

4. The electronic device according to claim 2, characterized in that, It also includes a second filter that selectively allows signals with frequencies within a second passband that are different from the first passband to pass through. The first filter includes the circuit section and the sub-circuit section. The first filter is connected to the first signal terminal. The second filter is connected to the second signal terminal.

5. The electronic device according to claim 2, characterized in that, The length of the path from the first signal terminal to the second signal terminal is greater than the length of the path when the center-to-center distance between the first electrode pad and the second electrode pad is the same as the center-to-center distance between the first terminal and the second terminal.

6. The electronic device according to claim 1, characterized in that, The shape of each of the plurality of electrode pads is circular when viewed from the stacking direction.

7. The electronic device according to claim 1, characterized in that, The shapes of the plurality of electrode pads when viewed from the stacking direction are similar to the shapes of the plurality of terminals when viewed from the stacking direction.

8. The electronic device according to claim 1, characterized in that, The first body also includes multiple through holes. The plurality of through holes are respectively connected to the plurality of electrode pads.

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