Chip system and electronic equipment
By concentrating the clock tree on a single die in a 3D chip and utilizing inter-die interconnects and metal wire coupling, the clock skew problem caused by cross-die process variations is solved, thereby improving the clock signal quality and performance of the chip system.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-25
- Publication Date
- 2026-03-27
AI Technical Summary
In 3D chip design, clock path deviations caused by cross-chip process variations affect the chip's clock quality and performance, making it difficult to achieve fully synchronous data transmission.
By setting the clock tree on a single die and coupling it with timing devices on other dies through inter-die interconnects and interconnect metal lines, the impact of cross-die process variations on the clock signal is reduced, thereby improving the clock signal quality.
By centralizing the clock tree on a single die, the impact of cross-die process variations on the clock signal is reduced, improving the clock signal quality and performance of the chip system and simplifying the clock tree structure.
Smart Images
Figure CN121745017A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and more particularly to a chip system and electronic device. Background Technology
[0002] Currently, with the increasing demand for chip functionality and computing power, a single die is no longer sufficient to meet the growing needs of various applications. As a result, chiplet and 3-dimensional (3D) stacking designs have become a hot topic in current chip design. Chiplets and 3D stacking can utilize multiple dies, such as 3D stacking multiple dies to integrate more functions.
[0003] In digital chips, data transmission between units is synchronized and controlled by clock signals. In 3D chips, different dies may be fabricated from different wafers or using different processes. Therefore, cross-chip variation (CCV) may exist between dies. Cross-chip variation refers to the deviation caused by process fluctuations between two different dies. Cross-chip variation causes clock path deviations on different dies, resulting in degraded clock quality of the 3D chip and affecting chip performance. Summary of the Invention
[0004] This application provides a chip system and electronic device for improving the clock quality of a 3D structured chip system and improving chip performance.
[0005] In a first aspect, a chip system is provided, comprising a first die and a second die, the first die and the second die being coupled through an inter-die interconnect interface, and multiple timing devices disposed on the first die and the second die, such as registers, flip-flops, static random-access memory (SRAM), etc.; the chip system also includes a clock tree, the clock tree being disposed in the first die, and the timing devices of the second die being coupled to the clock tree through the inter-die interconnect interface and interconnect metal lines to obtain clock signals.
[0006] The chip system provided in this application includes multiple dies. The clock tree is set on the first die, and the timing devices on the second die are coupled to the clock tree through inter-die interconnect interfaces and interconnect metal lines. It is not necessary to set the clock tree on the second die, thus avoiding the clock tree being distributed on different dies. The interconnect metal lines are less affected by cross-die process deviations. Therefore, by setting the clock tree on the first die, the impact of cross-die process deviations on the clock signal quality of the chip system can be reduced, thereby improving the clock signal quality of the chip system and improving the performance of the chip system.
[0007] In one possible implementation, the first die includes multiple timing devices, the clock inputs of which are coupled to a clock tree via interconnect metal lines.
[0008] In one possible implementation, the clock tree includes a multi-level clock driver, where the first-level clock driver is used to connect to a clock source, and the last-level clock driver is used to couple with the clock input of the timing device of the first die and the clock input of the timing device of the second die.
[0009] In one possible implementation, the clock driver includes an inverter or a buffer.
[0010] In one possible implementation, the chip system also includes a clock source, which is located on the first die or on the second die and transmitted from the second die to the first die through the die-to-die interconnect interface and interconnect metal lines. This can reduce the impact of cross-die process deviations on the clock signal quality of the chip system.
[0011] In a second aspect, a first die is provided, the first die including a multi-stage clock driver, the first stage clock driver in the multi-stage clock driver is used to receive a clock signal, and the last stage clock driver in the multi-stage clock driver is used to couple with the clock input terminal of a timing device of the first die or the second die to output a clock signal to the timing device.
[0012] In one possible implementation, the final-stage clock driver is used to couple to the clock input of the timing device on the second die via an inter-die interconnect interface and interconnect metal lines.
[0013] In one possible implementation, the final-level clock driver is used to couple to the clock input of the timing device of the first die via interconnect metal lines to output a clock signal to the timing device of the first die.
[0014] Thirdly, a second die is provided, the second die including a plurality of timing devices, wherein the clock input terminal of the timing devices of the second die is used to couple with a clock tree disposed on the first die to receive a clock signal.
[0015] In one possible implementation, the clock input of the timing device of the second die is used to couple with the clock driver of the first die via interconnect metal lines and die-to-die interconnection interface to obtain the clock signal provided by the clock driver of the first die.
[0016] Fourthly, an electronic device is provided, including a circuit board and a chip system provided in the first aspect and any implementation thereof, the chip system being disposed on the circuit board. Attached Figure Description
[0017] Figure 1 This is a schematic diagram of a general-purpose clock circuit;
[0018] Figure 2 A schematic diagram of a general-purpose 3D chip;
[0019] Figure 3 A schematic diagram of an electronic device provided in an embodiment of this application;
[0020] Figure 4 A schematic diagram of a chip system provided in an embodiment of this application;
[0021] Figure 5 A schematic diagram of another chip system provided in an embodiment of this application;
[0022] Figure 6 A schematic diagram of the clock tree of a chip system provided in an embodiment of this application;
[0023] Figure 7 A flowchart illustrating the clock tree generation method provided in this application embodiment. Detailed Implementation
[0024] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.
[0025] Hereinafter, the terms "first," "second," etc., are used for descriptive convenience only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "multiple" means two or more. For example, multiple processing units refer to two or more processing units.
[0026] Furthermore, in the embodiments of this application, "upper," "lower," "left," and "right" are not limited to the orientation of the components schematically placed in the accompanying drawings. It should be understood that these directional terms can be relative concepts, used for relative description and clarification, and can change accordingly depending on the orientation of the components in the accompanying drawings. In the accompanying drawings, for clarity, the thickness of layers and regions is exaggerated, and the dimensional proportions between the parts in the drawings do not reflect the actual dimensional proportions.
[0027] In the embodiments of this application, unless otherwise explicitly specified and limited, the term "connection" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium. In addition, the term "electrical connection" can be a direct electrical connection or an indirect electrical connection through an intermediate medium.
[0028] In this application, the term "module" typically refers to a logically divided functional structure. A "module" can be implemented purely in hardware, or a combination of hardware and software. In this application, "and / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, B existing alone, or both A and B existing simultaneously.
[0029] In this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being better or more advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.
[0030] A chip includes various processing units with different functions, such as memory and arithmetic logic unit (ALU). These processing units work together to realize the chip's functions. For example, data A is read from the first memory and data B is read from the second memory. The ALU performs operations on data A and data B. If these two data arrive at the ALU simultaneously, the operation can be performed directly. However, in most cases, due to different transmission paths, these two data cannot arrive at the ALU simultaneously. This requires a clock signal to synchronize the operation. For example, data A and data B are read from the memory and latched in the first clock cycle. At this time, it is not necessary to consider which data arrives first; it is only necessary to ensure that both data are ready before the next clock cycle. In the next clock cycle, the ALU performs operations on data A and data B, so that the operation result will not be wrong.
[0031] In a chip, data transmission between units and the state switching of timing devices are synchronized and controlled by a clock signal. The clock signal is a periodic pulse signal, also known as the system clock or reference clock, and its unit is Hertz (Hz). The chip contains multiple timing devices, such as registers, whose function is to latch arriving data and keep it stable until the next valid clock edge arrives, at which point the data is released. If the data is not synchronized, the data to be processed will not arrive synchronously, leading to incorrect calculation results. Therefore, a clock signal is needed to control data synchronization. Because the clock signal is synchronized, the data can also be synchronized, enabling synchronized data processing and ensuring error-free calculation results.
[0032] The clock signal in a chip is usually provided by a clock source combined with a clock network. A chip may include multiple clock regions located at different locations on the chip. Each clock region includes multiple timing devices such as registers, flip-flops, and static random-access memory (SRAM). The clock network is the topology of the internal clock circuit of the chip, which can synchronously transmit the clock signal to the clock regions located at various locations on the chip. For example, it can synchronously transmit the clock signal to the timing devices located in the central region of the chip and to the timing devices located in the edge region of the chip.
[0033] Clock networks are typically implemented using a clock tree structure. The clock signal from the clock source is propagated step-by-step through multiple stages of inverters or buffers to the clock inputs of all sequential circuits within the chip. Inverters, buffers, and other units with specific logic operation or data storage functions, composed of transistors and interconnects, can be called standard cells or clock drivers. The structure from the clock source to the sequential devices, formed by these standard cells and the metal traces connecting them, is called the clock tree. The clock tree plays a crucial role in the chip.
[0034] Figure 1 A schematic diagram of a clock circuit is shown, such as... Figure 1 As shown, the clock circuit includes a clock source 110 and a clock tree 120. The clock source 110 outputs a clock signal; for example, the clock source 110 may include a phase-locked loop (PLL). The clock tree 120 transmits and amplifies the clock signal to drive timing devices in subsequent circuits, such as register 130. Figure 1As shown, the clock tree 120 typically includes multiple levels of clock drivers 121. Each level of clock driver includes one or more clock drivers 121. Among them, the clock driver 121 connected to the clock source 110 can be called the main clock driver, and the last level of clock driver 121 can be used to connect timing devices such as register 130.
[0035] With the increasing demand for chip computing power and the approaching physical limits of semiconductor device miniaturization, single-die chips are no longer sufficient to meet the growing needs of various applications. Chiplet technology or 3D stacking design is rapidly advancing as a major solution to continue Moore's Law, and is receiving increasing attention from both research and industry.
[0036] Chip stacking and 3D stacking designs allow multiple dies to be stitched together as needed to achieve 3D stacking, meeting different application scenarios. Furthermore, by rationally controlling the size of the dies, chip yield can be improved, thereby reducing production costs. Designing 3D structured chips is more challenging than designing single dies, especially achieving full synchronization of clock signals, which has always been a difficult research problem in the industry.
[0037] A complete 3D chip is typically formed by stacking multiple 2D chips. For ease of explanation, each individual 2D chip will be referred to as a die. As the integrated circuit industry continues to develop and device sizes shrink, the fluctuations in integrated circuit manufacturing processes are also increasing, posing significant challenges to circuit designers. Multiple dies in a 3D chip may be fabricated from different wafers and may belong to different process corners. This results in process variations between different dies and wafers, known as cross-chip variation (CCV). CCV presents a significant challenge to the clock tree design of 3D chips.
[0038] like Figure 2 As shown, Figure 2 A schematic diagram of a 3D chip is shown, including a stacked first die 210 and a second die 220, typically stacked in the chip thickness direction. The first die 210 and the second die 220 are coupled via an inter-die interconnect interface 230. The 3D chip includes a clock tree comprising a first clock path 211 located on the first die 210 and a second clock path 221 located on the second die 220. Figure 2In the example, the first clock path 211 and the second clock path 221 have the same structure and length, for example, including clock drivers of the same number of stages. The clock signal provided by the clock source 240 is transmitted to the timing device 212 on the first die 210 through the first clock path 211; the clock signal provided by the clock source 240 is transmitted to the timing device 222 on the second die 220 through the second clock path 221. This application is applicable to clock trees containing clock paths of any different lengths. The fact that clock paths 211 and 221 have the same length is only a specific case used for ease of description. The first clock path 211 and the second clock path 221 are of the same length. Therefore, ideally, the clock signal should arrive at the timing device 212 on the first die 210 and the timing device 222 on the second die 220 at the same time. However, due to cross-die process deviations between the first die 210 and the second die 220, deviations may occur between the first clock path 211 and the second clock path 221. For example, if one clock driver in the first clock path 211 is weak, or one clock driver in the second clock path 221 is strong, these deviations will cause differences in the clock signals transmitted by the first clock path 211 and the second clock path 221, resulting in clock skew. Clock skew refers to the time offset of a clock source arriving at the clock input terminals of two different timing devices. Clock skew can be expressed as: T skew =T clk2 -T clk1 , among which, T skew Indicates clock skew, T clk1 and T clk2 These represent the times when the clock source arrives at the clock inputs of two different timing devices. Cross-chip process deviations cause the same clock signal to arrive at the timing devices on the first die 210 and the second die 220 at inconsistent times, affecting the quality of the clock signal and potentially causing the entire 3D chip to malfunction.
[0039] To address this issue, this application provides a chip system that can be applied to various devices, such as those used in… Figure 3 The electronic device shown, Figure 3 This is a schematic diagram of an electronic device 30 provided in an embodiment of this application. The electronic device 30 can be a terminal, such as a server 31, a mobile terminal 32, a tablet computer 33, a laptop computer 34, a desktop computer 35, or an augmented reality (AR) device. Figure 3 (not shown in the image) Virtual reality (VR) devices (virtual reality technology) Figure 3 (not shown in the image), vehicle terminal ( Figure 3 (not shown in the image), etc.
[0040] This chip system comprises multiple modularly assembled dies with specific functions, such as data storage, computation, signal processing, and data flow management. Based on a rich reserve of intellectual property cores (IP), the chip system proposes the concept of IP as a chiplet (IaaC), aiming to achieve "plug-and-play" functionality for specialized IPs using dies. For example, for some core processor IPs, the die can be a graphics processing unit (GPU) IP, a neural network processing unit (NPU) IP, a video processing unit (VPU) IP, a digital signal processing (DSP) IP, an image signal processor (ISP) IP, or a display processor IP. Furthermore, the die can also be mixed-signal IP or radio frequency (RF) IP.
[0041] The chip system in this application can also be referred to as a chiplet system or a die, meaning the bare die can also be called a chip or a chiplet. For example, this chip system can be applied to a system-on-a-chip (SoC), on which a bare die with multiple functions is integrated.
[0042] Figure 4 This is a schematic diagram of a chip system provided in an embodiment of this application. For example, the chip system includes multiple dies, such as a first die 410 and a second die 420, which are stacked in the direction of chip thickness; this stacking method is called three-dimensional stacking. The first die 410 and the second die 420 can also be stacked in other ways, such as 2.5D stacking. The stacked dies can be coupled to each other through an inter-die interconnect interface 430.
[0043] The chip system includes a clock circuit, which includes a clock source 440 and a clock tree 450. The clock tree 450 is used to amplify the clock signal generated by the clock source 440 and transmit it to timing devices such as registers on any die of the chip system, such as multiple timing devices located on the first die 410 and multiple timing devices located on the second die 420 in the embodiments of this application.
[0044] The clock tree 450 includes a multi-stage clock driver. The first-stage clock driver in the multi-stage clock driver is used to receive clock signals, and the last-stage clock driver in the multi-stage clock driver is used to couple with the clock input of a timing device to provide a clock signal to the timing device. In this embodiment, the clock tree 450 is disposed in the first die 410, so the first die 410 can be referred to as the clock die, and the second die 420 as the non-clock die. The clock tree 450 on the clock die is connected to the timing device on the non-clock die through an inter-die interconnect interface and interconnect metal lines. For example, the last-stage clock driver of the clock tree 450 located on the first die 410 is electrically connected to the second die 420 through the inter-die interconnect interface. Within the second die 420, this interconnect interface is connected to the clock input of a timing device (e.g., a register) located on the second die 420 through interconnect metal lines.
[0045] In the chip system provided in this application embodiment, the clock tree 450 is disposed on one of the dies. For example, the multi-level clock drivers of the clock tree 450 and the interconnecting metal lines between them are disposed on the first die 410. The last-level clock driver in the multi-level clock drivers is connected to the clock input terminal of the timing device located on the first die 410 or the second die 420 through the die-to-die interconnect interface and / or interconnecting metal lines. For timing devices located on different dies, most of their clock paths are located on the first die 410, and the clock paths outside the first die 410 only have the die-to-die interconnect interface and interconnecting metal lines. Since the electrical characteristics of the interconnecting metal lines are not sensitive to process fluctuations compared to the clock drivers (e.g., inverters, buffers, etc.), that is, the electrical characteristics of the metal interconnecting lines are less affected by cross-die process deviations, and since the multi-level clock drivers of the clock tree 450 and the interconnecting metal lines between the clock drivers are all disposed on the same die, the influence of cross-die process deviations on the clock tree can also be avoided. Therefore, the influence of cross-die process deviations on the clock signal in the chip system can be reduced, timing deterioration can be avoided, and the performance of the 3D structure chip can be improved.
[0046] Clock Tree 450 includes multi-level clock drivers, for example, see reference Figure 1The clock tree structure shown includes one or more clock drivers at each level, forming a multi-level clock buffer structure. Generally, the higher the level of the clock buffer structure, the more clock drivers there are. For example, the first level has one clock driver, the second level has two, the third level has two to four, and so on. The first-level clock driver is used to connect to the clock source 440. In some cases, the clock driver connected to the clock source 440 is also called the main clock driver. The final-level clock driver is used to couple to the clock input of the corresponding timing device to transmit the clock signal to the corresponding timing device. The clock drivers in the clock tree 450 can be understood as nodes in the clock tree 450. Their function is similar to a clock repeater, used to transmit, recover, and amplify clock signals to drive larger loads. The clock signal path from the clock source 440 to the timing device can be called a clock path. The driving capability of each clock path is limited. The driving capability of the clock path can be improved by setting up clock drivers or other devices, or another clock path can be added to drive more and larger loads.
[0047] In one possible implementation, taking the first timing device 411 located on the first die 410 and the second timing device 421 located on the second die 420 as examples, the last-level clock driver in the clock tree 450 includes the first clock driver. The first clock driver is coupled to the clock input terminal (denoted as CP in the figure) of the second timing device 421 on the second die 420 through the die-to-die interconnect interface 430 and the interconnect metal line. The last-level clock driver in the clock tree 450 also includes the second clock driver. The second clock driver is coupled to the clock input terminal (denoted as CP in the figure) of the first timing device 411 on the first die 410 through the interconnect metal line.
[0048] For example, in combination Figure 4The clock tree 450 includes a first clock path 451 and a second clock path 452. In the first clock path 451, the last-stage clock driver 4511 is coupled to the clock input of the first timing device 411 and provides a clock signal to the first timing device 411. In the second clock path 452, the last-stage clock driver 4521 is coupled to the clock input of the second timing device 421 through the die-to-die interconnect interface 430 and interconnect metal lines and provides a clock signal to the second timing device 421. The first clock path 451 and the second clock path 452 have the same length, for example, clock drivers with the same number of stages. In this embodiment, for example, the first clock path 451 includes a 6-level clock driver, and the second clock path 452 also includes a 6-level clock driver. Since the multi-level clock drivers and interconnects in the first clock path 451 and the second clock path 452 are all located on the same die, the first clock path 451 and the second clock path 452 will not be affected by cross-die process fluctuations. This can avoid clock skew caused by cross-die process deviations when the clock tree 450 is distributed on multiple dies. For the parts of the first clock path 451 and the second clock path 452 located outside the non-clock die, there are only interconnect metal lines. The interconnect metal lines are minimally affected by cross-die process deviations. Therefore, the clocking scheme provided in this embodiment can reduce the impact of cross-die process deviations on the clock signal.
[0049] Furthermore, since the multi-level clock drivers of the clock tree are all located on the same die, for example, the first clock path 451 and the second clock path 452 are both located on the first die 410, and the lengths of the first clock path 451 and the second clock path 452 are the same, then if the driving capability is strong enough, most of the first clock path 451 and the second clock path 452 can be combined into one, for example, see [reference missing]. Figure 5Only the first clock path 451 is set, and the first clock path 451 simultaneously drives the first timing device 411 located on the first die 410 and the second timing device 421 located on the second die 420. In this configuration, the last-stage clock driver 4511 in the first clock path 451 is coupled to the clock input of the first timing device 411 and also to the clock input of the second timing device 421. For example, the last-stage clock driver 4511 in the first clock path 451 is connected to the clock input of the first timing device 411 via interconnect metal lines, and the last-stage clock driver in the first clock path 451 is connected to the clock input of the second timing device 421 via die-to-die interconnect interfaces and metal interconnect lines. In this way, the common path between the clock path of the first timing device 411 located on the first die 410 and the clock path of the second timing device 421 located on the second die 420 is maximized. That is, the part from the clock source 440 to the last-stage clock driver in the first clock path 451 has only interconnect metal lines for non-common paths. This simplifies the clock tree structure and reduces the clock skew fluctuations between the two timing devices by making the common path between the clock paths of the two timing devices as long as possible, thereby reducing the impact of cross-die process deviations on clock signal quality.
[0050] In other words, for the clock tree disposed on the first die 410, its last-stage clock driver is used to connect the clock input terminals of the timing devices of the first die 410 and the clock input terminals of the timing devices of the second die 420. Part of the last-stage clock driver is electrically connected to the clock input terminals of the timing devices of the first die 410, and part of the last-stage clock driver is electrically connected to the clock input terminals of the timing devices of the second die 420. Some of the last-stage clock drivers can be electrically connected to both the clock input terminals of the timing devices of the first die 410 and the clock input terminals of the timing devices of the second die 420 simultaneously. The chip system also includes a clock source 440, which outputs a clock signal to the clock tree. The clock tree drives and amplifies this clock signal and transmits it to the timing devices on each die in the chip system. In this embodiment, the clock source 440 can be a phase-locked loop (PLL), and the clock source 440 can be disposed on the first die 410.
[0051] In some other possible implementations, the clock source 440 can also be set on other dies. For example, the clock source 440 can be set on the second die 420 and propagate from the second die 420 to the first die 410 through the die-to-die interconnect interface and interconnect metal lines. Since the clock tree is set on the first die, the propagation path of the clock source from the second die to the first die is the common path of all clock paths. When the clock tree is set on the first die, the impact of cross-die process deviation on the clock signal quality of the chip system can also be reduced.
[0052] See Figure 6 The clocking scheme provided in this application concentrates the clock tree structure, which was originally distributed on various dies, onto one die of the 3D chip, called the clock die. For example, the clock tree structure, which was originally distributed on different dies, is set on the first die. For timing devices on non-clock dies, the clock tree on the clock die is driven by the clock tree through the inter-die interconnect interface and interconnect metal lines. Since the on-chip process deviation is relatively controllable, the clock skew caused by process fluctuations in the clock signals obtained by timing devices on different dies is relatively small. For example, a certain clock path connects timing devices located on both clock dies and non-clock dies. The last-stage clock driver in this clock path is connected to the clock input terminal of the timing device on the non-clock die through the inter-die interconnect interface and interconnect metal lines. The interconnect metal lines are minimally affected by process fluctuations, thus reducing the impact of cross-die process deviations on the clock signal of the chip system.
[0053] For a complex chip system, there may be more than one clock signal, thus requiring different clock trees. For example, the first clock signal might be transmitted through a first clock tree, and the second clock signal through a second clock tree. For the first clock signal and the first clock tree, the first clock tree can be located on the first die, which then serves as the clock die for the first clock signal. For the second clock signal and the second clock tree, if the first and second clock signals are not synchronized or there is no timing path between them, the second clock tree can be located on the second die, which then serves as the clock die for the second clock signal. Alternatively, in one possible implementation, both the first and second clock trees can be located on the first die, which simultaneously serves as the clock die for both the first and second clock signals.
[0054] In the examples above, the chip system is illustrated by stacking a first die and a second die to form a 3D structure. The first die and the second die may not be stacked in the vertical direction. For example, they may be set in the horizontal direction. Alternatively, the chip system may include multiple dies set in the horizontal direction and multiple dies stacked in the vertical direction. By simply setting the clock tree on one of the dies, the impact of cross-die process deviation on the clock signal can be reduced.
[0055] This application also provides a method for generating a clock tree. In chip design, the implementation of a clock tree is called clock tree synthesis (CTS), which is usually performed after placement and before routing. The method provided in this application mainly focuses on this stage.
[0056] See Figure 7 The method provided in this application includes:
[0057] S1: Arrange sequential devices.
[0058] In this stage, all standard cells (including combinational logic, sequential logic devices, etc.) contained in the initial input are placed at different locations on the die using line length and timing-driven algorithms to ensure the best possible performance and power consumption. Then, the positions of these standard cells are fine-tuned (legalized) to meet the grid requirements of the manufacturing process.
[0059] S2: Combined clock input.
[0060] Since the chip system provided in this application sets most of the clock tree structure on a single clock die, after the placement of standard cells and other devices is completed, the clock inputs of the timing devices on the non-clock die need to be merged into the inter-die interconnect interface between the clock die and the non-clock die. This inter-die interconnect interface is then considered as a clock tree sink on the clock die. Because only interconnect metal lines exist between the clock inputs of the timing devices on the non-clock die and the inter-die interconnect interface, the delay of the interconnect metal lines can be calculated in advance and used as input parameters for clock tree synthesis, which is beneficial for flattening the clock trees of multiple inter-die timing devices.
[0061] S3: Clock Tree Synthesis.
[0062] Clock tree synthesis propagates the clock signal step-by-step to all timing devices within the chip in a manner consistent with physical design rules by winding the clock path and adding buffers, inverters, etc. In this embodiment, the clock inputs of all timing devices are merged onto a single die, or onto the inter-die interconnects between this die and other dies. These inter-die interconnects are also considered the endpoints of the clock tree, and clock tree synthesis is performed uniformly. Therefore, the standard cells and interconnect lines used in clock tree synthesis can be limited to this single die, i.e., the clock die. The clock inputs of all sequential logic on other dies, i.e., non-clock dies, are connected to the clock die via interconnect lines and inter-die interconnects. These inter-die interconnects include at least one of hybrid bonding and through-silicon vias (TSVs).
[0063] After clock tree synthesis is completed, the clock inputs of the sequential devices on the clock die are driven by the clock tree on the clock die, while the clock inputs of the sequential devices on the non-clock die are driven by the clock tree on the clock die, the die interconnect interface, and the interconnect metal lines of the non-clock die.
[0064] This application also provides a die, such as the first die in the foregoing embodiments. The first die includes a multi-level clock driver, which can be connected in a tree structure. The first-level clock driver in the multi-level clock driver is used to receive a clock signal, and the last-level clock driver in the multi-level clock driver is used to couple with the clock input terminal of a timing device to output a clock signal to the timing device. Here, the timing device can be a timing device located on the first die, or it can be a timing device located outside the first die.
[0065] For example, the final-level clock driver in a multi-stage clock driver includes a first clock driver, which is coupled to the clock input of a timing device on a second die to output a clock signal to the timing device on the second die. Exemplarily, since the first clock driver is located on the first die, and the timing device it drives is located on the second die, the first clock driver can be coupled to the clock input of the timing device on the second die through inter-die interconnects and interconnect wires, such as through-silicon vias (TSVs) or hybrid bonding. This avoids distributing the clock tree across different dies and prevents clock quality from being affected by cross-die process variations.
[0066] The first die also includes multiple timing devices, and the first clock driver is coupled to the clock input of the timing devices of the first die to output a clock signal to the timing devices of the first die. For example, the first clock driver is coupled to the input of the timing devices of the first die through interconnect metal lines.
[0067] As can be seen, the first die provided in this application embodiment is provided with a clock tree, which can be directly coupled to the timing devices on the second die without going through other clock drivers. The clock tree of the first die and the timing devices on the second die are connected only through the die-to-die interconnect interface and interconnect metal lines, which can reduce the impact of cross-die process deviation on the clock signal.
[0068] This application also provides another type of die, such as the second die in the foregoing embodiments. The second die includes multiple timing devices, and the clock input terminal of the timing device is used to couple with the clock tree disposed on the first die to receive a clock signal. For example, the clock input terminal of the timing device on the second die can be coupled with the clock tree disposed on the first die through interconnect metal lines and die interconnect interfaces.
[0069] This application also provides an electronic device, which includes a circuit board and a chip system provided in the foregoing embodiments of this application, the chip system being disposed on the circuit board.
[0070] The beneficial effects that the first die, the second die, and the electronic device provided in this embodiment can achieve are similar to the beneficial effects in the chip system provided above, and will not be repeated here.
[0071] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A chip system, characterized in that, The chip system includes a first die and at least one second die, wherein the first die and the second die are coupled through an inter-die interconnect interface; The chip system includes a clock tree disposed in the first die, and the second die includes multiple timing devices. The clock input terminals of the timing devices of the second die are coupled to the clock tree through the die-to-die interconnect interface and interconnect metal lines.
2. The chip system according to claim 1, characterized in that, The first die includes multiple timing devices, and the clock input terminals of the timing devices on the first die are coupled to the clock tree via interconnect metal lines.
3. The chip system according to claim 1 or 2, characterized in that, The clock tree includes a multi-level clock driver. The first-level clock driver in the multi-level clock driver is used to connect to a clock source, and the last-level clock driver in the multi-level clock driver is used to couple with the clock input terminals of the timing devices of the first die and the timing devices of the second die.
4. The chip system according to claim 3, characterized in that, The clock driver includes an inverter or a buffer.
5. The chip system according to any one of claims 1 to 4, characterized in that, It also includes a clock source, which is located on the first die or the second die.
6. A first bare wafer, characterized in that, The first die includes a multi-stage clock driver. The first stage clock driver in the multi-stage clock driver is used to receive a clock signal. The last stage clock driver in the multi-stage clock driver is used to couple with the clock input terminal of the timing device of the first die and the second die to output the clock signal to the timing device.
7. The first bare wafer according to claim 6, characterized in that, The final-level clock driver is used to couple to the clock input of the timing device on the second die via an inter-die interconnect interface and interconnect metal lines.
8. The first bare wafer according to claim 6 or 7, characterized in that, The final-stage clock driver is used to couple to the clock input of the timing device of the first die via interconnect metal lines to output the clock signal.
9. A second bare wafer, characterized in that, The second die includes a plurality of timing devices, the clock input of which is used to couple with a clock tree disposed on the first die to receive a clock signal.
10. The second bare wafer according to claim 9, characterized in that, The timing device is used to couple to a clock tree disposed on the first die via interconnect metal lines and die-to-die interconnect interfaces.
11. An electronic device, characterized in that, It includes a circuit board and a chip system as described in any one of claims 1 to 5, wherein the chip system is disposed on the circuit board.