100G UDP high-speed switching device based on FPGA

Abstract

The invention relates to a 100G UDP high-speed switching device based on an FPGA, and belongs to the field of communication countermeasure. Comprising a user data buffer interface module, a UDPICMPARP module, a sending buffer module, an MAC packet parsing / sending module, an ICMP parsing module, an ARP parsing module, a UDP receiving module and a receiving buffer module. According to the 100G UDP high-speed exchange protocol stack, a modularized and layered design method is adopted, a 100G high-speed exchange device improved through hardware and parallelization design does not depend on an interrupt response model of a traditional CPU, FPGA logic is adopted for real-time judgment, a single-cycle judgment mode is adopted for a data interface, UDP protocol analysis is adopted, and finally real-time transmission of data is achieved. The method is suitable for high-speed data transmission with large bandwidth and high sampling rate. The method has the characteristics of high data rate, low resource occupation, high flexibility, stable and reliable transmission and the like.

Description

Technical Field

[0001] This invention relates to a high-speed switching device in the field of communication, specifically a high-speed data exchange device for signals within an FPGA, which is used in the field of communication reconnaissance. Background Technology

[0002] With the rapid improvement of the performance of chips such as AD / DA and the interface performance between chips such as PCIe, SRIO, and GTH, the data I / O throughput rate between sensing, computing, and storage nodes in distributed electromagnetic spectrum monitoring networks has become a bottleneck restricting system applications. Traditional gigabit or even 10-gigabit Ethernet can no longer meet the needs of high-speed, large-volume, and multi-specification data transmission between network nodes.

[0003] After years of research and revision, the 100G transmission standard introduced by the IEEE 802.3ba standard has become the mainstream high-speed interface for core networks. Domestically and internationally, the main approach is to use CPU processing resources to implement the function. However, since UDP / IP protocol processing requires a large amount of CPU resources to complete, and spectrum monitoring network node equipment, which is limited by factors such as power consumption, size, and weight, often does not have CPU processing resources, it greatly restricts the promotion and application of 100G transmission on network node equipment. Summary of the Invention

[0004] This invention aims to solve the aforementioned problems and innovate in the field of high-speed data transmission by providing a 100G UDP high-speed switching device based on FPGA.

[0005] The technical solution adopted in this invention is as follows: A 100G UDP high-speed switching device based on FPGA includes a high-speed serial transceiver module (1), a user data buffer module (2), a transmit buffer module (4), a receive buffer module (7), and a 100G interface module (6). It is characterized in that it further includes a UDP_ICMP_ARP module (3), a link layer processing transceiver module (5), a protocol parsing module (8), and a UDP receiving module (9). The high-speed serial transceiver module (1) is used to receive high-speed sampling data transmitted from the signal processing board via the GTH bus protocol and send it to the user data buffer module (2). It is also used to receive high-speed data sent by the UDP receiving module (9) after protocol parsing. The user data buffer module (2) is used to buffer the high-speed sampling data transmitted from the high-speed serial transceiver module (1) and to prevent the loss of high-speed data by setting two large buffers and using the ping-pong reading method. At the same time, the buffered data is sent to the UDP_ICMP_ARP module (3). The UDP_ICMP_ARP module (3) is used to receive high-speed data sent by the user data buffer module (2) and perform protocol parsing. Specifically, the parsing includes a 64-byte MAC interface, a 64-byte user data interface, a 4-byte ARP local request interface (the data content is the peer IP and a 10-byte host ARP request interface). The MAC data content used to report the host side is 48 bits, the IP is 32 bits, and the parsed data is sent to the sending buffer module (4). At the same time, the UDP_ICMP_ARP module (3) also responds to the ICMP and ARP parsing results sent by the protocol parsing module (8). The sending buffer module (4), namely TX-AXIS-STREAM, sends data stream information to receive UDP parsing data sent by the UDP_ICMP_ARP module (3). It also sets up two large buffers and uses a ping-pong reading method to cache the data again. At the same time, it sends the cached data to the link layer processing transceiver module (5). The link layer processing transceiver module (5), namely the Xilinx 100G Ethernet Subsystem IP core, is used to receive the buffered data sent by the transmit buffer module (4), and perform MAC link layer data protocol parsing on the data, and send the parsed result to the 100g interface module (6) through the high-speed serial link; at the same time, the link layer processing transceiver module (5) receives the UDP data sent by the 100g interface module (6), and performs ICMP protocol parsing on the UDP data; The 100g interface module (6) is used to receive data sent by the link layer processing and sending module (5), and send the data to the outside via UDP protocol. At the same time, it receives data sent from the outside via UDP protocol and sends the data to the receiving link layer processing and sending module (5). The receive buffer module (7), namely RX-AXIS-STREAM, receives data stream information and is used to receive UDP parsing data sent by the 100g interface module (6). It also sets up two large buffers and uses a ping-pong reading method to buffer the data again. At the same time, it sends the buffered data to the protocol parsing module (8) and the UDP receiving module (9). The protocol parsing module (8) is used to receive the MAC data packets parsed by the buffer module (7) and send the parsed data to the high-speed serial transceiver module (1), while feeding back the parsed ICMP and ARP packet receipt information to the UDP_ICMP_ARP module (3). The UDP receiving module (9) receives the MAC data packets parsed by the protocol parsing module (8) and determines whether the MAC packet type field (double byte) is 0x0800, the MAC packet protocol terminator (single byte) is 0x11, and the MAC-UDP packet length is greater than 0. If the above conditions are met, the data and UDP frame header information are output. The frame header information includes the destination MAC, host source IP, host UDP source port number, host UDP destination port number, and host destination IP. It should be noted that the UDP frame header information will be output in parallel with the data. The host destination IP and destination MAC are used to distinguish whether it is a multicast. The above process is used to determine whether it is an ICMP packet or a UDP data packet. Then, different packets are output to the high-speed serial transceiver module (1). Furthermore, the high-speed serial transceiver interface module (1) includes a high-speed data receiving module (101) and a high-speed data transmitting module (102), and the two modules share the same high-speed interface resource; the high-speed sampling data receiving module (101) uses the receiving end of the high-speed interface, and the high-speed data transmitting module (102) uses the transmitting end of the high-speed interface. Both the high-speed data receiving module (101) and the high-speed data transmitting module (102) are connected via the GTH bus and adopt the AURORA64 / 66B protocol. Among them, the high-speed data receiving module (101) is used to receive high-speed raw sampling data or pre-processed data transmitted from the high-speed digital board and send the high-speed data to the user data buffer module (2); the high-speed data sending module (102) is used to receive secondary synthetic data generated by the high-speed calibration synthesis module (5) and send it to the photoelectric conversion interface through the backplane.

[0006] Furthermore, the link layer transceiver module (5) includes a MAC parsing module (501) and a MAC transceiver module (502). The MAC parsing module (501) is used to receive the high-speed data buffered data sent by the sending buffer module (4) and perform link layer protocol parsing on the buffered data. Since the bus width of MAC under 100G is 64 bytes, which exceeds the maximum number of bytes required by the protocol to be judged, the judgment condition adopts the parallel AND logic method and sends the parsed data into the MAC transceiver module (502). The MAC transceiver module (502) is used to receive the data parsed by the MAC parsing module (501) at the link layer. The 100GMAC uses little-endian mode on the FPGA and the interface width is 512 bits. In order to facilitate the reception and transmission of some data in RTL design, the corresponding AXIS interface is flipped by byte. The parsed data is sent to the 100g interface module (6). Furthermore, the protocol parsing module (8) includes an ICMP parsing module (801) and an ARP parsing module (802). The ICMP parsing module (801) is used to receive data from the link layer processing transceiver module (5), and to parse the data using ICMP packets. It also uses ICMP packets to determine whether the MAC packet IP field (four bytes) is the local FPGA board setting IP, whether the MAC packet protocol terminator (single byte) is 0x01, whether the MAC-ICMP message type field (single byte) is 0x08, and whether the MAC packet type field (double byte) is 0x0800. If the above conditions are met, the data packet will be directly fed back to the UDP_ICMP_ARP sending module (3) through the content received by the FIFO interface. At the same time, a data feedback packet is constructed based on the source IP and whether it is a request packet or a response packet. The protocol is parsed and explained, and then the feedback packet is sent to the high-speed serial transceiver module (1). The ARP parsing module (802) is used to receive data from the link layer processing transceiver module (5) and perform ARP packet parsing on the data. The ARP parsing module (802) is mainly used to manage the internal ARP table information. When a communication request arrives, it will first determine whether it is already in the ARP table. If not, it will determine whether the ARP table is full. If it is not full, it will add the ARP request to the list. If it is full, it will delete the oldest record and add it to the ARP table, and then return. If the request information already exists in the ARP table, it will generate an ARP request message. The high-speed serial transceiver module (1) will also be used to determine whether the current MAC packet type field (two bytes) is 0x0806, whether the MAC-ARP packet destination IP field (four bytes) is the corresponding value of the local FPGA board setting IP and the MAC-ARP packet protocol field (two bytes). If the value is 1, it means that the host is making an ARP request. If the value is 2, it means that the host is making an ARP response. At the same time, the host side IP / MAC can be reported through the FIFO interface. If it is an ARP request, the request packet is fed back to the UDP_ICMP_ARP sending module (3), triggering the ARP response of the FPGA board. If there is an ARP response, the FPGA board is notified that the IP of the peer device has been found.

[0007] Compared with the prior art, the present invention has the following advantages: 1. The high-speed switching device improved by hardware-based and parallel design does not rely on the traditional CPU interrupt response model. Instead, it uses FPGA logic for real-time judgment, adopts a single-cycle judgment method for the data interface, and performs ARP and UDP / IP protocol parsing on 64-byte packets to ultimately achieve real-time data transmission.

[0008] 2. This invention adopts a modular and layered design method, with FPGA as the slave device and PC as the master device, to achieve a stable data transmission rate of 86.4Gbps and a data transmission accuracy of 100%.

[0009] 3. This invention uses the axis-Stream data interface to realize multi-channel point-to-point, multicast, broadcast and other UDP data transmission, and supports 100G data exchange based on the device, supporting independent, cooperative and DMA working modes. Attached Figure Description

[0010] Figure 1 The diagram shown is a block diagram illustrating the principle of this invention.

[0011] Figure 2 The diagram shown is a schematic of a high-speed serial transceiver module.

[0012] Figure 3 The diagram shown is a flowchart of the link layer's transceiver module.

[0013] Figure 4 The diagram shows the processing flow of the protocol parsing module. Detailed Implementation

[0014] The present invention will now be described in further detail with reference to the accompanying drawings.

[0015] Figure 1 The block diagram of the present invention shown is as follows: A 100G UDP high-speed switching device based on FPGA includes a high-speed serial transceiver module (1), a user data buffer module (2), a transmit buffer module (4), a receive buffer module (7) and a 100G interface module (6). The device is characterized by further including a UDP_ICMP_ARP module (3), a link layer processing transceiver module (5), a protocol parsing module (8) and a UDP receiving module (9). The high-speed serial transceiver module (1) is used to receive high-speed sampling data transmitted from the signal processing board via the GTH bus protocol and send it to the user data buffer module (2). It is also used to receive high-speed data sent by the UDP receiving module (9) after protocol parsing. The user data buffer module (2) is used to buffer the high-speed sampling data transmitted from the high-speed serial transceiver module (1) and to prevent the loss of high-speed data by setting two large buffers and using the ping-pong reading method. At the same time, the buffered data is sent to the UDP_ICMP_ARP module (3). The UDP_ICMP_ARP module (3) is used to receive high-speed data sent by the user data buffer module (2) and perform protocol parsing. Specifically, the parsing includes a 64-byte MAC interface, a 64-byte user data interface, a 4-byte ARP local request interface (the data content is the peer IP and a 10-byte host ARP request interface). The MAC data content used to report the host side is 48 bits, the IP is 32 bits, and the parsed data is sent to the sending buffer module (4). At the same time, the UDP_ICMP_ARP module (3) also responds to the ICMP and ARP parsing results sent by the protocol parsing module (8). The sending buffer module (4), namely TX-AXIS-STREAM, sends data stream information to receive UDP parsing data sent by the UDP_ICMP_ARP module (3). It also sets up two large buffers and uses a ping-pong reading method to cache the data again. At the same time, it sends the cached data to the link layer processing transceiver module (5). The link layer processing transceiver module (5), namely the Xilinx 100G Ethernet Subsystem IP core, is used to receive the buffered data sent by the transmit buffer module (4), and perform MAC link layer data protocol parsing on the data, and send the parsed result to the 100g interface module (6) through the high-speed serial link; at the same time, the link layer processing transceiver module (5) receives the UDP data sent by the 100g interface module (6), and performs ICMP protocol parsing on the UDP data; The 100g interface module (6) is used to receive data sent by the link layer processing and sending module (5), and send the data to the outside via UDP protocol. At the same time, it receives data sent from the outside via UDP protocol and sends the data to the receiving link layer processing and sending module (5). The receive buffer module (7), namely RX-AXIS-STREAM, receives data stream information and is used to receive UDP parsing data sent by the 100g interface module (6). It also sets up two large buffers and uses a ping-pong reading method to buffer the data again. At the same time, it sends the buffered data to the protocol parsing module (8) and the UDP receiving module (9). The protocol parsing module (8) is used to receive the MAC data packets parsed by the buffer module (7) and send the parsed data to the high-speed serial transceiver module (1), while feeding back the parsed ICMP and ARP packet receipt information to the UDP_ICMP_ARP module (3). The UDP receiving module (9) receives the MAC data packets parsed by the protocol parsing module (8) and determines whether the MAC packet type field (double byte) is 0x0800, the MAC packet protocol terminator (single byte) is 0x11, and the MAC-UDP packet length is greater than 0. If the above conditions are met, the data and UDP frame header information are output. The frame header information includes the destination MAC, host source IP, host UDP source port number, host UDP destination port number, and host destination IP. It should be noted that the UDP frame header information will be output in parallel with the data. The host destination IP and destination MAC are used to distinguish whether it is a multicast. The above process is used to determine whether it is an ICMP packet or a UDP data packet. Then, different packets are output to the high-speed serial transceiver module (1). like Figure 2 As shown, the high-speed serial transceiver interface module (1) includes a high-speed data receiving module (101) and a high-speed data transmitting module (102), and the two modules share the same high-speed interface resource; the high-speed sampling data receiving module (101) uses the receiving end of the high-speed interface, and the high-speed data transmitting module (102) uses the transmitting end of the high-speed interface. Both the high-speed data receiving module (101) and the high-speed data transmitting module (102) are connected via the GTH bus and adopt the AURORA64 / 66B protocol. The high-speed data receiving module (101) is used to receive high-speed raw sampling data or pre-processed data transmitted from the high-speed digital board and send the high-speed data to the user data buffer module (2); the high-speed data sending module (102) is used to receive secondary synthesized data generated by the high-speed calibration synthesis module (5) and send it to the photoelectric conversion interface through the backplane.

[0016] like Figure 3 As shown, the link layer transceiver module (5) includes a MAC parsing module (501) and a MAC transceiver module (502). The MAC parsing module (501) is used to receive the high-speed data buffered data sent by the sending buffer module (4) and perform link layer protocol parsing on the buffered data. Since the bus width of MAC under 100G is 64 bytes, which exceeds the maximum number of bytes required by the protocol to be judged, the judgment condition adopts the parallel AND logic method and sends the parsed data into the MAC transceiver module (502). The MAC transceiver module (502) is used to receive the data parsed by the MAC parsing module (501) at the link layer. The 100GMAC uses little-endian mode on the FPGA and the interface width is 512 bits. In order to facilitate the reception and transmission of some data in RTL design, the corresponding AXIS interface is flipped byte by byte. The parsed data is sent to the 100g interface module (6).

[0017] like Figure 4 As shown, the protocol parsing module (8) includes an ICMP parsing module (801) and an ARP parsing module (802). The ICMP parsing module (801) is used to receive data from the link layer processing transceiver module (5), and to parse the data using ICMP packets. It also uses ICMP packets to determine whether the MAC packet IP field (four bytes) is the local FPGA board setting IP, whether the MAC packet protocol terminator (single byte) is 0x01, whether the MAC-ICMP message type field (single byte) is 0x08, and whether the MAC packet type field (double byte) is 0x0800. If the above conditions are met, the data packet will be directly fed back to the UDP_ICMP_ARP sending module (3) through the content received by the FIFO interface. At the same time, a data feedback packet is constructed based on the source IP and whether it is a request packet or a response packet. The protocol is parsed and explained, and then the feedback packet is sent to the high-speed serial transceiver module (1). The ARP resolution module (802) receives data from the link layer processing transceiver module 5 and performs ARP packet parsing. The ARP resolution module (802) mainly manages the internal ARP table information. When a communication request arrives, it first checks whether the request is already in the ARP table. If not, it checks whether the ARP table is full. If not, it adds the ARP request to the list. If it is full, it deletes the oldest record and adds it to the ARP table, then returns. If the request information already exists in the ARP table, it generates an ARP request message for the high-speed serial transceiver module 1. At the same time, the ARP resolution module (802) checks whether the current MAC packet type field (two bytes) is 0x0806, whether the MAC-ARP packet destination IP field (four bytes) is the corresponding value of the local FPGA board setting IP and the MAC-ARP packet protocol field (two bytes). If the value is 1, it indicates that the host is making an ARP request; if the value is 2, it indicates that the host is making an ARP response. At the same time, the host side IP / MAC can be reported through the FIFO interface. If it is an ARP request, the request packet is fed back to the UDP_ICMP_ARP sending module (3), triggering the ARP response of the FPGA board. If there is an ARP response, the FPGA board is notified that the IP of the peer device has been found.

[0018] Signal transmission process: The high-speed sampled data transmitted by the signal processing board is transmitted through the GTH bus and adopts the AURORA64 / 66B protocol. It first enters the high-speed serial transceiver module (1). The high-speed data receiving module (101) of this module converts the high-speed serial data into a parallel data stream and completes the parsing and adaptation of the physical layer protocol. The parallel data stream is sent to the user data buffer module (2). This module buffers and shapes the high-speed burst data by setting two large buffers and adopting a ping-pong reading method to prevent data loss caused by the rate mismatch of subsequent processing modules and ensure that the data stream smoothly enters the protocol encapsulation stage. Then the data is sent to the UDP_ICMP_ARP module (3) and the protocol is parsed. The parsed data is sent to the sending buffer module (4) and the parsing results of ICMP and ARP sent by the protocol parsing module (8) are responded to at the same time.

[0019] Signal reception process: The MAC transceiver module (502) and MAC parsing module (501) of the link layer processing transceiver module (5) cooperate to perform MAC layer frame parsing on the received data, stripping the preamble, frame check sequence, etc., and extracting the complete IP data packet (which may contain UDP, ICMP or ARP messages), and outputting a standard AXIS data stream. The parsed data enters the receiving buffer module (7). This module uses a double-buffered ping-pong mechanism for buffering, and its key logic lies in data copying and parallel distribution: the same data stream is sent to the protocol parsing module (8) and the UDP receiving module (9) at the same time to realize the parallel processing of control messages and data messages.

Claims

1. A 100G UDP high-speed switching device based on FPGA, comprising a high-speed serial transceiver module (1), a user data buffer module (2), a transmit buffer module (4), a receive buffer module (7), and a 100G interface module (6), characterized in that, It also includes the UDP_ICMP_ARP module (3), the link layer processing and receiving module (5), the protocol parsing module (8), and the UDP receiving module (9); The high-speed serial transceiver module (1) is used to receive high-speed sampling data transmitted from the signal processing board via the GTH bus protocol and send it to the user data buffer module (2). It is also used to receive high-speed data sent by the UDP receiving module (9) after protocol parsing. The user data buffer module (2) is used to buffer the high-speed sampling data transmitted from the high-speed serial transceiver module (1) and to prevent the loss of high-speed data by setting two large buffers and using the ping-pong reading method. At the same time, the buffered data is sent to the UDP_ICMP_ARP module (3). The UDP_ICMP_ARP module (3) is used to receive high-speed data sent by the user data buffer module (2) and perform protocol parsing. Specifically, the parsing includes a 64-byte MAC interface, a 64-byte user data interface, a 4-byte ARP local request interface - the data content is the peer IP and a 10-byte host ARP request interface; among which, the MAC data content used to report the host side is 48 bits and the IP is 32 bits, and the parsed data is sent to the sending buffer module (4). At the same time, the UDP_ICMP_ARP module (3) responds to the parsing results of ICMP and ARP sent by the protocol parsing module (8). The sending buffer module (4), namely TX-AXIS-STREAM, sends data stream information to receive UDP parsing data sent by the UDP_ICMP_ARP module (3). It also sets up two large buffers and uses a ping-pong reading method to cache the data again. At the same time, it sends the cached data to the link layer processing transceiver module (5). The link layer processing transceiver module (5), namely the Xilinx 100G Ethernet Subsystem IP core, is used to receive the buffered data sent by the transmit buffer module (4), and perform MAC link layer data protocol parsing on the data, and send the parsed result to the 100g interface module (6) through the high-speed serial link; at the same time, the link layer processing transceiver module (5) receives the UDP data sent by the 100g interface module (6), and performs ICMP protocol parsing on the UDP data; The 100g interface module (6) is used to receive data sent by the link layer processing and sending module (5), and send the data to the outside via UDP protocol. At the same time, it receives data sent by the outside via UDP protocol and sends the data to the link layer processing transceiver module (5). The receive buffer module (7), namely RX-AXIS-STREAM, receives data stream information and is used to receive UDP parsing data sent by the 100g interface module (6). It also sets up two large buffers and uses a ping-pong reading method to buffer the data again. At the same time, it sends the buffered data to the protocol parsing module (8) and the UDP receiving module (9). The protocol parsing module (8) is used to receive the MAC data packets parsed by the buffer module (7) and send the parsed data to the high-speed serial transceiver module (1), while feeding back the parsed ICMP and ARP packet receipt information to the UDP_ICMP_ARP module (3). The UDP receiving module (9) receives the MAC data packets parsed by the protocol parsing module (8) and determines whether the MAC packet type field (double byte) is 0x0800, the MAC packet protocol terminator (single byte) is 0x11, and the MAC-UDP packet length is greater than 0. If the above conditions are met simultaneously, the data and UDP frame header information are output. The frame header information includes the destination MAC, host-side source IP, host-side UDP source port number, host-side UDP destination port number, and host-side destination IP. It should be noted that the UDP frame header information will be output in parallel with the data, and whether it is a multicast is distinguished by the host-side destination IP and destination MAC. The above process is used to determine whether it is an ICMP packet or a UDP data packet, and then different packets are output to the high-speed serial transceiver module (1).

2. The 100G UDP high-speed switching device based on FPGA according to claim 1, characterized in that, The high-speed serial transceiver interface module (1) includes a high-speed data receiving module (101) and a high-speed data transmitting module (102), and the high-speed data receiving module (101) and the high-speed data transmitting module (102) share the same high-speed interface resource; the high-speed sampling data receiving module (101) uses the receiving end of the high-speed interface, and the high-speed data transmitting module (102) uses the transmitting end of the high-speed interface. Both the high-speed data receiving module (101) and the high-speed data transmitting module (102) are connected via the GTH bus and adopt the AURORA64 / 66B protocol. The high-speed data receiving module (101) is used to receive high-speed raw sampling data or pre-processed data transmitted from the high-speed digital board and send the high-speed data to the user data buffer module (2); the high-speed data sending module (102) is used to receive secondary synthesized data generated by the high-speed calibration synthesis module (5) and send it to the photoelectric conversion interface through the backplane.

3. The 100G UDP high-speed switching device based on FPGA according to claim 1, characterized in that, The link layer processing transceiver module (5) includes a MAC parsing module (501) and a MAC transceiver module (502). The MAC parsing module (501) is used to receive the high-speed data buffered data sent by the sending buffer module (4) and perform link layer protocol parsing on the buffered data. Since the bus width of MAC under 100G is 64 bytes, which exceeds the maximum number of bytes required by the protocol to be judged, the judgment condition adopts the parallel AND logic method and sends the parsed data into the MAC transceiver module (502). The MAC transceiver module (502) is used to receive the data parsed by the MAC parsing module (501) at the link layer. The 100G MAC uses little-endian mode on the FPGA and the interface width is 512 bits. In order to facilitate the reception and transmission of some data in RTL design, the corresponding AXIS interface is flipped byte by byte. The parsed data is sent to the 100g interface module (6).

4. The 100G UDP high-speed switching device based on FPGA according to claim 1, characterized in that, The protocol parsing module (8) includes an ICMP parsing module (801) and an ARP parsing module (802); The ICMP parsing module (801) is used to receive data from the link layer processing transceiver module (5), and to parse the data using ICMP data packets. It also uses ICMP data packets to determine whether the MAC packet IP field is the local FPGA board setting IP, whether the MAC packet protocol terminator is 0x01, whether the MAC-ICMP message type field is 0x08, and whether the MAC packet type field is 0x0800. If the above conditions are met, the data packet will be directly fed back to the UDP_ICMP_ARP sending module (3) through the content received by the FIFO interface. At the same time, it constructs a data feedback packet based on the source IP and whether it is a request packet or a response packet, and parses and explains the protocol. Then, it sends the feedback packet to the high-speed serial transceiver module (1). The ARP parsing module (802) is used to receive data from the link layer processing transceiver module (5) and perform ARP packet parsing on the data. The ARP parsing module (802) is used to manage the internal ARP table information. When a communication request arrives, it first checks whether it is already in the ARP table. If not, it checks whether the ARP table is full. If not, it adds the ARP request to the list. If it is full, it deletes the oldest record and adds it to the ARP table, and then returns. If the request information already exists in the ARP table, it generates an ARP request message. The high-speed serial transceiver module (1) also performs ARP parsing. 802) By judging whether the current MAC packet type field is 0x0806, whether the destination IP field of the MAC-ARP packet is the corresponding value of the IP and MAC-ARP packet protocol field set by the local FPGA board, if the value is 1, it means that the host is making an ARP request; if the value is 2, it means that the host is making an ARP response. At the same time, the host side IP / MAC can be reported through the FIFO interface. If it is an ARP request, the request packet is fed back to the UDP_ICMP_ARP sending module (3), triggering the ARP response of the FPGA board. If there is an ARP response, the FPGA board is notified that the IP of the peer device has been found.

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