Low-probability display fault test system and method supporting AT and ATX dual modes
By using a low-probability display fault testing system that supports both AT and ATX modes and employs a photoelectric detection module to monitor brightness in real time, the system solves the problems of the concealment and difficulty in reproducing low-probability display faults, achieving automated detection and elimination, adapting to different ambient lighting conditions, and ensuring product quality.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-30
- Publication Date
- 2026-03-31
AI Technical Summary
Existing technologies are insufficient for effectively testing and eliminating low-probability display faults in computer hardware, industrial control, and consumer electronics, especially probabilistic display failures that occur upon power-on. These faults are characterized by their high degree of concealment, difficulty in reproduction, significant harm, and complexity in diagnosis.
A low-probability display fault testing system supporting both AT and ATX modes is adopted, including an analog signal configuration module, a display output module, a photoelectric detection module, and a dual-mode power control module. The photoelectric detection module monitors the brightness in real time, and the main control module is used to configure parameters and statistically analyze test results, supporting automated testing.
It enables automated detection and elimination of low-probability display faults, avoids complex image processing, adapts to different ambient lighting conditions, ensures that there are no potential display faults before the product leaves the factory, and is compatible with traditional AT and modern ATX power supply equipment.
Smart Images
Figure CN121762974A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of electronic equipment reliability testing and automated testing technology, specifically to a low-probability display fault testing system and method that supports both AT and ATX modes. Background Technology
[0002] In fields such as computer hardware, industrial control, and consumer electronics, circuit boards (including motherboards, graphics cards, industrial control boards, etc.) are core components. The display function serves as an indispensable human-machine interface for intelligent electronic devices, and its reliability directly affects customer use. "Probabilistic display failure upon startup" is a typical low-probability failure mode. Although its occurrence rate is usually one in a thousand (0.1%) or even lower, this failure has the following characteristics: High concealment: Due to the extremely low probability of failure, it is difficult to detect in conventional functional tests and aging tests; Difficult to reproduce: It requires a large number of repeated power on / off operations to trigger, making manual testing almost impossible; Highly dangerous: Once it occurs, it may cause the system to malfunction, and may have serious consequences in critical application scenarios (such as industrial control and medical equipment); Diagnosis is complex: the cause of the fault may involve multiple aspects such as power timing, signal integrity, firmware initialization, and component parameter drift; In summary, it is currently difficult to test for such low-probability display faults, which means that there is a potential for low-probability display faults in electronic devices before they leave the factory. Summary of the Invention
[0003] To address the aforementioned issues, this invention provides a low-probability display fault testing system and method that supports both AT and ATX modes, ensuring that potential low-probability display faults are completely eliminated before the product leaves the factory.
[0004] This invention adopts the following technical solution: a low-probability display fault testing system supporting both AT and ATX modes, comprising: The analog signal configuration module is used to configure test parameters, including power-on duration, power-off waiting time, detection delay time, detection duration, number of samples, and number of tests. The display output module is connected to the monitor under test and is used to display the test status of the monitor under test, including fault indication status, running indication status and standby indication status. The photoelectric detection module is used to achieve adaptive brightness detection; A dual-mode power control module is used to switch between AT mode and ATX mode. The main control module is connected to the analog signal configuration module, display output module, photoelectric detection module, and dual-mode power control module, and is used to realize parameter configuration, power supply mode switching, brightness detection of the display under test, and statistical analysis of detection results.
[0005] Further, the main control module includes a controller U1, a crystal oscillator X1, an interface J1, capacitors C1~C9, capacitor C36, and resistors R1~R4; the photoelectric detection module includes a capacitor C10 and resistors R5~R7; the controller U1 is an STM32F030R8T6 controller; the resistor R5 is a photoresistor; the interface J1 is a debugging interface; one end of resistor R1 is connected to a voltage of 3.3V, and the other end of resistor R1 is connected to one end of capacitors C4~C9 and then connected to a voltage of 33V; one end of capacitor C1 is connected to one end of crystal oscillator X1 and then connected to pin 3 of controller U1; one end of capacitor C2 is connected to the other end of crystal oscillator X1 and then connected to controller U1. Pin 4 of the controller U1 is connected to the controller U1 via a connection between one end of resistor R2 and one end of capacitor C3. The other ends of capacitors C1-C9 are grounded. One end of resistor R5 is connected to a 33V voltage. The other end of resistor R5 is connected to one end of resistor R6. The other end of resistor R6 is connected to one end of resistor R7 and capacitor C36, and then connected to pin 24 of the controller U1. The other ends of resistor R7 and capacitor C36 are grounded. One end of resistors R3 and R4 is connected to a 33V voltage. The other ends of resistors R3 and R4 are connected to pins 59 and 58 of the controller U1, respectively. Pins 2-4 of interface J1 are connected to pins 49, 46, and 7 of the controller U1, respectively. Further, the analog signal configuration module includes capacitors C11~C24, resistors R8~R21, rotary encoders H1~H3, rotary encoders M1~M3, rotary encoders S1~S3, rotary encoder TW, rotary encoder N, rotary encoder ER, rotary encoder TH, and rotary encoder TL; the A terminal of rotary encoder H1 is connected to one end of resistor R8 and capacitor C11; the A terminal of rotary encoder M1 is connected to one end of resistor R9 and capacitor C12; the A terminal of rotary encoder S1 is connected to one end of resistor R10 and capacitor C13; the A terminal of rotary encoder H2 is connected to one end of resistor R11 and capacitor C14; the A terminal of rotary encoder M2 is connected to one end of resistor R12 and capacitor C15; the A terminal of rotary encoder S2 is connected to one end of resistor R13 and capacitor C16; Terminal A of rotary encoder H3 is connected to one end of resistor R14 and capacitor C17; terminal A of rotary encoder M3 is connected to one end of resistor R15 and capacitor C18; terminal A of rotary encoder S3 is connected to one end of resistor R16 and capacitor C19; terminal A of rotary encoder TW is connected to one end of resistor R17 and capacitor C20; terminal A of rotary encoder N is connected to one end of resistor R18 and capacitor C21; terminal A of rotary encoder ER is connected to one end of resistor R19 and capacitor C22; terminal A of rotary encoder TH is connected to one end of resistor R20 and capacitor C23; terminal A of rotary encoder TL is connected to one end of resistor R21 and capacitor C24; the other ends of resistors R8 to R21 are connected to a voltage of 33V, and the other ends of capacitors C11 to C24 are grounded. Furthermore, it also includes: a reference brightness calibration module, connected to the main control module, for implementing reference brightness calibration; An isolation power management module, connected to the main control module, is used to achieve filtering isolation and provide stable voltage; Furthermore, the reference brightness calibration module includes dual-position DIP switches SW1 and SW2, a push-button switch BC, and resistors R22 to R26; one end of resistor R22 is connected to one end of dual-position DIP switch SW1, the other end of dual-position DIP switch SW1 is connected to a voltage of 33V via resistor R23, and the other end of resistor R22 is grounded; one end of resistor R24 is connected to one end of dual-position DIP switch SW2, the other end of dual-position DIP switch SW2 is connected to a voltage of 33V via resistor R25, and the other end of resistor R24 is grounded; one end of push-button switch BC is connected to pin 56 of controller U1, and the other end of push-button switch BC is grounded via resistor R26; Further, the display output module includes interface J2, capacitor C25, resistors R27~R29, and light-emitting diodes LED1~LED3; LED1~LED3 are yellow, green, and red light-emitting diodes, respectively; interface J2 is connected to the display under test, pins 2 and 3 of interface J2 are connected to pins 58 and 59 of controller U1, one end of LED1~LED3 is connected to pins 42, 43, and 44 of controller U1, the other end of LED1~LED3 is connected to one end of resistors R27~R29, the other end of resistors R27~R29 is connected to one end of capacitor C25 and then connected to a voltage of 33V, and the other end of capacitor C25 is grounded; Furthermore, the isolated power management module includes a voltage regulator U2 and capacitors C26 to C34; one end of capacitors C26 to C28 is connected to a voltage of 12V, one end of capacitors C29 to C31 is connected to pin 3 of the voltage regulator U2, one end of capacitors C32 to C34 is connected to pin 2 of the voltage regulator U2, and the other end of capacitors C26 to C34 is grounded. Further, the dual-mode power control module includes optocouplers U3 and U4, interfaces J3-J7, capacitor C35, resistors R30-R33, fuse F1, transistor Q1, and relay RELAY1; resistor R33 is a varistor; interface J4 is a 220V input interface, interface J5 is a 220V output interface, interface J6 is an ATX control signal output interface, and interface J7 is a ground interface; pin 3 of the voltage regulator U2 is connected to pin 1 of interface J3, interface J3 is connected to the power supply, pin 1 of interface J4 is connected to one end of fuse F1, the other end of fuse F1 is connected to one end of resistor R33, the other end of resistor R33 is connected to one end of capacitor C35, the other end of capacitor C35 is grounded, one end of resistor R30 is connected to pin 39 of controller U1, and the resistor... The other end of R30 is connected to the base of transistor Q1. The collector of transistor Q1 is connected to pin 2 of optocoupler U4. Pin 1 of optocoupler U4 is connected to 33V via resistor R31. Pin 3 of optocoupler U4 is grounded. Pin 4 of optocoupler U4 is connected to one end of the coil of relay RELAY1. The other end of the coil of relay RELAY1 is connected to 12V. One end of the contact of relay RELAY1 is connected to the other end of resistor R33. The other end of the contact of relay RELAY1 is connected to pin 1 of interface J5. One end of resistor R32 is connected to pin 40 of controller U1. The other end of resistor R32 is connected to pin 2 of optocoupler U3. Pin 1 of optocoupler U3 is connected to 33V. Pin 4 of optocoupler U3 is connected to interface J6. Pin 3 of optocoupler U3 is connected to interface J7. This invention also provides a low-probability display fault testing method supporting both AT and ATX modes, comprising the following steps: S1. Power on and initialize, then configure the test parameters through the analog signal configuration module. The test parameters include power-on duration, power-off waiting time, detection delay time, detection duration, number of samples, and number of tests. S2. Ensure that the display under test is displaying content normally and is facing the photoelectric detection module. The photoelectric detection module continuously samples at a set time interval. The main control module obtains the average value of the sampled data to achieve the reference brightness calibration. S3. Select the power control mode according to the type of the monitor device under test, i.e., select one of the AT mode or ATX mode, and then perform the startup test in the corresponding power control mode. S4. Perform tests according to the set loop logic until the preset target number of tests is reached; S5. After completing all the preset target number of tests, obtain the failure rate based on the test results; finally, power off the system to prepare for the next test.
[0006] Furthermore, step S4 also includes the following steps: S4.1 The main control module controls the power-on of the display device under test according to the selected power control mode, and starts timing at the same time; S4.2. When powered on, wait for the preset detection delay time; S4.3 After the delay ends, during the detection duration, the photoelectric detection module continuously samples multiple times at a set time interval to obtain the average brightness value AVG of the samples; S4.4 Subtract the detected average brightness value (AVG) from the reference brightness value. If the difference is within the allowable threshold error range, the display is considered normal. If the difference exceeds the threshold error range, the display is considered to have failed, and the number of failures is incremented by 1. S4.5 Continue to maintain the power-on state and wait for the remaining power-on time until the power-on time ends, then the main control module controls the display device under test to power off. S4.6 After waiting for the preset power-off waiting time, increment the number of tests by 1. S4.7 Determine whether the preset target number of tests has been reached. If not, return to step S4.1 and start the next test loop. If yes, exit the loop and proceed to step S5.
[0007] The beneficial effects of this invention are that it monitors the light emission status of the display under test in real time through a photoelectric detection module, avoiding complex image processing and expensive camera equipment. It can also adapt to different ambient lighting conditions and display brightness characteristics, capture extremely low probability display faults, and realize large-scale, long-term, and repeatable power-on and power-off cycle tests on the display device under test. This ensures that the potential for low probability display faults is completely eliminated before the product leaves the factory. Furthermore, it is compatible with traditional AT power supplies and modern ATX power supplies, achieving wide device compatibility and having good practical value. Attached Figure Description
[0008] Figure 1 This is a structural block diagram of the present invention; Figure 2 This is a schematic diagram illustrating the connection principle between the main control module and the photoelectric detection module in this invention. Figure 3 This is a circuit schematic diagram of the analog signal configuration module in this invention; Figure 4 This is a connection diagram of the reference brightness calibration module in this invention; Figure 5 This is a connection diagram of the display output module in this invention; Figure 6 This is a connection schematic diagram of the isolated power management module in this invention; Figure 7 This is a connection schematic diagram of the dual-mode power control module in this invention. Detailed Implementation
[0009] like Figures 1-7 As shown, the present invention provides a low-probability display fault testing system supporting both AT and ATX modes, comprising: The analog signal configuration module is used to configure test parameters, including power-on duration, power-off waiting time, detection delay time, detection duration, number of samples, and number of tests. The display output module is connected to the monitor under test and is used to display the test status of the monitor under test, including fault indication status, running indication status and standby indication status. The photoelectric detection module is used to achieve adaptive brightness detection; A dual-mode power control module is used to switch between AT mode and ATX mode. The main control module is connected to the analog signal configuration module, display output module, photoelectric detection module, and dual-mode power control module. It is used to realize parameter configuration, power supply mode switching, brightness detection of the display under test, and statistical analysis of test results.
[0010] The main control module includes controller U1, crystal oscillator X1, interface J1, capacitors C1~C9, capacitor C36, and resistors R1~R4; the photoelectric detection module includes capacitor C10 and resistors R5~R7; controller U1 uses an STM32F030R8T6 controller; resistor R5 is a photoresistor; interface J1 is a debugging interface; one end of resistor R1 is connected to a 3.3V voltage, and the other end of resistor R1 is connected to one end of capacitors C4~C9 and then connected to a 33V voltage; one end of capacitor C1 is connected to one end of crystal oscillator X1 and then connected to pin 3 of controller U1; one end of capacitor C2 is connected to the other end of crystal oscillator X1 and then connected to controller U1. Pin 4 of the controller is connected to pin 7 of controller U1 via one end of resistor R2 and one end of capacitor C3. The other ends of capacitors C1 to C9 are grounded. One end of resistor R5 is connected to a voltage of 33V. The other end of resistor R5 is connected to one end of resistor R6. The other end of resistor R6 is connected to one end of resistor R7 and capacitor C36, and then connected to pin 24 of controller U1. The other ends of resistor R7 and capacitor C36 are grounded. One end of resistors R3 and R4 is connected to a voltage of 33V. The other ends of resistors R3 and R4 are connected to pins 59 and 58 of controller U1, respectively. Pins 2 to 4 of interface J1 are connected to pins 49, 46, and 7 of controller U1, respectively.
[0011] The analog signal configuration module includes capacitors C11~C24, resistors R8~R21, rotary encoders H1~H3, rotary encoders M1~M3, rotary encoders S1~S3, rotary encoder TW, rotary encoder N, rotary encoder ER, rotary encoder TH, and rotary encoder TL. Terminal A of rotary encoder H1 is connected to one end of resistor R8 and capacitor C11; terminal A of rotary encoder M1 is connected to one end of resistor R9 and capacitor C12; terminal A of rotary encoder S1 is connected to one end of resistor R10 and capacitor C13; terminal A of rotary encoder H2 is connected to one end of resistor R11 and capacitor C14; terminal A of rotary encoder M2 is connected to one end of resistor R12 and capacitor C15; and terminal A of rotary encoder S2 is connected to one end of resistor R13 and capacitor C16. The A terminal of rotary encoder H3 is connected to one end of resistor R14 and capacitor C17; the A terminal of rotary encoder M3 is connected to one end of resistor R15 and capacitor C18; the A terminal of rotary encoder S3 is connected to one end of resistor R16 and capacitor C19; the A terminal of rotary encoder TW is connected to one end of resistor R17 and capacitor C20; the A terminal of rotary encoder N is connected to one end of resistor R18 and capacitor C21; the A terminal of rotary encoder ER is connected to one end of resistor R19 and capacitor C22; the A terminal of rotary encoder TH is connected to one end of resistor R20 and capacitor C23; the A terminal of rotary encoder TL is connected to one end of resistor R21 and capacitor C24; the other ends of resistors R8 to R21 are connected to a 33V voltage, and the other ends of capacitors C11 to C24 are grounded.
[0012] The system also includes: a reference brightness calibration module, which is connected to the main control module and is used to perform reference brightness calibration; The isolated power management module, connected to the main control module, is used to achieve filtering and isolation and provide stable voltage; Furthermore, the reference brightness calibration module includes dual-position DIP switches SW1 and SW2, a push switch BC, and resistors R22 to R26. One end of resistor R22 is connected to one end of dual-position DIP switch SW1, and the other end of dual-position DIP switch SW1 is connected to a voltage of 33V via resistor R23. The other end of resistor R22 is grounded. One end of resistor R24 is connected to one end of dual-position DIP switch SW2, and the other end of dual-position DIP switch SW2 is connected to a voltage of 33V via resistor R25. The other end of resistor R24 is grounded. One end of push switch BC is connected to pin 56 of controller U1, and the other end of push switch BC is grounded via resistor R26.
[0013] The display output module includes interface J2, capacitor C25, resistors R27~R29, and LEDs LED1~LED3. LEDs LED1~LED3 are yellow, green, and red LEDs, respectively. Interface J2 is connected to the display under test. Pins 2 and 3 of interface J2 are connected to pins 58 and 59 of controller U1, respectively. One end of LEDs LED1~LED3 is connected to pins 42, 43, and 44 of controller U1, respectively. The other end of LEDs LED1~LED3 is connected to one end of resistors R27~R29, and the other end of resistors R27~R29 is connected to one end of capacitor C25 and then connected to a voltage of 33V. The other end of capacitor C25 is grounded.
[0014] The isolated power management module includes a voltage regulator U2 and capacitors C26 to C34. One end of capacitors C26 to C28 is connected to a voltage of 12V. One end of capacitors C29 to C31 is connected to pin 3 of voltage regulator U2. One end of capacitors C32 to C34 is connected to pin 2 of voltage regulator U2. The other ends of capacitors C26 to C34 are all grounded.
[0015] The dual-mode power control module includes optocouplers U3 and U4, interfaces J3-J7, capacitor C35, resistors R30-R33, fuse F1, transistor Q1, and relay RELAY1; resistor R33 is a varistor; interface J4 is a 220V input interface, interface J5 is a 220V output interface, interface J6 is an ATX control signal output interface, and interface J7 is a ground interface; pin 3 of voltage regulator U2 is connected to pin 1 of interface J3, interface J3 is connected to the power supply, pin 1 of interface J4 is connected to one end of fuse F1, the other end of fuse F1 is connected to one end of resistor R33, the other end of resistor R33 is connected to one end of capacitor C35, the other end of capacitor C35 is grounded, and one end of resistor R30 is connected to pin 39 of controller U1. The other end of R30 is connected to the base of transistor Q1. The collector of transistor Q1 is connected to pin 2 of optocoupler U4. Pin 1 of optocoupler U4 is connected to a voltage of 33V via resistor R31. Pin 3 of optocoupler U4 is grounded. Pin 4 of optocoupler U4 is connected to one end of the coil of relay RELAY1. The other end of the coil of relay RELAY1 is connected to a voltage of 12V. One end of the contact of relay RELAY1 is connected to the other end of resistor R33. The other end of the contact of relay RELAY1 is connected to pin 1 of interface J5. One end of resistor R32 is connected to pin 40 of controller U1. The other end of resistor R32 is connected to pin 2 of optocoupler U3. Pin 1 of optocoupler U3 is connected to a voltage of 33V. Pin 4 of optocoupler U3 is connected to interface J6. Pin 3 of optocoupler U3 is connected to interface J7.
[0016] This invention also provides a low-probability display fault testing method supporting both AT and ATX modes, comprising the following steps: S1. Power on and initialize, then configure the test parameters through the analog signal configuration module. The test parameters include power-on duration, power-off waiting time, detection delay time, detection duration, number of samples, and number of tests. Specifically, test parameters are configured using multiple rotary encoders: 1. Timing parameter settings (via rotary encoder) Power-on duration setting: The total duration for which the display device under test remains powered on during a single test is set via rotary encoder H1 (0-23 hours), rotary encoder M1 (0-59 minutes), and rotary encoder S1 (0-59 seconds); Power-off waiting time setting: The power-off waiting time between two power-on cycles can be set via rotary encoder H2, rotary encoder M2, and rotary encoder S2; Detection delay time setting: The detection delay time from powering on the device to starting brightness detection can be set via rotary encoder H3, rotary encoder M3, and rotary encoder S3; 2. Detection parameter settings (via rotary encoder) Detection window time: The detection duration window for a single brightness detection is set by rotating the encoder TW (0-59 seconds); Number of samplings: The number of times the photoresistor is sampled within the detection window time is set by the rotary encoder N (1-100 times); Error range: The allowable percentage error for brightness determination is set by the rotary encoder Er (0-99%). 3. Target number of repetitions (via rotary encoder) Target number of tests: The total number of tests is set by combining the rotary encoder TH (hundreds digit, 0-99) and the rotary encoder TL (units digit, 0-99). The calculation formula is: Target number of tests T = TH×100 + TL; S2. Ensure that the display under test is displaying content normally and facing the photoelectric detection module. Press and hold the button BC. The photoelectric detection module will continuously sample at 100ms intervals. After releasing the button BC, the controller U1 will automatically calculate the average value of the samples and use the average value of the samples as the reference brightness value, thereby realizing the reference brightness calibration. Replacing complex image processing with average value comparison can reduce the amount of computation by more than 99% and reduce the failure rate. S3. Select the power control mode according to the type of the monitor device under test, i.e., select either AT mode or ATX mode; then perform the startup test in the corresponding power control mode, i.e., switch the dual-position DIP switch SW2 to the RUN position, which means that the system will immediately start the automatic cycle test and the green LED2 will light up; switch the dual-position DIP switch SW2 to the STOP position, which means that the system will enter the standby state and the yellow LED1 will light up. In AT mode: when the dual-position DIP switch SW1 is set to the AT position, the dual-mode power control module directly controls the AC power supply of the display device under test through interface J5 (i.e., 220V output interface) and relay RELAY1. ATX mode: Set the dual-position DIP switch SW1 to the ATX position. The dual-mode power control module outputs the ATX power-on signal through interfaces J6 and J7 to control the power-on timing signal of the display device under test. S4. Perform tests according to the set loop logic until the preset target number of tests is reached; Furthermore, step S4 also includes the following steps: S4.1 The main control module controls the power-on of the display device under test according to the selected power control mode, and starts timing the total power-on time. The total power-on time is set by rotary encoder H1 (0-23 hours), rotary encoder M1 (0-59 minutes), and rotary encoder S1 (0-59 seconds). S4.2. When powered on, wait for the preset detection delay time; S4.3 After the delay ends, during the detection duration, the photoelectric detection module continuously samples multiple times at a set time interval to obtain the average brightness value AVG of the samples; S4.4 Subtract the detected average brightness value (AVG) from the reference brightness value. If the difference is within the allowable threshold error range, the display is considered normal and the green LED2 remains lit. If the difference exceeds the threshold error range, the display is considered to have failed, the red LED3 lights up, and the number of failures is incremented by 1. S4.5 Regardless of the test result, continue to maintain the power-on state and wait for the remaining power-on time until the power-on time ends, at which point the main control module controls the display device under test to power off. S4.6 After waiting for the preset power outage waiting time, increment the total number of tests by 1 and update the current test progress in real time: number of tests completed / number of failures. S4.7 Determine whether the preset target number of tests has been reached. If not, return to step S4.1 and start the next test loop; if yes, exit the loop and proceed to step S5. Through a single cycle of step S4, namely power-on control → delay wait → detection window → brightness judgment → remaining power-on wait → power-off control → interval wait → count update; Loop control: The total number of loops is set by T=TH×100+TL, and the test will stop automatically when the total number of tests is reached; thus, unattended long-term stress testing can be achieved, and extremely low probability faults can be detected and displayed. S5. After completing all the preset target number of tests, obtain the failure rate based on the test results. That is, the test display shows the complete test statistics, including: total number of tests, number of failures, and failure rate (number of failures / total number of tests × 100%). Finally, the system was powered off, and all records were cleared in preparation for the next test.
[0017] This invention enables highly configurable test parameter settings through dual-position DIP switches SW1 and SW2, push-button switch BC, and multiple rotary encoders. It uses photoresistors to monitor the brightness of the display under test in real time, replacing the camera and simplifying the image recognition problem into a brightness detection problem. It also supports dual power supply control modes (i.e., AT mode and ATX mode), enabling automated capture and statistics of display faults with extremely low probability.
[0018] In summary, this invention achieves independent adjustment of power-on duration, power-off interval, and detection delay through multiple rotary encoders. It forms a complete detection closed loop through photosensitive detection → brightness judgment → counting statistics. Furthermore, the maximum number of tests can be set through rotary encoders TH and TL to avoid infinite loops. In addition, power mode control is synchronized with detection, and the counting and failure statistics are automatically correlated, which can reduce misoperation, avoid coordination problems among multiple devices, and improve detection accuracy.
[0019] The following table shows the functions of each component: It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.
[0020] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.
Claims
1. A low probability display failure test system supporting AT and ATX dual mode, characterized in that: The application relates to a display testing device. The display testing device comprises an analog signal configuration module, a display output module, a photoelectric detection module and a dual-mode power control module. The analog signal configuration module is used for configuring test parameters, and the test parameters include power-on duration, power-off waiting time, detection delay time, detection duration, sampling times and test times. The display output module is connected with a display to be tested and is used for displaying the test working state of the display to be tested, including a fault indication state, a running indication state and a standby indication state. The photoelectric detection module is used for realizing adaptive brightness detection. The dual-mode power control module is used for realizing dual-mode switching of AT mode and ATX mode.
2. The low probability fault test system supporting AT and ATX dual mode according to claim 1, characterized in that: The main control module is connected with the analog signal configuration module, the display output module, the photoelectric detection module and the dual-mode power control module, and is used for realizing parameter configuration, power supply mode switching, display brightness detection and detection result statistics. The main control module comprises a controller U1, a crystal oscillator X1, an interface J1, capacitors C1-C9, a capacitor C36 and resistors R1-R4. The photoelectric detection module comprises a capacitor C10 and resistors R5-R7. The controller U1 is an STM32F030R8T6 controller. One end of the resistor R1 is connected with a voltage of 3.3 V, the other end of the resistor R1 is connected with one end of the capacitor C4-C9 and then connected with a voltage of 33 V, one end of the capacitor C1 is connected with one end of the crystal oscillator X1 and then connected with the 3th pin of the controller U1, one end of the capacitor C2 is connected with the other end of the crystal oscillator X1 and then connected with the 4th pin of the controller U1, one end of the resistor R2 is connected with one end of the capacitor C3 and then connected with the 7th pin of the controller U1, and the other ends of the capacitors C1-C9 are grounded. One end of the resistor R5 is connected with a voltage of 33 V, the other end of the resistor R5 is connected with one end of the resistor R6, the other end of the resistor R6 is connected with one end of the resistor R7 and the capacitor C36 and then connected with the 24th pin of the controller U1, and the other ends of the resistor R7 and the capacitor C36 are grounded. One end of the resistor R3 is connected with one end of the resistor R4 and then connected with a voltage of 33 V, and the other ends of the resistors R3 and R4 are connected with the 59th and 58th pins of the controller U1. The 2nd-4th pins of the interface J1 are connected with the 49th, 46th and 7th pins of the controller U1.
3. The low probability fault test system supporting AT and ATX dual modes according to claim 2, characterized in that: The analog signal configuration module comprises capacitors C11-C24, resistors R8-R21, rotary encoders H1-H3, rotary encoders M1-M3, rotary encoders S1-S3, a rotary encoder TW, a rotary encoder N, a rotary encoder ER, a rotary encoder TH, and a rotary encoder TL. The A end of the rotary encoder H1 is connected to the resistors R8 and the one end of the capacitor C11. The A end of the rotary encoder M1 is connected to the resistors R9 and the one end of the capacitor C12. The A end of the rotary encoder S1 is connected to the resistors R10 and the one end of the capacitor C13. The A end of the rotary encoder H2 is connected to the resistors R11 and the one end of the capacitor C14. The A end of the rotary encoder M2 is connected to the resistors R12 and the one end of the capacitor C15. The A end of the rotary encoder S2 is connected to the resistors R13 and the one end of the capacitor C16. The A end of the rotary encoder H3 is connected to the resistors R14 and the one end of the capacitor C17. The A end of the rotary encoder M3 is connected to the resistors R15 and the one end of the capacitor C18. The A end of the rotary encoder S3 is connected to the resistors R16 and the one end of the capacitor C19. The A end of the rotary encoder TW is connected to the resistors R17 and the one end of the capacitor C20. The A end of the rotary encoder N is connected to the resistors R18 and the one end of the capacitor C21. The A end of the rotary encoder ER is connected to the resistors R19 and the one end of the capacitor C22. The A end of the rotary encoder TH is connected to the resistors R20 and the one end of the capacitor C23. The A end of the rotary encoder TL is connected to the resistors R21 and the one end of the capacitor C24. The other ends of the resistors R8-R21 are connected to a voltage of 33 V, and the other ends of the capacitors C11-C24 are grounded.
4. The low probability fault test system supporting AT and ATX dual modes according to claim 2, characterized in that: It also comprises a reference brightness calibration module connected to the main control module for realizing reference brightness calibration. An isolation power management module connected to the main control module for realizing filtering and isolation and providing stable voltage.
5. The low probability fault test system supporting AT and ATX dual modes according to claim 4, characterized in that: The reference brightness calibration module comprises dual-bit DIP switches SW1 and SW2, a press switch BC, and resistors R22-R26. One end of the resistor R22 is connected to one end of the dual-bit DIP switch SW1, the other end of the dual-bit DIP switch SW1 is connected to the resistor R23 and then connected to a voltage of 33 V, and the other end of the resistor R22 is grounded. One end of the resistor R24 is connected to one end of the dual-bit DIP switch SW2, the other end of the dual-bit DIP switch SW2 is connected to the resistor R25 and then connected to a voltage of 33 V, and the other end of the resistor R24 is grounded. One end of the press switch BC is connected to pin 56 of the controller U1, and the other end of the press switch BC is connected to the resistor R26 and then grounded.
6. The low probability fault test system supporting AT and ATX dual modes according to claim 2, characterized in that: The display output module includes interface J2, capacitor C25, resistors R27-R29, light emitting diodes LED1-LED3; the light emitting diodes LED1-LED3 are yellow light emitting diode, green light emitting diode and red light emitting diode respectively; the interface J2 is connected with the display to be tested, the 2th and 3th pins of the interface J2 are connected with the 58th and 59th pins of the controller U1 respectively, one end of the light emitting diodes LED1-LED3 is connected with the 42th, 43th and 44th pins of the controller U1 respectively, the other end of the light emitting diodes LED1-LED3 is connected with one end of the resistors R27-R29 respectively, the other end of the resistors R27-R29 is connected with one end of the capacitor C25, and the other end of the capacitor C25 is grounded.
7. The low probability fault test system supporting AT and ATX dual modes according to claim 2, characterized in that: The isolated power management module includes voltage stabilizer U2 and capacitors C26-C34; one end of the capacitors C26-C28 is connected and grounded after being connected with a voltage of 12V, one end of the capacitors C29-C31 is connected with the 3th pin of the voltage stabilizer U2, one end of the capacitors C32-C34 is connected with the 2th pin of the voltage stabilizer U2, and the other end of the capacitors C26-C34 is grounded.
8. The low probability fault test system supporting AT and ATX dual modes according to claim 7, characterized in that: The dual-mode power control module includes optocouplers U3 and U4, interfaces J3-J7, capacitor C35, resistors R30-R33, fuse F1, triode Q1 and relay RELAY1; the resistor R33 is a pressure sensitive resistor; the interface J4 is a 220V input interface, the interface J5 is a 220V output interface, the interface J6 is an ATX control signal output interface, and the interface J7 is a grounding interface; the 3th pin of the voltage stabilizer U2 is connected with the 1th pin of the interface J3, the interface J3 is connected with a power supply, the 1th pin of the interface J4 is connected with one end of the fuse F1, the other end of the fuse F1 is connected with one end of the resistor R33, the other end of the resistor R33 is connected with one end of the capacitor C35, the other end of the capacitor C35 is grounded, one end of the resistor R30 is connected with the 39th pin of the controller U1, the other end of the resistor R30 is connected with the base of the triode Q1, the collector of the triode Q1 is connected with the 2th pin of the optocoupler U4, the 1th pin of the optocoupler U4 is connected with the resistor R31 and grounded after being connected with a voltage of 33V, the 3th pin of the optocoupler U4 is grounded, the 4th pin of the optocoupler U4 is connected with one end of the coil of the relay RELAY1, the other end of the coil of the relay RELAY1 is connected with a voltage of 12V, one end of the contacts of the relay RELAY1 is connected with the other end of the resistor R33, the other end of the contacts of the relay RELAY1 is connected with the 1th pin of the interface J5, one end of the resistor R32 is connected with the 40th pin of the controller U1, the other end of the resistor R32 is connected with the 2th pin of the optocoupler U3, the 1th pin of the optocoupler U3 is connected with a voltage of 33V, the 4th pin of the optocoupler U3 is connected with the interface J6, and the 3th pin of the optocoupler U3 is connected with the interface J7.
9. A low probability display failure test method supporting AT and ATX dual modes, characterized by: The method comprises the following steps: S1, power-on initialization, and then configuration test parameters through the analog signal configuration module, wherein the test parameters include power-on duration, power-off waiting time, detection delay time, detection duration, sampling times, test times; S2, ensure that the display under test displays normal content and faces the photoelectric detection module, the photoelectric detection module continuously samples at a set time interval, and the master control module obtains a sampling average value according to the sampling data to realize reference brightness calibration; S3, select a power supply control mode according to the type of the display under test, that is, select one of the AT mode and the ATX mode, and then perform start-up test under the corresponding power supply control mode; S4, perform test according to the set cycle logic until the preset target test times are reached; S5, after completing all the preset target test times, obtain a failure rate according to the test results; and finally, the system is powered off to prepare for the next test.
10. The method of claim 9, wherein: In the step S4, the following steps are further included: S4.1, the master control module controls the display under test to be powered on according to the selected power supply control mode, and simultaneously starts timing; S4.2, in the power-on state, wait for a preset detection delay time; S4.3, after the delay ends, the photoelectric detection module continuously samples multiple times at a set time interval within the detection duration to obtain a sampled brightness average value AVG; S4.4, subtract the detected brightness average value AVG from the reference brightness value, if the difference between the two values is within the allowable threshold error range, it is determined that the display is normal, if the difference between the two values exceeds the threshold error range, it is determined that the display fails, and the failure times are accumulated by 1; S4.5, continue to maintain the power-on state, and wait for the remaining power-on time until the power-on time ends, and the master control module controls the display under test to be powered off; S4.6, after waiting for a preset power-off waiting time, the test times are accumulated by 1; S4.7, judge whether the preset target test times have been reached, if not, return to step S4.1 to start the next test cycle; if yes, exit the cycle and enter step S5.