A method for correcting data of a failed row in a source memory
By dividing the memory into a main memory area and an auxiliary memory area, the chip yield problem caused by eFuse failure lines was solved, achieving area optimization and cost reduction.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- 沐曦集成电路(南京)有限公司
- Filing Date
- 2026-03-04
- Publication Date
- 2026-05-01
AI Technical Summary
In the existing technology, electronic fuses (eFuse) have chip yield problems due to failures during production, which leads to increased chip costs. Existing solutions such as dual memory and dual bit designs occupy a large chip area.
The memory is divided into a main memory area and a secondary memory area. Failed line data is stored in the secondary memory area, and the actual stored data finally read from the main memory area is corrected through the secondary memory area.
It significantly reduces the memory footprint, effectively repairs faulty rows of data, balances performance and cost advantages, and reduces chip costs.
Smart Images
Figure CN121764413B_ABST
Abstract
Description
A method for correcting data errors in source memory Technical Field
[0001] This invention relates to the field of chip design technology, and in particular to a method for correcting data errors in source memory. Background Technology
[0002] An electronic fuse (eFuse) is a one-time programmable memory device based on semiconductor technology, combining the functions of an electronic fuse and data storage. Its core principle utilizes the metal connection structure within an integrated circuit. When a specific programming voltage is applied, the metal connection irreversibly melts, permanently changing the corresponding memory cell from the default logic value "0" to the logic value "1". This process is implemented at the hardware level, offering high reliability, similar to the melting mechanism of a traditional fuse, but integrated electronically and addressably within the chip. In eFuse manufacturing, yield issues exist due to varying process technologies. If a cell cannot be programmed to "1", the eFuse's functionality will be limited, forcing the entire chip to be scrapped and significantly increasing chip costs.
[0003] To improve yield, a common approach in logic design is to employ redundancy. The first method uses dual memory. Specifically, it uses one eFuse memory and one specific memory, simultaneously writing the same data to the same location in both memories. To ensure yield, two identical copies of the data need to be written to the same memory simultaneously. When reading data, based on the same specific memory, the two identical copies of data from different locations are retrieved and bitwise ORed to obtain the final value. This ensures that even if a specific location in the eFuse memory fails to write a 1, the OR operation will still read a 1. However, this method requires four times the memory area of the baseline data. The second method uses a dual bit design. Using one eFuse memory, for each 32-bit row, during programming, the same value is written to both the lower 16 bits and the higher 16 bits simultaneously. When reading data, additional timing control logic is needed to simultaneously read the higher 16 bits and the lower 16 bits and perform a bitwise OR operation, thus ensuring that even if only one of the higher or lower 16 bits fails, a correct 1 can still be read. However, this method requires twice the storage area of the original eFuse memory.
[0004] Although the above methods effectively improve yield, the drawbacks are also obvious: whether using dual memory or dual bit design, they require a large chip area, significantly increasing the cost of the chip. Summary of the Invention
[0005] To address the issue of large area occupied by dual memory, this invention provides a first solution: a data correction method for failed rows in a source memory. The method includes the following steps: reading actual stored data from the source main memory area of the source memory and writing the actual stored data into the target main memory area of the target memory; the source memory and the target memory are independent of each other, the source memory is a one-time programmable memory, and the target memory is a read / write memory; wherein, the source memory includes the source main memory area and the source auxiliary memory area; the source main memory area is used to store the actual stored data; the source auxiliary memory area is used to store at least one storage entry for a failed row, the storage entry including a storage entry status identifier; when the storage entry status identifier in the storage entry is a valid identifier, the storage entry also includes the failed row address and reference data, the failed row being a hardware-damaged storage row in the source main memory area, and the reference data being the data actually to be stored in the corresponding failed row; wherein, the target memory includes the target main memory area and the target auxiliary memory area. The method further involves reading the storage entry in the source auxiliary memory area and writing the content of the storage entry into the target auxiliary memory area. Each storage entry in the target auxiliary storage area is read. If the storage entry status identifier in the current storage entry is a valid identifier, the reference data is written to the target main storage area according to the address of the failed row in the current storage entry to obtain the corrected actual storage data. Storage entry status identifier.
[0006] Furthermore, to address the issue of the large area occupied by the dual-bit design scheme, this invention provides a second solution: a data correction method for failed rows in a source memory. The method includes the following steps: extracting the failed row address from the storage entry status identifier of each storage entry in the source auxiliary storage area of the source memory to obtain a set of failed row addresses; wherein the source memory includes a source main storage area and the source auxiliary storage area; wherein the source memory is a one-time programmable memory; the source main storage area is used to store the actual stored data; the source auxiliary storage area is used to store at least one storage entry for a failed row, the storage entry including a storage entry status identifier; when the storage entry status identifier in the storage entry is a valid identifier, the storage entry also includes a failed row address and reference data, the failed row being a storage row with hardware damage in the source main storage area, and the reference data being the data actually to be stored in the corresponding failed row. When reading actual stored data in the source memory, if the row address of the currently read storage row exists in the set of invalid row addresses, then based on the row address of the currently read storage row, the storage entries in the auxiliary storage area are searched for and matched for invalid row addresses. If the match is successful, the reference data in the matched storage entry is read directly to obtain the corrected actual stored data.
[0007] The present invention has at least the following beneficial effects:
[0008] The two data correction methods provided by this invention both divide the memory into a main memory area and an auxiliary memory area. Failed row data is stored in the auxiliary memory area, and the auxiliary memory area is used to correct the actual stored data ultimately read from the main memory area. If the capacity of the source main memory area is Q and the capacity of the auxiliary memory area is x, the first data correction method occupies an area of 2(Q+x), while the existing dual-memory scheme requires an area of 4Q. The second data correction method occupies an area of Q+x, while the existing dual-bit scheme requires an area of 2Q. Both solutions can significantly reduce the occupied area, and while reducing the area, they can still effectively repair the failed row data in the source main memory area, thus balancing performance and cost advantages. Attached Figure Description
[0009] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0010] Figure 1 is a flowchart of a data correction method for a faulty row in a source memory according to Embodiment 1 of the present invention;
[0011] Figure 2 is a flowchart of a data correction method for a faulty row in a source memory provided in Embodiment 2 of the present invention. Detailed Implementation
[0012] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0013] Unless otherwise defined, all technical and scientific terms used in the embodiments of this invention have the same meaning as commonly understood by those skilled in the art.
[0014] To address the aforementioned technical problems, this invention divides the memory into a main memory area and an auxiliary memory area. Failed row data is stored in the auxiliary memory area, and the auxiliary memory area is used to correct the actual stored data ultimately read from the main memory area. Since the amount of failed row data is relatively small, the space occupied by the auxiliary memory area is also small. To solve the problem of the large area occupied by dual memory and dual-bit designs, this invention provides Embodiment 1 and Embodiment 2, respectively.
[0015] Example 1
[0016] Please refer to Figure 1, which illustrates a method for correcting data in a faulty row in a source memory. The method includes the following steps:
[0017] S100: Read the actual stored data from the source main storage area of the source memory and write the actual stored data into the target main storage area of the target memory; the source memory and the target memory are independent of each other, the source memory is a one-time programmable memory, and the target memory is a read-write memory; wherein, the source memory includes the source main storage area and the source auxiliary storage area; the source main storage area is used to store the actual stored data; the source auxiliary storage area is used to store at least one storage entry for a failed row, the storage entry includes a storage entry status identifier, when the storage entry status identifier in the storage entry is a valid identifier, the storage entry also includes the failed row address and reference data, the failed row is a storage row in the source main storage area with hardware damage, and the reference data is the data that is actually to be stored in the corresponding failed row; wherein, the target memory includes the target main storage area and the target auxiliary storage area.
[0018] In this system, once data is written to the source memory, its stored contents cannot be modified or erased; they can only be read.
[0019] In one embodiment, the source memory is an electronic fuse (eFuse), an anti-fuse, or a read-only memory (ROM). Other types of one-time programmable memories also fall within the scope of this invention.
[0020] It should be noted that the actual stored data in the source memory cannot be changed, but the actual stored data may be exactly the same as the expected reference data; or the expected reference data may not be written correctly due to hardware failure in the source memory, resulting in the actual stored data in the storage row being different from the expected reference data.
[0021] By partitioning the actual stored data and the baseline data of the failed rows, effective isolation can be achieved, ensuring the integrity of the actual stored data. Furthermore, by storing the baseline data of the failed rows in a dedicated source auxiliary storage area, there is no need to dynamically allocate storage space, which can guarantee the complete storage of the baseline data of the failed rows, avoid fragmented storage, and ensure that the baseline data of the failed rows can be stored continuously.
[0022] In one embodiment, the storage capacity of the source memory is N times the storage capacity of the source auxiliary storage area, where N is a positive number. In one embodiment, N = 20. That is, the storage capacity of the auxiliary storage area is 5% of the storage capacity of the target storage space. In another embodiment, N can also be equal to 10, 15, 25, or 30. Other values of N also fall within the protection scope of this invention.
[0023] In one implementation, the source auxiliary storage area stores the storage entries for all failed rows in the source main storage area.
[0024] The storage entry status identifier is used to identify whether the current storage entry includes valid invalid row information, and occupies 1 bit.
[0025] In one implementation, when the storage entry status flag is at a logic high level, it indicates that the current storage entry still stores the address of a failed row and its reference data, which can be used for subsequent replacement operations. When the storage entry status flag is at a logic low level, it indicates that the current storage entry does not store the address of a failed row and its reference data.
[0026] The failure line address is used to record the specific location information of the storage line in the source main storage area where the hardware is damaged, or in other words, to record the specific location information of the storage line in the main storage area that is different from the reference data.
[0027] The reference data for the failed row is used to store the actual data to be stored in the failed row. The bit width of the reference data is the same as the data bit width of the storage row. For example, if each storage row stores 32 bits of data, then the reference data stored in that storage entry is also 32 bits of data.
[0028] In this invention, all storage entries in the source auxiliary storage area have the same storage format. For each storage entry, control information and data information can be stored in two separate rows, or these two types of information can be stored consecutively. Other storage methods also fall within the scope of protection of this invention. The control information includes a storage entry status identifier and the address of the failed row.
[0029] In one implementation, control information and data information are stored in two rows. Each storage entry has a preset storage format: each entry occupies two rows of storage space. The first row stores control data including the entry status identifier, the address of the failed entry, and reserved fields. The second row stores the corresponding baseline data. This storage format has simple logic, facilitates storage and retrieval, and provides compatibility for future functional expansion.
[0030] In one implementation, for storage divided into two rows, the data is written sequentially according to the index number of the storage row from largest to smallest, and the storage row with the largest index number is used first when writing; wherein, the storage entry status identifier and the address of the invalid row are stored in the same storage row, and the corresponding base data is stored in the next storage row with the index number immediately below it and which has not been used.
[0031] In one implementation, for the method of storing control information and data information contiguously, the preset storage format for each storage entry is: the data in each storage entry is stored contiguously without inter-row separation. This storage format significantly improves the utilization of storage space and reduces storage fragmentation caused by row alignment.
[0032] In one implementation, for contiguous storage, entries are written sequentially according to their index numbers in descending order, with the storage row with the largest index number being used first. Within a storage row, starting from the least significant bit side, entries are written sequentially towards the most significant bit side according to a preset step size, such that earlier entries occupy lower bit positions and later entries occupy higher bit positions. The preset step size is the total bit width occupied by the control and data information within a storage entry.
[0033] In one implementation, the step of identifying the failed row includes: comparing the actual stored data with the reference data row by row, bit by bit; and marking the current row as a failed row when there are rows with different bits. That is, as long as any bit in a stored row is found to be inconsistent with the corresponding bit in the reference data, the stored row is immediately marked as a failed row. In other words, the failure determination does not distinguish between single-bit errors and multi-bit errors. Whether the difference is one bit or multiple bits, as long as the failure condition is met, the current stored row will be marked as a failed row.
[0034] The target memory and the source memory are independent of each other and are different memories used to store the data in the source memory.
[0035] In one embodiment, the target memory is random access memory (RAM) or static random access memory (SRAM). Other types of read / write memory also fall within the scope of this invention.
[0036] In one implementation, the target memory and the source memory have the same two-dimensional structure. That is, both the target memory and the source memory physically include the same number of rows and the same number of columns; in other words, their row dimensions and column dimensions are equal. For example, if the source memory is 128 rows × 32 columns, then the target memory is also 128 rows × 32 columns. This configuration allows data to be directly written from a row in the source memory to the corresponding row address in the target memory, without address offset calculations or buffer rearrangement, thus simplifying data movement logic and reducing control overhead. Simultaneously, the identical structure avoids storage space fragmentation or unused areas caused by mismatched area sizes, improving overall storage utilization. It is understood that although in another implementation the target memory can have a larger two-dimensional structure than the source memory, using the same two-dimensional structure has significant advantages in terms of control overhead and storage utilization.
[0037] In one implementation, the target memory is divided into a target main memory area and a target auxiliary memory area using the same logical partitioning method as the source memory. The fact that both have the same two-dimensional structure ensures that not only are their row addresses aligned, but their region partitioning is also perfectly aligned.
[0038] Since the data in the source memory can only be read and not repaired, it is necessary to move the actual stored data to the target main memory area of the read-write memory to prepare for subsequent data repair.
[0039] In one implementation, the source memory and the target memory each include multiple storage rows and have the same row address space. When writing data from the source memory to the target memory, the data is written from a storage row in the source memory to a storage row in the target memory with the same row address. In other words, the source memory and the target memory are aligned in the row address space, and storage rows with the same logical index correspond to the same physical row address. Therefore, after reading data from a storage row with a certain logical index in the source memory, the same row address can be used to write the data to the corresponding storage row in the target memory. Whether it is the movement of actual stored data in the source main storage area or the movement of corresponding storage entries in the source auxiliary storage area, the same row address is used for data movement. This configuration allows data to be read and written without address offset, simplifying the logic and reducing control overhead.
[0040] S200: Read the storage entry in the source auxiliary storage area and write the content of the storage entry into the target auxiliary storage area.
[0041] Similarly, moving storage entries from the source auxiliary storage area to the target auxiliary storage area of the read-write memory is also a preparation for subsequent data repair.
[0042] S300: Read the storage entries in the target auxiliary storage area. If the status identifier of the storage entry in the current storage entry is a valid identifier, write the reference data into the target main storage area according to the address of the failed row in the current storage entry. When all storage entries in the target auxiliary storage area have been read and all corresponding reference data have been written into the target main storage area, the corrected actual storage data is obtained.
[0043] When the reference data is written to the target main storage area based on the address of the failed row, the original failed row data is directly overwritten. Once the reference data for all storage entries in the target secondary storage area has been written to the target main storage area, the data in the target main storage area is corrected. At this point, when the user reads the data in the target main storage area, they will obtain the corrected data, thus effectively repairing the failed row data in the source main storage area.
[0044] In one implementation, when storage entries are written sequentially in descending order of storage row index number, and the storage row with the largest index number is used first during writing, the determination step in S300 to determine that all storage entries in the target auxiliary storage area have been read includes: reading the storage entries in the source auxiliary storage area sequentially in descending order of storage row index number; if the storage entry status identifier of the current storage entry is invalid, then all entries have been read.
[0045] In one implementation, for the two-row storage method, in S300, the step of writing the reference data into the target main storage area further includes: obtaining the address of the failed row in the current storage entry; reading the reference data in the next storage row in descending order of index number; and writing the reference data into the address of the failed row in the target main storage area. In one implementation, the reading of the storage entry status identifier and the failed row address can be achieved by directly reading the storage entry status identifier and the failed row address as a whole and then parsing them as a whole. Alternatively, a strategy of reading the storage entry status identifier first and then reading the failed row address can be adopted. In another implementation, for the two-row storage method, a strategy of directly reading and parsing both rows of data at once can also be adopted, that is, reading the storage entry status identifier, the failed row address, and the reference data as a whole at once, and then parsing them. Other types of reading strategies also fall within the protection scope of this invention.
[0046] In one implementation, for contiguous storage, after reading the storage entry in the target auxiliary storage area in step S300, the method further includes parsing the current storage entry to obtain the storage entry status identifier, the failed row address, and the baseline data. In another implementation, a strategy of reading each field in each storage entry sequentially can also be used; or a strategy of first reading the storage entry status identifier and the failed row address, and then reading the data, can also be used. Other types of reading methods also fall within the scope of this invention.
[0047] In summary, the present invention provides a data correction method for failed rows in the source memory, which only requires adding a source auxiliary storage area and a target memory that synchronously maps the source memory data. When the total amount of reference data is Q, the capacity of its source main storage area is Q, and the capacity of its auxiliary storage area is x, then the total occupied area is 2(Q+x), where x is much smaller than Q. In contrast, the existing dual-memory scheme requires an area of 4Q. Therefore, the present invention achieves significant optimization in terms of storage area, greatly reducing the occupied area. Furthermore, the present invention repairs the corresponding failed rows in the main storage area through storage entries in the auxiliary storage area, effectively improving chip yield. This method, while significantly reducing the occupied area, can still effectively repair failed row data in the source main storage area, balancing performance and cost advantages.
[0048] Based on the same inventive concept, in order to solve the problem of the large area occupied by the dual-bit design, the present invention provides two embodiments.
[0049] Example 2
[0050] Please refer to Figure 2, which illustrates a method for correcting data errors in a source memory, the method comprising the following steps:
[0051] P100, extract the failed row addresses to obtain a set of failed row addresses based on the storage entry status identifiers of each storage entry in the source auxiliary storage area of the source memory; wherein, the source memory includes a source main storage area and the source auxiliary storage area; wherein, the source memory is a one-time programmable memory; the source main storage area is used to store actual stored data; the source auxiliary storage area is used to store at least one failed row storage entry, the storage entry includes the storage entry status identifier, when the storage entry status identifier in the storage entry is a valid identifier, the storage entry also includes a failed row address and reference data, the failed row is a storage row in the source main storage area with hardware damage, and the reference data is the data that is actually to be stored in the corresponding failed row.
[0052] It should be noted that the description of the source memory in Embodiment 1 also applies to Embodiment 2, and will not be repeated here.
[0053] It should be noted that in Embodiment 2, a target memory is no longer required. Instead, only a source memory is used, along with corresponding control logic, to achieve the purpose of data correction.
[0054] The set of failed row addresses includes the failed row addresses bound to the status identifiers of all valid storage entries in the source secondary storage area. The purpose of extracting the set of failed row addresses is to determine whether the currently read storage row is a failed row when reading the corresponding storage row in the source primary storage area.
[0055] In one implementation, when storage entries are written sequentially in descending order of storage row index numbers, and the storage row with the largest index number is used first during writing, the step of extracting the address of the failed row in P100 includes: sequentially reading the storage entries in the source auxiliary storage area in descending order of storage row index numbers; if the storage entry status identifier of the current storage entry is a valid identifier, then the address of the failed row in the current storage entry is placed into the set of failed row addresses; if the storage entry status identifier of the current storage entry is an invalid identifier, then the extraction ends.
[0056] P200, when reading actual stored data in the source memory, if the row address of the currently read storage row exists in the set of failed row addresses, then based on the row address of the currently read storage row, the failed row address search and matching is performed on the storage entries in the auxiliary storage area. If the matching is successful, the reference data in the matched storage entry is directly read to obtain the corrected actual stored data.
[0057] In one implementation, the search and matching uses a comparator array, which compares the row address of the currently read storage row with one or more pre-stored invalid row addresses in parallel. When the row address of the currently read storage row is the same as any invalid row address, a matching signal is output to confirm a successful match.
[0058] Hardware-based lookup and matching can be completed within one clock cycle, significantly improving the speed of lookup and matching. Other types of lookup and matching methods also fall within the scope of this invention.
[0059] It should be noted that when reading data from the source primary storage area, if it is determined that the current reading is of a failed row, the corresponding baseline data in the source secondary storage area is read directly, instead of reading the failed row data in the primary storage area, thereby achieving data repair.
[0060] In summary, the data correction method for failed rows in the source memory provided by this invention only requires dividing the source memory into a source main memory area and a source auxiliary memory area. Instead of reading the corresponding failed rows in the source main memory area, the corresponding reference data in the source auxiliary memory area is directly read. When the total amount of reference data is Q, the total occupied area is Q+x, where x is the area of the source auxiliary memory area, and x is much smaller than Q. In comparison, the existing double-bit scheme requires an area of 2Q. Therefore, this invention significantly reduces the occupied area. Furthermore, this invention repairs the corresponding failed rows in the source main memory area using storage entries in the source auxiliary memory area, effectively improving chip yield. This method also effectively repairs failed row data while significantly reducing the occupied area, balancing performance and cost advantages.
[0061] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is used as an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.
[0062] While specific embodiments of the invention have been described in detail by way of example, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of the invention. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of the invention. The scope of this invention is defined by the appended claims.
Claims
1. A method for correcting data errors in a source memory, characterized in that, The method includes the following steps: reading actual stored data from the source main storage area of the source memory and writing the actual stored data into the target main storage area of the target memory; the source memory and the target memory are independent of each other, the source memory is a one-time programmable memory, and the target memory is a read-write memory; wherein, the source memory includes the source main storage area and the source auxiliary storage area; the source main storage area is used to store the actual stored data; the source auxiliary storage area is used to store at least one storage entry of a failed row, the storage entry includes a storage entry status identifier, and when the storage entry status identifier in the storage entry is a valid identifier, the storage entry... It also includes the address of the failed line and reference data, wherein the failed line is a storage line in the source main storage area with hardware failure, and the reference data is the actual data to be stored in the corresponding failed line; wherein, the target memory includes the target main storage area and the target auxiliary storage area; read the storage entries in the source auxiliary storage area and write the contents of the storage entries into the target auxiliary storage area; read each storage entry in the target auxiliary storage area, and if the storage entry status identifier in the current storage entry is a valid identifier, write the reference data into the target main storage area according to the address of the failed line in the current storage entry to obtain the corrected actual storage data.
2. The method according to claim 1, characterized in that, The default storage format for each storage entry is as follows: each storage entry occupies two rows of storage space. The first row stores metadata including the storage entry status identifier, the address of the failed row, and the reserved fields. The second row stores the corresponding baseline data.
3. The method according to claim 1, characterized in that, The default storage format for each storage entry is: data in each storage entry is stored contiguously without line breaks.
4. The method according to claim 1, characterized in that, The source memory and the target memory each include multiple storage rows and have the same row address space; when the actual stored data is written to the target main storage area of the target memory, the actual stored data is written from the storage row of the source memory to the storage row with the same row address in the target memory.
5. The method according to claim 1, characterized in that, The source memory and the target memory have the same two-dimensional structure.
6. The method according to claim 1, characterized in that, The storage capacity of the source memory is N times the storage capacity of the source auxiliary storage area, where N is a positive number.
7. The method according to claim 1, characterized in that, The step of identifying the failed row includes: comparing the actual stored data with the reference data row by row, bit by bit; when there are rows with different bits, the current row is marked as a failed row.
8. A method for correcting data errors in a source memory, characterized in that, The method includes the following steps: extracting the failed row addresses to obtain a set of failed row addresses based on the storage entry status identifiers of each storage entry in the source auxiliary storage area of the source memory; wherein, the source memory includes a source main storage area and the source auxiliary storage area; wherein, the source memory is a one-time programmable memory; the source main storage area is used to store actual stored data; the source auxiliary storage area is used to store at least one failed row storage entry, the storage entry includes the storage entry status identifier, when the storage entry status identifier in the storage entry is a valid identifier, the storage entry also includes a failed row address and reference data, the failed row is a storage row in the source main storage area with hardware damage, and the reference data is the data that the corresponding failed row is actually to be stored; when reading the actual stored data in the source memory, if the row address of the currently read storage row exists in the set of failed row addresses, then based on the row address of the currently read storage row, a failed row address lookup and matching is performed on the storage entries in the auxiliary storage area, if the matching is successful, then the reference data in the matched storage entry is directly read to obtain the corrected actual stored data.
9. The method according to claim 8, characterized in that, When storage entries are written sequentially in descending order of their index numbers, and the storage row with the largest index number is used first during writing, the step of extracting the address of the failed row includes: sequentially reading the storage entries in the source auxiliary storage area in descending order of their index numbers; if the storage entry status identifier of the current storage entry is a valid identifier, then the address of the failed row in the current storage entry is added to the set of failed row addresses; if the storage entry status identifier of the current storage entry is an invalid identifier, then the extraction ends.
10. The method according to claim 8, characterized in that, The search and matching process uses a comparator array, which compares the row address of the currently read storage row with one or more pre-stored invalid row addresses in parallel. When the row address of the currently read storage row is the same as any invalid row address, a matching signal is output to confirm a successful match.
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