Data recovery method and device, electronic equipment and storage medium
By modifying the mapping relationship between LBA and PBA, data recycling without data movement was achieved, solving the problems of high power consumption and low efficiency in the existing technology, reducing system power consumption and improving recycling efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-24
- Publication Date
- 2026-03-31
AI Technical Summary
Existing technologies involve a large amount of unnecessary data movement and command transmission during the waste recycling process, resulting in high system power consumption and low recycling efficiency.
By sending an LBA remapping instruction to the memory, the mapping relationship between LBA and PBA is modified, changing the original mapping between LBA segments and original PBA segments to a mapping between target LBA segments and original PBA segments, thereby achieving data reclamation.
This reduces data movement and command transmission during the data recycling process, lowers system power consumption, and improves recycling efficiency.
Smart Images
Figure CN121764818A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of terminal technology, and in particular to a data retrieval method, apparatus, electronic device, and storage medium. Background Technology
[0002] In current mobile device systems, such as Android operating systems, a flash-friendly file system (F2FS) is typically used to adapt to storage media such as non-volatile memory (NAND) that cannot be overwritten. However, the F2FS file system generates a large number of junk files during use. The accumulation of these junk files occupies valuable storage space, which necessitates periodic garbage collection to free up storage space.
[0003] In the garbage collection process, in addition to removing invalid data, it is also necessary to reclaim valid data. Traditional techniques typically reclaim valid data as follows: valid data in the file system is read from storage into memory, then this data is rewritten to other free locations in storage, and finally the data in the original memory area is marked as invalid. However, this process involves a large amount of unnecessary data movement and command transmission, resulting in high system power consumption and low recycling efficiency. Summary of the Invention
[0004] This application provides a data recycling method, apparatus, electronic device, and storage medium that can reduce unnecessary data movement and command transmission during the data recycling process, reduce system power consumption, and improve recycling efficiency.
[0005] In a first aspect, embodiments of this application provide a data recycling method applied to an electronic device, the electronic device including a processor and a memory. During data recycling, the method includes: the processor sending a logical block address (LBA) remapping instruction to the memory, the LBA remapping instruction indicating that valid data corresponding to the original LBA segment be transferred to a target LBA segment by modifying the mapping relationship, the valid data corresponding to the original LBA segment being stored in the original physical block address (PBA) segment; in response to the LBA remapping instruction, the memory modifying the mapping between the original LBA segment and the original PBA segment to a mapping between the target LBA segment and the original PBA segment.
[0006] This solution can be applied in scenarios where file systems (e.g., F2FS) require data reclamation.
[0007] It should be understood that when the memory modifies the mapping between the original LBA segment and the original PBA segment to a mapping between the target LBA segment and the original PBA segment, the original LBA segment no longer has a mapping relationship with the original PBA segment, and therefore no longer has a mapping relationship with the valid data stored in the original PBA segment, thus releasing the storage space of the original LBA segment; while the target LBA segment has a mapping relationship with the original PBA segment, and therefore has a mapping relationship with the valid data stored in the original PBA segment. That is, this application transfers the valid data corresponding to the original LBA segment to the target LBA segment by modifying the mapping relationship, thereby realizing the reclamation of the valid data of the original LBA segment without actual data relocation.
[0008] This application proposes that during data reclamation, the processor can send an LBA remapping instruction to the memory to instruct the memory to reclaim the original LBA data by changing the mapping relationship between LBA and PBA (i.e., changing the mapping between the original LBA segment and the original PBA segment to the mapping between the target LBA segment and the original PBA segment). This can reduce unnecessary data movement and command transmission during the data reclamation process, reduce system power consumption, and improve reclamation efficiency.
[0009] In conjunction with the first aspect described above, in some implementations of the first aspect, modifying the mapping between the original LBA segment and the original PBA segment to a mapping between the target LBA segment and the original PBA segment includes: reading an L2P mapping table and a P2L mapping table, which include the mapping relationship between the original LBA segment, the target LBA segment, and the original PBA segment; and modifying the L2P mapping table and the P2L mapping table to change the mapping between the original LBA segment and the original PBA segment to a mapping between the target LBA segment and the original PBA segment. Based on this, the modification of the LBA and PBA mapping relationship can be achieved in a simple way.
[0010] It should be understood that in the read L2P mapping table, the original LBA segment and the original PBA segment are mapped to each other, while the target LBA segment is in an idle state and is not mapped to a PBA. In the read P2L mapping table, the original PBA segment and the original LBA segment are mapped to each other. However, in the modified L2P mapping table, the target LBA segment and the original PBA segment are mapped to each other, while the original LBA segment is in an idle state and is not mapped to a PBA. In the modified P2L mapping table, the original PBA segment and the target LBA segment are mapped to each other.
[0011] It should be understood that the mapping table read may also include mapping relationships between other LBAs and other PBAs, and this application does not limit this.
[0012] In conjunction with the first aspect described above, in some implementations of the first aspect, modifying the mapping between the original LBA segment and the original PBA segment to the mapping between the target LBA segment and the original PBA segment by modifying the L2P mapping table and the P2L mapping table includes: writing the original PBA segment into the PBA entry corresponding to the target LBA segment in the L2P mapping table, and simultaneously marking the PBA entry corresponding to the original LBA segment as invalid; modifying the LBA entry corresponding to the original PBA segment in the P2L mapping table from the original LBA segment to the target LBA segment. Based on this, the modification of the LBA and PBA mapping relationship can be achieved in a simple way.
[0013] In conjunction with the first aspect above, in some implementations of the first aspect, the original LBA segment includes n original LBAs, the target LBA segment includes n target LBAs, and modifying the mapping between the original LBA segment and the original PBA segment to the mapping between the target LBA segment and the original PBA segment by modifying the L2P mapping table and the P2L mapping table includes: reading the PBA entry corresponding to the i-th original LBA among the n original LBAs in the L2P mapping table, where i is traversed from 1 to n; in the i-th original LBA... When the PBA entry corresponding to an LBA includes the original PBA, the included original PBA is written into the PBA entry corresponding to the i-th target LBA among the n target LBAs, and the PBA entry corresponding to the i-th original LBA is marked as invalid; the LBA entry corresponding to the original PBA in the P2L mapping table is modified from the i-th original LBA to the i-th target LBA; or, when the PBA entry corresponding to the i-th original LBA does not include the original PBA, no modification is made.
[0014] In one possible implementation, each original LBA in the above original LBA segment corresponds to an original PBA; in another possible implementation, there are one or more original LBAs in the above original LBA segment that do not have a corresponding PBA (i.e., they are in an idle state).
[0015] To ensure the accuracy of modifications to the L2P and P2L mapping tables, this application proposes that when modifying the L2P mapping table, the system analyzes whether each original LBA corresponds to a PBA. If a PBA is present, the corresponding PBA is written into the target LBA's entry, and the original LBA's corresponding PBA entry is marked as invalid. If no corresponding PBA is present, no modification is performed. Based on this modified mapping relationship, the LBA entry corresponding to each original PBA in the P2L mapping table is then modified.
[0016] In conjunction with the first aspect above, in some implementations of the first aspect, reading the L2P mapping table and the P2L mapping table includes reading the L2P mapping table and the P2L mapping table from NAND or static random access memory (SRAM).
[0017] SRAM is located in the memory controller and is used to cache NAND data, such as L2P and P2L mapping tables.
[0018] In conjunction with the first aspect above, in some implementations of the first aspect, after the memory modifies the mapping between the original LBA segment and the original PBA segment to the mapping between the target LBA segment and the original PBA segment, the method further includes: the memory sending a prompt message to the processor, the prompt message being used to indicate that the mapping relationship modification has been completed.
[0019] In conjunction with the first aspect above, in some implementations of the first aspect, the LBA remapping instruction includes the starting address of the address range of the original LBA segment, the starting address of the address range of the target LBA segment, and the length of the address range of the LBA segment.
[0020] In conjunction with the first aspect above, in some implementations of the first aspect, the memory includes universal flash storage (UFS) or solid state drive (SSD).
[0021] Secondly, embodiments of this application provide a data recycling apparatus, including a processor and a memory. The processor is configured to, during data recycling, send an LBA remapping instruction to the memory. The LBA remapping instruction instructs that valid data corresponding to the original LBA segment be transferred to a target LBA segment by modifying the mapping relationship, and that the valid data corresponding to the original LBA segment is stored in the original PBA segment. In response to the LBA remapping instruction, the memory is configured to modify the mapping between the original LBA segment and the original PBA segment to a mapping between the target LBA segment and the original PBA segment.
[0022] Thirdly, embodiments of this application provide an apparatus included in an electronic device, which has the function of implementing the behaviors of the electronic device in the above aspects and possible implementations thereof. The functions can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more modules or units corresponding to the above functions. For example, a detection module or unit, a processing module or unit, etc.
[0023] Fourthly, embodiments of this application provide an electronic device including the apparatus described in the second or third aspect above.
[0024] Fifthly, embodiments of this application provide a computer-readable storage medium storing instructions that, when executed on a computer, cause the computer to perform any of the possible methods described in the first aspect.
[0025] Sixthly, embodiments of this application provide a computer program product containing instructions that, when run on a computer, cause the computer to perform any of the possible methods described in the first aspect above.
[0026] The technical effects achieved by the second to sixth aspects mentioned above are similar to those achieved by the corresponding technical means in the first aspect mentioned above, and will not be repeated here. Attached Figure Description
[0027] Figure 1 This is a schematic diagram of a traditional data recycling method;
[0028] Figure 2 This is a schematic diagram illustrating the changes in mapping relationships during traditional data recycling.
[0029] Figure 3 This is a schematic diagram of command transmission provided in an embodiment of this application;
[0030] Figure 4 This is a schematic diagram illustrating the changes in mapping relationships during data recycling, provided in an embodiment of this application.
[0031] Figure 5 This is a schematic diagram of the hardware structure of an electronic device 100 provided in an embodiment of this application;
[0032] Figure 6 This is a flowchart illustrating a data recovery method provided in an embodiment of this application;
[0033] Figure 7 This is a flowchart illustrating a specific implementation of the data recovery method provided in this application embodiment;
[0034] Figure 8 This is a schematic diagram showing the L2P mapping table before and after modification, as provided in an embodiment of this application.
[0035] Figure 9 This is a schematic diagram of a P2L mapping table before and after modification, provided in an embodiment of this application;
[0036] Figure 10 This is a schematic diagram of the structure of a data recovery device provided in an embodiment of this application. Detailed Implementation
[0037] To facilitate a clear description of the technical solutions in the embodiments of this application, the terms "first" and "second" are used in the embodiments of this application to distinguish identical or similar items with essentially the same function and purpose. For example, "first chip" and "second chip" are used only to distinguish different chips and do not limit their order. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and the terms "first" and "second" do not necessarily imply that they are different.
[0038] It should be noted that, in the embodiments of this application, the terms "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design scheme described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or design schemes. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.
[0039] In this application embodiment, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.
[0040] To facilitate understanding, the terminology used in this application will be introduced below.
[0041] NAND flash memory is a non-volatile storage technology commonly found in devices such as Universal Serial Bus (USB) flash drives, Secure Digital (SD) cards, SSDs, and UFS. NAND flash memory offers high write speeds and large storage capacities, but due to its physical characteristics, updating data cannot be done by directly overwriting the existing data. Instead, the corresponding storage block must first be erased before the new data is written.
[0042] F2FS file system: This is a file system specifically designed for NAND flash memory. It employs a journal-structured design, in which all write operations are appended to the end of the file system, rather than attempting to overwrite old data. This way, when you need to change a portion of a file's content, you only need to write the new data and a reference to the new data, without needing to erase and rewrite the entire flash memory block, making it ideally suited to the characteristics of NAND flash memory.
[0043] UFS is a high-performance flash memory storage standard that offers higher data transfer speeds and lower power consumption than traditional embedded multimedia card (eMMC) storage. In UFS devices, the F2FS file system is typically used to manage storage space.
[0044] Memory: Memory is the part of a computer used to temporarily store running applications and data. Compared to NAND flash memory, memory has a faster read and write speed, but it is volatile and the data will be lost when the power is turned off.
[0045] Garbage collection is a key step in the F2FS file system for managing NAND flash memory. By migrating valid data to a new location and marking the original location as invalid, it optimizes storage space usage, reduces write amplification, and extends the lifespan of NAND flash memory.
[0046] Write amplification: This describes the phenomenon where, during a data write operation, the actual amount of data written by the memory exceeds the amount of data written by the host.
[0047] LBA and PBA: The index in which data is stored inside memory (e.g., UFS or SSD devices) can be called an address, and there is a one-to-one correspondence between the address and the data. From the processor's perspective, as long as an LBA is given, the memory will return the data stored at that address. However, due to the insert-before-write and non-overwrite characteristics of NAND flash memory, an additional address system is maintained inside the memory, which is called PBA.
[0048] It should be understood that LBA is an abstract, hardware-independent address representation used by the processor and memory for data transfer; PBA is the address where data is actually stored in NAND flash memory. There is a natural one-to-one mapping between PBA and data. PBA is usually managed by the memory controller and is generally not exposed to the outside world.
[0049] LBA to PBA mapping (logical-to-physical mapping, L2P) and PBA to LBA mapping (physical-to-logical mapping, P2L): To establish the mapping relationship between LBAs and data, the memory also maintains a set of mapping relationships between LBAs and PBAs, namely L2P and P2L. L2P is the mapping process that converts LBAs to PBAs, and it is used to determine the actual physical location of data on the storage medium. P2L is the mapping process that converts PBAs to LBAs, and it is used to retrieve the logical address of data from its physical location on the storage medium.
[0050] The following is a detailed description of the proposed solution with reference to the accompanying drawings.
[0051] Figure 1 This is a schematic diagram of a traditional data recovery method, such as... Figure 1 As shown, traditional techniques typically involve the following steps to recover data:
[0052] The first step, effective data reading, specifically includes the following steps:
[0053] S11, the processor sends a command to the memory to read valid data, for example, read10;
[0054] S12, the memory controller reads valid data from the NAND;
[0055] S13, the memory controller sends valid data to the memory;
[0056] The second step, writing valid data, includes the following steps:
[0057] S21, the processor sends a command to the memory to write valid data, for example, write10;
[0058] S22, the memory controller reads valid data from memory;
[0059] S23, the memory controller rewrites the read valid data to other free locations in the NAND;
[0060] The third step is to mark the original data as invalid, which includes the following steps:
[0061] S31, the processor sends an invalid command, such as unmap, to the memory to mark the data in the original region of memory as invalid.
[0062] As an example, suppose that before data reclamation, the valid data data0 and data1 have LBAs of 0 and 1 respectively, and their PBAs are also 0 and 1, and all other LBAs and PBAs are in an idle state. Then, there will be relationships between the LBAs, PBAs, and valid data as follows: Figure 2 The mapping relationship is shown in (a) above; assuming that during the data reclamation process, the processor wants to move valid data data0 and data1 from LBA 0 and 1 and PBA 0 and 1 to other free locations, it can do so through... Figure 1 The method shown first reads data0 and data1, then writes them to other free locations, for example, to locations where LBA and PBA are both 2 and 3. It then marks the data corresponding to positions 0 and 1 in LBA and PBA as invalid, thus making positions 0 and 1 in LBA and PBA free. Figure 2 As shown in (b) of the diagram.
[0063] As can be seen, based on the above traditional data reclamation method, the mapping relationship between LBA, PBA and valid data has changed, and the reclamation process involves a large number of command transmissions (e.g., read10, write10 and unmap commands) and data movement (i.e. movement of valid data), resulting in high system power consumption and low reclamation efficiency.
[0064] Based on this, this application proposes that during data reclamation, the processor can send an LBA remap instruction to the memory to instruct the memory to reclaim the original LBA data by changing the mapping relationship between LBA and PBA (i.e., changing the mapping between the original LBA segment and the original PBA segment to the mapping between the target LBA segment and the original PBA segment), thereby achieving data reclamation of the original LBA with only one command (e.g., ...). Figure 3 The LBA remap shown achieves data reclamation and avoids data movement (e.g., Figure 4 (as shown), which can reduce system power consumption and improve recycling efficiency.
[0065] As an example, Figure 4 This is a schematic diagram illustrating the changes in mapping relationships during data recycling, as provided in an embodiment of this application. Figure 4 As shown, assuming that before data reclamation, the valid data data0 and data1 are stored with LBAs of 0 and 1 (i.e., original LBA segments) and PBAs of 0 and 1 (i.e., original PBA segments), and all other LBAs and PBAs are in an idle state, then there will be gaps between LBAs, PBAs, and valid data as follows: Figure 4The mapping relationship is shown in (a) above; assuming that during the data reclamation process, the processor wants to move the valid data data0 and data1 from LBA 0 and 1 to the free locations 2 and 3 of LBA (i.e., the target LBA segment), it can send the following to the memory: Figure 3 The LBA remapping instruction shown in the diagram instructs the memory to change the mapping between LBA 0 and 1 and PBA 0 and 1, so that LBA 2 and 3 are mapped to PBA 0 and 1, without any movement of the corresponding data data0 and data1 during the entire process. Figure 4 As shown in (b) of the diagram.
[0066] The solution of this application can be applied to electronic devices including processors and memory. Optionally, the aforementioned electronic devices can also be referred to as user equipment (UE), terminal equipment, or user terminals, etc. The electronic devices can be, but are not limited to, mobile phones, tablets, desktops, laptops, handheld computers, notebook computers, in-vehicle systems, ultra-mobile personal computers (UMPCs), netbooks, cellular phones, personal digital assistants (PDAs), augmented reality (AR) / virtual reality (VR) devices, etc. The embodiments of this application do not limit this.
[0067] For example, Figure 5 This is a schematic diagram of the hardware structure of an electronic device 100 provided in an embodiment of this application. The electronic device 100 may include a processor 110, an external memory interface 120, an internal memory 121, a USB interface 130, a charging management module 140, a power management module 141, a battery 142, antenna 1, antenna 2, a mobile communication module 150, a wireless communication module 160, an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, a headphone jack 170D, a sensor module 180, buttons 190, a motor 191, an indicator 192, a camera 193, a display screen 194, and a subscriber identification module (SIM) card interface 195, etc. The sensor module 180 may include pressure sensors, gyroscope sensors, barometric pressure sensors, magnetic sensors, accelerometers, distance sensors, proximity sensors, fingerprint sensors, temperature sensors, touch sensors, ambient light sensors, bone conduction sensors, etc.
[0068] It is understood that the structures illustrated in the embodiments of this application do not constitute a specific limitation on the electronic device 100. In other embodiments of this application, the electronic device 100 may include more or fewer components than illustrated, or combine some components, or split some components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.
[0069] Processor 110 may include one or more processing units, such as application processors, satellite communication processors, modem processors, graphics processing units (GPUs), image signal processors (ISPs), controllers, video codecs, digital signal processors (DSPs), baseband processors, and / or neural network processing units (NPUs). These different processing units may be independent devices or integrated into one or more processors.
[0070] The controller can generate operation control signals based on the instruction opcode and timing signals to complete the control of instruction fetching and execution.
[0071] The processor 110 may also include a memory for storing instructions and data. In some embodiments, the memory in the processor 110 is a cache memory. This memory can store instructions or data that the processor 110 has just used or that are used repeatedly. If the processor 110 needs to use the instruction or data again, it can retrieve it from the memory. This avoids repeated accesses, reduces the waiting time of the processor 110, and thus improves the efficiency of the system.
[0072] The charging management module 140 receives charging input from a charger. The charger can be a wireless charger or a wired charger. In some wired charging embodiments, the charging management module 140 receives charging input from the wired charger via the USB interface 130. In some wireless charging embodiments, the charging management module 140 receives wireless charging input via the wireless charging coil of the electronic device 100. While charging the battery 142, the charging management module 140 can also supply power to the electronic device via the power management module 141.
[0073] The power management module 141 connects the battery 142, the charging management module 140, and the processor 110. The power management module 141 receives input from the battery 142 and / or the charging management module 140 to power the processor 110, internal memory 121, display screen 194, camera 193, and wireless communication module 160, etc. In some other embodiments, the power management module 141 may also be located within the processor 110. In other embodiments, the power management module 141 and the charging management module 140 may be located in the same device.
[0074] The wireless communication function of electronic device 100 can be realized through antenna 1, antenna 2, mobile communication module 150, wireless communication module 160, modem processor and baseband processor, etc.
[0075] Antenna 1 and antenna 2 are used to transmit and receive electromagnetic wave signals.
[0076] The mobile communication module 150 can provide solutions for wireless communication, including 2G / 3G / 4G / 5G, applied to the electronic device 100. The mobile communication module 150 may include at least one filter, switch, power amplifier, low noise amplifier (LNA), etc. In some embodiments, at least some functional modules of the mobile communication module 150 may be housed in the same device as at least some modules of the processor 110.
[0077] The wireless communication module 160 can provide solutions for wireless communication applications on the electronic device 100, including wireless local area networks (WLANs) (such as wireless fidelity (Wi-Fi) networks), Bluetooth (BT), global navigation satellite system (GNSS), frequency modulation (FM), near field communication (NFC), and infrared (IR) technologies. The wireless communication module 160 can be one or more devices integrating at least one communication processing module. The wireless communication module 160 receives electromagnetic waves via antenna 2, performs frequency modulation and filtering of the electromagnetic wave signals, and sends the processed signal to processor 110. The wireless communication module 160 can also receive signals to be transmitted from processor 110, perform frequency modulation and amplification, and convert them into electromagnetic waves for radiation via antenna 2.
[0078] In some embodiments, antenna 1 of electronic device 100 is coupled to mobile communication module 150, and antenna 2 is coupled to wireless communication module 160, so that electronic device 100 can communicate with networks and other devices through wireless communication technology.
[0079] Electronic device 100 implements display functions through a GPU, a display screen 194, and an application processor. The GPU is a microprocessor for image processing, connected to the display screen 194 and the application processor. The GPU is used to perform mathematical and geometric calculations and for graphics rendering. Processor 110 may include one or more GPUs, which execute program instructions to generate or modify display information.
[0080] The display screen 194 is used to display images, display videos, and receive swipe operations, etc. The display screen 194 includes a display panel. The display panel can be a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active-matrix organic light-emitting diode (AMOLED), a flexible light-emitting diode (FLED), a Miniled LED, a MicroLED, a Micro-OLED, a quantum dot light-emitting diode (QLED), etc. In some embodiments, the electronic device 100 may include one or N display screens 194, where N is a positive integer greater than 1.
[0081] Electronic device 100 can perform shooting functions through ISP, camera 193, video codec, GPU, display 194 and application processor.
[0082] The ISP is used to process data fed back from the camera 193. For example, when taking a picture, the shutter is opened, and light is transmitted through the lens to the camera's photosensitive element. The light signal is converted into an electrical signal, and the camera's photosensitive element transmits the electrical signal to the ISP for processing, transforming it into an image visible to the naked eye. The ISP can also optimize parameters such as exposure and color temperature of the shooting scene. In some embodiments, the ISP can be set in the camera 193.
[0083] Camera 193 is used to capture still images or videos. An object is projected onto a photosensitive element by generating an optical image through the lens. The photosensitive element can be a charge-coupled device (CCD) or a complementary metal-oxide-semiconductor (CMOS) phototransistor. The photosensitive element converts the light signal into an electrical signal, which is then passed to an ISP for conversion into a digital image signal. The ISP outputs the digital image signal to a DSP for processing. The DSP converts the digital image signal into image signals in standard RGB, YUV, or other formats. In some embodiments, the electronic device 100 may include one or N cameras 193, where N is a positive integer greater than 1.
[0084] Digital signal processors (DSPs) are used to process digital signals. Besides digital image signals, they can also process other digital signals. For example, when electronic device 100 selects a frequency, the DSP can perform Fourier transforms on the frequency energy.
[0085] Video codecs are used to compress or decompress digital video. Electronic device 100 may support one or more video codecs. Thus, electronic device 100 can play or record videos in various encoding formats, such as Moving Picture Experts Group (MPEG) 1, MPEG2, MPEG3, MPEG4, etc.
[0086] An NPU (Neural Processing Unit) is a computational processor for neural networks (NNs). By borrowing the structure of biological neural networks, such as the transmission patterns between neurons in the human brain, it can rapidly process input information and continuously learn on its own. NPUs enable intelligent cognitive applications in electronic devices, such as image recognition, facial recognition, speech recognition, and text understanding.
[0087] The external storage interface 120 can be used to connect an external memory card, such as a Micro SD card, to expand the storage capacity of the electronic device 100. The external memory card communicates with the processor 110 through the external storage interface 120 to perform data storage functions. For example, music, video, and other files can be saved on the external memory card.
[0088] Internal memory 121 can be used to store executable program code, including instructions. Internal memory 121 may include a program storage area and a data storage area. The program storage area may store the operating system, at least one application program required for a function (such as sound playback, image playback, etc.). The data storage area may store data created during the use of electronic device 100 (such as audio data, phonebook, etc.). Furthermore, internal memory 121 may include high-speed random access memory and may also include non-volatile memory, such as at least one disk storage device, flash memory, UFS, etc. Processor 110 executes various functional applications and data processing of electronic device 100 by running instructions stored in internal memory 121 and / or instructions stored in memory located within the processor.
[0089] Electronic device 100 can implement audio functions, such as music playback and recording, through audio module 170, speaker 170A, receiver 170B, microphone 170C, headphone jack 170D, and application processor.
[0090] Buttons 190 include a power button, volume buttons, etc. Buttons 190 can be mechanical buttons or touch-sensitive buttons. Electronic device 100 can receive button input and generate key signal inputs related to user settings and function control of electronic device 100.
[0091] Motor 191 can generate vibration alerts. Motor 191 can be used for incoming call vibration alerts or for touch vibration feedback. For example, touch operations applied to different applications (such as taking photos, playing audio, etc.) can correspond to different vibration feedback effects. Touch operations applied to different areas of the display screen 194 can also correspond to different vibration feedback effects from motor 191. Different application scenarios (such as time reminders, receiving messages, alarm clocks, games, etc.) can also correspond to different vibration feedback effects. The touch vibration feedback effect can also be customized.
[0092] Indicator 192 can be an indicator light, used to indicate charging status, power changes, or to indicate messages, missed calls, notifications, etc.
[0093] The SIM card interface 195 is used to connect a SIM card. The SIM card can be inserted into or removed from the SIM card interface 195 to make contact with and separate from the electronic device 100. The electronic device 100 can support one or N SIM card interfaces, where N is a positive integer greater than 1. The SIM card interface 195 can support Nano SIM cards, Micro SIM cards, SIM cards, etc. Multiple cards can be inserted into the same SIM card interface 195 simultaneously. The multiple cards can be of the same or different types. The SIM card interface 195 is also compatible with different types of SIM cards. The SIM card interface 195 is also compatible with external memory cards. The electronic device 100 interacts with the network through the SIM card to realize functions such as calls and data communication. In some embodiments, the electronic device 100 uses an eSIM, i.e., an embedded SIM card. The eSIM card can be embedded in the electronic device 100 and cannot be separated from the electronic device 100.
[0094] Figure 6 This is a flowchart illustrating a data recycling method provided in an embodiment of this application. This method 600 can be applied to electronic devices including processors and memory. This method 600 is mainly applied in scenarios where data recycling is required in file systems (e.g., F2FS). This method 600 includes steps S610 and S620, which will be described in detail below.
[0095] S610: During data reclamation, the processor sends an LBA remapping instruction to the memory;
[0096] The LBA remapping instruction is used to instruct the transfer of valid data corresponding to the original LBA segment to the target LBA segment by modifying the mapping relationship. The valid data corresponding to the original LBA segment is stored in the original PBA segment.
[0097] Optionally, the address range of the original LBA segment can be contiguous, for example, the address range of the original LBA segment is from address 0 to address 10; or, the address range of the original LBA segment can be non-contiguous, for example, the address range of the original LBA segment includes addresses 0 to address 5 and addresses 8 to address 12.
[0098] Similarly, the address ranges of the target LBA segment and the original PBA segment can be contiguous or non-contiguous, without limitation.
[0099] When the address ranges of both the original LBA segment and the target LBA segment are contiguous, the parameters in the LBA remapping instruction can include the starting address of the original LBA segment's address range, the starting address of the target LBA segment's address range, and the length of the LBA segment's address range. For example, if the address range of the original LBA segment is from address 0 to address 9, and the address range of the target LBA segment is from address 20 to address 29, the parameters in the LBA remapping instruction can include the starting address 0 of the original LBA segment's address range, the starting address 20 of the target LBA segment's address range, and the length 10 of the LBA segment's address range.
[0100] When the address ranges of the original LBA segment and / or the target LBA segment are not contiguous, the parameters in the LBA remapping instruction may include the starting address of each address range in the original LBA segment, the starting address of each address range in the target LBA segment, and the length of each address range. For example, if the address range of the original LBA segment includes addresses 0 to 5 and addresses 8 to 12, and the address range of the target LBA segment is addresses 20 to 30, the parameters in the LBA remapping instruction may include the starting address 0 and the length 6 of the first address range of the original LBA segment, the starting address 8 and the length 5 of the second address range of the original LBA segment, and the starting address 20 and the length 11 of the address range of the target LBA segment.
[0101] Optionally, the processor can be a system on chip (SOC), and the memory can be UFS or SSD, etc. This application does not limit the specific processor.
[0102] S620, in response to the LBA remapping instruction, modifies the mapping between the original LBA segment and the original PBA segment to a mapping between the target LBA segment and the original PBA segment.
[0103] It should be understood that when the memory modifies the mapping between the original LBA segment and the original PBA segment to a mapping between the target LBA segment and the original PBA segment, the original LBA segment no longer has a mapping relationship with the original PBA segment, and therefore no longer has a mapping relationship with the valid data stored in the original PBA segment, thus releasing the storage space of the original LBA segment; while the target LBA segment has a mapping relationship with the original PBA segment, and therefore has a mapping relationship with the valid data stored in the original PBA segment. That is, this application transfers the valid data corresponding to the original LBA segment to the target LBA segment by modifying the mapping relationship, thereby realizing the reclamation of the valid data of the original LBA segment without actual data relocation.
[0104] In one possible implementation, the memory can modify the mapping relationship between LBA and PBA by modifying the L2P and P2L mapping tables. Specifically, the L2P and P2L mapping tables, which include the mapping relationship between the original LBA segment, the target LBA segment, and the original PBA segment, can be read first. Then, the mapping between the original LBA segment and the original PBA segment can be changed to a mapping between the target LBA segment and the original PBA segment by modifying the L2P and P2L mapping tables. Based on this, the modification of the LBA and PBA mapping relationship can be achieved in a simple way.
[0105] It should be understood that in the read L2P mapping table, the original LBA segment and the original PBA segment are mapped to each other, while the target LBA segment is in an idle state and is not mapped to a PBA. In the read P2L mapping table, the original PBA segment and the original LBA segment are mapped to each other. However, in the modified L2P mapping table, the target LBA segment and the original PBA segment are mapped to each other, while the original LBA segment is in an idle state and is not mapped to a PBA. In the modified P2L mapping table, the original PBA segment and the target LBA segment are mapped to each other.
[0106] It should be understood that the mapping table read above may also include mapping relationships between other LBAs and other PBAs, and this application does not limit this.
[0107] Alternatively, the L2P mapping table and P2L mapping table can be read from NAND or static random access memory (SRAM). The SRAM, located in the memory controller, is used to cache data from the NAND, such as the L2P and P2L mapping tables.
[0108] Optionally, the L2P mapping table and P2L mapping table can be modified as follows: the original PBA segment is written into the PBA entry corresponding to the target LBA segment in the L2P mapping table, and the PBA entry corresponding to the original LBA segment is marked as invalid; and the LBA entry corresponding to the original PBA segment in the P2L mapping table is modified from the original LBA segment to the target LBA segment.
[0109] Optionally, each original LBA in the above original LBA segment corresponds to an original PBA; or, there may be one or more original LBAs in the above original LBA segment that do not have a corresponding PBA (i.e., they are in an idle state).
[0110] To ensure the accuracy of modifications to the L2P and P2L mapping tables, this application proposes that when modifying the L2P mapping table, the system analyzes whether each original LBA corresponds to a PBA. If a PBA is present, the corresponding PBA is written into the target LBA's entry, and the original LBA's corresponding PBA entry is marked as invalid. If no corresponding PBA is present, no modification is performed. Based on this modified mapping relationship, the LBA entry corresponding to each original PBA in the P2L mapping table is then modified.
[0111] As an example, suppose the original LBA segment includes n original LBAs and the target LBA segment includes n target LBAs. In practice, we can read the PBA entry corresponding to the i-th original LBA among the n original LBAs in the L2P mapping table, where i is traversed from 1 to n (i.e., each original LBA is traversed sequentially). When the PBA entry corresponding to the i-th original LBA includes an original PBA, the included original PBA is written into the PBA entry corresponding to the i-th target LBA among the n target LBAs, and the PBA entry corresponding to the i-th original LBA is marked as invalid. The corresponding LBA entry in the P2L mapping table is modified from the i-th original LBA to the i-th target LBA. Alternatively, if the PBA entry corresponding to the i-th original LBA does not include an original PBA, no modification is made.
[0112] After step S620 is executed, the memory can also send a prompt message to the processor, which indicates that the mapping relationship has been modified.
[0113] In summary, this application sends an LBA remapping instruction to the memory via the processor, instructing the memory to reclaim the original LBA data by changing the mapping relationship between LBA and PBA. This achieves data reclamation with only one command transmission, avoiding data movement, thereby reducing system power consumption and improving data reclamation efficiency. In addition, it can reduce the generation of garbage data in NAND, reduce write amplification, and improve device lifespan.
[0114] The following is combined Figure 7 The specific process of data recycling is illustrated with an example. It should be understood that, for ease of description, this example primarily uses the scenario where the original LBA segment includes n consecutive original LBAs and the target LBA segment includes n consecutive target LBAs. Figure 7 As shown, the process 700 includes steps S701 to S710, which are described below.
[0115] S701: When data reclamation is required, the processor sends an LBA remapping instruction to the memory.
[0116] In this implementation, the parameters of the LBA remapping instruction include the starting addresses of n original LBAs (i.e., the first original LBA among n original LBAs), the starting addresses of n target LBAs (i.e., the first target LBA among n target LBAs), and the length n of the LBA segment. This means: valid data corresponding to a continuous region of length n starting from the first original LBA is transferred to a continuous region of length n starting from the first target LBA.
[0117] S702, in response to the LBA remapping instruction, reads the L2P mapping table and P2L mapping table from memory;
[0118] S703, let the initial value of i be 1;
[0119] This allows us to start from the first original LBA and traverse the continuous region from the first original LBA to the nth original LBA in the L2P mapping table.
[0120] S704, determine whether i is less than or equal to n;
[0121] If i is less than or equal to n, continue with step S705; if i is no longer less than or equal to n, continue with step S710.
[0122] S705, Read the PBA entry corresponding to the i-th original LBA in the L2P mapping table, and continue to execute step S706;
[0123] S706, determine whether the PBA entry corresponding to the i-th original LBA includes the original PBA;
[0124] If the original PBA is included, proceed to step S707; if the original PBA is not included (i.e., the i-th original LBA is in an idle state), no modification is made, and proceed to step S709.
[0125] S707, Write the included original PBA into the PBA entry corresponding to the i-th target LBA among the n target LBAs in the L2P mapping table, and mark the PBA entry corresponding to the i-th original LBA as invalid, and then continue to execute step S708.
[0126] S708, Modify the LBA entry corresponding to the original PBA in the P2L mapping table from the i-th original LBA to the i-th target LBA;
[0127] S709, let i+1, and return to step S704, that is, start traversing the next original LBA;
[0128] S710, the memory returns a notification message to the processor, which indicates that the mapping modification has been completed.
[0129] Taking the example where each of the n original LBAs corresponds to an original PBA. Figure 8 This is a schematic diagram showing the L2P mapping table before and after modification, as provided in an embodiment of this application. For example... Figure 8 As shown, after modifying the mapping relationship, the contents of the PBA entries corresponding to the n original LBAs (i.e., original LBA-1 to original LBA-n) are written into the PBA entries corresponding to the n target LBAs (i.e., target LBA-1 to target LBA-n), and the PBA entries corresponding to the n original LBAs are marked as invalid (corresponding to...). Figure 8 (NONE).
[0130] Taking the example where each of the n original LBAs corresponds to an original PBA. Figure 9 This is a schematic diagram showing the P2L mapping table before and after modification, as provided in an embodiment of this application. For example... Figure 9 As shown, after modifying the mapping relationship, the contents of the LBA entries corresponding to the n original PBAs (i.e., original PBA-1 to original PBA-n) are changed from the n original LBAs (i.e., original LBA-1 to original LBA-n) to the n target LBAs (i.e., target LBA-1 to target LBA-n).
[0131] It should be noted that, Figure 8 and Figure 9 This introduction is based on the example that each of the n original LBAs corresponds to an original PBA. In practice, the number of original PBAs corresponding to the n original LBAs may be less than n, and this is not a limitation.
[0132] The following, combined with Figure 10 This application describes a data recycling device 1000 provided in an embodiment. The device 1000 includes a processor 1010 and a memory 1020.
[0133] In this embodiment, the processor 1010 and memory 1020 are used by the device 1000 to execute the corresponding steps in the above method embodiments. For example, the processor 1010 is used to send an LBA remapping instruction to the memory 1020 during data reclamation. This LBA remapping instruction instructs the valid data corresponding to the original LBA segment to be transferred to the target LBA segment by modifying the mapping relationship. The valid data corresponding to the original LBA segment is stored in the original PBA segment. The memory 1020 is used to receive the LBA remapping instruction sent by the processor 1010 and, in response to the LBA remapping instruction, modify the mapping between the original LBA segment and the original PBA segment to a mapping between the target LBA segment and the original PBA segment.
[0134] It should be understood that other related steps performed by the processor 1010 and memory 1020 can be found in the description in the above method embodiments, and will not be repeated here.
[0135] This application also provides a computer program product comprising one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the flow or function according to the embodiments of this application is generated. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that a computer can store or a data storage device such as a server or data center that integrates one or more available media. For example, available media may include magnetic media (e.g., floppy disk, hard disk, or magnetic tape), optical media (e.g., digital versatile disc (DVD)), or semiconductor media (e.g., solid-state disk (SSD)).
[0136] This application also provides an electronic device, including the aforementioned device 1000.
[0137] This application also provides a computer-readable storage medium. The computer-readable storage medium stores a computer program or instructions. When the computer program or instructions are executed by a processor, they implement the methods described above. The methods described in the above embodiments can be implemented wholly or partially by software, hardware, firmware, or any combination thereof. If implemented in software, the functionality can be stored as one or more instructions or code on or transmitted over the computer-readable medium. The computer-readable medium can include computer storage media and communication media, and can also include any medium that can transfer a computer program from one place to another. The storage medium can be any target medium accessible by a computer.
[0138] As one possible design, computer-readable media may include compact disc read-only memory (CD-ROM), RAM, ROM, EEPROM, or other optical disc storage; computer-readable media may include disk storage or other disk storage devices. Furthermore, any connecting cable may also be appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave, then coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of media. As used herein, disks and optical discs include optical discs (CD), laser discs, optical discs, DVDs, floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically, while optical discs optically reproduce data using lasers. Combinations of the above should also be included within the scope of computer-readable media.
[0139] This application describes embodiments with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processing unit of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processing unit of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.
[0140] The above specific embodiments further illustrate the purpose, technical solution and beneficial effects of this application. It should be understood that the above are only specific embodiments of this application and are not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made on the basis of the technical solution of this application should be included within the scope of protection of this application.
Claims
1. A data recycling method, characterized by, The method is applied to an electronic device including a processor and a memory, and when data is recycled, the method includes: The processor sends a logical block address (LBA) remapping instruction to the memory, where the LBA remapping instruction is used to instruct that effective data corresponding to an original LBA segment is transferred to a target LBA segment by modifying a mapping relationship, and the effective data corresponding to the original LBA segment is stored in an original physical block address (PBA) segment; In response to the LBA remapping instruction, the memory modifies the mapping relationship between the original LBA segment and the original PBA segment to the mapping relationship between the target LBA segment and the original PBA segment.
2. The method of claim 1, wherein, The modification of the mapping relationship between the original LBA segment and the original PBA segment to the mapping relationship between the target LBA segment and the original PBA segment includes: reading an L2P mapping table and a P2L mapping table, and the L2P mapping table and the P2L mapping table include the mapping relationship between the original LBA segment, the target LBA segment, and the original PBA segment; modifying the mapping relationship between the original LBA segment and the original PBA segment to the mapping relationship between the target LBA segment and the original PBA segment by modifying the L2P mapping table and the P2L mapping table.
3. The method of claim 2, wherein, The modification of the mapping relationship between the original LBA segment and the original PBA segment to the mapping relationship between the target LBA segment and the original PBA segment by modifying the L2P mapping table and the P2L mapping table includes: writing the original PBA segment in a PBA table item corresponding to the target LBA segment in the L2P mapping table, and marking a PBA table item corresponding to the original LBA segment as invalid; modifying an LBA table item corresponding to the original PBA segment in the P2L mapping table from the original LBA segment to the target LBA segment.
4. The method of claim 3, wherein, The original LBA segment includes n original LBAs, and the target LBA segment includes n target LBAs, and the modification of the mapping relationship between the original LBA segment and the original PBA segment to the mapping relationship between the target LBA segment and the original PBA segment by modifying the L2P mapping table and the P2L mapping table includes: reading a PBA table item corresponding to an i-th original LBA in the n original LBAs in the L2P mapping table, where i is from 1 to n; when an original PBA is included in the PBA table item corresponding to the i-th original LBA, writing the included original PBA into a PBA table item corresponding to an i-th target LBA in the n target LBAs, and marking the PBA table item corresponding to the i-th original LBA as invalid; modifying an LBA table item corresponding to the corresponding original PBA in the P2L mapping table from the i-th original LBA to the i-th target LBA; or, when no original PBA is included in the PBA table item corresponding to the i-th original LBA, no modification is performed.
5. The method according to any one of claims 2 to 4, characterized in that, The reading of the L2P mapping table and the P2L mapping table includes: The L2P mapping table and the P2L mapping table are read from a non-volatile memory NAND or a static random memory SRAM.
6. The method according to any one of claims 1 to 5, characterized in that, After the memory modifies the mapping relationship between the original LBA segment and the original PBA segment to the mapping relationship between the target LBA segment and the original PBA segment, the method further comprises: The memory sends a prompt message to the processor, and the prompt message is used to prompt that the modification of the mapping relationship is completed.
7. The method according to any one of claims 1 to 6, characterized in that, The LBA remapping instruction comprises a start address of an address range of the original LBA segment, a start address of an address range of the target LBA segment, and a length of an address range of an LBA segment.
8. The method according to any one of claims 1 to 7, characterized in that, The memory comprises a universal flash memory UFS or a solid state disk SSD.
9. A data recycling apparatus, characterized by, Comprise: A processor and a memory, wherein, The processor is configured to send an LBA remapping instruction to the memory during data recycling, and the LBA remapping instruction is used to instruct to transfer valid data corresponding to an original logical block address LBA segment to a target LBA segment by modifying a mapping relationship, and the valid data corresponding to the original LBA segment is stored in an original physical block address PBA segment. In response to the LBA remapping instruction, the memory is configured to modify the mapping relationship between the original LBA segment and the original PBA segment to the mapping relationship between the target LBA segment and the original PBA segment.
10. An electronic device, comprising: The data recycling device as claimed in claim 9.
11. A computer readable storage medium, characterized in that, The computer readable storage medium stores instructions, and when the instructions are run on the computer, the computer executes the method as claimed in any one of claims 1 to 8.