Circuit board automatic analysis and intelligent quotation system based on artificial intelligence

Abstract

The invention discloses a circuit board automatic analysis and intelligent quotation system based on artificial intelligence, relates to the technical field of electronic manufacturing information processing, and is used for solving the problem of insufficient automation of circuit board quotation. According to the method, unified geometric topology representation containing geometric coordinates and layer attributes is constructed, clustering division is performed on a board based on the representation, an artificial intelligence model is utilized to identify functional areas such as high-density bonding pads, and the routing density, line width, line distance and via hole distribution of each area are calculated. Generating a complexity characteristic spectrum by combining the number of layers of the whole board and the total number of drilled holes, then determining candidate process paths according to the complexity characteristic spectrum and a process route library, calculating process complexity indexes according to drilling, pressing, impedance adjustment and testing processes, forming a quotation parameter vector containing a comprehensive complexity level and a key process load, and determining the process complexity according to the quotation parameter vector. And a material price factor and an equipment load factor are combined to be input into a quotation decision model for model updating, so that automatic generation and self-adaptive optimization of the circuit board quotation are realized.

Description

Technical Field

[0001] This invention relates to the field of electronic manufacturing information processing technology, and more specifically, to an automated circuit board analysis and intelligent quotation system based on artificial intelligence. Background Technology

[0002] In the field of circuit board manufacturing and electronic manufacturing services, circuit board quotation systems based on rule templates and experience parameters have been widely used. Such systems typically involve customers or engineering technicians uploading circuit board design files, and then manually filling in key parameters such as board length and width, number of layers, board thickness, minimum line width, minimum hole diameter, surface treatment type, and batch quantity on a webpage. The quotation program then calculates material costs, process costs, and gross profit margins according to preset formulas to generate a preliminary quotation. Existing technical solutions focus on improving parameter input efficiency and rule calculation speed, providing a reference price in a short time through parameter tables and pricing templates. The technical implementation involves the linkage of circuit board design data processing, production process configuration, and management information systems.

[0003] However, existing technologies have shortcomings in their ability to understand design documents and characterize process complexity at the front end of the quotation process. There is a lack of stable mapping between the design document parsing results and quotation parameters. The system usually only obtains dimensions, number of layers, and a few global indicators, and cannot extract features that significantly affect manufacturing difficulty and yield from the board structure, such as high-density pad areas, high-frequency signal areas, and high-current power supply areas. Process complexity is often simplified to a few levels, making it difficult to reflect the comprehensive impact of different area wiring densities and hole diameter combinations on drilling, lamination, and testing processes. At the same time, the quotation model is disconnected from the process route library and production line capabilities, making it impossible to calculate the process load factor under different process paths. It also fails to fully utilize the actual material consumption and gross profit data from historical orders to adaptively correct the model, resulting in insufficient sensitivity of the quotation results to complex design and process changes. It still relies heavily on the experience judgment of engineers, affecting the accuracy of the quotation and the reliability of the company's order acceptance decision. Summary of the Invention

[0004] To overcome the aforementioned deficiencies in the prior art, the following solution is proposed to address the problem of insufficient automation in circuit board pricing in the aforementioned background art.

[0005] To achieve the above objectives, the present invention provides the following technical solution:

[0006] An AI-based automated circuit board analysis and intelligent quotation system includes a design file parsing module, a board area recognition module, a process diagram construction module, a quotation parameter generation module, and a model optimization module, with each module connected by a signal.

[0007] The design file parsing module is used to receive circuit board design files, identify the format, extract contour layer, conductor layer, drilling data and component information, and generate a geometric topology representation in a unified coordinate system.

[0008] The board surface region identification module is used to cluster and divide the board surface into multiple board surface regions based on geometric topology representation, and to classify the board surface regions by purpose through artificial intelligence model, marking high-density pad regions, high-frequency signal regions and high-current power supply regions.

[0009] The process map construction module is used to calculate the trace density, minimum line width, minimum line spacing and via distribution for the board surface area. It combines the total number of layers and the total number of drill holes to generate a complexity feature map with the board surface area as nodes and the adjacent relationship of the area as edges.

[0010] The quotation parameter generation module is used to determine candidate process paths based on the complexity feature map and process route library, calculate the process complexity index of each process path, and form a quotation parameter vector containing the comprehensive complexity level and key process load factor.

[0011] The model optimization module is used to input the quotation parameter vector, material price factor, and equipment load factor into the quotation decision model to generate circuit board quotation results. After the order is completed, the actual cost data is collected to update the parameters of the quotation decision model.

[0012] Furthermore, the design file parsing module is used to perform syntax parsing and layer parsing on Gerber files, ODB files, and CAD project files, converting outlines, copper foil graphics, drill records, and component package data into spatial coordinates in a unified coordinate system. In the geometric topology representation, layer number, network number, and object number are written for each object, forming a set of objects in the geometric topology representation.

[0013] Furthermore, the design file parsing module is used to divide the layers into contour layers, conductor layers, drilling layers, solder mask layers, silkscreen layers, impedance-related layers, and mechanical layers based on the object set. Layers that only contain annotation text or reference lines and are not output as manufacturing data are deleted. In the geometric topology representation, the layer to which each object belongs and the manufacturing semantic category are recorded.

[0014] Furthermore, the board surface region identification module is used to perform spatial clustering of the board surface to generate an initial set of board surface regions based on the component pin density, trace density, via density and copper foil coverage in the geometric topology representation, and delete the initial board surface regions whose area is less than the minimum area threshold and whose number of objects is less than the minimum number of objects threshold according to the minimum area threshold and minimum object number threshold.

[0015] Furthermore, the board surface area recognition module is used to input the local image data and local topology sub-graph of each initial board surface area into the artificial intelligence model, and output the purpose labels of high-density pad area, high-frequency signal area, high current power supply area, impedance control area and gold finger area. It merges adjacent initial board surface areas containing blind holes or buried holes in the layer direction to form a cross-layer three-dimensional area that records information involving the number of layers and hole type combination.

[0016] Furthermore, the process map construction module is used to write the trace density, minimum line width, minimum line spacing, via diameter distribution, impedance control trace length, and copper foil coverage of each board area into the node attributes of the complexity feature map, write the adjacency relationship and cross-layer connection relationship between board areas into the edge attribute of the complexity feature map, and write the total number of layers, layer type distribution, total number of drill holes, and area of ​​special surface treatment areas into the global attributes of the complexity feature map.

[0017] Furthermore, the process map construction module is used to perform threshold determination and adjacency aggregation on nodes based on node attributes and edge attributes in the complexity feature map, identify drilling bottleneck areas, pressing sensitive areas and impedance adjustment sensitive areas, record drilling complexity labels for nodes belonging to drilling bottleneck areas, record pressing complexity labels for nodes belonging to pressing sensitive areas, and record impedance complexity labels for nodes belonging to impedance adjustment sensitive areas.

[0018] Furthermore, the quotation parameter generation module is used to select process routes from the process route library that are compatible with the number of circuit board layers and drilling structure based on the global attributes and node labels of the complexity feature map to form a set of candidate process routes, and to record a sequence of process segments including drilling process segment, lamination process segment, impedance adjustment process segment and testing process segment for each candidate process route.

[0019] Furthermore, the quotation parameter generation module is used to summarize the drilling complexity label, pressing complexity label, and impedance complexity label of the complexity feature map nodes involved in the corresponding process segment for each candidate process path, calculate the drilling complexity index, pressing complexity index, impedance complexity index, and testing complexity index, generate a comprehensive complexity level and yield risk factor according to the preset mapping relationship, and combine the comprehensive complexity level, key process complexity index, and yield risk factor into a quotation parameter vector.

[0020] Furthermore, the model optimization module is used to associate and store the quotation parameter vector, circuit board quotation result, actual material consumption, actual working hours, actual yield and actual gross profit to form training samples after the order is completed. The training samples are then input into the quotation decision model to adjust the parameters of the quotation decision model, and the mapping relationship between the comprehensive complexity level and the cost coefficient is adjusted according to the deviation between the actual cost and the estimated cost.

[0021] The technical effects and advantages of the artificial intelligence-based automated circuit board analysis and intelligent quotation system of the present invention are as follows:

[0022] This invention achieves automatic generation of complexity feature vectors from circuit board design documents to pricing decisions by constructing an automated processing chain that combines design document parsing, board area identification, process feature map generation, and pricing parameter generation. This reduces manual drawing reading and parameter entry, and lowers pricing fluctuations caused by experience differences.

[0023] Based on the complexity feature map and process route library, candidate process paths are inferred. At the path level, the complexity index of each key process, such as drilling, lamination, impedance adjustment, and testing, is calculated. The comprehensive complexity level and process load factor are input into the pricing decision model, so that the pricing results can reflect the local structural differences of the board and the actual process capability. The model optimization module incorporates the actual material consumption, working hours, and gross profit data from historical orders to continuously correct the pricing decision model. This ensures that the system maintains pricing accuracy and stability when new product forms and process conditions change, thereby improving pricing efficiency while taking into account cost control and profit management, and enhancing the order response capability and business decision-making level of circuit board manufacturers. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the structure of an automated circuit board analysis and intelligent quotation system based on artificial intelligence according to the present invention. Detailed Implementation

[0025] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0026] In order to achieve the above objectives, Figure 1 A schematic diagram of the structure of an automated circuit board analysis and intelligent quotation system based on artificial intelligence is given in this invention. Specifically, it includes a design file parsing module, a board area recognition module, a process diagram construction module, a quotation parameter generation module, and a model optimization module. The modules are connected by signals.

[0027] The design file parsing module is used to receive circuit board design files, identify the format, extract contour layer, conductor layer, drilling data and component information, and generate a geometric topology representation in a unified coordinate system.

[0028] The board surface region identification module is used to cluster and divide the board surface based on geometric topology representation to obtain the board surface region, and to classify the board surface region by purpose through artificial intelligence model, marking high-density pad region, high-frequency signal region and high current power supply region.

[0029] The process map construction module is used to calculate the trace density, minimum line width, minimum line spacing and via distribution for the board surface area. It combines the total number of layers and the total number of drill holes to generate a complexity feature map with the board surface area as nodes and the adjacent relationship of the area as edges.

[0030] The quotation parameter generation module is used to determine candidate process paths based on the complexity feature map and process route library, calculate the process complexity index of each process path, and form a quotation parameter vector containing the comprehensive complexity level and key process load factor.

[0031] The model optimization module is used to input the quotation parameter vector, material price factor, and equipment load factor into the quotation decision model to generate circuit board quotation results. After the order is completed, the actual cost data is collected to update the parameters of the quotation decision model.

[0032] The design file parsing module receives circuit board design files, identifies the format, extracts contour layer, conductor layer, drilling data, and component information, and generates a geometric topological representation in a unified coordinate system. Specifically, it includes:

[0033] The design file parsing module is deployed in the server-side quotation system and consists of a file receiving unit, a format recognition unit, a syntax parsing unit, and a geometric topology construction unit. The file receiving unit receives circuit board design files via a web upload interface, interface call, or design software plugin, temporarily storing the received files in a cache directory. The format recognition unit first classifies the input file into Gerber files, ODB files, and CAD project files based on the file extension and header characteristics. When a compressed file format is identified, the decompression program is invoked to expand the sub-files in the temporary directory, and then the format of each expanded sub-file is determined.

[0034] For design data identified as Gerber files, the syntax parsing unit parses layer definition statements and drawing statements according to the Gerber RS-274X standard, converting each drawing instruction into a line segment object, arc object, or polygon object, reading unit settings, zero suppression mode, and coordinate format, and uniformly converting the original coordinates into numerical coordinates in millimeters; at the same time, the accompanying drilling file is parsed according to the Excellon format, and the hole position coordinates, hole diameter, and hole type are recorded as drilling objects.

[0035] For design data identified as ODB files, the syntax parsing unit parses the ODB directory structure, reads the job, step, and layer description files, and converts the outline graphics, conductor graphics, drill entities, and solder mask graphics into internal objects. For design data identified as CAD engineering files, the syntax parsing unit reads the board outline, trace objects, pad objects, via objects, and component objects through the CAD interface, and extracts the spatial coordinates, dimensional parameters, and net name of each object.

[0036] The outline, copper foil pattern, drilling record, and component packaging data obtained from the above analysis are mapped to a unified coordinate system with the lower left corner of the board outline as the origin and millimeters as the unit through a unified coordinate conversion rule.

[0037] After completing the parsing of multi-format files, the geometric topology building unit establishes a data structure for the geometric topology representation in memory, organizing all objects into an object set. For each line segment object, arc object, polygon object, drill object, and pad object, the geometric topology building unit writes spatial coordinates, object number, layer number, and net number into the geometric topology representation. The object number is a unique integer identifier within the current design file, the layer number is generated according to the layer order, and the net number is generated according to the net name or net attribute mapping table.

[0038] Subsequently, the layer semantic segmentation subunit performs manufacturing semantic segmentation on the layers based on the object set. Layers containing board outline graphics are marked as outline layers, layers containing conductor graphics are marked as conductor layers, layers containing hole position records are marked as drilling layers, layers containing window areas are marked as solder mask layers, layers containing marking characters are marked as silkscreen layers, layers containing impedance characteristic descriptions or specific impedance structures are marked as impedance-related layers, and layers used only for outline annotation or mounting hole reference are marked as mechanical layers.

[0039] For layers that only contain dimension lines and text descriptions and are not output in the manufacturing process, the layer semantic partitioning subunit removes them from the geometric topology representation and no longer participates in subsequent analysis. For each retained object, the geometric topology construction unit adds a manufacturing semantic category field to its record to indicate whether the object belongs to a contour layer, conductor layer, drill layer, solder mask layer, silkscreen layer, impedance-related layer, or mechanical layer. Through the above processing, the geometric topology representation output by the design document parsing module simultaneously includes geometric information in a unified coordinate system, network connectivity between objects, and manufacturing semantic tags.

[0040] The board surface region identification module is used to cluster and divide the board surface into multiple board surface regions based on geometric topological representation, and then classify the board surface regions according to their uses using an artificial intelligence model, labeling high-density pad regions, high-frequency signal regions, and high-current power supply regions, specifically including:

[0041] The board area identification module is deployed in the same server environment as the design file parsing module. It processes the geometric topology representation through area candidate generation units, spatial clustering units, and application identification units. The area candidate generation unit first reads the object records of each conductor layer, drill layer, and impedance-related layer from the geometric topology representation. Based on the board area divided into grids of fixed size, it counts the number of component pins, trace lengths, vias, and copper foil coverage area in each grid cell. It calculates four indicators: component pin density, trace density, via density, and copper foil coverage. Grids with at least one indicator exceeding a preset reference value are marked as high-interest grids.

[0042] The spatial clustering unit uses high-interest grids as seed grids and performs clustering algorithms based on grid adjacency and index similarity. Connected high-interest grids with similar indices are merged into initial planar regions. Simultaneously, the geometric area and the number of objects contained in each initial planar region are calculated. For initial planar regions with a geometric area less than a minimum area threshold and a number of objects less than a minimum object count threshold, the spatial clustering unit removes them from the initial planar region set, thus forming a set of planar regions that meet the area and object count requirements. Each planar region in the set is assigned a unique region number and boundary polygon.

[0043] In another embodiment, the use identification unit in the board area identification module classifies the use of the board area based on an artificial intelligence model.

[0044] The application identification unit extracts local geometric data from the geometric topology representation of each board area, with the area boundary as the range, and generates a fixed-size local image block through a graphic rasterization method. At the same time, it constructs a local topology subgraph from the conductor objects, pad objects and drill objects in the corresponding area. The local topology subgraph records the network connection relationship and spatial adjacency relationship between objects.

[0045] The application identification unit inputs local image patches and local topological subgraphs as features into a pre-trained artificial intelligence model. During the training phase, the AI ​​model learns feature patterns of high-density pad areas, high-frequency signal areas, high-current power supply areas, impedance control areas, and gold finger areas based on historical circuit board samples. During the application phase, it outputs corresponding application category labels and category confidence scores. Based on the application category labels output by the AI ​​model, the application identification unit labels each board area as a high-density pad area, high-frequency signal area, high-current power supply area, impedance control area, or gold finger area, and writes the application category into the board area record for subsequent process pattern construction module to read.

[0046] In another embodiment, the board surface region identification module further includes a cross-layer region construction unit for processing board surface regions related to blind vias or buried vias. The cross-layer region construction unit identifies drill objects whose diameter is smaller than a preset blind via diameter threshold and whose start and end layer numbers are different, based on the drill object record in the geometric topology representation. These drill objects are then divided into a blind via object set and a buried via object set. The cross-layer region construction unit searches for board surface regions in the board surface region set that overlap with the projection positions of the blind via object set and the buried via object set. Board surface regions that overlap on different conductor layers but have the same application category in planar coordinates are merged into a cross-layer three-dimensional region. The cross-layer three-dimensional region record is then written with a list of conductor layer numbers, the corresponding blind via or buried via type, and the associated board surface region number.

[0047] Through the above processing, the set of board surface regions output by the board surface region recognition module includes both planar regions obtained based on spatial clustering and cross-layer three-dimensional regions obtained based on blind holes and buried holes. Each region has a clear purpose category label for subsequent process feature extraction and complexity feature map construction.

[0048] The process map construction module is used to calculate trace density, minimum trace width, minimum trace spacing, and via distribution for a given board area. Combining the total number of layers and total number of drill holes, it generates a complexity feature map with board areas as nodes and adjacent areas as edges. Specifically, it includes:

[0049] The process map construction module is deployed on the server side and interacts with the design file parsing module and the board area identification module via an internal bus. The process map construction module first reads the area number, boundary polygon, and corresponding conductor object, pad object, and drill object identifiers for each board area from the board area set output by the board area identification module. After completing the data reading, the process map construction module calculates the area based on the boundary polygon of each board area, calculates the trace length based on the total length of all conductor objects within the area, and divides the trace length by the area to obtain the trace density index.

[0050] When traversing conductor objects within a region, the process map construction module records the linewidth and minimum spacing values ​​of all conductor objects within that region. It selects the minimum linewidth value as the minimum linewidth index and the minimum spacing value as the minimum spacing index for that region. Simultaneously, based on the hole diameter and location of drilled objects within the region, the module categorizes and statistically analyzes the drilled objects according to diameter ranges, generating via distribution data for that region. This data includes the number of drilled holes in each diameter range and a list of their distribution locations within the region. The process map construction module associates and stores the trace density index, minimum linewidth index, minimum spacing index, and via distribution data with the board region number, providing a data foundation for subsequent writing of map node attributes.

[0051] Based on the above embodiments, the process map construction module also reads the total number of layers and the total number of drill holes from the geometric topology representation output by the design document parsing module, calculates the layer type distribution information of each conductor layer, and saves this information as the overall layer-level attributes of the board. Subsequently, the process map construction module initializes the data structure of the complexity feature map in memory, treats each board area as a graph node, assigns a region number to each graph node, and writes the corresponding trace density index, minimum line width index, minimum line spacing index, and via distribution data into the node attribute field. At the same time, copper foil coverage, impedance control trace length, and the region's purpose label can be written as supplementary node attributes. The process map construction module establishes an undirected edge in the complexity feature map when any two plate area boundaries share a common edge or vertex, based on the planar adjacency relationships of the polygonal boundaries of the plate areas. This undirected edge is recorded as an adjacency relationship edge. For cross-layer solid regions formed by cross-layer solid region construction units, the process map construction module establishes cross-layer connection edges between different plate area nodes belonging to the same cross-layer solid region, and records the conductor layer number involved and the associated blind via type or buried via type in the edge attributes. The process map construction module writes the total number of plate layers, layer type distribution, total number of drilled holes, and area of ​​special surface treatment regions into the global attribute fields of the complexity feature map, thereby simultaneously saving node-level features, edge-level relationships, and global process information in the same complexity feature map.

[0052] In another embodiment, after completing the construction of nodes and edges in the complexity feature map, the process map construction module performs threshold determination and adjacency aggregation operations on the node attributes and edge attributes in the complexity feature map to identify key process bottleneck areas. For each node, the process map construction module compares its routing density index, minimum line width index, minimum line spacing index, and via distribution data with a preset complexity threshold set. When the routing density index of a node is greater than the routing density threshold and the number of small-diameter drill holes in the via distribution data is greater than the corresponding threshold, the node is marked as a drilling bottleneck candidate node. When the minimum line width index of a node is less than the line width threshold and there are multiple nodes in the adjacent nodes that are used for high-frequency signal regions, the node is marked as a compression sensitive candidate node. When the impedance control routing length of a node is greater than the impedance length threshold and the number of cross-layer connection edges with impedance-related layers exceeds the cross-layer threshold, the node is marked as an impedance adjustment sensitive candidate node.

[0053] Based on this, the process map construction module uses the edge relationships in the complexity feature map to perform adjacency aggregation on candidate nodes. Multiple candidate nodes connected by adjacency or cross-layer connections are aggregated into drilling bottleneck regions, pressing sensitive regions, and impedance adjustment sensitive regions. Drilling complexity labels, pressing complexity labels, and impedance complexity labels are written into the node attributes respectively, providing a well-labeled complexity feature map input for the subsequent calculation of process complexity indicators by the quotation parameter generation module.

[0054] The pricing parameter generation module is used to determine candidate process paths based on complexity feature maps and process route libraries, calculate the process complexity index for each process path, and form a pricing parameter vector containing a comprehensive complexity level and key process load factors, specifically including:

[0055] The quotation parameter generation module is deployed on the server side and interacts with the process map construction module and the process route library through internal interfaces. The quotation parameter generation module first obtains a complete complexity feature map from the process map construction module. This map includes global attributes such as the total number of layers, layer type distribution, total number of drill holes, and area of ​​special surface treatment regions, as well as trace density, minimum trace width, minimum trace spacing, via distribution, impedance control trace length, copper foil coverage, and complexity tags for each board surface node. Simultaneously, the quotation parameter generation module reads pre-maintained process route data from the process route library. This data is indexed by the process route number and records the layer range, drill structure type, surface treatment method, and sequence of process steps for each process route. The sequence of process steps marks the order of drilling, lamination, impedance adjustment, and testing processes, as well as the equipment type corresponding to each process step.

[0056] The quotation parameter generation module matches the global attributes of the complexity feature map with the adaptation conditions recorded in the process route data. It selects process routes that meet the layer number condition, drilling structure condition, and surface treatment condition into the candidate process path set. For each process path in the candidate process path set, it retains the corresponding process segment sequence for complexity calculation.

[0057] The quotation parameter generation module calculates the process complexity index for each process path in the candidate process path set. For a given process path, the quotation parameter generation module selects a set of nodes associated with the drilling process segment of that process path from the complexity feature map. This set of nodes includes nodes marked as drilling bottleneck areas and nodes with high through-hole density and concentrated distribution of small-diameter boreholes.

[0058] The pricing parameter generation module summarizes the drilling complexity labels, via distribution data, corresponding area, and number of adjacent nodes in the node set, and obtains the drilling complexity index for the process path according to pre-set rules. For the lamination process, the pricing parameter generation module selects nodes marked as lamination-sensitive areas and nodes located in multi-layer stacked areas and thick copper stacked areas, and statistically analyzes the minimum linewidth, minimum line spacing, interlayer connection relationship, and area of ​​these nodes, and obtains the lamination complexity index for the process path according to pre-set combination rules.

[0059] For the impedance adjustment process segment, the quotation parameter generation module selects nodes marked as impedance adjustment sensitive areas and nodes whose impedance control trace length exceeds the threshold. It then performs statistics on the impedance control trace length, the number of cross-layer connections, and the number of adjacent high-frequency signal regions to obtain the impedance complexity index of the process path.

[0060] For the testing process segment, the quotation parameter generation module calculates the testing complexity index according to preset rules based on the total number of holes drilled on the board, the number of board areas, the number of nodes used for high-frequency signal areas and high-current power supply areas, and the distribution of complexity labels. The quotation parameter generation module combines the above-mentioned drilling complexity index, lamination complexity index, impedance complexity index and testing complexity index, and determines the comprehensive complexity level corresponding to the process path according to the preset complexity level classification rules.

[0061] The quotation parameter generation module generates a quotation parameter vector that includes the overall complexity level and the load factor of key processes based on the process complexity index.

[0062] Based on the drilling complexity index and the drilling equipment capacity recorded in the process route library, the drilling complexity index is mapped to a drilling load factor to represent the resource consumption of drilling equipment in this process path. Based on the pressing complexity index and layer number information, the pressing complexity index is mapped to a pressing load factor to represent the pressure on the pressing equipment from multiple pressing operations and alignment control. Based on the impedance complexity index, it is mapped to an impedance adjustment load factor to represent the possible debugging workload in the impedance adjustment stage. Based on the testing complexity index, it is mapped to a testing load factor to represent the number of test points and testing time pressure for online testing or flying probe testing. The quotation parameter generation module can also calculate the yield risk factor corresponding to this process path based on the above complexity indices and the actual yield of similar complexity feature maps in historical order data.

[0063] Finally, the quotation parameter generation module combines the complexity level, drilling load factor, lamination load factor, impedance adjustment load factor, testing load factor, and yield risk factor into a quotation parameter vector, and outputs it together with the process path number and circuit board design identifier, providing input parameters for the subsequent quotation decision model to generate circuit board quotation results.

[0064] The model optimization module is used to input the quotation parameter vector along with material price factors and equipment load factors into the quotation decision model to generate circuit board quotation results. After order completion, it collects actual cost data to update the parameters of the quotation decision model. Specifically, this includes:

[0065] The model optimization module is deployed on the server side and connects to the quotation parameter generation module, the material management system and the capacity management system through the data interface unit.

[0066] The data interface unit obtains the quotation parameter vector generated for the target circuit board from the quotation parameter generation module. At the same time, it reads the current raw material purchase price, transportation surcharge and related contract discount factor from the material management system, and reads the utilization rate, production scheduling tension and planned maintenance window information of key equipment from the capacity management system. The above material price factor and equipment load factor are aligned and normalized with the quotation parameter vector to form the quotation decision input feature vector.

[0067] The pricing decision model in the model optimization module is initialized as a multi-layered parametric calculation model. After receiving the pricing decision input feature vector, it calculates the intermediate features layer by layer according to the preset hierarchical calculation order, and finally outputs the circuit board pricing result. The pricing result, together with the corresponding pricing parameter vector, material price factor and equipment load factor, is written into the pricing record database for subsequent training sample construction.

[0068] After the order execution phase, the model optimization module, through its interface with the manufacturing execution system and cost accounting system, collects actual material consumption data, actual working hours data, actual production batch size, actual scrap quantity, rework frequency, and gross profit data corresponding to the quotation records. It establishes a one-to-one correspondence between this data and the quotation parameter vector and circuit board quotation results in the quotation records, forming a training sample set containing decision input features, model output results, and actual cost results. The parameter update unit within the model optimization module is activated at a fixed time period or when the number of training samples reaches a preset threshold. It selects a batch of samples from the training sample set, calculates the deviation between the circuit board quotation result in each sample and the target quotation calculated based on actual material consumption and actual working hours, and uses the magnitude of the deviation as an adjustment weight to gradually correct the parameters of each layer in the quotation decision model, causing the predicted results on the training samples to converge towards the target quotation.

[0069] After completing a round of parameter adjustment, the parameter update unit marks and saves the new model parameter version, while retaining the previous version as a rollback version. When the deviation of the new parameter version on subsequent samples continuously exceeds the preset tolerance range, the model optimization module switches back to the previous version of parameters and reduces the weight of the corresponding samples in subsequent training, thereby suppressing abnormal samples and abnormal cost fluctuations.

[0070] The above embodiments can be implemented, in whole or in part, by software, hardware, firmware, or any other combination thereof. When implemented using software, the above embodiments can be implemented, in whole or in part, in the form of a computer program product.

[0071] Those skilled in the art will recognize that the modules and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0072] In addition, the functional modules in the various embodiments of this application can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module.

[0073] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0074] In conclusion, the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. An automated circuit board analysis and intelligent quotation system based on artificial intelligence, characterized in that: It includes a design file parsing module, a board area recognition module, a process diagram construction module, a quotation parameter generation module, and a model optimization module, and the modules are connected by signals. The design file parsing module is used to receive circuit board design files, identify the format, extract contour layer, conductor layer, drilling data and component information, and generate a geometric topology representation in a unified coordinate system. The board surface region identification module is used to cluster and divide the board surface based on geometric topology representation to obtain the board surface region, and to classify the board surface region by purpose through artificial intelligence model, marking high-density pad region, high-frequency signal region and high current power supply region. The process map construction module is used to calculate the trace density, minimum line width, minimum line spacing and via distribution for the board surface area. It combines the total number of layers and the total number of drill holes to generate a complexity feature map with the board surface area as nodes and the adjacent relationship of the area as edges. The quotation parameter generation module is used to determine candidate process paths based on the complexity feature map and process route library, calculate the process complexity index of each process path, and form a quotation parameter vector containing the comprehensive complexity level and key process load factor. The model optimization module is used to input the quotation parameter vector, material price factor, and equipment load factor into the quotation decision model to generate circuit board quotation results. After the order is completed, the actual cost data is collected to update the parameters of the quotation decision model.

2. The automated circuit board analysis and intelligent quotation system based on artificial intelligence according to claim 1, characterized in that: The design file parsing module is used to perform syntax parsing and layer parsing on Gerber files, ODB files, and CAD project files. It converts outlines, copper foil graphics, drill records, and component package data into spatial coordinates in a unified coordinate system. In the geometric topology representation, it writes layer number, network number, and object number for each object, forming a set of objects in the geometric topology representation.

3. The automated circuit board analysis and intelligent quotation system based on artificial intelligence according to claim 2, characterized in that: The design file parsing module is used to divide layers into contour layers, conductor layers, drilling layers, solder mask layers, silkscreen layers, impedance-related layers, and mechanical layers based on the object collection. Layers that only contain annotation text or reference lines and are not output as manufacturing data are deleted. In the geometric topology representation, the layer to which each object belongs and the manufacturing semantic category are recorded.

4. The automated circuit board analysis and intelligent quotation system based on artificial intelligence according to claim 3, characterized in that: The board surface region identification module is used to perform spatial clustering of the board surface based on the component pin density, trace density, via density and copper foil coverage in the geometric topology representation to generate an initial set of board surface regions. It also deletes the initial board surface regions whose area is less than the minimum area threshold and whose number of objects is less than the minimum number of objects threshold based on the minimum area threshold and minimum object number threshold.

5. The automated circuit board analysis and intelligent quotation system based on artificial intelligence according to claim 4, characterized in that: The board area recognition module takes the local image data and local topology sub-graph of each initial board area as input to the artificial intelligence model, and outputs the purpose labels of high-density pad area, high-frequency signal area, high-current power supply area, impedance control area and gold finger area. It merges adjacent initial board areas containing blind or buried vias in the layer direction to form a cross-layer three-dimensional area that records information involving the number of layers and the combination of via types.

6. The automated circuit board analysis and intelligent quotation system based on artificial intelligence according to claim 5, characterized in that: The process map construction module is used to write the trace density, minimum line width, minimum line spacing, via diameter distribution, impedance control trace length, and copper foil coverage of each board area into the node attributes of the complexity feature map, write the adjacency relationship and cross-layer connection relationship between board areas into the edge attributes of the complexity feature map, and write the total number of layers, layer type distribution, total number of drill holes, and area of ​​special surface treatment areas into the global attributes of the complexity feature map.

7. The automated circuit board analysis and intelligent quotation system based on artificial intelligence according to claim 6, characterized in that: The process map construction module is used to perform threshold determination and adjacency aggregation on nodes based on node attributes and edge attributes in the complexity feature map, identify drilling bottleneck areas, pressing sensitive areas and impedance adjustment sensitive areas, record drilling complexity labels for nodes belonging to drilling bottleneck areas, record pressing complexity labels for nodes belonging to pressing sensitive areas, and record impedance complexity labels for nodes belonging to impedance adjustment sensitive areas.

8. The automated circuit board analysis and intelligent quotation system based on artificial intelligence according to claim 7, characterized in that: The quotation parameter generation module is used to select process routes from the process route library that are suitable for the number of circuit board layers and drilling structure based on the global attributes and node labels of the complexity feature map, forming a set of candidate process routes, and recording a sequence of process segments including drilling process segment, lamination process segment, impedance adjustment process segment and testing process segment for each candidate process route.

9. The automated circuit board analysis and intelligent quotation system based on artificial intelligence according to claim 8, characterized in that: The pricing parameter generation module is used to summarize the drilling complexity label, pressing complexity label, and impedance complexity label of the complexity feature map nodes involved in the corresponding process segment for each candidate process path, calculate the drilling complexity index, pressing complexity index, impedance complexity index, and testing complexity index, generate a comprehensive complexity level and yield risk factor according to the preset mapping relationship, and combine the comprehensive complexity level, key process complexity index, and yield risk factor into a pricing parameter vector.

10. The automated circuit board analysis and intelligent quotation system based on artificial intelligence according to claim 9, characterized in that: The model optimization module is used to associate and store the quotation parameter vector, circuit board quotation result, actual material consumption, actual working hours, actual yield and actual gross profit to form training samples after the order is completed. The training samples are then input into the quotation decision model to adjust the parameters of the quotation decision model. The mapping relationship between the comprehensive complexity level and the cost coefficient is adjusted according to the deviation between the actual cost and the estimated cost.

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