Battery equalization circuit, battery protection chip, protection board and protection system

Abstract

The invention discloses a battery equalization circuit, a battery protection chip, a protection board and a protection system, and the circuit comprises a first voltage division circuit, an equalization enabling circuit, an equalization control circuit, a first equalization switching circuit and a second equalization switching circuit, so that detection and control logic can be integrated in the battery protection chip. According to the invention, external discrete components are not needed for voltage judgment, the peripheral cost and the circuit board area are remarkably reduced, and meanwhile, the equalization starting point can be accurately calibrated before the battery protection chip leaves a factory through the trimmable first preset equalization difference and the second preset equalization difference, so that the problem of precision dispersion caused by component tolerance in a traditional scheme is solved, and the reliability of the battery protection chip is improved. And the consistency and the reliability of the battery protection chip are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of battery management, and in particular to a battery equalization circuit, a battery protection chip, a protection board and a protection system. BACKGROUND

[0002] In a series lithium battery pack, there is a problem of voltage inconsistency between each cell, which affects the overall performance and life of the battery pack. The existing equalization scheme is mostly implemented at the board level, and the equalization start threshold is determined by the parameters of external components. However, such a scheme has inherent defects: the equalization accuracy cannot be controlled and calibrated at the chip manufacturing stage, resulting in scattered equalization control points of the final product and difficulty in ensuring performance consistency. SUMMARY

[0003] Embodiments of the present application provide a battery equalization circuit, a battery protection chip, a protection board and a protection system to solve the problem of uncontrollable and uncalibrable equalization accuracy in the prior art.

[0004] A battery equalization circuit for equalization control of a first battery and a second battery in series, comprising a first voltage dividing circuit, an equalization enable circuit, an equalization control circuit, a first equalization switch circuit and a second equalization switch circuit. A first end of the first voltage dividing circuit is used to connect a positive electrode of the first battery, and a second end of the first voltage dividing circuit is connected with a ground terminal. The equalization enable circuit is connected with a first voltage dividing node of the first voltage dividing circuit and a first reference terminal, and is used to output an enable control signal when a first voltage dividing voltage provided by the first voltage dividing node is greater than a first reference voltage provided by the first reference terminal. The first equalization switch circuit is used to connect a first external equalization circuit and is connected with the positive electrode of the first battery and the ground terminal. The second equalization switch circuit is used to connect a second external equalization circuit and is connected with a positive electrode of the second battery and the ground terminal. The equalization control circuit is connected with the equalization enable circuit, a second voltage dividing node of the first voltage dividing circuit, the positive electrode of the first battery, the positive electrode of the second battery, the first equalization switch circuit and the second equalization switch circuit, and is used to enter an equalization control mode according to the enable control signal, receive a second voltage dividing voltage of the second voltage dividing node and a second battery voltage of the second battery, and control the first equalization switch circuit to work according to a first preset equalization difference, the second voltage dividing voltage and the second battery voltage, and control the second equalization switch circuit to work according to a second preset equalization difference, the second voltage dividing voltage and the second battery voltage.

[0005] Further, a voltage ratio of the first voltage division voltage to the second voltage division voltage is 1:4; and a voltage ratio of the second voltage division voltage to the first battery voltage of the first battery is 1:2.

[0006] Further, the equalization enabling circuit comprises a first comparator; A first input terminal of the first comparator is connected to the first voltage division node, a second input terminal of the first comparator is connected to the first reference terminal, and an output terminal of the first comparator is connected to the equalization control circuit.

[0007] Further, the equalization control circuit comprises two equalization bias circuits and two second comparators; the two equalization bias circuits are respectively configured to provide the first preset equalization difference and the second preset equalization difference; A first input terminal of each of the equalization bias circuits is connected to a positive electrode of the second battery, a second input terminal of each of the equalization bias circuits is connected to a positive electrode of the first battery, and a control terminal of each of the equalization bias circuits is configured to receive a bias control signal; First input terminals of the two second comparators are both connected to the second voltage division node, second input terminals of the two second comparators are respectively connected to output terminals of the two equalization bias circuits, output terminals of the two second comparators are respectively connected to the first equalization switch circuit and the second equalization switch circuit, and control terminals of the two second comparators are both connected to the equalization enabling circuit.

[0008] Further, the equalization bias circuit comprises a first switch tube, a second switch tube, a plurality of first resistors, and a plurality of fuses; The plurality of first resistors are connected in series between the positive electrode of the second battery and the second input terminal of the second comparator, and each of the first resistors is connected in parallel with one of the fuses. A first terminal of the first switch tube is connected to the positive electrode of the first battery, a second terminal of the first switch tube is connected to a first terminal of the second switch tube, a second terminal of the second switch tube is connected to the ground terminal, a connection node between the first switch tube and the second switch tube is connected to the second input terminal of the second comparator, a third terminal of the first switch tube is configured to receive a first bias control signal, and a third terminal of the second switch tube is configured to receive a second bias control signal.

[0009] Further, the first equalization switch circuit comprises a third switch tube, a fourth switch tube, and a fifth switch tube; The first end of the third switch is connected to the positive terminal of the first battery, the second end of the third switch is connected to the first end of the fourth switch, the second end of the fourth switch is connected to the first end of the fifth switch, and the second end of the fifth switch is connected to the ground terminal. The third terminal of the third switch is connected to the second terminal of the third switch, the third terminal of the fourth switch is used to receive the third bias control signal, and the third terminal of the fifth switch is connected to the equalization control circuit. The third and fifth switching transistors are enhancement-mode NMOS transistors; the fourth switching transistor is an enhancement-mode PMOS transistor.

[0010] Furthermore, the second equalization switch circuit includes a sixth switch transistor, a seventh switch transistor, and an equalization resistor; the first terminal of the sixth switch transistor is connected to the positive terminal of the second battery, the second terminal of the sixth switch transistor is connected to the first terminal of the seventh switch transistor through the equalization resistor, and the second terminal of the seventh switch transistor is connected to the ground terminal; the third terminals of the sixth switch transistor and the third terminal of the seventh switch transistor are connected together and connected to the equalization control circuit. The sixth switch is an enhancement-mode PMOS transistor; the seventh switch is an enhancement-mode NMOS transistor.

[0011] A battery protection chip includes a positive power supply pin, a negative power supply pin, a first equalization pin, a second equalization pin, a third equalization pin, and the aforementioned battery equalization circuit. The positive power supply pin is used to connect to the positive terminal of the first battery, the negative power supply pin is used to connect to the negative terminal of the second battery, the first equalization pin is used to connect to the first external equalization circuit connected in parallel with the first battery, the second equalization pin is used to connect to the negative terminal of the first battery and the positive terminal of the second battery, and the third equalization pin is used to connect to the second external equalization circuit connected in parallel with the second battery. The first terminal of the first voltage divider circuit is connected to the positive power supply pin, the first equalization switch circuit is connected to the first equalization pin, the second equalization switch circuit is connected to the second equalization pin and the third equalization pin, and the equalization control circuit is connected to the first equalization pin and the second equalization pin. When the first equalization switch circuit is turned on, the first external equalization circuit performs equalization control on the first battery; when the second equalization switch circuit is turned on, the second external equalization circuit performs equalization control on the second battery.

[0012] A battery protection board includes a substrate, a first external equalization circuit, a second external equalization circuit, and the aforementioned battery protection chip. The first external equalization circuit, the second external equalization circuit, and the battery protection chip are all disposed on the substrate. The first external equalization circuit is connected to the first equalization pin and is used to be connected in parallel with the first battery. The second external equalization circuit is connected to the third equalization pin and is used to connect in parallel with the second battery.

[0013] A battery protection system includes a first battery, a second battery, and the aforementioned battery protection board; The first battery and the second battery are connected in series; The battery protection board is connected to the first battery and the second battery.

[0014] This invention provides a battery balancing circuit, a battery protection chip, a protection board, and a protection system. The balancing control circuit enters a balancing control mode based on an enable control signal, receives the second voltage divider voltage from the second voltage divider node and the second battery voltage from the second battery, and controls the operation of the first balancing switch circuit based on a first preset balancing difference, the second voltage divider voltage, and the second battery voltage. Similarly, it controls the operation of the second balancing switch circuit based on a second preset balancing difference, the second voltage divider voltage, and the second battery voltage. This allows all detection and control logic to be integrated within the battery protection chip, eliminating the need for external discrete components for voltage judgment, significantly reducing external costs and board area. Furthermore, the adjustable first and second preset balancing differences enable precise calibration of the balancing start point before the battery protection chip leaves the factory, solving the accuracy dispersion problem caused by component tolerances in traditional solutions and improving the consistency and reliability of the battery protection chip. Attached Figure Description

[0015] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of a battery protection system in one embodiment of the present invention; Figure 2 This is a schematic diagram of a battery balancing circuit in one embodiment of the present invention; Figure 3 This is a schematic diagram of an equalization control circuit in one embodiment of the present invention; Figure 4 This is a schematic diagram of an equalization bias circuit in one embodiment of the present invention; Figure 5 This is another schematic diagram of the battery balancing circuit in one embodiment of the present invention; Figure 6 This is another schematic diagram of a battery protection system in one embodiment of the present invention.

[0017] In the diagram: 1. First external equalization circuit; 2. Second external equalization circuit; 3. Battery protection chip; 31. First voltage divider circuit; 32. Equalization enable circuit; 33. Equalization control circuit; 331. Two equalization bias circuits; 3311. Multiple first resistors; 3312. Multiple fuses; 332. Two second comparators; 34. First equalization switch circuit; 35. Second equalization switch circuit. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] It should be understood that the invention can be embodied in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0020] To fully understand this invention, detailed structures and steps will be presented in the following description to illustrate the technical solution proposed by this invention. Preferred embodiments of the invention are described in detail below; however, in addition to these detailed descriptions, the invention may have other embodiments.

[0021] like Figures 1 to 6As shown, this embodiment provides a battery balancing circuit for balancing a first battery BAT1 and a second battery BAT2 connected in series. The circuit includes a first voltage divider circuit 31, a balancing enable circuit 32, a balancing control circuit 33, a first balancing switch circuit 34, and a second balancing switch circuit 35. The first terminal of the first voltage divider circuit 31 is connected to the positive terminal of the first battery BAT1, and the second terminal of the first voltage divider circuit 31 is connected to the ground terminal GND. The balancing enable circuit 32 is connected to the first voltage divider node and the first reference terminal VREF of the first voltage divider circuit 31, and outputs an enable control signal when the first voltage divided by the first voltage divider node is greater than the first reference voltage provided by the first reference terminal VREF. The first balancing switch circuit 34 is connected to a first external balancing circuit 1 and the first battery BAT1. The positive terminal of the first battery BAT1 is connected to the ground terminal GND. The second equalization switch circuit 35 is used to connect the second external equalization circuit 2 and is connected to the positive terminal of the second battery BAT2 and the ground terminal GND. The equalization control circuit 33 is connected to the equalization enable circuit 32, the second voltage divider node of the first voltage divider circuit 31, the positive terminal of the first battery BAT1, the positive terminal of the second battery BAT2, the first equalization switch circuit 34 and the second equalization switch circuit 35. It is used to enter the equalization control mode according to the enable control signal, receive the second voltage divider voltage of the second voltage divider node and the second battery voltage of the second battery BAT2, and control the first equalization switch circuit 34 to work according to the first preset equalization difference, the second voltage divider voltage and the second battery voltage, and control the second equalization switch circuit 35 to work according to the second preset equalization difference, the second voltage divider voltage and the second battery voltage.

[0022] Among them, the first voltage divider node is as follows Figure 2 The 1 / 8VDD shown in the diagram has a second voltage divider node as follows: Figure 2 The 1 / 2VDD and BAL_EN shown are the output terminals of the equalization enable circuit 32.

[0023] For example, the battery balancing circuit is integrated into the battery protection chip 3. The first battery BAT1 and the second battery BAT2 can be lithium-ion batteries or sodium-ion batteries. The first external balancing circuit 1 is connected in parallel with the first battery BAT1 and is used to perform balancing control on the first battery BAT1 when it is turned on. The second external balancing circuit 2 is connected in parallel with the second battery BAT2 and is used to perform balancing control on the second battery BAT2 when it is turned on.

[0024] As an example, the first voltage divider circuit 31 includes multiple resistors connected in series and / or parallel to divide the voltage of the first battery. The first voltage divider node and the second voltage divider node are connection nodes between two adjacent resistors. Exemplarily, the first terminal of the first voltage divider circuit 31 is also connected to the positive terminal of the first battery BAT1 via an eighth switch. The control terminal V_CTRL of the eighth switch is used to receive start and stop signals to control the opening and closing of the battery equalization circuit. The control terminal of the eighth switch is connected to the logic control circuit inside the battery protection chip 3 to receive start and stop signals output by the logic control circuit. Exemplarily, the first voltage divider circuit 31 includes resistors R1 to R4.

[0025] As an example, the equalization enable circuit 32 is connected to the first voltage divider node and the first reference terminal VREF of the first voltage divider circuit 31. When the first voltage divider voltage provided by the first voltage divider node is greater than the first reference voltage provided by the first reference terminal VREF, it outputs an enable control signal to form a first voltage divider voltage based on the first battery voltage. This first voltage divider voltage is then compared with the first reference voltage. When the first voltage divider voltage is greater than the first reference voltage, it outputs an enable control signal to control the equalization control circuit 33 to perform battery equalization control. This reduces standby power consumption when the first voltage divider voltage is not greater than the first reference voltage, and also prevents false triggering when the first battery BAT1 is at a low voltage. Understandably, the magnitude of the first reference voltage can be set according to actual experience and requirements, and is not limited here.

[0026] As an example, when the equalization control circuit 33 receives the enable control signal, it is activated and enters the equalization control mode. It compares the second battery voltage with the second voltage divider voltage. In an ideal equalization state, the second battery voltage should equal the second voltage divider voltage. When there is a deviation between the second battery voltage and the second voltage divider voltage, it indicates that the voltages of the first battery BAT1 and the second battery BAT2 are inconsistent. To provide a judgment tolerance and achieve an adjustable function, the equalization control circuit 33 does not immediately act when the second battery voltage and the second voltage divider voltage are not equal. Instead, it introduces a first preset equalization difference and a second preset equalization difference. These first and second preset equalization differences are adjustable threshold values.

[0027] If the sum of the second battery voltage and the second preset equalization difference is less than the second voltage divider, it means that the second battery voltage is less than the ideal value, that is, less than the second voltage divider. The first battery voltage is too high, and the first battery BAT1 needs to be equalized. Then, the first equalization switch circuit 34 is turned on. The first equalization switch circuit 34 is connected to the positive terminal and ground terminal GND of the first battery BAT1. Thus, after the first equalization switch circuit 34 is turned on, a discharge path to ground is formed, and the first external equalization circuit 1 is turned on to discharge the first battery BAT1.

[0028] If the difference between the second battery voltage and the first preset equalization difference is greater than the second voltage divider voltage, it means that the second battery voltage is greater than the ideal value, that is, greater than the second voltage divider voltage. The second battery voltage is too high, and it is necessary to equalize the second battery BAT2. Then, the second equalization switch circuit 35 is turned on. The second equalization switch circuit 35 is connected to the positive terminal and ground terminal GND of the second battery BAT2. Thus, after the second equalization switch circuit 35 is turned on, a discharge path to ground is formed, and the second external equalization circuit 2 is turned on to discharge the second battery BAT2.

[0029] In this embodiment, the equalization control circuit 33 enters the equalization control mode according to the enable control signal, receives the second voltage divider voltage of the second voltage divider node and the second battery voltage of the second battery BAT2, and controls the first equalization switch circuit 34 to work according to the first preset equalization difference, the second voltage divider voltage and the second battery voltage, and controls the second equalization switch circuit 35 to work according to the second preset equalization difference, the second voltage divider voltage and the second battery voltage. This allows the detection and control logic to be fully integrated into the battery protection chip 3, eliminating the need for external discrete components for voltage judgment, significantly reducing external costs and circuit board area. At the same time, the adjustable first and second preset equalization differences enable precise calibration of the equalization start point before the battery protection chip 3 leaves the factory, solving the accuracy dispersion problem caused by component tolerances in traditional solutions, and improving the consistency and reliability of the battery protection chip 3.

[0030] In one embodiment, the voltage ratio of the first voltage divider to the second voltage divider is 1:4; the voltage ratio of the second voltage divider to the first battery voltage of the first battery BAT1 is 1:2.

[0031] This embodiment establishes a stable and symmetrical voltage detection reference by setting the ratio of the first voltage divider to the second voltage divider at 1:4, and the ratio of the second voltage divider to the first battery voltage at 1:2. The working principle is that, using the above ratios, the total voltage of the first battery BAT1 and the second battery BAT2 connected in series can be accurately converted into an intermediate reference voltage, namely the second voltage divider. Specifically, in an ideal balanced state, the voltages of the first and second batteries are equal, and the voltage of the second battery should be exactly equal to the reference point of the second voltage divider. Any deviation of the second battery voltage from the second voltage divider directly and linearly reflects the voltage difference between the first battery BAT1 and the second battery BAT2. Therefore, by directly comparing the second battery voltage with the second voltage divider, it is possible to accurately determine the battery with the higher voltage and the degree of the higher voltage in the first battery BAT1 and the second battery BAT2, thus laying the foundation for subsequent precise equalization control. Therefore, the above voltage division ratios not only simplify the circuit design but also ensure clear and reliable detection logic.

[0032] In one embodiment, the equalization enable circuit 32 includes a first comparator I0; the first input terminal of the first comparator I0 is connected to a first voltage divider node, the second input terminal of the first comparator I0 is connected to a first reference terminal VREF, and the output terminal of the first comparator I0 is connected to the equalization control circuit 33.

[0033] In this embodiment, the global enable judgment is realized through the first comparator I0. The first voltage divider voltage of the first voltage divider node is compared with the first reference voltage. Only when the total voltage of the battery protection system is high enough to meet the basic conditions for equalization operation, an effective enable control signal is output to the equalization control circuit 33. This effectively prevents the equalization function from being mistakenly activated when the battery voltage is too low. This not only reduces the system power consumption, but also avoids the risks that may be caused by equalization under abnormal conditions, thus improving the robustness of the system.

[0034] In one embodiment, the equalization control circuit 33 includes two equalization bias circuits 331 and two second comparators 332; the two equalization bias circuits 331 are respectively used to provide a first preset equalization difference and a second preset equalization difference; the first input terminal of each equalization bias circuit is connected to the positive terminal of the second battery BAT2, the second input terminal of each equalization bias circuit is connected to the positive terminal of the first battery BAT1, and the control terminal of each equalization bias circuit is used to receive a bias control signal; the first input terminals of both second comparators 332 are connected to a second voltage divider node, and the second input terminals of both second comparators 332 are respectively connected to the output terminal of an equalization bias circuit; the output terminals of both second comparators 332 are respectively used to connect to a first equalization switch circuit 34 and a second equalization switch circuit 35; the control terminals of both second comparators 332 are both connected to an equalization enable circuit 32. Figure 3 As shown, the outputs of the two second comparators are EN_BAL1 and EN_BAL2, respectively.

[0035] In this embodiment, when the control terminals of the two second comparators 332 receive an enable control signal, the two second comparators 332 begin to operate. The two second comparators 332 and the two equalization bias circuits 331 form two parallel detection channels. The equalization bias circuit in each detection channel, based on the received bias control signal, superimposes a direction-controllable and precisely adjustable offset voltage onto the second battery voltage. This offset voltage is the first or second preset equalization difference. The two second comparators 332 then use the second voltage divider voltage provided by the first voltage divider circuit 31 as a common reference voltage and compare it with the offset-processed second battery voltage. Specifically, one channel compares the second battery voltage minus the first preset equalization difference with the second voltage divider voltage to determine if the second battery voltage is too high; the other channel compares the second battery voltage plus the second preset equalization difference with the second voltage divider voltage to determine if the first battery voltage is too high. When any comparator detects that the condition is met, it outputs the corresponding equalization start signal to the first equalization switch circuit 34 or the second equalization switch circuit 35, thereby realizing accurate and rapid detection and independent control of the bidirectional voltage difference of the series battery pack, effectively improving the accuracy and response speed of equalization control.

[0036] In one embodiment, the equalization bias circuit includes a first switch Q1, a second switch Q2, a plurality of first resistors 3311, and a plurality of fuses 3312; the plurality of first resistors 3311 are connected in series between the positive terminal of the second battery BAT2 and the second input terminal of the second comparator, and each first resistor is connected in parallel with a fuse; the first terminal of the first switch Q1 is connected to the positive terminal of the first battery BAT1, the second terminal of the first switch Q1 is connected to the first terminal of the second switch Q2, and the second terminal of the second switch Q2 is connected to the ground terminal GND; the connection node between the first switch Q1 and the second switch Q2 is connected to the second input terminal of the second comparator; the third terminal of the first switch Q1 is used to receive a first bias control signal; the third terminal of the second switch Q2 is used to receive a second bias control signal.

[0037] As an example, the equalization bias circuit achieves a first preset equalization difference and a second preset equalization difference by generating a precisely adjustable offset voltage. Its operation is based on Ohm's law, using the voltage drop across the resistor network to control the voltage offset. The resistor network consists of multiple first resistors 3311, each with a fuse connected in parallel that short-circuits the corresponding first resistor when not blown. Exemplarily, the multiple first resistors 3311 are designed using a binary weighted approach. Exemplarily, the multiple first resistors 3311 include resistors R5 to R8; resistors R5 to R8 are short-circuited by fuses F1 to F4 respectively, and resistor R9 provides a reference resistance value. Initially, the minimum adjustment step value can be obtained by measuring the voltage drop across resistor R9; the resistance of resistor R8 is twice that of resistor R9, and the corresponding offset voltage is also twice that of resistor R9; the resistance and offset voltage of resistor R7 are twice that of resistor R8, and so on.

[0038] When the equalization bias circuit is working, the first bias control signal controls the conduction state of the first switch Q1, and the second bias control signal controls the conduction state of the second switch Q2, thereby determining the direction of the bias current. For example, when a first preset equalization difference is required, the first switch Q1 is turned on and the second switch Q2 is turned off, forming a current path from the positive terminal of the second battery BAT2 through the resistor network, the first switch Q1, and back to the positive terminal of the first battery BAT1. This current generates a voltage drop on the resistor network, making the voltage at the second input terminal of the second comparator the second battery voltage minus the first preset equalization difference. When a second preset equalization difference is required, the second switch Q2 is turned on and the first switch Q1 is turned off, forming a current path from the positive terminal of the second battery BAT2 through the resistor network, the second switch Q2, and back to the ground terminal GND. This current generates a voltage drop on the resistor network, making the voltage at the second input terminal of the second comparator the second battery current plus the second preset equalization difference. Optionally, the first and second bias control signals are generated by the logic control module inside the battery protection chip 3. The first switch Q1 is an enhancement-mode NMOS transistor, and the second switch Q2 is an enhancement-mode PMOS transistor. The drain of the first switch Q1 is connected to the positive terminal of the first battery BAT1, the source of the first switch Q1 is connected to the drain of the second switch Q2, and the source of the second switch Q2 is connected to the ground terminal GND.

[0039] During the manufacturing stage of the battery protection chip 3, the connected resistance value can be precisely adjusted by laser-fusing the corresponding fuse, thereby setting the specific values ​​of the first and second preset equalization differences. Through this binary weighted adjustment method, the required equalization start-up voltage difference can be accurately synthesized based on the minimum step value. This mechanism allows both equalization start-up thresholds to be independently and accurately calibrated during the manufacturing stage, achieving high product consistency and customization requirements.

[0040] In one embodiment, the first equalization switch circuit 34 includes a third switch Q3, a fourth switch Q4, and a fifth switch Q5; the first terminal of the third switch Q3 is connected to the positive terminal of the first battery BAT1, the second terminal of the third switch Q3 is connected to the first terminal of the fourth switch Q4, the second terminal of the fourth switch Q4 is connected to the first terminal of the fifth switch Q5, and the second terminal of the fifth switch Q5 is connected to the ground terminal GND; the third terminal of the third switch Q3 is connected to the second terminal of the third switch Q4, the third terminal of the fourth switch Q4 is used to receive a third bias control signal, and the third terminal of the fifth switch Q5 is connected to the equalization control circuit 33; the third switch Q3 and the fifth switch Q5 are enhancement-mode NMOS transistors; and the fourth switch Q4 is an enhancement-mode PMOS transistor.

[0041] As an example, the drain of the third switch Q3 is connected to the positive terminal of the first battery BAT1, the source of the third switch Q3 is connected to the drain of the fourth switch Q4, the source of the fourth switch Q4 is connected to the drain of the fifth switch Q5, and the source of the fifth switch Q5 is connected to the ground terminal GND; the gate of the third switch Q3 is connected to the source of the third switch Q3, the gate of the fourth switch Q4 is used to receive the third bias control signal, and the gate of the fifth switch Q5 is connected to the equalization control circuit 33.

[0042] In this embodiment, the first equalization switch circuit 34 acts as a high-side switch. The diode connection of the third switch transistor Q3 provides it with a stable self-bias voltage. When the equalization control circuit 33 outputs an effective equalization control signal to the gate of the fifth switch transistor Q5, Q5 is turned on first, and then a complete conduction path is established through the gate bias control of the fourth switch transistor Q4. The phased turn-on method ensures the reliability of the switching process and effectively avoids the generation of shoot-through current. When the first equalization switch circuit 34 is fully turned on, a low-level signal is generated at the first equalization pin BAL1 of the battery protection chip 3. This low-level signal directly drives the first external equalization circuit 1 connected to the first equalization pin BAL1, thereby constructing a discharge circuit for the first battery BAT1. The first external equalization circuit 1 is connected in parallel with the first battery BAT1 to achieve discharge equalization of the first battery BAT1, which not only provides a stable bias but also ensures the reliability and efficiency of the switch control.

[0043] In one embodiment, the second equalization switch circuit 35 includes a sixth switch Q6, a seventh switch Q7, and an equalization resistor; the first terminal of the sixth switch Q6 is connected to the positive terminal of the second battery BAT2, the second terminal of the sixth switch Q6 is connected to the first terminal of the seventh switch Q7 through the equalization resistor, and the second terminal of the seventh switch Q7 is connected to the ground terminal GND; the third terminals of the sixth switch Q6 and the seventh switch Q7 are connected together and connected to the equalization control circuit 33; the sixth switch Q6 is an enhancement-mode PMOS transistor; and the seventh switch Q7 is an enhancement-mode NMOS transistor.

[0044] As an example, the drain of the sixth switch Q6 is connected to the positive terminal of the second battery BAT2, the source of the sixth switch Q6 is connected to the drain of the seventh switch Q7 through an equalization resistor, and the source of the seventh switch Q7 is connected to the ground terminal GND; the gates of the sixth switch Q6 and the seventh switch Q7 are connected together and connected to the equalization control circuit 33.

[0045] In this embodiment, the second equalization switch circuit 35 employs a complementary symmetrical design to achieve low-side switching functionality. It switches between on and off states by simultaneously controlling the gate voltages of the sixth switch Q6 and the seventh switch Q7. When the equalization control circuit 33 outputs a valid equalization control signal, the sixth switch Q6 and the seventh switch Q7 conduct synchronously, forming a complete discharge loop from the positive terminal of the second battery BAT2 through the equalization resistor to ground. The equalization resistor acts as a current limiter during this process, ensuring stable system operation by controlling the equalization current within a safe range. This connection relationship makes the switching action faster and more reliable, while ensuring good linearity of the on-resistance. Precise timing coordination achieves safe equalization control of the second battery BAT2.

[0046] This embodiment provides a battery protection chip 3, including a positive power supply pin VDD, a negative power supply pin VSS, a first balancing pin BAL1, a second balancing pin VC, a third balancing pin BAL2, and the aforementioned battery balancing circuit. The positive power supply pin VDD is used to connect to the positive terminal of the first battery BAT1, the negative power supply pin VSS is used to connect to the negative terminal of the second battery BAT2, the first balancing pin BAL1 is used to connect to the first external balancing circuit 1 connected in parallel with the first battery BAT1, the second balancing pin VC is used to connect to the negative terminal of the first battery BAT1 and the positive terminal of the second battery BAT2, and the third balancing pin BAL2 is used to connect to the first external balancing circuit 1 connected in parallel with the first battery BAT1. The first external equalization circuit 2 is connected in parallel with the second battery BAT2; the first terminal of the first voltage divider circuit 31 is connected to the positive power supply pin VDD; the first equalization switch circuit 34 is connected to the first equalization pin BAL1; the second equalization switch circuit 35 is connected to the second equalization pin VC and the third equalization pin BAL2; the equalization control circuit 33 is connected to the first equalization pin and the second equalization pin VC; when the first equalization switch circuit 34 is turned on, the first external equalization circuit 1 performs equalization control on the first battery BAT1; when the second equalization switch circuit 35 is turned on, the second external equalization circuit 2 performs equalization control on the second battery BAT2.

[0047] This embodiment provides a battery protection board, including a substrate (not shown in the figure), a first external equalization circuit 1, a second external equalization circuit 2, and the aforementioned battery protection chip 3; the first external equalization circuit 1, the second external equalization circuit 2, and the battery protection chip 3 are all disposed on the substrate; the first external equalization circuit 1 is connected to the first equalization pin BAL1 and is used to connect in parallel with the first battery BAT1; the second external equalization circuit 2 is connected to the third equalization pin BAL2 and is used to connect in parallel with the second battery BAT2.

[0048] For example, the power supply pin of the battery protection chip 3 is connected to the positive terminal of the first battery BAT1 through a first filter circuit formed by resistor R1 and capacitor C1. The second equalization pin VC is connected to the positive terminal of the second battery BAT2 through a first filter circuit formed by resistor R2 and capacitor C2.

[0049] For example, the first external equalization circuit 1 includes a first transistor and a resistor RC1 connected in series. The second external equalization circuit 2 includes a second transistor and a resistor RC2 connected in series.

[0050] When the internal first equalization switch circuit 34 or the second equalization switch circuit 35 is turned on, the potential of the first equalization pin BAL1 or the third equalization pin BAL2 is pulled low. The pulled-low signal turns on the first transistor in the first external equalization circuit 1 or the second transistor in the second external equalization circuit 2, thereby equalizing the discharge of the first battery BAT1 or the second battery BAT2. This process continues until the voltage of the first battery BAT1 or the second battery BAT2 is consistent, greatly simplifying peripheral applications.

[0051] This embodiment provides a battery protection system, including a first battery BAT1, a second battery BAT2, and the aforementioned battery protection board; the first battery BAT1 and the second battery BAT2 are connected in series; the battery protection board is connected to the first battery BAT1 and the second battery BAT2.

[0052] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A battery balancing circuit for balancing a first battery and a second battery connected in series, characterized in that, It includes a first voltage divider circuit, an equalization enable circuit, an equalization control circuit, a first equalization switch circuit, and a second equalization switch circuit. The first terminal of the first voltage divider circuit is connected to the positive terminal of the first battery, and the second terminal of the first voltage divider circuit is connected to the ground terminal. The equalization enable circuit is connected to the first voltage divider node and the first reference terminal of the first voltage divider circuit, and is used to output an enable control signal when the first voltage divider voltage provided by the first voltage divider node is greater than the first reference voltage provided by the first reference terminal. The first equalization switch circuit is used to connect to the first external equalization circuit and is connected to the positive terminal of the first battery and the ground terminal. The second equalization switch circuit is used to connect to the second external equalization circuit and is connected to the positive terminal of the second battery and the ground terminal. The equalization control circuit is connected to the equalization enable circuit, the second voltage divider node of the first voltage divider circuit, the positive terminal of the first battery, the positive terminal of the second battery, the first equalization switch circuit, and the second equalization switch circuit. It is used to enter the equalization control mode according to the enable control signal, receive the second voltage divider voltage of the second voltage divider node and the second battery voltage of the second battery, and control the first equalization switch circuit to work according to the first preset equalization difference, the second voltage divider voltage, and the second battery voltage, and control the second equalization switch circuit to work according to the second preset equalization difference, the second voltage divider voltage, and the second battery voltage.

2. The battery balancing circuit according to claim 1, characterized in that, The voltage ratio of the first voltage divider to the second voltage divider is 1:4; the voltage ratio of the second voltage divider to the first battery voltage of the first battery is 1:

2.

3. The battery balancing circuit according to claim 1, characterized in that, The equalization enable circuit includes a first comparator; The first input terminal of the first comparator is connected to the first voltage divider node, the second input terminal of the first comparator is connected to the first reference terminal, and the output terminal of the first comparator is connected to the equalization control circuit.

4. The battery balancing circuit according to claim 1, characterized in that, The equalization control circuit includes two equalization bias circuits and two second comparators; the two equalization bias circuits are respectively used to provide the first preset equalization difference and the second preset equalization difference; The first input terminal of each of the equalization bias circuits is connected to the positive terminal of the second battery, the second input terminal of each of the equalization bias circuits is connected to the positive terminal of the first battery, and the control terminal of each of the equalization bias circuits is used to receive a bias control signal. The first input terminals of the two second comparators are both connected to the second voltage divider node, and the second input terminals of the two second comparators are respectively connected to the output terminal of the equalization bias circuit; the output terminals of the two second comparators are respectively used to connect the first equalization switch circuit and the second equalization switch circuit. The control terminals of both second comparators are connected to the equalization enable circuit.

5. The battery balancing circuit according to claim 4, characterized in that, The equalization bias circuit includes a first switching transistor, a second switching transistor, multiple first resistors, and multiple fuses; Multiple first resistors are connected in series between the positive terminal of the second battery and the second input terminal of the second comparator, and each first resistor is connected in parallel with a fuse. The first terminal of the first switch is connected to the positive terminal of the first battery, the second terminal of the first switch is connected to the first terminal of the second switch, and the second terminal of the second switch is connected to the ground terminal; the connection node between the first switch and the second switch is connected to the second input terminal of the second comparator; the third terminal of the first switch is used to receive a first bias control signal; and the third terminal of the second switch is used to receive a second bias control signal.

6. The battery balancing circuit according to claim 1, characterized in that, The first equalization switching circuit includes a third switch, a fourth switch, and a fifth switch; The first end of the third switch is connected to the positive terminal of the first battery, the second end of the third switch is connected to the first end of the fourth switch, the second end of the fourth switch is connected to the first end of the fifth switch, and the second end of the fifth switch is connected to the ground terminal. The third terminal of the third switch is connected to the second terminal of the third switch, the third terminal of the fourth switch is used to receive the third bias control signal, and the third terminal of the fifth switch is connected to the equalization control circuit. The third and fifth switching transistors are enhancement-mode NMOS transistors; the fourth switching transistor is an enhancement-mode PMOS transistor.

7. The battery balancing circuit according to claim 1, characterized in that, The second equalization switch circuit includes a sixth switch transistor, a seventh switch transistor, and an equalization resistor; the first terminal of the sixth switch transistor is connected to the positive terminal of the second battery, the second terminal of the sixth switch transistor is connected to the first terminal of the seventh switch transistor through the equalization resistor, and the second terminal of the seventh switch transistor is connected to the ground terminal; the third terminals of the sixth switch transistor and the third terminal of the seventh switch transistor are connected together and connected to the equalization control circuit. The sixth switch is an enhancement-mode PMOS transistor; the seventh switch is an enhancement-mode NMOS transistor.

8. A battery protection chip, characterized in that, It includes a power positive pin, a power negative pin, a first equalization pin, a second equalization pin, a third equalization pin, and a battery equalization circuit as described in any one of claims 1 to 7; The positive power supply pin is used to connect to the positive terminal of the first battery, the negative power supply pin is used to connect to the negative terminal of the second battery, the first equalization pin is used to connect to the first external equalization circuit connected in parallel with the first battery, the second equalization pin is used to connect to the negative terminal of the first battery and the positive terminal of the second battery, and the third equalization pin is used to connect to the second external equalization circuit connected in parallel with the second battery. The first terminal of the first voltage divider circuit is connected to the positive power supply pin, the first equalization switch circuit is connected to the first equalization pin, the second equalization switch circuit is connected to the second equalization pin and the third equalization pin, and the equalization control circuit is connected to the first equalization pin and the second equalization pin. When the first equalization switch circuit is turned on, the first external equalization circuit performs equalization control on the first battery; when the second equalization switch circuit is turned on, the second external equalization circuit performs equalization control on the second battery.

9. A battery protection board, characterized in that, It includes a substrate, a first external equalization circuit, a second external equalization circuit, and the battery protection chip as described in claim 8; The first external equalization circuit, the second external equalization circuit, and the battery protection chip are all disposed on the substrate. The first external equalization circuit is connected to the first equalization pin and is used to be connected in parallel with the first battery. The second external equalization circuit is connected to the third equalization pin and is used to connect in parallel with the second battery.

10. A battery protection system, characterized in that, Includes a first battery, a second battery, and the battery protection board as described in claim 9; The first battery and the second battery are connected in series; The battery protection board is connected to the first battery and the second battery.

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