Digital attenuator and radio frequency front-end system, design method

Abstract

The digital attenuator and the radio frequency front-end system and the design method provided by the application, the digital attenuator is mentioned, different structure forms of attenuation units are adopted for different attenuation interval, the influence of parasitic effect on wideband performance is reduced while realizing wide attenuation adjustment range and fine attenuation step coexist, the cascade order of the attenuation unit is optimized, and the interstage network is introduced between part of the attenuation units, the consistency of the equivalent impedance of the digital attenuator under different attenuation states is effectively improved, so that the input and output matching requirements can be met in the whole attenuation range, the relative phase change between different attenuation states is reduced by introducing the phase compensation structure in the attenuation branch, and the consistency of the signal in the wideband radio frequency system under multiple attenuation states is improved; the structure of the digital attenuator has good scalability and process adaptability, and is suitable for wideband radio frequency front-end system under advanced CMOS process condition.

Description

Technical Field

[0001] This application relates to the field of radio frequency integrated circuit technology, and in particular to digital attenuators and radio frequency front-end systems and design methods. Background Technology

[0002] With the rapid development of high-speed communication systems and broadband RF front-end technologies, digital attenuators are widely used in amplitude control and dynamic range management of RF front-ends due to their stable structure, simple control, and ease of fine gain adjustment. Common topologies include distributed structures, switch-path structures, and switch-embedded structures. Among these, the switch-embedded structure has certain advantages in broadband RF applications because it helps reduce parasitic effects and maintain a compact structure. However, as digital attenuators are gradually implemented using advanced CMOS processes such as 28nm, the reduction in device size makes parasitic capacitance, parasitic resistance, and interconnect parasitic effects increasingly significant under high-frequency broadband conditions. At the same time, limitations in the manufacturing process lead to insufficient voltage swing and narrowing of the device's operating range, making the equivalent electrical characteristics of the attenuation network prone to fluctuations under different operating conditions, posing a challenge to optimizing the broadband performance of digital attenuators.

[0003] In existing technologies, digital attenuators face three major technical challenges: First, the coordinated design of a wide attenuation adjustment range and fine attenuation steps is difficult, and the differences in the structure and parasitic effects of different attenuation units can seriously affect attenuation accuracy, insertion loss, and echo characteristics. Second, under different attenuation states, the equivalent transmission path and impedance distribution of the attenuation network are different, which can easily introduce additional phase changes, and the phase error will accumulate after multiple stages are cascaded, destroying signal consistency. Third, the cascading of multiple attenuation units results in different equivalent input and output impedance characteristics of the digital attenuator under different attenuation states, making it difficult to meet the input and output matching requirements across the entire attenuation range. Summary of the Invention

[0004] The technical problems to be solved in this application are three major technical challenges faced by digital attenuators: First, the coordinated design of a wide attenuation adjustment range and fine attenuation steps is difficult, and the differences in the structure and parasitic effects of different attenuation units will seriously affect the attenuation accuracy, insertion loss and echo characteristics; Second, under different attenuation states, the equivalent transmission path and impedance distribution of the attenuation network are different, which can easily introduce additional phase changes, and the phase error will accumulate after multi-stage cascading, destroying signal consistency; Third, the cascading of multi-stage attenuation units results in different equivalent input and output impedance characteristics of the digital attenuator under different attenuation states, making it difficult to meet the input and output matching requirements across the entire attenuation range.

[0005] To address the aforementioned problems, or at least partially address the aforementioned technical issues, this application provides a digital attenuator and RF front-end system, and a design method.

[0006] In a first aspect, the present invention discloses a digital attenuator, which includes a differential input terminal, a differential output terminal, an input cascaded inductor group, multiple attenuation unit components, multiple small attenuation components, and an output cascaded inductor group. The input cascaded inductor group is connected to the attenuation unit components or the small attenuation components, and the output cascaded inductor group is connected to the attenuation unit components or the small attenuation components. The attenuation unit components and the small attenuation components are arranged at intervals. The input cascaded inductor group, multiple attenuation unit components, multiple small attenuation components, and the output cascaded inductor group are arranged in a differential structure. The differential signal is input at the differential input terminal, passes through the input cascaded inductor group, multiple attenuation unit components, multiple small attenuation components and the output cascaded inductor group, and is output from the differential output terminal as a processed differential signal.

[0007] Preferably, the attenuation unit assembly is divided into medium attenuation unit and large attenuation unit according to the attenuation amount.

[0008] Preferably, the large attenuation unit adopts a Π-type attenuation structure.

[0009] Preferably, the intermediate attenuation unit adopts a T-shaped attenuation structure.

[0010] Preferably, the small attenuation component includes a small attenuation unit and an inductor group, and the small attenuation unit and the inductor group are connected.

[0011] Preferably, the small attenuation unit adopts a simplified T-type attenuation structure.

[0012] Secondly, the present invention discloses an radio frequency front-end system, which includes the aforementioned digital attenuator.

[0013] Thirdly, this invention discloses a design method for a radio frequency front-end system, used in the aforementioned radio frequency front-end system, comprising, Obtain the attenuation requirements of several attenuation units and attenuators with different attenuation values. The attenuation requirements include the total attenuation adjustment range and the attenuation step accuracy. Based on the attenuation requirements of the RF front-end system and the structural characteristics of each attenuation unit, the cascading order of the attenuation units is determined to obtain a digital attenuator. In this attenuator, the attenuation unit with large attenuation is set in the middle of the attenuation network, and attenuation units with medium or small attenuation are set on both sides of the attenuation unit along the signal transmission direction. A corresponding cascading network is configured between adjacent attenuation units. The radio frequency front-end system is constructed based on the digital attenuator, and the radio frequency front-end system is obtained.

[0014] Preferably, the following steps are then included: Configure different attenuation states, input signals and run the RF front-end system to verify the transmission characteristics of the RF front-end system and its digital attenuators.

[0015] Preferably, the cascading order of the attenuation units is determined based on the attenuation requirements of the attenuator and the structural characteristics of each attenuation unit to obtain a digital attenuator, specifically including the following steps: Acquire the requirements data of the RF front-end system for amplitude control and dynamic range, analyze and refine these requirements data, clarify the total attenuation adjustment range and attenuation step accuracy of the digital attenuator, and obtain the core design parameters of the digital attenuator. Data on the implementation difficulty of different attenuation ranges, structural characteristics of Π-type, T-type, and simplified T-type attenuation units, and attenuation adaptability data are obtained. These data are classified and matched, and attenuation units are grouped according to attenuation size. Corresponding attenuation unit structural forms are matched for different attenuation ranges to obtain attenuation unit grouping schemes and attenuation unit structural types for each group. Initial data is obtained, including attenuation theoretical parameters, system characteristic impedance data, and on-resistance and parasitic capacitance model data of switching devices. The initial data is then used for calculation, design, and verification. The resistance value of each attenuation unit is calculated based on the passive impedance matching attenuation network theory. The size of the switching transistor is designed by combining the parasitic parameter suppression theory and the insertion loss optimization theory. S-parameter verification is then carried out on a single attenuation unit to obtain the resistance value parameters of each attenuation unit, the size parameters of the switching transistor, and the performance verification report of a single attenuation unit. The structural characteristic data of each attenuation unit is obtained. The structural characteristic data includes the equivalent input impedance, equivalent output impedance, parasitic capacitance distribution, phase delay and frequency correlation data under different attenuation states. The structural characteristic data is analyzed and optimized. The optimal cascading sequence is determined according to the structural characteristics of the attenuation unit. At the same time, the corresponding cascading network is configured for the connection requirements of different types of attenuation units, and the attenuation unit cascading sequence scheme and the inductance and other parameter configuration scheme of the cascading network are obtained. A digital attenuator is constructed by combining all the data obtained above.

[0016] The technical solution provided in this application has the following advantages compared with the prior art: This application provides a digital attenuator and RF front-end system, as well as a design method. The digital attenuator, by employing attenuation units with different structural forms for different attenuation ranges, achieves both a wide attenuation adjustment range and fine attenuation steps while reducing the impact of parasitic effects on broadband performance. By optimizing the cascading sequence of attenuation units and introducing inter-stage networks between some attenuation units, the equivalent impedance consistency of the digital attenuator under different attenuation states is effectively improved, ensuring that it meets input-output matching requirements across the entire attenuation range. Furthermore, by introducing a phase compensation structure in the attenuation branch, the relative phase change between different attenuation states is reduced, improving the signal consistency in broadband RF systems under multiple attenuation states. The digital attenuator structure of this invention has good scalability and process adaptability, making it suitable for broadband RF front-end systems under advanced CMOS process conditions.

[0017] The method involves first obtaining attenuation requirements such as the total attenuation range and step accuracy of attenuation units and attenuators with different attenuation levels. Then, combining the attenuation requirements of the RF front-end system with the structural characteristics of each attenuation unit, the cascading order of the attenuation units is determined. The large attenuation unit is placed in the middle of the attenuation network, with medium and small attenuation units arranged sequentially on both sides along the signal transmission direction. Corresponding cascading networks are configured between adjacent attenuation units to construct a digital attenuator. Finally, the overall construction of the RF front-end system is completed based on this digital attenuator. The transmission characteristics of the system and the digital attenuator can also be verified by configuring the system under different attenuation states and input signals. The process of determining the cascading order to construct the digital attenuator requires multiple precise design steps, including demand analysis to refine design indicators, matching unit structure forms according to attenuation levels, designing unit parameters based on attenuation theory and performing single-unit verification, and analyzing unit structural characteristics to optimize cascading and network configuration. This method integrates the structural characteristics of attenuation units with the requirements of the RF front-end system throughout the entire process, from demand-side design to unit design and cascade optimization. This ensures a high degree of compatibility between the digital attenuator and the RF front-end system. The cascade design principle with the large attenuation unit in the center effectively reduces impedance disturbances and improves the overall matching performance of the system. The multi-step verification process ensures design accuracy from the unit to the system level, allowing the final RF front-end system to fully leverage the performance advantages of the digital attenuator and achieve comprehensive optimization of attenuation adjustment, phase consistency, and input-output matching. Furthermore, the design method is standardized, replicable, and adaptable to the design requirements of RF front-end systems in different broadband RF application scenarios. Attached Figure Description

[0018] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This application provides a schematic diagram of the overall structure of a digital attenuator; Figure 2 A schematic diagram of the cascading sequence and cascading network configuration of multiple attenuation units in a digital attenuator provided in this application; Figure 3 A schematic diagram of the half-circuit structure of the attenuation unit corresponding to different attenuation amounts in a digital attenuator provided in this application; Figure 4 This application provides an equivalent circuit diagram of a T-type attenuation unit in a digital attenuator under reference and attenuation states. Figure 5 A detailed flowchart of a design method for an RF front-end system provided in this application; Figure 6 The detailed flowchart of step S2 of the design method of the radio frequency front-end system provided in this application.

[0021] Explanation of reference numerals in the attached figures: 1. Digital attenuator; 11. Differential input terminal; 12. Differential output terminal; 13. Input cascaded inductor group; 14. Attenuation unit assembly; 141. Medium attenuation unit; 142. Large attenuation unit; 15. Small attenuation component; 151. Small attenuation unit; 152. Inductor group; 16. Output cascaded inductor group. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0023] Firstly, see Figures 1-4This invention discloses a digital attenuator 1, which includes a differential input terminal 11, a differential output terminal 12, an input cascaded inductor group 13, multiple attenuation unit components 14, multiple small attenuation components 15, and an output cascaded inductor group 16. The input cascaded inductor group 13 is connected to either the attenuation unit component 14 or the small attenuation component 15, and the output cascaded inductor group 16 is also connected to either the attenuation unit component 14 or the small attenuation component 15. The attenuation unit component 14 and the small attenuation component 15 are spaced apart. The input cascaded inductor group 13, the multiple attenuation unit components 14, the multiple small attenuation components 15, and the output cascaded inductor group 16 are arranged in a differential structure. A differential signal is input to the differential input terminal 11, and after passing through the input cascaded inductor group 13, the multiple attenuation unit components 14, the multiple small attenuation components 15, and the output cascaded inductor group 16, the processed differential signal is output from the differential output terminal 12.

[0024] Specifically, the digital attenuator 1 adopts a fully differential architecture design. Its core components include a differential input terminal 11, a differential output terminal 12, an input cascaded inductor group 13, multiple attenuation unit components 14, multiple small attenuation components 15, and an output cascaded inductor group 16. The connection and layout of each component follow fixed rules. The input cascaded inductor group 13 is connected to the attenuation unit component 14 or the small attenuation component 15 as needed. Similarly, the output cascaded inductor group 16 is adapted to connect to the attenuation unit component 14 or the small attenuation component 15. The attenuation unit component 14 and the small attenuation component 15 are arranged in an alternating manner. The input cascaded inductor group 13, all attenuation unit components 14, small attenuation components 15, and output cascaded inductor group 16 are all configured in a differential structure. The signal transmission path is that the differential signal input at the differential input terminal 11 passes through the input cascaded inductor group 13, each attenuation unit component 14, each small attenuation component 15, and the output cascaded inductor group 16 in sequence, and then the processed differential signal is output from the differential output terminal 12. The fully differential structure effectively suppresses common-mode interference at the architectural level, improving the consistency and anti-interference capability of signal transmission under broadband conditions, and adapting to the RF application requirements of advanced CMOS technology. The attenuation unit component 14 and the small attenuation component 15 are arranged alternately, and combined with the flexible connection of the input and output cascaded inductor group 16, the layout of the attenuation network is more reasonable, which can realize the step-by-step precise control of large, medium and small attenuation, taking into account both wide attenuation range and fine step requirements. All core components are set according to the differential structure to ensure the symmetry of differential signal transmission and avoid signal imbalance that introduces additional loss and distortion. The modular component design makes the attenuator structure more compact, which is easy to integrate into the RF front-end system. Moreover, the cooperation between the cascaded inductor group 152 and the attenuation component optimizes the overall input and output matching performance of the attenuator, reduces reflection loss during signal transmission, and improves the overall transmission efficiency of the attenuator.

[0025] The attenuation unit component 14 is divided into a medium attenuation unit 141 and a large attenuation unit 142 according to the attenuation amount. The large attenuation unit 142 adopts a Π-type attenuation structure, and the medium attenuation unit 141 adopts a T-type attenuation structure.

[0026] Specifically, the attenuation unit component 14 is divided into two categories according to the attenuation amount: medium attenuation unit 141 and large attenuation unit 142. Both adopt a switch-embedded passive resistor attenuation network architecture, and both integrate a core resistor network, CMOS switching transistor, and phase compensation capacitor. The differential positive / inverting paths of each unit are symmetrically configured with the same resistor network and devices to ensure the symmetry of differential signal transmission. At the same time, connection terminals are reserved for connection with cascaded inductor group 152 and other attenuation / small attenuation components 15 to realize modular cascading.

[0027] The large attenuation unit 142 includes two symmetrical series resistors, one parallel resistor, a CMOS switching transistor (including a direct-path switch and a resistor branch switch), and a phase compensation capacitor. Each of the differential positive and negative paths is independently configured with a complete Π-type resistor network and supporting components. The two series resistors are connected in series along the single-path signal transmission direction, and the parallel resistor is connected between the connection node of the two series resistors and ground, forming a classic Π-type passive attenuation network. The CMOS switching transistor is embedded in the Π-type resistor branch and the direct-path signal branch, respectively. The phase compensation capacitor is connected in parallel across the parallel resistor. The differential dual-path Π-type network is completely symmetrical and is integrated into the differential link of the attenuator. The switching between the reference state (direct-path on, resistor branch off) and the attenuation state (resistor branch on, direct-path off) is achieved by switching the switches on and off. The impedance characteristics of the Π-type network are used to achieve precise control of the large attenuation.

[0028] The intermediate attenuation unit 141 includes a central series resistor, two symmetrical parallel resistors, a CMOS switching transistor (including a direct-path switch and a resistor branch switch), and a phase compensation capacitor. The differential positive and negative paths are also independently configured with a complete set of T-type resistor networks and supporting devices. The central series resistor is connected in series to the single-path signal main transmission link. The two parallel resistors are respectively connected between the input node and output node of the central series resistor and ground, forming a standard T-type passive attenuation network. The CMOS switching transistor is embedded in the T-type resistor branch and the signal direct-path branch. The phase compensation capacitor is connected in parallel across the central series resistor. The T-type network of the differential dual path is strictly symmetrical and modularly connected to the differential link of the attenuator. The reference state and attenuation state are switched by switching on and off. The impedance matching characteristics of the T-type network are used to achieve precise control of the intermediate attenuation. At the same time, a connection interface with the cascaded inductor is reserved to adapt to the impedance transition of adjacent components.

[0029] The small attenuation component 15 includes a small attenuation unit 151 and an inductor group 152. The small attenuation unit 151 is connected to the inductor group 152. The small attenuation unit 151 adopts a simplified T-type attenuation structure.

[0030] Specifically, the small attenuation component 15 includes a small attenuation unit 151 and an inductor group 152. The overall design follows a differential symmetrical design. Each of the differential positive and negative paths is equipped with an identical small attenuation unit 151 and inductor group 152. The two parts are fixedly connected through a preset interface to jointly realize small-step attenuation control and cascaded impedance matching. At the same time, connection terminals are reserved for input / output cascaded inductor group 16 and other attenuation unit components 14 to ensure smooth connection between the component and the overall link of the attenuator.

[0031] Among them, the small attenuation unit 151 adopts a simplified T-type passive attenuation network design to adapt to the small step attenuation requirements. It includes one series resistor, one parallel resistor, two CMOS switching transistors (corresponding to the resistor branch and the direct connection branch respectively), and one phase compensation capacitor (configured as needed to suppress high-frequency parasitic phase shift). Each differential dual path is symmetrically configured with one set of the above components. The simplified T-network retains the core branches of the T-structure. A series resistor is directly connected in series with the main transmission link of the single-path signal, serving as the core control element for small attenuation. One end of a parallel resistor is connected to the middle node of the series resistor, and the other end is grounded, forming the basic architecture of the simplified T-type attenuation network. CMOS switching transistors are embedded in the resistor branches (series resistor + parallel resistor branch) and the direct signal connection branch, respectively, to switch between the attenuation state and the reference state. In the attenuation state, the resistor branch switch is on, and the direct connection branch switch is off, allowing the signal to attenuate in small steps through the simplified T-type resistor network. In the reference state, the direct connection branch switch is on, and the resistor branch switch is off, allowing direct signal transmission and reducing insertion loss. A phase compensation capacitor is connected in parallel across the series resistor to compensate for parasitic phase distortion at high frequencies. The simplified T-network of the differential dual-path is completely symmetrical, ensuring unbalanced differential signal transmission and avoiding the introduction of additional common-mode interference. Inductor group 152 is the impedance matching auxiliary part of small attenuation component 15. Its core function is to optimize the impedance transition between small attenuation unit 151 and adjacent components (other attenuation units, input / output cascaded inductor group 16), and suppress parasitic reflections. One end of a single inductor is fixedly connected to the output terminal of small attenuation unit 151 of the corresponding path, and the other end serves as the external connection terminal of small attenuation component 15 for connecting other components. The two differential inductors and matching resistors of inductor group 152 are symmetrically arranged, consistent with the differential structure of small attenuation unit 151, to ensure the symmetry of differential signal transmission of the entire small attenuation component 15. At the same time, through the filtering and impedance adjustment of the inductors, the attenuation accuracy and signal transmission stability of small attenuation unit 151 are further optimized.

[0032] The digital attenuator 1 disclosed in this invention adopts a fully differential structure design. It consists of a differential input terminal 11, a differential output terminal 12, an input cascaded inductor group 13, multiple attenuation unit components 14, multiple small attenuation components 15, and an output cascaded inductor group 16. The input and output cascaded inductor groups 16 are connected to the attenuation unit components 14 or the small attenuation components 15 as needed, and the attenuation unit components 14 and the small attenuation components 15 are arranged alternately. All core components follow the differential structure. The attenuation unit components 14 are divided into medium and large attenuation units 142. The large attenuation unit 142 adopts a Π-type attenuation structure, and the medium attenuation unit 141 adopts a T-type attenuation structure. The small attenuation components 15 are composed of a small attenuation unit 151 with a simplified T-type attenuation structure connected to the inductor group 152. After the differential signal is input from the input terminal, it is processed sequentially by the input cascaded inductor group 13, various attenuation components, and the output cascaded inductor group 16 before being output from the differential output terminal 12. It is understandable that the digital attenuator 1 adopts a fully differential structure, which can effectively suppress common-mode interference and improve the consistency of broadband signal transmission. The Π-type, T-type, and simplified T-type structures adapted according to the attenuation amount take into account the accuracy of different attenuation amounts and the control of parasitic effects. The attenuation unit component 14 and the small attenuation component 15 are arranged at intervals and matched with a dedicated cascaded inductor group 152, which optimizes the impedance matching between different attenuation units. The small attenuation component 15 integrates the inductor group 152 to further improve the stability of small step attenuation. The overall structure realizes the synergistic optimization of wide attenuation range, fine step and full-band matching performance, and is suitable for broadband RF applications of advanced CMOS technology.

[0033] Furthermore, a multi-stage programmable attenuator is achieved under broadband conditions, combining a wide attenuation adjustment range with fine attenuation adjustment steps. This simultaneously reduces the impact of different attenuation unit structures and their parasitic effects on attenuation accuracy and transmission characteristics. The relative phase change introduced by digital attenuator 1 under different attenuation states is reduced, improving signal consistency across these states to meet the phase stability requirements of broadband RF systems. With cascaded multi-stage attenuator units, through reasonable structural configuration and network design, digital attenuator 1 can maintain input-output matching performance across the entire attenuation range, enhancing system stability and availability under broadband conditions.

[0034] Secondly, the present invention discloses a radio frequency (RF) front-end system, which includes the aforementioned digital attenuator 1. The RF front-end system integrates the aforementioned digital attenuator 1, incorporating the differential structure, multi-type attenuation unit adaptation, and cascaded inductor optimization of the digital attenuator 1 into the signal link of the RF front-end, serving as the core unit for programmable amplitude adjustment and power control in the link.

[0035] Specifically, digital attenuator 1 is a core passive / active integrated device in the RF front-end system that enables programmable amplitude adjustment and signal power control. It directly serves the signal gain regulation, impedance matching optimization, and dynamic range expansion requirements of the RF front-end system and is a key adjustment unit for the signal link in the system. In addition to digital attenuator 1, the RF front-end system also includes core components such as antennas, RF switches, low-noise amplifiers, power amplifiers, filters, mixers, oscillators, and phase shifters. The RF signals received / transmitted by the antenna are first switched by the RF switch to change the transmit / receive link. The signals in the receiving link are then filtered to remove noise. The signal is pre-amplified by a low-noise amplifier, and then sent to a mixer after the power is precisely adjusted by a digital attenuator 1. It is then mixed with the local oscillator signal generated by the oscillator to complete the frequency conversion. After frequency conversion, the signal can be combined with a phase shifter to adjust the phase before entering the subsequent baseband processing. In the transmission link, the baseband signal is frequency converted by the mixer, filtered by the filter, and then amplified by the power amplifier. It is then regulated to the target transmission power by the digital attenuator 1 and finally transmitted by the antenna through the RF switch. The digital attenuator 1 can be flexibly connected in series between the amplification, filtering, and frequency conversion units of the transceiver link according to system requirements to achieve precise power control and impedance matching coordination throughout the entire link.

[0036] It is understandable that the RF front-end system, by leveraging the high-performance characteristics of digital attenuator 1, achieves precise and programmable control of signal power in the RF front-end link, solving the problem of difficulty in simultaneously achieving attenuation adjustment, impedance matching, and phase consistency in traditional RF front-end systems. The differential structure of digital attenuator 1 is highly compatible with the differential signal transmission requirements of the RF front-end, effectively improving the broadband transmission performance, anti-interference capability, and dynamic range of the entire RF front-end system. At the same time, the modular design of digital attenuator 1 makes the structure of the RF front-end system more compact and its process adaptability stronger, thus improving the signal processing accuracy and operational stability of the RF front-end system as a whole.

[0037] Thirdly, see Figures 5-6 This invention discloses a design method for a radio frequency (RF) front-end system, used in the aforementioned RF front-end system, comprising, Step S1: Obtain the attenuation requirements of several attenuation units and attenuators with different attenuation amounts. The attenuation requirements include the total attenuation adjustment range and the attenuation step accuracy. Step S2: Based on the attenuation requirements of the RF front-end system and the structural characteristics of each attenuation unit, determine the cascading order of the attenuation units to obtain a digital attenuator. The attenuation unit with large attenuation is set in the middle of the attenuation network, and attenuation units with medium or small attenuation are set on both sides of the large attenuation unit along the signal transmission direction. The cascading network is configured between adjacent attenuation units. Step S3: Construct the RF front-end system based on the digital attenuator to obtain the RF front-end system.

[0038] Specifically, in step S1, by considering the application scenarios and performance indicators of the RF front-end system, the total attenuation adjustment range and attenuation step accuracy required by the digital attenuator are determined. At the same time, basic information of attenuation units with various preset attenuation amounts is collected, and the core attributes such as the attenuation range and structural form of different attenuation units are sorted out. This anchors the core requirements and device fundamentals from the design source, avoiding subsequent designs from deviating from system performance requirements. In addition, sorting out the attenuation unit information in advance improves the efficiency and targeting of subsequent cascade designs.

[0039] Specifically, in step S2, based on attenuation requirements, the equivalent impedance, parasitic characteristics, phase delay, and other structural characteristics of each attenuation unit are extracted. Following the principle of placing the large attenuation unit in the middle of the attenuation network and arranging medium / small attenuation units sequentially on both sides, the optimal cascading sequence is determined. Simultaneously, based on the structural types of adjacent attenuation units, suitable cascading networks are configured between them. Finally, the overall design and construction of the digital attenuator are completed. By combining attenuation requirements with the structural characteristics of the attenuation units and through a scientific cascading sequence and network configuration, the digital attenuator achieves a wide attenuation range, fine-stepping, and impedance matching performance, thus optimizing the attenuation network's performance. The centrally located large attenuation unit effectively reduces impedance disturbances caused by large attenuation amounts. The targeted configuration of the cascading network optimizes transmission matching between different attenuation units, ensuring that the designed digital attenuator fully adapts to the attenuation requirements of the RF front-end system. Furthermore, the differential structure and the adaptability design of multiple attenuation unit types further enhance the broadband performance and phase consistency of the digital attenuator.

[0040] Specifically, in step S3, the designed digital attenuator is integrated into the signal transceiver link of the RF front-end system. According to the overall architecture of the RF front-end system, the link connection between the digital attenuator and core components such as antennas, RF switches, amplifiers, and filters is completed, and a complete RF front-end system is built. This achieves the organic integration of the digital attenuator and the RF front-end system, allowing the digital attenuator to serve as the core power regulation unit and be integrated into the overall signal processing link of the RF front-end system, giving full play to its programmable amplitude regulation function. The RF front-end system is built based on the customized digital attenuator design, ensuring high compatibility of components within the system and avoiding performance loss caused by mismatch between general attenuators and system links. This gives the RF front-end system the inherent advantages of precise power regulation and wideband matching from an architectural perspective. At the same time, the modular integration method also improves the convenience of system construction.

[0041] It is understandable that the process involves first obtaining the attenuation requirements, such as the total attenuation range and step accuracy of attenuation units and attenuators with different attenuation levels, and then determining the cascading order of attenuation units based on the attenuation requirements of the RF front-end system and the structural characteristics of each attenuation unit. Large attenuation units are placed in the middle of the attenuation network, with medium and small attenuation units arranged sequentially on both sides along the signal transmission direction. Corresponding cascaded networks are configured between adjacent attenuation units to construct a digital attenuator. Finally, the overall construction of the RF front-end system is completed based on this digital attenuator. Furthermore, the transmission characteristics of the system and the digital attenuator can be verified by configuring different attenuation states and input signals. The process of determining the cascading order to construct the digital attenuator requires multiple precise design steps, including demand analysis to refine design specifications, matching unit structure according to attenuation levels, designing unit parameters based on attenuation theory and performing single-unit verification, and analyzing unit structural characteristics to optimize cascading and network configuration. This method integrates the structural characteristics of attenuation units with the requirements of the RF front-end system throughout the entire process, from demand-side design to unit design and cascade optimization. This ensures a high degree of compatibility between the digital attenuator and the RF front-end system. The cascade design principle with the large attenuation unit in the center effectively reduces impedance disturbances and improves the overall matching performance of the system. The multi-step verification process ensures design accuracy from the unit to the system level, allowing the final RF front-end system to fully leverage the performance advantages of the digital attenuator and achieve comprehensive optimization of attenuation adjustment, phase consistency, and input-output matching. Furthermore, the design method is standardized, replicable, and adaptable to the design requirements of RF front-end systems in different broadband RF application scenarios.

[0042] Step S3 is followed by the following steps: Step S4: Configure different attenuation states, input signals and run the RF front-end system to verify the transmission characteristics of the RF front-end system and its digital attenuators.

[0043] Specifically, the RF front-end system is configured with different attenuation states across the entire attenuation range. Standard RF test signals are input into the system and the system is run. Through testing methods such as S-parameter simulation and transient simulation, the core transmission characteristics of the system and its digital attenuators, such as attenuation accuracy, phase consistency, input-output matching, and insertion loss, are detected and analyzed. The completed RF front-end system is fully verified, the collaborative working effect of the digital attenuators and the overall system is examined, and potential performance issues during the design and integration process are identified. The verification method covering the entire attenuation state can comprehensively test the transmission performance of the RF front-end system under different operating conditions, ensuring that the system meets the preset performance requirements across the entire attenuation range. At the same time, design defects are promptly identified and reported, providing data support for subsequent performance optimization and ensuring the operational stability and performance reliability of the final delivered RF front-end system.

[0044] Step S2 specifically includes the following steps: Step S21: Obtain the required data of the RF front-end system for amplitude control and dynamic range, analyze and refine these required data, clarify the total attenuation adjustment range and attenuation step accuracy of the digital attenuator, and obtain the core design parameters of the digital attenuator. Step S22: Obtain implementation difficulty data for different attenuation ranges, structural characteristics and attenuation adaptability data of Π-type, T-type and simplified T-type attenuation units, classify and match these data, group the attenuation units according to the attenuation size, match the corresponding attenuation unit structure form for different attenuation ranges, and obtain the attenuation unit grouping scheme and the attenuation unit structure type corresponding to each group. Step S23: Obtain initial data, including attenuation theoretical parameters, system characteristic impedance data, and on-resistance and parasitic capacitance model data of switching devices. Perform calculation, design, and verification processing on the initial data. Calculate the resistance value of each attenuation unit based on the passive impedance matching attenuation network theory. Design the size of the switching transistor by combining parasitic parameter suppression theory and insertion loss optimization theory. Then, perform S-parameter verification on a single attenuation unit to obtain the resistance value parameters of each attenuation unit, the size parameters of the switching transistor, and the performance verification report of a single attenuation unit. Step S24: Obtain the structural characteristic data of each attenuation unit. The structural characteristic data includes the equivalent input impedance, equivalent output impedance, parasitic capacitance distribution, phase delay and frequency correlation characteristic data under different attenuation states. Analyze and optimize the structural characteristic data, determine the optimal cascading sequence according to the structural characteristics of the attenuation unit, and configure the corresponding cascading network according to the connection requirements of different types of attenuation units to obtain the attenuation unit cascading sequence scheme and the inductance and other parameter configuration scheme of the cascading network. Step S25: Construct a digital attenuator by combining all the data obtained above.

[0045] Specifically, starting from the requirements of the RF front-end system, the core design indicators of the digital attenuator, such as the total attenuation adjustment range and attenuation step accuracy, are analyzed and extracted. Then, the implementation difficulty of different attenuation ranges and the structural characteristics and attenuation adaptability data of Π-type, T-type, and simplified T-type attenuator units are obtained. Attenuator units are grouped according to the attenuation amount and matched with corresponding structural forms. Next, based on the initial data such as attenuation theoretical parameters, system characteristic impedance, and switching device model data, the resistance value of the attenuator unit is calculated through the passive impedance matching attenuation network theory. The size of the switching transistor is designed in combination with the parasitic parameter suppression and insertion loss optimization theory to complete the S-parameter verification of a single attenuator unit. Subsequently, the equivalent impedance, parasitic capacitance distribution, phase delay, and other structural characteristic data of each attenuator unit under different attenuation states are extracted. After analysis and optimization, the optimal cascading order of the attenuator units is determined, and a suitable cascading network is configured for adjacent attenuator units of different types. Finally, all design data and schemes are integrated to complete the overall construction of the digital attenuator.

[0046] In step S23, the attenuation theoretical parameters and the system characteristic impedance are first obtained. Device on-resistance Parasitic capacitance Model data. The specific processing steps in step S23, taking a 50Ω system as an example, are calculated according to attenuation theory. First, the attenuation amount in dB is converted into a voltage attenuation factor k, as shown in the following formula: ; Where A is the target attenuation amount (dB).

[0047] Then, calculate the resistance of the T-type attenuation unit using the following formula: ; ; The formula for calculating the resistance of a Π-type attenuation unit is as follows: ; ; Based on the on-resistance The formula for correcting the actual resistance value is as follows: ; according to and A compromise design for the W / L size of the switching transistor, where increasing the W / L reduces... But increase When the W / L ratio is reduced, the decrease is reduced. But increase Simulation iterations are performed within the target frequency band to minimize insertion loss.

[0048] It is understandable that step S2, from system requirements to unit design and then to cascade optimization, completes the precise design of the digital attenuator throughout the entire process. Through multi-dimensional data acquisition and professional theoretical support, the selection, parameter design, and cascade configuration of the attenuator units are highly compatible with the attenuation requirements of the RF front-end system. At the same time, through scientific cascade rules and network configuration, the impedance matching and signal transmission characteristics of the attenuation network are optimized. The entire process is data-driven and based on professional attenuation theory, ensuring the accuracy and rationality of the attenuator unit parameter design. The method of matching the corresponding structural form according to the attenuation amount takes into account the implementation accuracy and parasitic effect control of different attenuation amounts. The cascade design with large attenuator units in the center and the targeted cascade network configuration effectively reduce impedance disturbances and improve the overall matching performance of the attenuation network. Moreover, the single-unit verification stage avoids unit performance defects in advance, so that the final constructed digital attenuator can meet the broadband application requirements of the RF front-end system in terms of attenuation accuracy, phase consistency, and input / output matching.

[0049] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0050] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0051] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0052] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0053] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0054] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. The illustrative expressions of the above terms in this specification should not be construed as necessarily referring to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0055] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Since these modifications and variations fall within the scope of the claims and their equivalents, this invention also intends to include these modifications and variations.

[0056] The above description describes specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A digital attenuator, characterized in that, It includes a differential input terminal, a differential output terminal, an input cascaded inductor group, multiple attenuation unit components, multiple small attenuation components, and an output cascaded inductor group. The input cascaded inductor group is connected to the attenuation unit components or small attenuation components, and the output cascaded inductor group is connected to the attenuation unit components or small attenuation components. The attenuation unit components and small attenuation components are set at intervals. The input cascaded inductor group, multiple attenuation unit components, multiple small attenuation components, and the output cascaded inductor group are arranged in a differential structure. A differential signal is input at the differential input terminal, passes through the input cascaded inductor group, multiple attenuation unit components, multiple small attenuation components and the output cascaded inductor group, and is output from the differential output terminal as a processed differential signal; The attenuation unit components are divided into medium attenuation units and large attenuation units according to the attenuation amount. The large attenuation unit adopts a Π-type attenuation structure, while the medium attenuation unit adopts a T-type attenuation structure. The intermediate attenuation unit includes a central series resistor, two symmetrical parallel resistors, a CMOS switching transistor, and a phase compensation capacitor. The differential positive and negative paths are also each independently configured with a complete T-type resistor network and supporting devices. The central series resistor is connected in series to the single-path signal main transmission link, and the two parallel resistors are respectively connected between the input node and output node of the central series resistor and ground, forming a standard T-type passive attenuation network. The CMOS switching transistor is embedded in the T-type resistor branch and the signal direct connection branch. The phase compensation capacitor is connected in parallel across the central series resistor. The T-type network of the differential dual path is strictly symmetrical. The large attenuation unit includes two symmetrical series resistors, one parallel resistor, a CMOS switching transistor, and a phase compensation capacitor. The differential positive and negative paths are each independently configured with a complete Π-type resistor network and supporting devices. The two series resistors are connected in series along the single-path signal transmission direction, and the parallel resistor is connected between the connection node of the two series resistors and ground, forming a Π-type passive attenuation network. The CMOS switching transistor is embedded in the Π-type resistor branch and the signal direct connection branch respectively, and the phase compensation capacitor is connected in parallel across the parallel resistor. The differential dual-path Π-type network is completely symmetrical.

2. The digital attenuator according to claim 1, characterized in that, The small attenuation component includes a small attenuation unit and an inductor group, which are connected together.

3. The digital attenuator according to claim 2, characterized in that, The small attenuation unit adopts a simplified T-type attenuation structure; The small attenuation unit includes one series resistor, one parallel resistor, two CMOS switching transistors, and one phase compensation capacitor. Each differential dual path is symmetrically configured with one set of the above components. The series resistor is directly connected in series with the main transmission link of the single-path signal; One end of the parallel resistor is connected to the middle node of the series resistor, and the other end is grounded. The CMOS switching transistors are embedded in the resistor branch composed of series resistors and parallel resistors and the signal direct connection branch, respectively. In the decay state, the resistor branch switch is turned on and the direct connection branch switch is turned off. The signal is attenuated in small steps through a simplified T-type resistor network. In the reference state, the direct connection branch switch is turned on and the resistor branch switch is turned off. The signal is transmitted directly. A phase compensation capacitor is connected in parallel across the series resistor to compensate for parasitic phase distortion at high frequencies.

4. A radio frequency front-end system, characterized in that, Includes the digital attenuator described in any one of claims 1-3 above.

5. A design method for a radio frequency front-end system, used in the radio frequency front-end system of claim 4, characterized in that, include, Obtain the attenuation requirements of several attenuation units and attenuators with different attenuation values. The attenuation requirements include the total attenuation adjustment range and the attenuation step accuracy. Based on the attenuation requirements of the RF front-end system and the structural characteristics of each attenuation unit, the cascading order of the attenuation units is determined to obtain a digital attenuator. In this attenuator, the attenuation unit with large attenuation is set in the middle of the attenuation network, and attenuation units with medium or small attenuation are set on both sides of the attenuation unit along the signal transmission direction. A corresponding cascading network is configured between adjacent attenuation units. The radio frequency front-end system is constructed based on the digital attenuator, and the radio frequency front-end system is obtained.

6. The method according to claim 5, characterized in that, The following steps are then included: Configure different attenuation states, input signals and run the RF front-end system to verify the transmission characteristics of the RF front-end system and its digital attenuators.

7. The method according to claim 6, characterized in that, The cascading order of the attenuation units is determined based on the attenuation requirements of the attenuator and the structural characteristics of each attenuation unit, resulting in a digital attenuator. This process includes the following steps: Acquire the requirements data of the RF front-end system for amplitude control and dynamic range, analyze and refine these requirements data, clarify the total attenuation adjustment range and attenuation step accuracy of the digital attenuator, and obtain the core design parameters of the digital attenuator. Data on the implementation difficulty of different attenuation ranges, structural characteristics of Π-type, T-type, and simplified T-type attenuation units, and attenuation adaptability data are obtained. These data are classified and matched, and attenuation units are grouped according to attenuation size. Corresponding attenuation unit structural forms are matched for different attenuation ranges to obtain attenuation unit grouping schemes and attenuation unit structural types for each group. Initial data is obtained, including attenuation theoretical parameters, system characteristic impedance data, and on-resistance and parasitic capacitance model data of switching devices. The initial data is then used for calculation, design, and verification. The resistance value of each attenuation unit is calculated based on the passive impedance matching attenuation network theory. The size of the switching transistor is designed by combining the parasitic parameter suppression theory and the insertion loss optimization theory. S-parameter verification is then carried out on a single attenuation unit to obtain the resistance value parameters of each attenuation unit, the size parameters of the switching transistor, and the performance verification report of a single attenuation unit. The structural characteristic data of each attenuation unit is obtained. The structural characteristic data includes the equivalent input impedance, equivalent output impedance, parasitic capacitance distribution, phase delay and frequency correlation data under different attenuation states. The structural characteristic data is analyzed and optimized. The optimal cascading sequence is determined according to the structural characteristics of the attenuation unit. At the same time, the corresponding cascading network is configured for the connection requirements of different types of attenuation units, and the attenuation unit cascading sequence scheme and the inductance and other parameter configuration scheme of the cascading network are obtained. A digital attenuator is constructed by combining all the data obtained above.

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