Semiconductor device and method for generating layout plan thereof

Abstract

The embodiment of the invention discloses a semiconductor device and a method for generating a layout plan of the semiconductor device. An embodiment semiconductor device includes a first circuit cell and a second circuit cell adjoining the first circuit cell at a cell boundary between the first circuit cell and the second circuit cell. The first circuit unit includes first one or more conductive lines in a first metallization line region of a first metallization layer, and includes first one or more via structures under the first metallization layer. The second circuit unit includes a second one or more conductive lines in a second metallization line region of the first metallization layer, and includes a second one or more via structures under the first metallization layer. The first metallization line region and the second metallization line region are separated by a shared space extending along the cell boundary. The first one or more via structures and the second one or more via structures are located within a region having a zigzag pattern along the cell boundary.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to semiconductor devices and methods of generating layout plans thereof. BACKGROUND

[0002] Integrated circuits (ICs) include one or more semiconductor devices. In designing a semiconductor device, a designer can indicate dimensions and shapes of various features of the semiconductor device in a layout plan in a layout plan of the semiconductor device. Components and structures of the semiconductor structure are typically formed based on forming and / or removing features of various layers of semiconductor material or structures indicated by the layout plan in the layout plan. In some applications, a semiconductor device includes a set of modules that perform higher-order functions according to design specifications of the semiconductor device. These modules are typically built from combinations of circuit cells, each of which represents one or more semiconductor structures configured to perform a particular function. In some applications, the layout plan includes layout cells corresponding to various circuit cells, and has pre-designed layout plans, which are sometimes referred to as standard cells. In many applications, templates of the standard cells are stored in a standard cell library (for simplicity, referred to as a “library” or “cell library” hereinafter) that is accessible by various tools, such as electronic design automation (EDA) tools, that can be used to generate, optimize, and verify designs of semiconductor devices.

[0003] As semiconductor devices become smaller and more complex, some features of the same layer of semiconductor material or structure can be too close to be fabricated at the same time due to design rules of the corresponding fabrication process. Conversely, fabrication features that are too close to each other due to design rules can be fabricated based on multiple patterning using multiple masks, which can increase the cost of fabricating the additional masks, increase the cost of performing additional photolithography, deposition, and / or removal processes, increase the complexity of aligning different masks of the same layer, and / or reduce the yield of fabricating the semiconductor device. SUMMARY

[0004] According to an aspect of an embodiment of the present application, there is provided a semiconductor device, comprising: a first circuit unit comprising a first one or more electrically conductive lines in a first metallization line region of a first metallization layer and comprising a first one or more via structures below the first metal layer; and a second circuit unit adjoining the first circuit unit at a unit boundary between the first circuit unit and the second circuit unit, the second circuit unit comprising a second one or more electrically conductive lines in a second metallization line region of the first metallization layer and comprising a second one or more via structures below the first metallization layer, wherein the first metallization line region and the second metallization line region are separated by a shared space extending along the unit boundary, the first one or more via structures and the second one or more via structures are located within a first region having a first zigzag pattern along the unit boundary based on the first one or more via structures between the first metallization layer and a first one or more drain / source electrically conductive structures of the first circuit unit and the second one or more via structures between the first metallization layer and a second one or more drain / source electrically conductive structures of the second circuit unit, and the first one or more via and the second one or more via structures are located within a second region having a second zigzag pattern along the unit boundary based on the first one or more via structures between the first metallization layer and a first one or more gate structures of the first circuit unit and the second one or more via structures between the first metallization layer and a second one or more gate structures of the second circuit unit.

[0005] According to yet another aspect of the embodiments of the present application, a method of generating a layout plan of a semiconductor device is provided, including: placing a first layout cell in the layout plan, the first layout cell indicating a first circuit cell, including a first one or more conductive line patterns indicating a first one or more conductive lines in a first metallization line region of a first metallization layer, and including a first one or more via patterns indicating a first one or more via structures below the first metallization layer; placing a second layout cell in the layout plan, the second layout cell being contiguous with the first layout cell at a cell boundary between the first layout cell and the second layout cell, the second layout cell indicating a second circuit cell, including a second one or more conductive line patterns indicating a second one or more conductive lines in a second metallization line region of the first metallization layer, and including a second one or more via patterns indicating a second one or more via structures below the first metallization layer; and storing the layout plan including the first layout cell and the second layout cell into a memory of a processing device, wherein the first metallization line region and the second metallization line region are separated by a shared space extending along the cell boundary, the first one or more via patterns and the second one or more via patterns are located within a first region having a first zigzag pattern along the cell boundary based on the first one or more via patterns and the second one or more via patterns belonging to a first via layer between the first metallization layer and a drain / source conductive layer in the layout plan, and the first one or more via patterns and the second one or more via patterns are located within a second region having a second zigzag pattern along the cell boundary based on the first one or more via patterns and the second one or more via patterns belonging to a second via layer between the first metallization layer and a gate layer in the layout plan.

[0006] According to yet another aspect of the embodiments of the present application, a method for generating a layout floorplan of a semiconductor device is provided, comprising: obtaining, from a plurality of placement locations of the layout floorplan, a placement location group for indicating a target layout cell of a target circuit cell, each of the plurality of placement locations of the layout floorplan has a width corresponding to a gate pitch of the layout floorplan along a first direction and has a height corresponding to a standard cell height of the layout floorplan along a second direction, wherein the plurality of placement locations: includes placement locations of a first row, includes first placement locations of a first placement type and second placement locations of a second placement type arranged in an alternating manner along the first direction, and is available for placing a standard layout cell of the standard cell height in a nominal form, and includes placement locations of a second row, includes third placement locations of a flipped first placement type and fourth placement locations of a flipped second placement type arranged in an alternating manner along the first direction, and is available for placing a standard layout cell in a flipped form, the flipped form corresponds to an axis mirror of the nominal form along the first direction, a shared space is defined along a boundary between the first row and the second row, the shared space is free of any layout pattern in a first metallization layer of the layout floorplan, a first placement location of the placement locations of the first row is adjacent to a fourth placement location of the placement locations of the second row, a second placement location of the placement locations of the first row is adjacent to a third placement location of the placement locations of the second row, the first placement type indicates that a via pattern disposed at a neighboring side of the respective placement location in an opposite second direction is accommodated below the first metallization layer of the layout floorplan, and the second placement type indicates that any via pattern disposed at the neighboring side of the respective placement location in the opposite second direction is prohibited below the first metallization layer of the layout floorplan; placing one of a plurality of candidate layout cells associated with the target circuit cell as the target layout cell on the placement location group based on a placement location type of an edge placement location of the placement location group in the opposite first direction; and storing the layout floorplan including the layout cell into a memory of a processing device. BRIEF DESCRIPTION OF DRAWINGS

[0007] Various aspects of the disclosure can be best understood from the following detailed description when read with the accompanying drawings. It is emphasized that, according to common practice, the various drawings are not to scale. On the contrary, the dimensions of the various components are arbitrarily expanded or reduced for the clarity of discussion.

[0008] Figure 1 is a block diagram of a semiconductor device according to some embodiments.

[0009] Figure 2 is a cross-sectional view of a semiconductor device according to some embodiments.

[0010] Figures 3A-3E is a layout floorplan of various layout cell examples according to some embodiments.

[0011] Figures 4A-4B is a layout plan view of different portions of a first layout plan example according to some embodiments.

[0012] Figures 5A-5B is a layout plan view of different portions of a second layout plan example according to some embodiments.

[0013] Figure 6 is a schematic view of a plurality of placement locations of a layout plan of a semiconductor device according to some embodiments.

[0014] Figure 7A is a layout plan view of portions of a base layout cell example according to some embodiments.

[0015] Figures 7B-7I is a layout plan view of various portions of different layout cell examples based on a base layout cell according to some embodiments. Figure 7A

[0016] Figures 8A-8C is a simplified layout plan view of various flip variants of a base candidate layout cell according to some embodiments.

[0017] Figures 9A-9B is a simplified layout plan view of a layout plan example according to some embodiments.

[0018] Figure 10A is a circuit diagram of AND-OR-INVERT (AOI) logic according to some embodiments.

[0019] Figures 10B-10D is a layout plan view of a candidate layout cell for AOI logic in Figure 10A according to some embodiments.

[0020] Figure 11A is a circuit diagram of NAND logic according to some embodiments.

[0021] Figures 11B-11C is a layout plan view of a candidate layout cell for NAND logic in Figure 11A according to some embodiments.

[0022] Figures 12A-12B is a diagram of a simplified layout plan example according to some embodiments.

[0023] Figure 13 is a flowchart of a method of generating a layout plan of a semiconductor device according to some embodiments.

[0024] Figure 14 is a flowchart of a method of generating a layout plan of a semiconductor device according to some embodiments. ​

[0025] Figure 15 is a block diagram of an electronic design automation (EDA) system in accordance with some embodiments.

[0026] Figure 16 is a block diagram of an integrated circuit (IC) manufacturing system and an IC manufacturing flow associated therewith in accordance with some embodiments. DETAILED DESCRIPTION

[0027] The following disclosure provides many different embodiments, or examples, of different features of the present disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the disclosure in any way. For example, the formation of a first component over or on a second component can include embodiments where the first component and the second component are formed in direct contact, and where there can be an additional component formed between the first component and the second component such that the first component and the second component do not contact directly. Also, the present disclosure can refer to reference numerals shown in the drawings, and / or alphabetic literals to refer to aspects of the present disclosure in various examples. This repetition is for the purpose of simplicity and clarity and does not indicate a relationship between the different embodiments and / or configurations discussed.

[0028] In addition, spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for ease of description to describe one element or component's relationship to another element(s) or component(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. Additionally, the term "by" can mean "comprising" or "consisting of. In the present disclosure, the phrase "one of A, B, and C" means "A, B, and / or C" (A, B, C, A and B, A and C, B and C, or A, B, and C), unless otherwise indicated, and does not mean one element from A, one element from B, and one element from C.

[0029] In some applications, a semiconductor device configured based on a backside power delivery network (BSPDN) includes conductive tracks for powering on the backside of a substrate, with the advantage of a wider conductive track for powering and a smaller cell size on the front side of the substrate. In some applications, as the cell size (e.g., cell height) is reduced, some features of the circuit cell can be too close, so these features can only be practically manufactured by applying a more complex photolithography process and / or introducing additional masks, which corresponds to an increase in manufacturing cost and / or a decrease in yield.

[0030] In some embodiments, according to the present application, by applying constraints and / or rules, the via patterns adjacent to the cell boundaries are restricted to be within the regions having the zigzag pattern. Thus, without increasing the cell height, the via pitch of these via patterns is effectively increased. In some embodiments, the semiconductor devices and corresponding layout plan based on one or more embodiments of the present disclosure will reduce or eliminate the necessity of applying more complex photolithography processes and / or introducing additional masks, which corresponds to reduced manufacturing cost and / or improved yield.

[0031] Figure 1 is a block diagram of a semiconductor device 100 according to some embodiments of the present disclosure. In some embodiments, the semiconductor device 100 corresponds to an IC device or a portion of an IC device.

[0032] As shown in Figure 1 the semiconductor device 100 includes at least one circuit macro 110. In some embodiments, the circuit macro 110 corresponds to a set of semiconductor components configured as a memory, a controller, one or more logic gates, etc. The circuit macro 110 includes one or more circuit cells, such as circuit cell 112, circuit cell 114, and circuit cell 116. In some embodiments, each of the circuit cells 112, 114, and 116 corresponds to one or more layout cells including a layout pattern indicative of transistors formed based on one or more active regions extending along a first direction (e.g., X direction) and one or more gate structures extending along a second direction (e.g., Y direction). In some embodiments, each of the circuit cells 112, 114, and 116 (and the corresponding layout cells) has a respective cell height H1, H2, and H3 measurable along the second direction.

[0033] In some embodiments, each of the layout cells of circuit cells 112, 114, and 116 includes a layout pattern that indicates respective conductive lines of various transistors of circuit cells 112 and 116 within one or more metallization layers and electrically connected. In some embodiments, semiconductor device 100 defines a plurality of power rail regions extending along the first direction that are configured to carry a first power voltage (e.g., VDD) or a second power voltage (e.g., VSS or ground). In some embodiments, a circuit cell includes a first side extending along a power rail region and a second side extending along another power rail region. In some embodiments, a circuit cell that does not have any other power rail regions between its first and second sides is sometimes referred to as having a standard cell height. In some embodiments based on more compact designs for some processing nodes, a circuit cell having a standard cell height includes up to four or five metallization regions (in addition to the power rail regions) extending along the first direction in a lowest metallization layer (also referred to as an M0 layer) above the transistors of the circuit cell. In some embodiments, any one of cell heights Hl, H2, and H3 has a standard cell height (e.g., a 1H cell), two standard cell heights (e.g., a 2H cell), or three standard cell lengths (e.g., a 3H cell). In some embodiments, the circuit cells in circuit macro 110 correspond to a plurality of standard cell heights or a height less than one standard cell (e.g., a 1 / 2H cell).

[0034] Figure 2 is a cross-sectional view of a semiconductor device (e.g., semiconductor device 100) in accordance with some embodiments. In some embodiments, the cross-sectional view is a simplified cross-sectional view in which many features are simplified or not depicted.

[0035] Figure 2semiconductor device 100 includes a substrate 210, an active region 212, and a gate structure 214 formed at least partially in the substrate 210. In this example, the semiconductor device 100 includes a metal-to-drain / source (MD) structure 222 coupled to the active region 212. In this example, the semiconductor device 100 includes a via-to-drain (VD) structure coupled to the MD structure 222 and a via-to-gate (VG) structure coupled to the gate structure 214 at a VD / VG layer above the substrate 210 (with respect to the direction Z). In some embodiments, the semiconductor device 100 further includes a plurality of metallization layers (e.g., M0, M1, M2, …, Mn-1, and Mn layers) and a plurality of via layers (e.g., V0, V1, V2, …, Vn-2, and Vn-1 layers) above the substrate 210 (n is a positive integer). In some embodiments, the number of metallization layers above the substrate 210 is in the range of 8 to 14. In some embodiments, the Vn-1 layer represents a via structure between conductive lines in the Mn-1 layer and the Mn layer. In some embodiments, the M0 layer represents a first metallization layer above the substrate 210. In some embodiments, the plurality of metallization layers and the plurality of via layers include a conductive material including copper, aluminum, gold, tungsten, combinations thereof, and the like.

[0036] As a non-limiting example, Figure 2 The semiconductor device 100 in also includes conductive structures disposed below the substrate 210. For example, the semiconductor device 100 further includes backside metallization layers BM0 and BM1 and backside via layers BVD and BV0. In this example, the BVD layer represents a backside via structure between the active region 212 and a backside conductive line in the BM0 layer and connecting the active region 212 and the backside conductive line; the BV0 layer represents a backside via structure between the backside conductive lines in the BM0 layer and the BM1 layer and connecting the backside conductive lines. In some embodiments, the BM0 layer represents a first metallization layer below the substrate 210. In this example, there are two backside metallization layers and corresponding via layers. In some embodiments, the number of backside metallization layers below the substrate 210 is in the range of 2 to 6. In some embodiments, some or all of the backside conductive structures (e.g., the backside metallization layers BM0 and BM1 and the backside via layers BVD and BV0) are at least partially embedded in the substrate 210. In some embodiments, the backside metallization layers BM0 and BM1 and the backside via layers BVD and BV0 include a conductive material including copper, aluminum, gold, tungsten, combinations thereof, and the like. In some other embodiments, the semiconductor device does not include any backside conductive structures.

[0037] In some embodiments, the semiconductor device 100 includes one or more redistribution layers and conductive pad structures on the one or more redistribution layers Figure 2(Not shown in the image). In some embodiments, the semiconductor device 100 further includes conductive terminal structures (e.g., conductive bumps, copper pillar bumps, solder bumps, etc.) above the conductive pad structure. Figure 2 (Not shown in the image). In some embodiments, the semiconductor device 100 further includes one or more back-side redistribution layers and one or more back-side conductive pad structures beneath the back-side redistribution layers (not shown in the image). Figure 2 (Not shown in the image). In some embodiments, the semiconductor device 100 further includes a back-side conductive terminal structure (e.g., conductive bumps, copper pillar bumps, solder bumps, etc.) located below the back-side conductive pad structure. Figure 2 (Not shown in the image).

[0038] Figure 3A This is a layout plan view of a first layout unit example 300A according to some embodiments. As a non-limiting example, Figure 3A Only a portion of the first layout unit 300A is shown. Figure 3A In the diagram, the first layout unit 300A corresponds to a first circuit unit and has a unit boundary 302. The first layout unit 300A has metallization regions 312, 314, 322, 324, 326, and 328 extending along a first direction (e.g., the X direction) and a lowest metallization layer (e.g., ...) above the substrate. Figure 2 The M0 layer is arranged one after another along the second direction (e.g., the Y direction) in the resulting semiconductor device (also known as on the front side of the semiconductor device).

[0039] In some embodiments, the layout patterns in metallized regions 312 and 314 indicate conductive lines for carrying power supply voltages (e.g., VDD, VSS, or ground). In some embodiments, the layout patterns in metallized regions 322, 324, 326, and 328 indicate conductive lines for connecting various elements of the first circuit unit. In some embodiments, the power network for supplying power based on metallized regions 312 and 314 in the MO layer is also referred to as a front-side power delivery network (FSPDN) configuration. Figure 3A In the first layout unit 300A, along the second direction, there is a first standard unit height Ha, which is used to accommodate metallized regions 312, 314, 322, 324, 326 and 328.

[0040] Figure 3B This is a layout plan view of a second layout unit example 300B according to some embodiments. As a non-limiting example, Figure 3B Only a portion of the second layout unit 300B is shown. Figure 3BIn the second layout unit 300B, there corresponds to a second circuit unit and has a unit boundary 306. The second layout unit 300B has metallization regions 332, 334, 342, 344, 346, and 348 extending along a first direction (e.g., the X direction). The metallization regions 342, 344, 346, and 348 are located above the lowest metallization layer (e.g., above the substrate). Figure 2 The metallization regions 332 and 334 are arranged one after another in the M0 layer (e.g., along the second direction, such as the Y direction) in the resulting semiconductor device. Furthermore, metallization regions 332 and 334 are arranged in the metallization layer (e.g., below the substrate) Figure 2 In the BMO layer (also referred to as the back side of the resulting semiconductor device). In some embodiments, metallization regions 342, 344, 346, and 348 have a common shape with the metallization layer (also referred to as the back side of the resulting semiconductor device). Figure 3A The metallization regions 322, 324, 326 and 328 in the second direction have linewidths and line pitches that are equivalent or the same.

[0041] In some embodiments, the layout patterns in metallized regions 332 and 334 indicate conductive lines for carrying power supply voltages (e.g., VDD, VSS, or ground). In some embodiments, the layout patterns in metallized regions 342, 344, 346, and 348 indicate conductive lines for connecting various elements of the second circuit unit. In some embodiments, the power network for supplying power based on metallized regions 332 and 334 in the BMO layer is also referred to as a Backside Power Delivery Network (BSPDN) configuration. Figure 3B In this configuration, the second layout unit 300B has a second standard cell height Hb along a second direction for accommodating metallized regions 342, 344, 346, and 348. Compared to the first layout unit 300A, which has metallized regions 312 and 314 for power supply on the front side, the second standard cell height Hb is smaller than the first standard cell height Ha by having metallized regions 332 and 334 for power supply on the rear side. Therefore, the standard cell based on the BSPDN configuration has a smaller cell height and a wider rear-side metallized region than the corresponding cell based on the FSPDN configuration.

[0042] Figure 3C This is a layout plan view of a third layout unit example 300C according to some embodiments. As a non-limiting example, Figure 3C Only a portion of the third layout unit 300C is shown. Figure 3C In the middle, the third layout unit 300C corresponds to the third circuit unit based on the BSPDN configuration, and Figure 3C The metallized area on the back side used for power supply is not shown. Figure 3CIn this embodiment, the third layout cell 300C has a cell boundary 352 and four metallization regions 354 extending along a first direction (e.g., the X direction) in the lowest metallization layer (e.g., the M0 layer). In some embodiments, the third layout cell 300C is also referred to as a 4M0 layout cell. Furthermore, the third layout cell 300C also includes a gate pattern 356 representing a gate structure within the cell boundary 352 and a pseudo gate pattern 358 representing pseudo gate structures on the left and right segments (opposite sides relative to the X direction) of the cell boundary 352.

[0043] exist Figure 3C In this configuration, the metallized regions 354 do not overlap with the upper and lower segments (opposite sides relative to the Y direction) of the cell boundary 352. Therefore, the upper side of the third layout cell 300C is suitable for adjacency to another layout cell that has no metallized region in its lowest metallized layer (e.g., the M0 layer) overlapping the lower segment of its cell boundary, thereby defining a shared space along the upper segment of the cell boundary 352. Furthermore, the lower side of the third layout cell 300C is suitable for adjacency to another layout cell that has no metallized region in its lowest metallized layer (e.g., the M0 layer) overlapping the upper segment of its cell boundary, thereby defining a shared space along the lower segment of the cell boundary 352.

[0044] Figure 3D This is a layout plan view of a fourth layout unit example 300D according to some embodiments. As a non-limiting example, Figure 3D Only a portion of the fourth layout unit 300D is shown. Figure 3D In the middle, the fourth layout unit 300D corresponds to the fourth circuit unit based on the BSPDN configuration, and Figure 3D The metallized area on the back side used for power supply is not depicted. Figure 3D In this embodiment, the fourth layout cell 300D has a cell boundary 362 and five metallization regions 364 extending along a first direction (e.g., the X direction) in the lowest metallization layer (e.g., the M0 layer). In some embodiments, the fourth layout cell 300D is also referred to as a 5M0 layout cell. Furthermore, the fourth layout cell 300D includes a gate pattern 366 representing a gate structure within the cell boundary 362 and a pseudo-gate pattern 368 representing pseudo-gate structures on the left and right segments (opposite sides relative to the X direction) of the cell boundary 362.

[0045] exist Figure 3D In, with Figure 3CThe example in FIG. 3B is similar, and the metallization regions 364 do not overlap the upper and lower segments (opposite sides with respect to the Y direction) of the cell boundary 362. Thus, the upper side of the fourth layout cell 300D is suitable for abutting another layout cell and defines a shared space along the upper segment of the cell boundary 362. In addition, the lower side of the fourth layout cell 300D is suitable for abutting another layout cell and defines a shared space along the lower segment of the cell boundary 362.

[0046] Figure 3E is a layout plan of a fifth layout cell example 300E according to some embodiments. As a non-limiting example, Figure 3E Only a portion of the fifth layout cell 300E is shown. In Figure 3E , the fifth layout cell 300E corresponds to a fifth circuit cell configured based on the BSPDN, and Figure 3E , the metallization regions for the backside of the power supply are not shown. In Figure 3E , the fifth layout cell 300E has a cell boundary 372, four metallization regions 374 within the cell boundary 372 extending along a first direction (e.g., the X direction) in a lowest metallization layer (e.g., the M0 layer), and one metallization region 375 in the lowest metallization layer and extending along a lower segment of the cell boundary 372. In some embodiments, the fifth layout cell 300E is also referred to as a layout cell of 4.5M0. In addition, the fifth layout cell 300E further includes gate patterns 376 indicating gate structures within the cell boundary 372 and pseudo gate patterns 378 indicating pseudo gate structures on the left and right segments (opposite sides with respect to the X direction) of the cell boundary 372.

[0047] In Figure 3E , the metallization regions 374 do not overlap the upper segment of the cell boundary 372. Thus, the upper side of the fifth layout cell 300E is suitable for abutting another layout cell and defines a shared space along the upper segment of the cell boundary 372. However, the metallization region 375 overlaps the lower segment of the cell boundary 372. Thus, the lower side of the fifth layout cell 300E is suitable for abutting another layout cell that has a metallization region overlapping the upper segment of its cell boundary, thereby defining a shared metallization region along the lower segment of the cell boundary 372.

[0048] Figure 4A and Figure 4B are layout plan views of different portions of a first layout plan example 400 according to some embodiments. As a non-limiting example, Figure 4A and Figure 4B The layout patterns in FIG. 4A only constitute a portion of the first layout plan 400. In Figure 4A and Figure 4B other layout cells and layout patterns of the first layout plan 400 are omitted in FIG. 4A and FIG. 4B, respectively.

[0049] Figure 4A includes Figure 4A and Figure 4B a legend of various types of layout patterns used in Figure 4A and Figure 4B In and

[0050] the layout pattern includes a poly gate (PO) pattern of layout patterns indicative of a poly gate structure. In some embodiments, the poly gate structure is used as a functional gate structure, a dummy gate structure, or a placeholder structure on which functional structures and dummy structures are formed. In this non-limiting example, the PO pattern is spaced apart from each other along a first direction (e.g., X direction) at a contact poly pitch (1 CPP, also referred to as a gate pitch). Figure 4A Figure 4B In Figure 4A and Figure 4B the layout pattern includes an M0 layout pattern for conductive lines at a lowest metallization layer (e.g., M0 layer) above the gate structure, an M1 layout pattern for conductive lines at another metallization layer (e.g., M1 layer) above the lowest metallization layer, a VD layout pattern for via structures connecting drain / source terminals to respective conductive lines at the M0 layer, a VG layout pattern for via structures connecting gate structures to respective conductive lines at the M0 layer, and a VO layout pattern for via structures connecting conductive lines of the M0 layer and respective conductive lines of the M1 layer.

[0051] In Figures 4A to 4B the first layout plan view 400 includes three layout units 410, 420, and 430 stacked on each other in a second direction (e.g., Y direction). Each of the layout units 410, 420, and 430 includes, based on the BSPDN configuration, conductive lines for power supply located at a backside of the resulting semiconductor device, and conductive lines within four conductive regions extending along a first direction (e.g., X direction) in an M0 layer (represented by the M0 layout pattern) at a frontside of the resulting semiconductor device.

[0052] In Figure 4AIn this configuration, layout unit 410 is adjacent to layout unit 420. Layout unit 410 includes a conductive line pattern 412 indicating conductive lines in the metallized region of the M0 layer, and a via pattern (e.g., via pattern 414) indicating via structures below the M0 layer, the via structures being configured to connect corresponding drain / source terminals to the conductive lines indicated by conductive line pattern 412. Layout unit 420 includes a conductive line pattern 422 indicating conductive lines in the metallized region of the M0 layer, and a via pattern (e.g., via pattern 424) indicating via structures below the M0 layer, the via structures being configured to connect corresponding drain / source terminals to the conductive lines indicated by conductive line pattern 422. In some embodiments, conductive line patterns 412 and 422 are arranged based on a metallization pitch (M0 pitch) along a second direction.

[0053] exist Figure 4A In the middle, layout unit 420 is adjacent to layout unit 430. Layout unit 420 includes a conductive line pattern 425 indicating conductive lines in another metallized area of ​​the M0 layer, a conductive line pattern 426 indicating conductive lines in the metallized area of ​​the M1 layer, a via pattern 427 indicating via structures between conductive lines indicated by conductive line pattern 425 and corresponding PO patterns, and a via pattern 428 indicating via structures between conductive lines indicated by conductive line pattern 425 in the M0 layer and conductive lines indicated by conductive line pattern 426 in the M1 layer.

[0054] The layout unit 430 includes a conductive line pattern 432 indicating conductive lines in another metallized region of the M0 layer, a conductive line pattern 434 indicating conductive lines in another metallized region of the M1 layer, a via pattern 436 indicating via structures between conductive lines indicated by conductive line pattern 432 and corresponding PO patterns, and a via pattern 438 indicating via structures between conductive lines indicated by conductive line pattern 432 in the M0 layer and conductive lines indicated by conductive line pattern 434 in the M1 layer. In some embodiments, conductive line patterns 425 and 432 are arranged based on the same metallization pitch as the M0 pitch between conductive line patterns 412 and 422.

[0055] In this non-limiting example, via pattern 414 and via pattern 424 face each other on the cell boundary between layout cell 410 and layout cell 420, are aligned with each other in the second direction (e.g., Y direction), and are arranged based on a via pitch (referred to and labeled as “VD pitch”). In this non-limiting example, via pattern 427 and via pattern 436 are opposite each other across the cell boundary, are aligned with each other in the second direction, and are arranged based on a via pitch (referred to and labeled as “VG pitch”). In this non-limiting example, via pattern 428 and via pattern 438 are opposite each other across the cell boundary, are aligned with each other in the second direction, and are arranged based on a via pitch (referred to and labeled as “V0 pitch”). Further, conductive line pattern 426 and conductive line pattern 434 are spaced apart by an end-to-end distance (referred to and labeled as “M1 EtE”).

[0056] In Figure 4A In this non-limiting example, based on the BSPDN configuration, there is no metallization region for power supply on the M0 layer between layout cell 410 and layout cell 420 and between layout cell 420 and layout cell 430. As a result, the cell height and / or the placement density of the cells in the second direction (e.g., Y direction) is limited by the capability of the manufacturing process for the minimum size of VD pitch, VG pitch, V0 pitch, and M1 EtE. In this example, the via pitch (VD pitch, VG pitch, or V0 pitch) is equal to the metallization pitch (M0 pitch). In some embodiments, to reduce the cell height, the minimum size of VD pitch, VG pitch, V0 pitch, and M1 EtE would be very small (e.g., less than 20 nanometers, nm) such that the corresponding structures can only be implemented based on more complex photolithography processes and / or introduction of additional masks, which corresponds to increased manufacturing cost and / or reduced yield.

[0057] In Figure 4B In this non-limiting example, first layout planar view 400 includes a CMD pattern 442 shared by layout cell 410 and layout cell 420, which indicates removal of material for defining drain / source terminals. Figure 4B In this non-limiting example, first layout planar view 400 also includes a CPO pattern 446 shared by layout cell 420 and layout cell 430, which indicates removal of material for defining gate structures. Figure 4B In this non-limiting example, based on the BSPDN configuration, the cell height and / or the placement density of the cells in the second direction is also limited by the capability of the removal process with respect to the minimum size of the CMD pattern width (e.g., width Wcmd) and the CMO pattern width (example width Wcpo).

[0058] Figures 5A to 5Bis a layout plan of different parts of the second layout plan example 500 according to some embodiments. As a non-limiting example, Figure 5A and Figure 5B constitute only part of the second layout plan 500. Other layout cells and layout patterns of the second layout plan 500 are omitted in Figure 5A and Figure 5B . Figure 5A includes a legend of various types of layout patterns used in Figure 5A and Figure 5B , which are the same as the legend presented in Figure 4A , and thus a detailed description thereof is omitted.

[0059] In Figure 5A and Figure 5B , the second layout plan 500 includes three layout cells 510, 520, and 530 stacked on top of each other in a second direction (e.g., Y direction). In some embodiments, the layout cells 510, 520, and 530 correspond to the layout cells 410, 420, and 430 in Figure 4A and Figure 4B . In this non-limiting example, the layout cell 520 is shifted by 1 CPP in a first direction (e.g., X direction) compared to the first layout plan 400 in Figure 4A and Figure 4B .

[0060] In Figure 5A , the layout cell 510 and the layout cell 520 include a VD pattern adjacent to a cell boundary between the layout cell 510 and the layout cell 520. When the layout cell 520 is offset by 1 CPP relative to the layout cell 510, the VD pattern adjacent to the cell boundary is located within a first region 542 having a first zigzag pattern along the cell boundary. Compared to the first layout plan 400, the VD pattern adjacent to the cell boundary has a via pitch (labeled as 'VD pitch') that is greater than a metallization pitch (M0 pitch) between two M0 patterns adjacent to the cell boundary. In this example, the via pitch (VD pitch') is the square root of the sum of (i) the square of the metallization pitch (M0 pitch) and (ii) the square of 1 CPP.

[0061] In Figure 5AIn particular, layout cell 520 and layout cell 530 include a VG pattern adjacent to a cell boundary between layout cell 520 and layout cell 530, and a VI pattern adjacent to a cell boundary between layout cell 520 and layout cell 530. When layout cell 520 is offset by 1 CPP relative to layout cell 530, the VG pattern adjacent to the cell boundary is within a second region 546 having a second zigzag pattern along the cell boundary. In comparison to first layout floorplan 400, the VG pattern adjacent to the cell boundary has a via pitch (labeled as VG pitch’) that is greater than the metallization pitch (M0 pitch). In this example, the via pitch (VG pitch’) is the square root of the sum of (i) the square of the metallization pitch (M0 pitch) and (ii) the square of 1 CPP. Similarly, the VO pattern adjacent to the cell boundary has a via pitch (labeled as VO pitch’) that is greater than the metallization pitch (M0 pitch). In some embodiments, the VD pitch’, the VG pitch’, and / or the VO pitch’ is at least twice the metallization pitch (e.g., M0 pitch) or at least the gate pitch (e.g., 1 CPP). In some embodiments, an end-to-end distance (labeled as Ml EtE’) between Ml patterns aligned along the second direction in layout floorplan 500 is greater than the Ml EtE in Figure 4A In some embodiments, the end-to-end distance (Ml EtE’) is also greater than the metallization pitch (M0 pitch).

[0062] In Figure 5A In the non-limiting example in Figure 4A In comparison to the example in Figure 5A The via pitch (VD pitch’ and VG pitch’) of the VD pattern and / or the VG pattern and / or the Ml EtE’ of the example in is magnified. In some embodiments, to achieve the same cell height, the magnified size of the VD pitch’, the VG pitch’, the VO pitch’, and / or the Ml EtE’ would reduce or eliminate the necessity of applying more complex photolithography processes and / or introducing additional masks, which corresponds to reduced manufacturing cost and / or improved yield in comparison to the example in Figure 4A

[0063] In Figure 5B In particular, layout cell 520 and layout cell 530 include a VG pattern adjacent to a cell boundary between layout cell 520 and layout cell 530, and a VI pattern adjacent to a cell boundary between layout cell 520 and layout cell 530. When layout cell 520 is offset by 1 CPP relative to layout cell 530, the VG pattern adjacent to the cell boundary is within a second region 546 having a second zigzag pattern along the cell boundary. In comparison to first layout floorplan 400, the VG pattern adjacent to the cell boundary has a via pitch (labeled as VG pitch’) that is greater than the metallization pitch (M0 pitch). In this example, the via pitch (VG pitch’) is the square root of the sum of (i) the square of the metallization pitch (M0 pitch) and (ii) the square of 1 CPP. Similarly, the VO pattern adjacent to the cell boundary has a via pitch (labeled as VO pitch’) that is greater than the metallization pitch (M0 pitch). In some embodiments, the VD pitch’, the VG pitch’, and / or the VO pitch’ is at least twice the metallization pitch (e.g., M0 pitch) or at least the gate pitch (e.g., 1 CPP). In some embodiments, an end-to-end distance (labeled as Ml EtE’) between Ml patterns aligned along the second direction in layout floorplan 500 is greater than the Ml EtE in Figure 5B ​In the second layout plan 500, a CPO pattern 556 shared by layout units 520 and 530 is also included, which indicates the removal of material for defining the gate structure. This is achieved through... Figure 5A The widths (Wcmd' and Wcpo') of the movable VD and VG patterns, CMD pattern 552 and CPO pattern 556 are increased at different portions along the respective cell boundaries without affecting the functionality of the corresponding drain / source terminals and gate structure. The resulting CMD pattern 552 and CPO pattern 556 have their respective serrated patterns along the respective cell boundaries. Figure 5B In the unrestricted examples, based on BSPDN configuration, and Figure 4A and Figure 4B Compared to the examples in the previous examples, the restrictions on cell height and / or cell placement density are relaxed by increasing the dimensions based on the CMD pattern width (e.g., width Wcmd') and CMO pattern width (e.g., width Wcpo' in the example). In some embodiments, the CMD pattern width (e.g., width Wcmd') and CMO pattern width (e.g., width Wcpo') are greater than the metallization pitch (e.g., M0 pitch) and are the same or within a 10% variation range.

[0064] Figure 5A and Figure 5B The layout plan view 500 is shown as a non-limiting example. In some embodiments, the VD and / or VG patterns of adjacent layout cells are placed within the corresponding areas of the zigzag pattern, regardless of whether the layout cells are misaligned, depending on how the layout cells are prepared as standard cells in the cell library and the arrangement of the placement positions of the layout cells.

[0065] Therefore, according to one or more embodiments of this disclosure, considering Figure 5A and Figure 5BIn some embodiments, the semiconductor device manufactured based on the BSPDN configuration includes a first circuit unit and a second circuit unit adjacent to the first circuit unit. In some embodiments, the first circuit unit includes a first one or more conductive lines in a first metallization line region of a first metallization layer (e.g., M0 layer) and includes a first one or more via structures below the first metal layer. In some embodiments, the second circuit unit includes a second one or more conductive lines in a second metallization line region of the first metallization layer (e.g., M0 layer) and includes a second one or more via structures below the first metal layer. In some embodiments, the first metallization line region and the second metallization line region are along a unit boundary. In some embodiments, based on a first one or more via structures between the first one or more drain / source conductive structures of the first circuit unit and the first metallization layer (i.e., via structures of the VD layer), and a second one or more via structures between the second one or more drain / source conductive structures of the second circuit unit and the first metallization layer (i.e., via structures of the VD layer), the first one or more via structures and the second one or more via structures are within a first region having a first zigzag pattern along the unit boundary (e.g., as shown in the first region 542). In some embodiments, based on a first one or more via structures between the first one or more gate structures of the first circuit unit and the first metallization layer (i.e., via structures of the VG layer), and a second one or more via structures between the second one or more gate structures of the second circuit unit and the first metallization layer (i.e., via structures of the VG layer), the first one or more via structures and the second one or more via structures are within a second region having a second zigzag pattern along the unit boundary (e.g., as shown in the second region 546).

[0066] In some embodiments, the cell boundaries extend along a first direction (e.g., the X direction), the first metallization line region and the second metallization line region are disposed based on a metallization pitch (e.g., M0 pitch) along a second direction (e.g., the Y direction) different from the first direction. In some embodiments, based on first one or more via structures (i.e., VD layer via structures) between the first metallization layer and first one or more drain / source conductive structures of the first circuit cell, and second one or more via structures (i.e., VD layer via structures) between the first metallization layer and second one or more drain / source conductive structures of the second circuit cell, the first one or more via structures and the second one or more via structures are disposed based on a first minimum via pitch (e.g., VD pitch) that is greater than the metallization pitch (e.g., M0 pitch). In some embodiments, based on first one or more via structures (i.e., VG layer via structures) between the first metallization layer and first one or more gate structures of the first circuit cell, and second one or more via structures (i.e., VG layer via structures) between the first metallization layer and second one or more gate structures of the second circuit cell, the first one or more via structures and the second one or more via structures are disposed based on a second minimum via pitch (e.g., VG pitch) that is greater than the metallization pitch (e.g., M0 pitch).

[0067] In some embodiments, the first circuit cell further includes third one or more via structures (i.e., V0 layer via structures) between the first metallization line region and a third metallization line region of a second metallization layer above the first metallization layer, and the second circuit cell further includes fourth one or more via structures between the second metallization line region and a fourth metallization line region of the second metallization layer. In some embodiments, the third one or more via structures are spaced apart from the fourth one or more via structures based on a third minimum via pitch (e.g., V0 pitch) that is at least greater than the metallization pitch (e.g., M0 pitch).

[0068] In some embodiments, the first circuit cell further includes a third conductive line of a second metallization layer (e.g., M1 layer), the second circuit cell further includes a fourth conductive line of the second metallization layer, and the third conductive line and the fourth conductive line are aligned along the second direction (e.g., the Y direction). In some embodiments, the third conductive line and the fourth conductive line are disposed based on a minimum end-to-end distance (e.g., M1 EtE) along the second direction that is greater than the metallization pitch (e.g., M0 pitch).

[0069] In some embodiments, the first one or more drain / source conductive structures and the second one or more drain / source conductive structures are spaced apart based on a CMD pattern (e.g., the CMD pattern 552) having a third zigzag pattern along the cell boundary. In some embodiments, the first one or more gate structures and the second one or more gate structures are spaced apart based on a CPO pattern (e.g., the PO pattern 556) having a fourth zigzag pattern along the cell boundary.

[0070] Figure 6 is a schematic diagram of a plurality of placement locations 600 of a layout plan of a semiconductor device according to some embodiments. In Figure 6 each rectangular box with the number 1, 2, vertically flipped 1, or vertically flipped 2 represents a placement location of a corresponding placement type. In some embodiments, each of the plurality of placement locations of the layout plan has a width along a first direction (e.g., the X direction) that corresponds to a gate pitch (e.g., 1 CPP) of the layout plan, and a height along a second direction (e.g., the Y direction) that corresponds to a standard cell height (e.g., 1H) of the layout plan.

[0071] In Figure 6 the plurality of placement locations 600 includes a plurality of rows of placement locations, such as rows 612, 614, 615, 616, and 617. In this example, rows 612, 614, and 616 include placement locations of a first placement type (labeled with the number 1) and placement locations of a second placement type (labeled with the number 2) that are arranged in an alternative manner along the first direction (e.g., the X direction), and are usable for placing standard layout cells of a standard cell height in a nominal form (e.g., a direction stored in a cell library). In addition, rows 615 and 617 include placement locations of a flipped first placement type (labeled as flipped 1) and a flipped second placement type (labeled as flipped 2) that are arranged in an alternative manner along the first direction (e.g., the X direction), and are usable for placing standard layout cells in a flipped form that corresponds to a mirror image of the nominal form about an axis along the first direction.

[0072] In this example, the placement locations of the first placement type (labeled with the number 1) in a row are contiguous with the placement locations of the flipped second placement type (labeled as flipped 2) in an adjacent row; and the placement locations of the second placement type (labeled with the number 2) in a row are contiguous with the placement locations of the flipped first placement type (labeled as flipped 1) in an adjacent row. Thus, the plurality of placement locations 600 includes the first placement type / flipped first placement type and the second placement type / flipped second placement type arranged in a checkerboard manner.

[0073] In some embodiments, the first placement type represents that a via pattern (e.g., a VD pattern or a VG pattern) is accommodated under the first metallization layer of the layout floorplan to be disposed adjacent to the reverse second direction side (e.g., also referred to and illustrated as the left side in Figure 6 ) of the corresponding placement location. In some embodiments, the second placement type represents that any via pattern (e.g., a VD pattern or a VG pattern) is prohibited to be adjacent to the reverse second direction side (e.g., also referred to and illustrated as the left side in Figure 6 ) of the corresponding placement location under the first metallization layer of the layout floorplan. Figure 6 In a non-limiting example in

[0074] In Figure 6 , to place a target layout cell 620 having a cell height of 1H and a cell width of 5CPP, a placement location group 630 is identified, which includes five consecutive placement locations in the same row (e.g., row 614) for placing the target layout cell 620. For example, the target layout cell 620 includes VD patterns 622, 624, and 626 of the first, third, and fifth regions defined by the gate pattern at its bottom, and is thus configured to be placed at the five consecutive placement locations with placement type markings [1, 2, 1, 2, 1].

[0075] In some embodiments, each circuit cell includes a plurality of candidate layout cells associated therewith for placement with the leftmost edge location being the first placement type, the flipped first placement type, the second placement type, and the flipped second placement type. In some embodiments, one of the plurality of candidate layout cells associated with a circuit cell is selected as a target layout cell at a placement location group based on the placement location type of the edge placement location (e.g., the leftmost edge location) of the placement location group in the reverse first direction. For example, the target layout cell 620 can be determined based on the leftmost edge placement location of the placement location group being the first placement type (marked with the number 1). Based on the checkerboard arrangement of the plurality of placement locations and the pre-designed candidate layout cells, as shown in Figure 5A and Figure 5B , placement constraints or guidelines of the zigzag pattern based on various features can be incorporated into electronic design automation (EDA) tools to enable efficient and / or automated cell placement.

[0076] Figures 7A-12B Non-limiting examples of candidate layout cells corresponding to various circuit cells. There can be one or more other methods to prepare candidate layout cells for use in conjunction with the checkerboard arrangement of the plurality of placement locations in Figure 6 to satisfy the constraints and guidelines in Figure 5A and Figure 5B . Figures 7A-7I , Figures 10B-10D and Figures 11B-11C include legends for various types of layout patterns identical to those presented in Figure 4A , and thus a detailed description thereof is omitted.

[0077] Figure 7A is a layout plan of a portion of a base layout cell example 700A according to some embodiments. In Figure 7A , the base layout cell 700A includes a PO pattern and M0 regions for conductive line patterns at the M0 layer as shown in the legend. In this non-limiting example, the base layout cell 700A has a cell width of 5 CPP along a first direction (e.g., X direction) and a cell height of 1 H along a second direction (e.g., Y direction), where CPP corresponds to a gate pitch and H corresponds to a standard cell height as described above. In this non-limiting example, the base layout cell 700A occupies five layout regions 701, 702, 703, 704, and 705 defined by adjacent PO patterns, where each layout region has a height of 1 H and a width of 1 CPP, corresponding to the placement locations in Figure 6 .

[0078] Figure 7B is a layout plan of a portion of a first layout cell 700B example based on the base layout cell 700A of Figure 7A according to some embodiments. In Figure 7B , the first layout cell 700B includes a PO pattern and M0 regions for conductive line patterns at the M0 layer as shown in the legend. In Figure 7B , the first layout cell 700B further includes a VD pattern candidate at layout region 701 located at the upper and bottom portions of the layout region 701; a VD pattern candidate at layout region 703 located at the upper and bottom portions of the layout region 703; and a VD pattern candidate at layout region 705 located at the upper and bottom portions of the layout region 705. Thus, each of the layout regions 701, 703, and 705 is based on accommodating a VD pattern at opposite sides adjacent to the layout region, while each of the layout regions 702 and 704 is based on prohibiting any VD pattern at opposite sides adjacent to the layout region. In this example, VD pattern candidates adjacent to the cell boundaries are allowed within regions 712, 714, and 716 parallel to the direction of the PO pattern. In some embodiments, a complementary counterpart to the example in Figure 7B is defined based on the first layout cell 700B such that each of the layout regions 701, 703, and 705 is based on prohibiting any VD pattern at opposite sides adjacent to the layout region, while each of the layout regions 702 and 704 is based on accommodating a VD pattern at opposite sides adjacent to the layout region.

[0079] Figure 7C is a layout plan of a portion of a first layout cell 700B example based on the base layout cell 700A of Figure 7Aa layout plan view of a portion of a second layout cell example 700C of the base layout cell 700A according to some embodiments. In Figure 7C the second layout cell 700C includes PO patterns and M0 regions for conductive line patterns at the M0 layer as indicated by the legend. In Figure 7C the second layout cell 700C also includes VG pattern candidates at layout regions 701, 703, and 705 adjacent to the upper side of the second layout cell 700C; and VG pattern candidates at layout regions 702 and 704 adjacent to the lower side of the second layout cell 700C. Thus, each of the layout regions 701, 703, and 705 is based on accommodating a VG pattern adjacent to one side of the layout region, while each of the layout regions 702 and 704 is based on prohibiting any VG pattern adjacent to the other side of the layout region. In this example, VG pattern candidates adjacent to the cell boundaries are allowed within regions 722 and 724 parallel to the direction of the PO patterns. In some embodiments, the second layout cell 700C defines a complementary counterpart to the example in Figure 7C .

[0080] Figure 7D is a layout plan view of a portion of a third layout cell 700D example of the base layout cell 700A according to some embodiments based on Figure 7A . In Figure 7D the third layout cell 700D includes PO patterns and M0 regions for conductive line patterns at the M0 layer as indicated by the legend. In Figure 7D the third layout cell 700D includes four layout regions 701', 702', 703', and 704' with respective PO patterns placed at their centers. In some embodiments, to determine the placement location type, the layout regions 701', 702', 703', and 704' are respectively associated with the layout regions 701, 702, 703, and 704 in Figure 7A .

[0081] In Figure 7D the third layout cell 700D also includes VG pattern candidates at the layout region 701' located at the upper and bottom portions of the layout region 701'; VG pattern candidates located at the upper and bottom portions of the layout region 703'. Thus, each of the layout regions 701' and 703' is based on accommodating a VG pattern adjacent to opposite sides of the layout region, while each of the layout regions 702' and 704' is based on prohibiting any VG pattern adjacent to opposite sides of the layout region. In this example, VG pattern candidates adjacent to the cell boundaries are allowed within regions 722 and 724 parallel to the direction of the PO patterns. In some embodiments, the third layout cell 700D defines a complementary counterpart to the example in Figure 7DThe complementary counterparts in the example are such that each of the layout areas 701' and 703' is based on prohibiting any VG pattern adjacent to the opposite side of the layout area, while each of the layout areas 702' and 704' is based on accommodating VG patterns adjacent to the opposite side of the layout area.

[0082] Figure 7E Based on some embodiments Figure 7A The layout plan of part of the fourth layout unit example 700E of the basic layout unit 700A. Figure 7E In the diagram, the fourth layout unit 700E includes a PO pattern and an M0 region for conductive line patterns at the M0 layer, as shown in the figure. Figure 7E In this embodiment, the fourth layout unit 700E also includes VG pattern candidates at layout areas 701' and 703' adjacent to the lower side of the fourth layout unit 700E; and VG pattern candidates at layout areas 702' and 704' adjacent to the upper side of the fourth layout unit 700E. Therefore, each of layout areas 701' and 703' is based on accommodating a VG pattern adjacent to one side of the layout area, while each of layout areas 702' and 704' is based on accommodating a VG pattern adjacent to the other side of the layout area. In this example, VG pattern candidates adjacent to the unit boundary are allowed within the region 728 with the zigzag pattern. In some embodiments, the fourth layout unit 700E is defined based on a vertically flipped fourth layout unit 700E. Figure 7E The complementary counterpart of the example in [the example].

[0083] Figure 7F Based on some embodiments Figure 7A The layout plan of the fifth layout unit 700F, an example of the basic layout unit 700A. Figure 7F In the diagram, the fifth layout unit 700F includes a PO pattern and an M0 region for conductive line patterns at the M0 layer, as shown in the example. Figure 7F In this embodiment, the fifth layout unit 700F also includes V0 pattern candidates located at the upper and lower parts of layout area 701; and V0 pattern candidates located at the upper and lower parts of layout area 703. Therefore, each of layout areas 701 and 703 is based on accommodating V0 patterns adjacent to the opposite side of the layout area, while each of layout areas 702 and 704 is based on prohibiting any V0 patterns adjacent to the opposite side of the layout area. In this example, V0 pattern candidates adjacent to the unit boundary are allowed within regions 732 and 734 parallel to the direction of the PO pattern. In some embodiments, the fifth layout unit 700F defines... Figure 7F The complementary counterparts of the examples in the example are such that each of the layout areas 701 and 703 is based on prohibiting any V0 pattern adjacent to the opposite side of the layout area, while each of the layout areas 702 and 704 is based on accommodating the V0 pattern adjacent to the opposite side of the layout area.

[0084] Figure 7G is a layout plan view of a portion of a sixth layout unit 700G example based on the base layout unit 700A according to some embodiments. In this example, the sixth layout unit 700G includes PO patterns and M0 regions for conductive line patterns at the M0 layer, as indicated by the legend. In this example, the upper and lower M0 regions adjacent to the upper and lower unit boundaries are adapted to form M0 conductive line patterns 742 associated with respective V0 patterns in Figure 7A Figure 7G Figure 7G In this example, the sixth layout unit 700G also includes V0 pattern candidates at layout regions 703 and 705 adjacent to the upper side of the sixth layout unit 700G; and V0 pattern candidates at layout regions 702 and 704 adjacent to the lower side of the sixth layout unit 700G. Thus, each of the layout regions 703 and 705 is based on accommodating a V0 pattern adjacent to one side of the layout region, while each of the layout regions 702 and 704 is based on accommodating a V0 pattern adjacent to the other side of the layout region. In this example, V0 pattern candidates adjacent to the unit boundaries are allowed within the area 738 having a zigzag pattern. In some embodiments, a complementary counterpart to the example in Figure 7G

[0085] Figure 7H is a layout plan view of a portion of a seventh layout unit 700H example based on the base layout unit 700A according to some embodiments. In this example, the seventh layout unit 700H includes PO patterns and M0 regions for conductive line patterns at the M0 layer, as indicated by the legend. In this example, the upper and lower M0 regions adjacent to the upper and lower unit boundaries are adapted to form M0 conductive line patterns 742 associated with respective V0 patterns in Figure 7A Figure 7H Figure 7H In this example, the upper and lower M0 regions adjacent to the upper and lower unit boundaries are adapted to form M0 conductive line patterns 742 associated with respective V0 patterns in Figure 7F In some embodiments, a complementary counterpart to the example in Figure 7F Figure 7H

[0086] Figure 7I is a layout plan view of a portion of an eighth layout unit 700I example based on the base layout unit 700A according to some embodiments. In this example, the eighth layout unit 700I includes PO patterns and M0 regions for conductive line patterns at the M0 layer, as indicated by the legend. In this example, the upper and lower M0 regions adjacent to the upper and lower unit boundaries are adapted to form M0 conductive line patterns 742 associated with respective V0 patterns in Figure 7A Figure 7I Figure 7I In this example, the upper and lower M0 regions adjacent to the upper and lower unit boundaries are adapted to form M0 conductive line patterns 742 associated with respective V0 patterns in Figure 7G In some embodiments, a complementary counterpart to the example in Figure 7G Figure 7I ​​​​​​​​​​complementary counterparts of the examples shown in

[0087] In some embodiments, Figures 7B-7I Various combinations of constraints represented by the examples and corresponding complementary counterparts of the examples in Figures 7A-7I In some embodiments, as non-limiting examples, Figure 6 The candidate layout units for placement location groups of the first placement type shown in Figure 7B , Figure 7D , Figure 7F and Figure 7H The first constraint combination based on the examples in Figure 7B , Figure 7E , Figure 7F and Figure 7H The second constraint combination based on the examples in Figure 7C , Figure 7D , Figure 7G and Figure 7I The third constraint combination based on the complementary counterparts of the examples in Figure 7C , Figure 7E , Figure 7G , and Figure 7I The fourth constraint combination based on the complementary counterparts of the examples in Figure 6 In some embodiments, as non-limiting examples, Figure 7B , Figure 7D , Figure 7F and Figure 7H The fifth constraint combination based on the complementary counterparts of the examples in Figure 7B , Figure 7E , Figure 7F and Figure 7H The sixth constraint combination based on the complementary counterparts of the examples in Figure 7C , Figure 7D , Figure 7G and Figure 7I The seventh constraint combination based on the examples in Figure 7C , Figure 7E , Figure 7G and Figure 7I The eighth constraint combination based on the examples in

[0088] Furthermore, not all flipped variants of the candidate layout units can be used to satisfy the constraints and criteria as shown in Figure 5A , Figure 5B and 6 In this regard, Figures 8A-8Care simplified layout floorplans of various flip variants of the base candidate layout cell according to some embodiments. In Figures 8A-8C In

[0089] In Figure 8A In the case where the cell width of the base candidate layout cell 812 is an odd number of CPP (e.g., the cell width is 5 CPP), the scenario where the leftmost edge placement location is of a particular placement type (e.g., the first placement type, labeled with the number 1 in this example) can be accommodated. In some embodiments, when there is a VD pattern, a V0 pattern, or an M0 track pattern associated with a V0 pattern adjacent to the lower side of the base candidate layout cell 812, and there is no VG pattern adjacent to the lower side of the base candidate layout cell 812, the horizontally flipped variant 814 (e.g., flipped with respect to the Y axis, indicated by the arrow with the label “MY”) of the base candidate layout cell 812 is still applicable for the case where the leftmost edge placement location is of the particular placement type. In some embodiments, when there is a VG pattern adjacent to the lower side of the base candidate layout cell 812, the horizontally flipped variant 814 is completely unusable. In some embodiments, when there is no VD pattern, V0 pattern, M0 track pattern associated with a V0 pattern, or VG pattern adjacent to the lower side of the base candidate layout cell 812, there is no restriction on using the horizontally flipped variant 814.

[0090] In Figure 8BIn some embodiments, the base candidate layout cell 822 has an even number of CPPs for a cell width (e.g., a cell width of 6 CPPs), and is usable for scenarios where the leftmost edge placement location is a particular placement type (e.g., a first placement type, labeled with the numeral 1 in this example). In some embodiments, a horizontally flipped variant 824 of the base candidate layout cell 822 is usable for scenarios where the leftmost edge placement location is a different placement type (e.g., a second placement type, labeled with the numeral 2 in this example) when there is a VD pattern, a V0 pattern, or an M0 track pattern associated with a V0 pattern adjacent to the bottom side of the base candidate layout cell 822, and there is no VG pattern adjacent to the top side of the base candidate layout cell 822. In some embodiments, the horizontally flipped variant 824 of the base candidate layout cell 822 is still usable for scenarios where the leftmost edge placement location is the particular placement type (e.g., the first placement type, labeled with the numeral 1 in this example) when there is no VD pattern, V0 pattern, or M0 track pattern associated with a V0 pattern adjacent to the bottom side of the base candidate layout cell 822, and there is a VG pattern adjacent to the bottom side of the base candidate layout cell 822. In some embodiments, the horizontally flipped variant 824 is completely unusable when there is a VD pattern, V0 pattern, M0 track pattern associated with a V0 pattern, or VG pattern adjacent to the bottom side of the base candidate layout cell 822. In some embodiments, there is no restriction on using the horizontally flipped variant 824 when there is no VD pattern, V0 pattern, M0 track pattern associated with a V0 pattern, or VG pattern adjacent to the bottom side of the base candidate layout cell 822.

[0091] In Figure 8C In this example with a cell height of 2H, the top-left corner edge placement location will be a flipped version of a different placement type (e.g., a flipped second placement type, labeled with a flipped numeral 2 in this example). In some embodiments, a vertically flipped variant 834 of the base candidate layout cell 832 (e.g., flipped with respect to the X-axis, indicated by the arrow with the label “MX”) is usable for scenarios where the bottom-left corner placement location is another placement type.

[0092] Figure 9A is a simplified layout plan view of a portion of a layout plan example 900A in accordance with some embodiments. In Figure 9A In this example, the layout plan 900A includes a plurality of placement locations, as referenced in Figure 6Similarly illustrated, where each rectangular box having the number 1, 2, 1 flipped vertically, or 2 flipped vertically represents a placement location of a different placement type. According to Figures 8A-8C the examples in Figure 9A the various layout cells serve as non-limiting examples of how layout cells and variants thereof can be placed with respect to placement locations.

[0093] In Figure 9A , a first base layout cell 910 is used for a set of placement collections where the leftmost edge placement location is of a first layout type. In this example, the cell width of the first base layout cell 910 is 5 CPP and the cell height is 1 H. In some embodiments, a layout cell 912 based on the first base layout cell 910 can also be used for scenarios where the leftmost edge placement location is of the first placement type. In some embodiments, a layout cell 914 based on the first base layout cell 910 flipped vertically can be used for scenarios where the leftmost edge placement location is of the flipped first placement type. In some embodiments, a layout cell 916 based on the first base layout cell 910 flipped horizontally can be used for scenarios where the leftmost edge placement location is of the first placement type. Further, in some embodiments, a layout cell 918 based on the layout cell 916 flipped vertically can be used for scenarios where the leftmost edge placement location is of the flipped first placement type.

[0094] Further, in this example, a second base layout cell 920 is used for a set of placement collections where the leftmost edge placement location is of a second layout type. In this example, the cell width of the second base layout cell 920 is 5 CPP and the cell height is 1 H. In some embodiments, a layout cell 922 based on the second base layout cell 920 flipped vertically can be used for scenarios where the leftmost edge placement location is of the flipped second layout type. In some embodiments, layout cells 924 and 926 based on the second base layout cell 920 flipped horizontally can be used for scenarios where the leftmost edge placement location is of the second placement type. Further, in some embodiments, a layout cell 928 based on the layout cell 926 flipped vertically can be used for scenarios where the leftmost edge placement location is of the flipped second placement type.

[0095] In some embodiments, according to Figure 9AIn the example, candidate layout units for circuit units having a cell width of 5 CPP and a cell height of 1 H include at least a first basic layout unit 910 with a first placement type at the leftmost edge and a second basic layout unit 920 with a second placement type at the leftmost edge. Simultaneously, a horizontally flipped first basic layout unit (e.g., layout unit 916) can also be used for the leftmost edge placement, i.e., the first placement type; and a horizontally flipped second basic layout unit (e.g., layout unit 926) can also be used for the scenario where the leftmost edge placement is the second layout type. That is, in some embodiments, in order to... Figure 6 The placement of the circuit cells (width: 5 CPP and height: 1 H) in the circuit provides four layout cell variations to meet the requirements. Figure 5A and Figure 5B The constraints and criteria are shown in the example.

[0096] Figure 9B This is a simplified layout plan view of a portion of layout plan example 900B according to some embodiments. Figure 9B In the layout plan 900B, there are multiple placement positions, as shown in the reference. Figure 6 Similarly shown, each rectangle with the numbers 1, 2, vertically flipped 1, or vertically flipped 2 indicates the placement position. According to Figures 8A-8C Examples in, Figure 9B The various layout units in the example serve as non-restrictive examples of how layout units and their variants can be placed relative to their placement location.

[0097] exist Figure 9B In this example, the basic layout unit 960 is used for a set of placements where the lower left edge placement position is a first layout type. In this example, the basic layout unit 960 has a unit width of 9 CPP and a unit height of 2H. In some embodiments, the layout unit 962 based on the basic layout unit 960 can also be used in scenarios where the lower left edge placement position is a first placement type and the upper left edge placement position is a flipped second placement type. In some embodiments, the layout unit 964 based on the vertically flipped basic layout unit 960 can be used in scenarios where the lower left edge placement position is a flipped second placement type. In some embodiments, the layout unit 976 based on the horizontally flipped basic layout unit 960 can be used in scenarios where the lower left edge placement position is a first placement type. Furthermore, in some embodiments, the layout units 972 and 974 based on the vertically flipped layout unit 970 can be used in scenarios where the lower left edge placement position is a second placement type.

[0098] In some embodiments, according to Figure 9BIn the example of FIG. 9, a candidate placement cell for a circuit cell having a cell width of 9 CPP and a cell height of 2H includes at least a base placement cell (e.g., base placement cell 960) with a lower-left corner edge placement location of a first placement type and a vertically flipped base placement cell (e.g., placement cell 964) with a lower-left corner edge placement location of a second placement type. That is, in some embodiments, two placement cell variants are prepared for a circuit cell (width: 9 CPP, height: 2H) to be placed in a layout with Figure 6 In the example of FIG. 9, a candidate placement cell for a circuit cell having a cell width of 9 CPP and a cell height of 2H includes at least a base placement cell (e.g., base placement cell 960) with a lower-left corner edge placement location of a first placement type and a vertically flipped base placement cell (e.g., placement cell 964) with a lower-left corner edge placement location of a second placement type. That is, in some embodiments, two placement cell variants are prepared for a circuit cell (width: 9 CPP, height: 2H) to be placed in a layout with Figure 5A and Figure 5B In the example of FIG. 9, a candidate placement cell for a circuit cell having a cell width of 9 CPP and a cell height of 2H includes at least a base placement cell (e.g., base placement cell 960) with a lower-left corner edge placement location of a first placement type and a vertically flipped base placement cell (e.g., placement cell 964) with a lower-left corner edge placement location of a second placement type. That is, in some embodiments, two placement cell variants are prepared for a circuit cell (width: 9 CPP, height: 2H) to be placed in a layout with

[0099] Figure 10A is a circuit diagram of an AND-OR-INVERT (AOI) logic 1000A according to some embodiments. In Figure 10A In the example of FIG. 9, a candidate placement cell for a circuit cell having a cell width of 9 CPP and a cell height of 2H includes at least a base placement cell (e.g., base placement cell 960) with a lower-left corner edge placement location of a first placement type and a vertically flipped base placement cell (e.g., placement cell 964) with a lower-left corner edge placement location of a second placement type. That is, in some embodiments, two placement cell variants are prepared for a circuit cell (width: 9 CPP, height: 2H) to be placed in a layout with Figure 10A In the example of FIG. 9, a candidate placement cell for a circuit cell having a cell width of 9 CPP and a cell height of 2H includes at least a base placement cell (e.g., base placement cell 960) with a lower-left corner edge placement location of a first placement type and a vertically flipped base placement cell (e.g., placement cell 964) with a lower-left corner edge placement location of a second placement type. That is, in some embodiments, two placement cell variants are prepared for a circuit cell (width: 9 CPP, height: 2H) to be placed in a layout with

[0100] In the example of FIG. 9, a candidate placement cell for a circuit cell having a cell width of 9 CPP and a cell height of 2H includes at least a base placement cell (e.g., base placement cell 960) with a lower-left corner edge placement location of a first placement type and a vertically flipped base placement cell (e.g., placement cell 964) with a lower-left corner edge placement location of a second placement type. That is, in some embodiments, two placement cell variants are prepared for a circuit cell (width: 9 CPP, height: 2H) to be placed in a layout with

[0101] In the example of FIG. 9, a candidate placement cell for a circuit cell having a cell width of 9 CPP and a cell height of 2H includes at least a base placement cell (e.g., base placement cell 960) with a lower-left corner edge placement location of a first placement type and a vertically flipped base placement cell (e.g., placement cell 964) with a lower-left corner edge placement location of a second placement type. That is, in some embodiments, two placement cell variants are prepared for a circuit cell (width: 9 CPP, height: 2H) to be placed in a layout with Figure 10AIn particular, the gate terminals of the P-type transistor 1014 and the N-type transistor 1022 are electrically coupled to the input terminal Al of the AOI logic 1000A. The gate terminals of the P-type transistor 1018 and the N-type transistor 1024 are electrically coupled to the input terminal A2 of the AOI logic 1000A. The gate terminals of the P-type transistor 1012 and the N-type transistor 1026 are electrically coupled to the input terminal Bl of the AOI logic 1000A. The gate terminals of the P-type transistor 1016 and the N-type transistor 1028 are electrically coupled to the input terminal B2 of the AOI logic 1000A. Thus, the AOI logic 1000A is configured to perform a logic operation based on the expression ZN = / (AlA2 + BlB2).

[0102] Figures 10B-10D is according to some embodiments Figure 10A a layout plan of a candidate placement unit of the AOI logic 1000A in Figures 10B-10D includes a legend of various types of layout patterns used therein, which are the same as the legends presented in Figure 4A and thus the detailed description thereof is omitted. In some embodiments, the candidate placement unit in Figures 10B-10D satisfies constraints based on various combinations of examples in Figures 7B-7E In some embodiments, multiple candidate placement units of the AOI logic 1000A can be used for having the leftmost (or lower-left) edge placement location as the first placement type or the second placement type, as shown in examples in Figure 6 and with reference to examples in Figures 7A to 9B

[0103] In Figure 10B , the cell width of the placement unit 1000B is 5 CPP and the cell height is 1 H. The placement unit 1000B is consistent with the constraint combinations based on examples in Figure 7B and Figure 7D The placement unit 1000B is also consistent with the constraint combinations based on examples in Figure 7B and Figure 7E In this example, the placement unit 1000B includes the VG patterns 1012, 1014, 1016, and 1018 corresponding to the input terminals Al, A2, Bl, and B2 in Figure 10A In this example, the placement unit 1000B also includes the Ml conductive line pattern 1022 corresponding to the output terminal ZN in Figure 10A

[0104] In Figure 10C , the cell width of the placement unit 1000B is 3 CPP and the cell height is 2 H. The placement unit 1000C is consistent with the constraint combinations based on examples in Figure 7C and Figure 7D In this example, the placement unit 1000C includes the VG patterns 1012, 1014, 1016, and 1018 corresponding to the input terminals Al, A2, Bl, and B2 in Figure 10A ​​input terminals A1, A2, B1, and B2 in the layout unit 1000C correspond to the VG patterns 1032, 1034, 1036, and 1038, respectively. In this example, the layout unit 1000C also includes the M1 conductive line pattern 1040 corresponding to the output terminal ZN in the layout unit 1000C. Figure 10A In this example, the layout unit 1000C includes the VG patterns 1032, 1034, 1036, and 1038 corresponding to the input terminals A1, A2, B1, and B2, respectively, in the layout unit 1000C. In this example, the layout unit 1000C also includes the M1 conductive line pattern 1040 corresponding to the output terminal ZN in the layout unit 1000C.

[0105] In Figure 10D , the layout unit 1000D has a cell width of 5 CPP and a cell height of 1 H. The layout unit 1000D is consistent with the constraints of the example based on Figure 7C and Figure 7E . In this example, the layout unit 1000D includes the VG patterns 1052, 1054, 1056, and 1058 corresponding to the input terminals A1, A2, B1, and B2, respectively, in the layout unit 1000D. In this example, the layout unit 1000D also includes the M1 conductive line pattern 1062 corresponding to the output terminal ZN in the layout unit 1000D. Figure 10A In this example, the layout unit 1000D includes the VG patterns 1052, 1054, 1056, and 1058 corresponding to the input terminals A1, A2, B1, and B2, respectively, in the layout unit 1000D. In this example, the layout unit 1000D also includes the M1 conductive line pattern 1062 corresponding to the output terminal ZN in the layout unit 1000D. Figure 10A

[0106] Figure 11A is a circuit diagram of NAND logic 1100A in accordance with some embodiments. In Figure 11A , the NAND logic 1100A includes P-type transistors 1112 and 1114 and N-type transistors 1116 and 1118. In Figure 11A , a first drain / source terminal of the P-type transistor 1112 and a first drain / source terminal of the P-type transistor 1114 are electrically coupled to a first power supply (labeled VDD). A second drain / source terminal of the P-type transistor 1112 and a second source / drain terminal of the P-type transistor 1114 are electrically coupled to an output terminal ZN of the NAND logic 1100A. A first drain / source terminal of the N-type transistor 1116 is electrically coupled to the output terminal ZN. A second drain / source terminal of the N-type transistor 1116 is electrically coupled to a first drain / source terminal of the N-type transistor 1118. A second drain / source terminal of the N-type transistor 1118 is electrically coupled to a second power supply (labeled GND).

[0107] In Figure 11A , gate terminals of the P-type transistor 1112 and the N-type transistor 1116 are electrically coupled to an input terminal A1 of the NAND logic 1100A. Gate terminals of the P-type transistor 1114 and the N-type transistor 1118 are electrically coupled to an input terminal A2 of the NAND logic 1100A. Thus, the NAND logic 1100A is configured to perform a logical operation based on the expression ZN = / A1A2.

[0108] Figures 11B-11C is a layout plan of a candidate layout unit for the NAND logic 1100A in Figure 11A in accordance with some embodiments. Figures 11B-11C ​including various types of layout patterns used therein, which are the same as the legends presented in Figure 4A and a detailed description thereof is omitted. In some embodiments, Figures 11B-11C satisfy the constraints based on Figures 7B-7E of the examples in Figure 6 and with reference to the examples in Figures 7A to 9B

[0109] In Figure 11B , the cell width of the layout cell 1100B is 3 CPP and the cell height is 1 H. The layout cell 1100B is consistent with the constraint combinations based on FIG. 7B and FIG. 7D , based on the constraint combinations of FIG. 7B and FIG. 7E , or based on the constraint combinations of FIG. 7C and FIG. 7D . In this example, the layout cell 1100B includes VG patterns 1122 and 1124 corresponding to input terminals Al and A2 in FIG. 11 A . In this example, the layout cell 1100B also includes M0 conductive line pattern 1132 corresponding to output terminal ZN in FIG. 11 A .

[0110] In FIG. 11 C , the cell width of the layout cell 1100C is 3 CPP and the cell height is 1 H. The layout cell 1100C is consistent with the constraint combinations based on FIG. 7C and FIG. 7E . In this example, the layout cell 1100C includes VG patterns 1142 and 1144 corresponding to input terminals Al and A2 in FIG. 11 A . In this example, the layout cell 1100C also includes M0 conductive line pattern 1152 corresponding to output terminal ZN in FIG. 11 A .

[0111] FIG. 12A is a diagram of a simplified layout plane example 1200A according to some embodiments. In FIG. 12A , the layout plane example 1200A includes a plurality of layout cells, which include gate patterns and corresponding VD patterns (not labeled). In FIG. 12A , based on the placement locations and constraints of the examples in FIG. 6 and taking into account the implementation examples in FIGS. 7A-11C , the VD patterns adjacent to the cell boundaries are arranged within regions 1210 having a sawtooth shape along the cell boundaries, satisfying as FIG. 5A ​constraints and guidelines shown.

[0112] FIG. 12B is a diagram of a simplified layout plan example 1200B, in accordance with some embodiments. In FIG. 12B the layout plan example 1200B includes a plurality of layout cells, including a gate pattern and a corresponding VG pattern (not labeled). In FIG. 12B the layout plan example 1200B, the VG pattern adjacent to the cell boundary is arranged within a region 1220 having a sawtooth shape along the cell boundary, based on the placement locations and constraints in the example of FIG. 6 and taking into account the implementation example in FIGS. 7A-11C satisfies the constraints and guidelines shown. FIG. 5A

[0113] FIG. 13 is a flowchart of a method 1300 of generating a layout plan of a semiconductor device, in accordance with some embodiments. In some embodiments, the various operations of the method 1300 correspond to various combinations of the examples in FIGS. 6-12B to satisfy the constraints or guidelines of the sawtooth pattern based on various features as shown in FIG. 5A and FIG. 5B In some embodiments, the method 1300 corresponds to one or more operations performed based in whole or in part on the EDA system 1500 as shown in FIG. 15 and / or the integrated circuit (IC) fabrication system 1600 as shown in FIG. 16 As shown in FIG. 13 the method 1300 includes blocks 1310-1330.

[0114] At block 1310, a first layout cell (e.g., the layout cell 510 or the layout cell 520 in FIGS. 5A-5B is placed in a layout plan (e.g., the layout plan 500). In some embodiments, the first layout cell indicates a first circuit cell, including a first one or more conductive line patterns (e.g., an M0 pattern for an M0 layer) indicating a first one or more conductive lines in a first metallization line region of a first metallization layer, and including a first one or more via patterns (e.g., a VD pattern for a VD layer or a VG pattern for a VG layer) indicating a first one or more via structures below the first metallization layer.

[0115] At block 1320, a second layout cell (e.g., the layout cell 510 or the layout cell 520 in FIGS. 5A-5B ​In some embodiments, the second layout unit represents a second circuit unit and abuts the first layout unit at a unit boundary between them. In some embodiments, the second layout unit includes a second one or more conductive line patterns (e.g., M0 patterns for an M0 layer) indicative of a second one or more conductive lines in a second metallization line region of the first metallization layer, and includes a second one or more via patterns (e.g., VD patterns for a VD layer or VG patterns for a VG layer) indicative of a second one or more via structures below the first metallization layer. In some embodiments, the first metallization line region and the second metallization line region are separated by a shared space that extends along the unit boundary.

[0116] In some embodiments, based on a first one or more via patterns and a second one or more via patterns (e.g., VD patterns for a VD layer) belonging to a first via layer between the first metallization layer and the drain / source conductive layer of the layout floorplan, the first one or more via patterns and the second one or more via patterns are located within a first region (e.g., first region 542 in FIG. 5A In some embodiments, based on a first one or more via patterns and a second one or more via patterns (e.g., VG patterns for a VG layer) belonging to a second via layer between the first metallization layer and the gate layer of the layout floorplan, the first one or more via patterns and the second one or more via patterns are located within a second region (e.g., second region 546 in FIG. 5A

[0117] At block 1330, the layout floorplan including the first layout unit and the second layout unit is stored in a memory of a processing device (e.g., EDA system 1500 in FIG. 15

[0118] In some embodiments, the unit boundary extends along a first direction, and the first metallization line region and the second metallization line region are disposed based on a metallization pitch along a second direction different from the first direction (e.g., M0 pitch in FIG. 5A In some embodiments, based on a first one or more via patterns and a second one or more via patterns (e.g., VD patterns for a VD layer) belonging to a first via layer between the first metallization layer and the drain / source conductive layer of the layout floorplan, the first one or more via patterns and the second one or more via patterns are located within a first region (e.g., first region 542 in FIG. 5A ​​the first one or more via patterns and the second one or more via patterns are set based on a first minimum via pitch (e.g., a VD pitch in FIG. 6B) that is greater than a metallization pitch (e.g., a VD pitch in FIG. 6A) and a second minimum via pitch (e.g., a VG pitch in FIG. 6B) that is greater than a gate pitch (e.g., a VG pitch in FIG. 6A). FIG. 5A the first one or more via patterns and the second one or more via patterns are set based on a first minimum via pitch (e.g., a VD pitch in FIG. 6B) that is greater than a metallization pitch (e.g., a VD pitch in FIG. 6A) and a second minimum via pitch (e.g., a VG pitch in FIG. 6B) that is greater than a gate pitch (e.g., a VG pitch in FIG. 6A).

[0119] In some embodiments, one or more gate patterns (e.g., a PO pattern in FIG. 6B) in the gate layer of the layout plan are set based on a gate pitch (e.g., a VG pitch in FIG. 6A) along the first direction. FIG. 5A In some embodiments, one or more gate patterns (e.g., a PO pattern in FIG. 6B) in the gate layer of the layout plan are set based on a gate pitch (e.g., a VG pitch in FIG. 6A) along the first direction. FIG. 5A In some embodiments, the first minimum via pitch (e.g., a VD pitch in FIG. 6B) is one of at least twice a metallization pitch or at least a gate pitch. FIG. 5A In some embodiments, the second minimum via pitch (e.g., a VG pitch in FIG. 6B) is one of at least twice a metallization pitch or at least a gate pitch. FIG. 5A In some embodiments, the second minimum via pitch (e.g., a VG pitch in FIG. 6B) is one of at least twice a metallization pitch or at least a gate pitch.

[0120] In some embodiments, the first layout cell further includes a third one or more via patterns (e.g., a V0 pattern of the layout cell 520 in FIG. 6B) belonging to a third via layer between the first metallization line region and a third metallization layer (e.g., a Ml layer) above the first metallization layer (e.g., a M0 layer); and the second layout cell further includes a fourth one or more via patterns (e.g., a V0 pattern of the layout cell 530 in FIG. 6B) belonging to the third via layer. FIG. 5A In some embodiments, the third one or more via patterns are spaced apart from the fourth one or more via patterns based on a third minimum via pitch (e.g., a V0 pitch in FIG. 6B) that is greater than a metallization pitch (e.g., a VD pitch in FIG. 6A). FIG. 5A In some embodiments, the third minimum via pitch is one of at least twice a metallization pitch or at least a gate pitch. FIG. 5A In some embodiments, the first layout cell further includes a third conductive line pattern (e.g., a Ml pattern of the cell 520 in FIG. 6B) of a second metallization layer (e.g., a Ml layer); and the second layout cell further includes a fourth conductive line pattern (e.g., a Ml pattern of the cell 530 in FIG. 6B) of the second metallization layer, and the third conductive line pattern and the fourth conductive line pattern are aligned along a second direction.

[0121] In some embodiments, the third conductive line pattern and the fourth conductive line pattern are based on a minimum end-to-end distance (e.g., a Ml pitch in FIG. 6B) along the second direction that is greater than a metallization pitch (e.g., a VD pitch in FIG. 6A). FIG. 5A In some embodiments, the third conductive line pattern and the fourth conductive line pattern are based on a minimum end-to-end distance (e.g., a Ml pitch in FIG. 6B) along the second direction that is greater than a metallization pitch (e.g., a VD pitch in FIG. 6A). FIG. 5A In some embodiments, the third conductive line pattern and the fourth conductive line pattern are based on a minimum end-to-end distance (e.g., a Ml pitch in FIG. 6B) along the second direction that is greater than a metallization pitch (e.g., a VD pitch in FIG. 6A). FIG. 5BM1 in FIG. 6A is set.

[0122] In some embodiments, the first layout cell and the second layout cell include portions of a CMD pattern (e.g., FIG. 5B of FIG. 6A, for defining the first one or more drain / source conductive structures of the first circuit cell and the second one or more drain / source conductive structures of the second circuit cell. In some embodiments, the CMD pattern has a third zigzag pattern along the cell boundary. In some embodiments, the first layout cell and the second layout cell include portions of a CPO pattern (e.g., FIG. 14 of FIG. 6A, for defining the first one or more gate structures of the first circuit cell and the second one or more gate structures of the second circuit cell. In some embodiments, the CPO pattern has a fourth zigzag pattern along the cell boundary.

[0123] FIGS. 6-12B is a flowchart of a method 1400 of generating a layout plan of a semiconductor device, in accordance with some embodiments. In some embodiments, various operations of the method 1400 correspond to various combinations of examples in FIG. 5A to meet constraints or criteria of zigzag patterns based on various features as shown in FIG. 5B and FIG. 15 In some embodiments, the method 1400 corresponds to one or more operations performed based in whole or in part on an EDA system 1500 as shown in FIG. 16 and / or an integrated circuit (IC) fabrication system 1600 as shown in FIG. 14 As shown in FIG. 6 the method 1400 includes blocks 1410-1430.

[0124] At block 1410, a set of placement positions (e.g., FIG. 6 of FIG. 6A) is obtained from a plurality of placement positions (e.g., FIG. 6 of FIG. 6A) of a layout plan of a target layout cell indicative of a target circuit cell. In some embodiments, each of the plurality of placement positions of the layout plan has a width along a first direction corresponding to a gate pitch (e.g., FIG. 6 of FIG. 6A) of the layout plan and a height along a second direction corresponding to a standard cell height (e.g., FIG. 5Acorresponding second direction. In some embodiments, the plurality of placement locations includes a first row of placement locations (e.g., row 612, 614, or 616) including first placement locations of a first placement type and second placement locations of a second placement type arranged in an alternating fashion along the first direction, which can be used to place a standard layout cell in a nominal form having a standard cell height. In some embodiments, the plurality of placement locations includes a second row of placement locations (e.g., row 615 or 617) including third placement locations of a flipped first placement type and fourth placement locations of a flipped second placement type arranged in an alternating fashion along the first direction, which can be used to place a standard layout cell in a flipped form corresponding to an axis mirror of the nominal form along the first direction. In some embodiments, the target layout cell has a cell height that is a standard cell height, or the cell height of the target layout cell is twice the standard cell height.

[0125] In some embodiments, as illustrated in the example of FIG. 5B and FIG. 6 , a shared space is defined along a boundary between the first row and the second row, where the shared space is free of any layout pattern in the first metallization layer of the layout floorplan. In some embodiments, as illustrated in the non-limiting example of FIG. 6 , a first placement location of the first row of placement locations is adjacent to a fourth placement location of the second row of placement locations. In some embodiments, as illustrated in the non-limiting example of FIG. 6 , a second placement location of the first row of placement locations is adjacent to a third type placement location of the second row of placement locations. In some embodiments, the first placement type indicates that a via pattern is accommodated under the first metallization layer of the layout floorplan disposed adjacent to a reverse second direction side of the corresponding placement location. In some embodiments, the second placement type indicates that any via pattern is prohibited from being disposed under the first metallization layer of the layout floorplan adjacent to a reverse second direction side of the corresponding placement location.

[0126] At block 1420, one of a plurality of candidate layout cells associated with the target circuit cell is placed as a target layout cell at the placement location group based on a placement location type (e.g., a leftmost edge placement location) of an edge placement location of the placement location group in a reverse first direction, as described in the non-limiting example of FIGS. 7A-11C , where the candidate layout cell is prepared according to the example of FIG. 5A .

[0127] In some embodiments, the plurality of candidate layout cells associated with the target circuit cell includes a candidate layout cell including a first one or more layout regions and a second one or more layout regions arranged in an alternating fashion along the first direction, and each of the first one or more layout regions and the second one or more layout regions corresponds to a respective placement location.

[0128] In some embodiments, each of the first one or more layout regions is based on accommodating, under the first metallization layer of the layout plane, a via pattern that is adjacently placed with a first side of the candidate layout cell, and prohibiting placement, under the first metallization layer of the layout plane, of any via pattern that is adjacently placed with a second side of the candidate layout cell. In some embodiments, each of the second one or more layout regions is based on accommodating, under the first metallization layer of the layout plane, a second via pattern that is adjacently placed with the second side of the candidate layout cell, and prohibiting placement, under the first metallization layer of the layout plane, of any via pattern that is adjacently placed with the first side of the candidate layout cell. In some embodiments, the first side and the second side of the candidate layout cell are opposite sides with respect to the second direction.

[0129] In some embodiments, each of the first one or more layout regions is based on accommodating, under the first metallization layer of the layout plane, a via pattern that is adjacently placed with a first side of the candidate layout cell, and prohibiting placement, under the first metallization layer of the layout plane, of any via pattern that is adjacently placed with a second side of the candidate layout cell. In some embodiments, each of the second one or more layout regions is based on accommodating, under the first metallization layer of the layout plane, a second via pattern that is adjacently placed with the second side of the candidate layout cell, and prohibiting placement, under the first metallization layer of the layout plane, of any via pattern that is adjacently placed with the first side of the candidate layout cell. In some embodiments, the first side and the second side of the candidate layout cell are opposite sides with respect to the second direction.

[0130] In some embodiments, the via pattern is between the first metallization layer of the layout plane and the first one or more drain / source conductive layers (e.g., the VD pattern in FIG. 5A In some embodiments, the via pattern is between the first metallization layer of the layout plane and the first one or more gate layers (e.g., the VG pattern in FIG. 15 In some embodiments, the via pattern is between the first metallization layer of the layout plane and the first one or more gate layers (e.g., the VG pattern in

[0131] At block 1430, the layout plane graph including the layout cell is stored in a memory of a processing device (e.g., the EDA system 1500 in FIG. 15 At block 1430, the layout plane graph including the layout cell is stored in a memory of a processing device (e.g., the EDA system 1500 in

[0132] FIG. 16 is a block diagram of an EDA system 1500 according to some embodiments. In some embodiments, the EDA system 1500 includes an automatic placement and routing (APR) system. According to some embodiments, the methods described herein with respect to layout cell placement are implementable, e.g., using the EDA system 1500.

[0133] In some embodiments, the EDA system 1500 is a general purpose computing device including a hardware processor 1502 and a memory 1504, the memory 1504 including a non-transitory computer readable storage medium. Among other things, the memory 1504 is encoded (i.e., stored) with computer program code 1506 (i.e., a set of executable instructions). Execution of the instructions 1506 by the hardware processor 1502 represents (at least in part) an EDA tool that implements some or all of the methods (hereinafter referred to as the processes and / or methods) described herein in accordance with one or more embodiments.

[0134] The processor 1502 is electrically coupled to the memory 1504 via a bus 1508. The processor 1502 is also electrically coupled to an I / O interface 1510 by the bus 1508. A network interface 1512 is also electrically connected to the processor 1502 via the bus 1508. The network interface 1512 is connected to a network 1514, enabling the processor 1502 and the memory 1504 to connect to external elements via the network 1514. The processor 1502 is configured to execute the computer program code 1506 encoded in the memory 1504 to make the system 1500 available to perform some or all of the processes and / or methods. In one or more embodiments, the processor 1502 is a central processing unit (CPU), a multi-processor, a distributed processing system, an application specific integrated circuit (ASIC), and / or a suitable processing unit.

[0135] In one or more embodiments, the memory 1504 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). For example, the memory 1504 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), rigid disk, and / or optical disk. In one or more embodiments that use optical disks, the memory 1504 includes compact disk read-only memory (CD-ROM), compact disk read / write (CD-R / W), and / or digital video disk (DVD).

[0136] In one or more embodiments, the memory 1504 stores computer program code 1506 that is configured to make the system 1500 (where such execution represents (at least in part) an EDA tool) available to perform some or all of the processes and / or methods. In one or more embodiments, the memory 1504 also stores information that facilitates the performance of some or all of the processes and / or methods. In one or more embodiments, the memory 1504 stores a standard cell library 1507 that includes standard cells disclosed herein. In one or more embodiments, the memory 1504 stores one or more layout maps 1509 corresponding to one or more layouts disclosed herein.

[0137] EDA system 1500 includes I / O interface 1510. I / O interface 1510 is coupled to external circuits. In one or more embodiments, I / O interface 1510 includes a keyboard, a keypad, a mouse, a trackball, a trackpad, a touchscreen, and / or cursor direction keys for communicating information and commands to processor 1502.

[0138] EDA system 1500 also includes network interface 1512 coupled to processor 1502. Network interface 1512 allows system 1500 to communicate with network 1514 to which one or more other computer systems are connected. Network interface 1512 includes a wireless network interface, such as Bluetooth, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface, such as Ethernet, USB, or IEEE- 1364. In one or more embodiments, part or all of the processes and / or methods are implemented in two or more systems 1500.

[0139] System 1500 is configured to receive information through I / O interface 1510. The information received through I / O interface 1510 includes one or more of instructions, data, design rules, standard cell libraries, and / or other parameters for processing by processor 1502. The information is transferred to processor 1502 via bus 1508. EDA system 1500 is configured to receive information related to a UI through I / O interface 1510. The information is stored in memory 1504 as user interface (UI) 1542.

[0140] In some embodiments, part or all of the processes and / or methods are implemented as a standalone software application executed by a processor. In some embodiments, part or all of the processes and / or methods are implemented as a software application that is part of an additional software application. In some embodiments, part or all of the processes and / or methods are implemented as a plug-in to a software application. In some embodiments, at least one of the processes and / or methods is implemented as a software application that is part of an EDA tool. In some embodiments, part or all of the processes and / or methods are implemented as a software application used by EDA system 1500. In some embodiments, a tool such as Design Compiler® from CADENCE DESIGN SYSTEMS, INC. or another suitable layout generation tool is used to generate the layout plan including the standard cells.

[0141] In some embodiments, the processes are implemented as functions of a program stored in a non-transitory computer readable recording medium. Examples of the non-transitory computer readable recording medium include, but are not limited to, one or more of external / removable and / or internal / built-in storage or storage units, such as one or more of optical storage (e.g., DVD), magnetic storage (e.g., hard disk), semiconductor memory (e.g., ROM), RAM, memory cards, and the like.

[0142] FIG. 16 is a block diagram of an integrated circuit (IC) manufacturing system 1600 and its associated IC manufacturing flow in accordance with some embodiments. In some embodiments, at least one of (A) one or more semiconductor masks or (B) at least one component in a semiconductor integrated circuit layer is manufactured using the manufacturing system 1600 based on a layout plan.

[0143] In FIG. 16 the IC manufacturing system 1600 includes entities that interact in the design, development, and manufacturing cycle and / or services related to manufacturing IC devices 1660, such as a design house 1620, a mask house 1630, and an IC foundry / fabric (Fab) 1650. The entities in the system 1600 are connected through a communication network. In certain embodiments, the communication network is a single network. The communication network includes wired and / or wireless communication channels. Each entity interacts with and provides services to and receives services from one or more other entities. In some embodiments, two or more of the design house 1620, the mask house 1630, and the IC foundry 1650 are owned by a single larger company. In some embodiments, two or more of the design house 1620, the mask house 1630, and the IC foundry 1650 coexist in a common facility and use common resources.

[0144] The design house (or design team) 1620 generates an IC design layout 1622. The IC design layout 1622 includes various geometric patterns designed for the IC devices 1660. The geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that make up various components of the IC devices 1660 to be manufactured. The layers combine to form various IC features. For example, portions of the IC design layout 1622 include various IC features, such as active regions, gate electrodes, source and drain electrodes, metal lines or vias for interlayer interconnections, and openings for pads, that are to be formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. The design house 1620 implements appropriate design processes to form the IC design layout 1622. The design processes include one or more of logic design, physical design, or placement and routing. The IC design layout 1622 is presented in the form of one or more data files with geometric pattern information. For example, the IC design layout 1622 can be represented in a GDSII file format or a DFII file format.

[0145] The mask room 1630 includes data preparation 1632 and mask manufacturing 1644. The mask room 1630 uses the IC design layout 1622 to manufacture one or more masks 1645 for use in fabricating individual layers of the IC device 1660 according to the IC design layout plan 1622. The mask room 1630 performs mask data preparation 1632 in which the IC design layout 1622 is converted to a representative data file (RDF). The mask data preparation 1632 provides the RDF to the mask manufacturing 1644. The mask manufacturing 1644 includes a mask writer. The mask writer converts the RDF to an image on a substrate, such as a mask (reticle) 1645 or a semiconductor wafer 1653. The design layout 1622 is manipulated by the mask data preparation 1632 to conform to the particular characteristics of the mask writer and / or the requirements of the IC foundry 1650. In ​ In some embodiments, the mask data preparation 1632 and the mask manufacturing 1644 can be collectively referred to as mask data preparation.

[0146] In some embodiments, the mask data preparation 1632 includes optical proximity correction (OPC) that uses lithography enhancement techniques to compensate for image errors, such as can be caused by diffraction, interference, other process effects, etc. The OPC adjusts the IC design layout 1622. In some embodiments, the mask data preparation 1632 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase shift masks, other suitable techniques, etc. or combinations thereof. In some embodiments, inverse lithography techniques (ILT) are also used, which treat the OPC as an inverse imaging problem.

[0147] In some embodiments, the mask data preparation 1632 includes a mask rule checker (MRC) that checks the IC design layout 1622 that has been processed in the OPC using a set of mask creation rules that contain certain geometric and / or connectivity restrictions to ensure sufficient margins to account for variability of the semiconductor manufacturing process, etc. In some embodiments, the MRC modifies the IC design layout 1622 to compensate for lithographic implementation effects during the mask manufacturing 1644, which can undo some of the modifications performed by the OPC to satisfy the mask creation rules.

[0148] In some embodiments, mask data preparation 1632 includes lithography process check (LPC), which simulates the processing to be performed by IC foundry 1650 to manufacture IC device 1660. LPC simulates the processing based on IC design layout 1622 to create a simulated manufactured device, such as IC device 1660. The processing parameters in the LPC simulation can include parameters related to various processes of the IC manufacturing cycle, parameters related to tools used to manufacture the IC, and / or other aspects of the manufacturing process. The LPC takes into account various factors, such as, for example, aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, and / or combinations thereof. In some embodiments, after the LPC creates a simulated manufactured device, if the shape of the simulated device is not close enough to meet design rules, then OPC and / or MRC are repeated to further refine IC design layout 1622.

[0149] It should be appreciated that the above description of mask data preparation 1632 has been simplified for clarity. In some embodiments, data preparation 1632 includes additional features, such as logic operations (LOP) that modify IC design layout 1622 according to manufacturing rules. Furthermore, the processes applied to IC design layout 1622 during data preparation 1632 can be performed in various different orders.

[0150] After mask data preparation 1632 and during mask manufacturing 1644, a mask 1645 or a set of masks 1645 is manufactured based on the modified IC design layout 1622. In some embodiments, mask manufacturing 1644 includes performing one or more photolithography exposures based on the IC design layout 1622. In some embodiments, based on the modified IC design layout 1622, a pattern is formed on a mask (photomask or reticle) 1645 using an e-beam or multiple e-beams mechanism. The mask 1645 can be formed using various techniques. In some embodiments, the mask 1645 is formed using binary technology. In some embodiments, the mask pattern includes opaque regions and transparent regions. A beam of radiation, such as an ultraviolet (UV) beam, used to expose a layer of image-sensitive material (e.g., photoresist) that has been coated on a wafer, is blocked by the opaque regions and transmitted through the transparent regions. In one example, a binary mask version of the mask 1645 includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque regions of the binary mask. In another example, the mask 1645 is formed using phase shift technology. In a phase shift mask (PSM) version of the mask 1645, various features in the pattern formed on the phase shift mask are configured to have appropriate phase differences to improve resolution and imaging quality. In various examples, the phase shift mask can be an attenuated PSM or an alternating PSM. The mask generated by mask manufacturing 1644 is used for various processes. For example, such mask is used in an ion implantation process to form various doped regions in a semiconductor wafer 1653, the mask is used in an etching process to form various etched regions in a semiconductor wafer 1654, and / or used in other suitable processes.

[0151] The IC foundry 1650 is an IC manufacturing enterprise that includes one or more manufacturing facilities for manufacturing various different IC products. In some embodiments, the IC foundry 1650 is a semiconductor foundry. For example, there can be one manufacturing facility for front-end manufacturing (front-end-of-line (FEOL) manufacturing) of multiple IC products, while a second manufacturing facility can provide back-end manufacturing (back-end-of-line (BEOL) manufacturing) for interconnection and packaging of the IC products, and a third manufacturing facility can provide other services for the foundry business.

[0152] The IC foundry 1650 includes manufacturing tools 1652 configured to perform various manufacturing operations on semiconductor wafers 1653 to manufacture IC devices 1660 according to masks (e.g., masks 1645). In various embodiments, the manufacturing tools 1652 include one or more of a wafer stepper, an ion implant machine, a photoresist coater, a process chamber (e.g., a CVD chamber or an LPCVD furnace), a CMP system, a plasma etching system, a wafer cleaning system, or other manufacturing equipment capable of performing one or more suitable manufacturing processes described herein.

[0153] IC foundry 1650 uses the mask 1645 manufactured by the mask room 1630 to manufacture an IC device 1660. Thus, the IC foundry 1650 uses the IC design layout 1622, at least indirectly, to manufacture the IC device 1660. In some embodiments, a semiconductor wafer 1653 is manufactured by the IC foundry 1650 using the mask 1645 to form the IC device 1660. In some embodiments, the IC manufacturing includes performing one or more photolithography exposures based at least indirectly on the IC design layout 1622. The semiconductor wafer 1653 includes a silicon substrate or other suitable substrate having material layers formed thereon. The semiconductor wafer 1653 also includes one or more of various doped regions, dielectric features, multilevel interconnects, etc. (formed in subsequent manufacturing steps).

[0154] In some aspects, a semiconductor device includes a first circuit unit including a first one or more conductive lines located in a first metallization line region of a first metallization layer and including a first one or more via structures located below the first metallization layer; and a second circuit unit contiguous with the first circuit unit at a unit boundary between the first circuit unit and the second circuit unit, the second circuit unit including a second one or more conductive lines located in a second metallization line region of the first metallization layer and including a second one or more via structures located below the first metallization layer. The first metallization line region and the second metallization line region are separated by a shared space extending along the unit boundary. The first one or more via structures are located within a first region having a first zigzag pattern along the unit boundary based on the first one or more via structures between the first metallization layer and a first one or more drain / source conductive structures of the first circuit unit and the second one or more via structures between the first metallization layer and a second one or more drain / source conductive structures of the second circuit unit. The first one or more via and the second one or more via structures are located within a second region having a second zigzag pattern along the unit boundary based on the first one or more via structures between the first metallization layer and a first one or more gate structures of the first circuit unit and the second one or more via structures between the first metallization layer and a second one or more gate structures of the second circuit unit.

[0155] In some embodiments, the cell boundary extends along a first direction, the first and second metallization line regions are disposed based on a metallization pitch along a second direction different from the first direction, the first and second one or more via structures are disposed based between the first metallization layer and the first one or more drain / source conductive structures of the first circuit cell and between the first metallization layer and the second one or more drain / source conductive structures of the second circuit cell, the first and second one or more via structures are disposed based on a first minimum via pitch greater than the metallization pitch, and the first and second one or more via structures are disposed based between the first metallization layer and the first one or more gate structures of the first circuit cell and between the first metallization layer and the second one or more gate structures of the second circuit cell, the first and second one or more via structures are disposed based on a second minimum via pitch greater than the metallization pitch.

[0156] In some embodiments, the first and second one or more gate structures are disposed based on a gate pitch along the first direction, the first minimum via pitch is one of at least twice the metallization pitch or at least the gate pitch, and the second minimum via pitch is one of at least twice the metallization pitch or at least the gate pitch.

[0157] In some embodiments, the first circuit cell further includes a third one or more via structures between the first metallization line region and a third metallization line region of a second metallization layer above the first metallization layer, the second circuit cell further includes a fourth one or more via structures between the second metallization line region and a fourth metallization line region of the second metallization layer, and the third and fourth one or more via structures are spaced apart based on a third minimum via pitch greater than at least the metallization pitch.

[0158] In some embodiments, the third minimum via pitch is one of at least twice the metallization pitch or at least the gate pitch.

[0159] In some embodiments, the first circuit cell further includes a third conductive line of the second metallization layer, the second circuit cell further includes a fourth conductive line of the second metallization layer, the third and fourth conductive lines are aligned along the second direction, and the third and fourth conductive lines are disposed based on a minimum end-to-end distance along the second direction greater than the metallization pitch.

[0160] In some embodiments, the first and second one or more drain / source conductive structures are spaced apart based on a cut diffusion over metal (CMD) pattern, and the CMD pattern has a third zigzag pattern along the cell boundary.

[0161] In some embodiments, the first one or more gate structures and the second one or more gate structures are spaced apart based on a cut poly-silicon (CPO) pattern, and the CPO pattern has a fourth zigzag pattern along the cell boundary.

[0162] In some aspects, a method of generating a layout plan for a semiconductor device includes placing a first layout cell in the layout plan, and placing a second layout cell in the layout plan. The first layout cell is indicative of a first circuit cell, including a first one or more conductive line patterns indicative of a first one or more conductive lines in a first metallization line region of a first metallization layer, and including a first one or more via patterns indicative of a first one or more via structures below the first metallization layer. The second layout cell is contiguous with the first layout cell at a cell boundary between the first layout cell and the second layout cell, the second layout cell is indicative of a second circuit cell, including a second one or more conductive line patterns indicative of a second one or more conductive lines in a second metallization line region of the first metallization layer, and including a second one or more via patterns indicative of a second one or more via structures below the first metallization layer. The method further includes storing the layout plan including the first layout cell and the second layout cell into a memory of a processing device. The first metallization line region and the second metallization line region are separated by a shared space extending along the cell boundary. Based on the first one or more via patterns and the second one or more via patterns belonging to a first via layer between the first metallization layer and a drain / source conductive layer in the layout plan, the first one or more via patterns and the second one or more via patterns are located within a first region having a first zigzag pattern along the cell boundary. Based on the first one or more via patterns and the second one or more via patterns belonging to a second via layer between the first metallization layer and a gate layer in the layout plan, the first one or more via patterns and the second one or more via patterns are located within a second region having a second zigzag pattern along the cell boundary.

[0163] In some embodiments, the cell boundary extends along a first direction, the first metallization line region and the second metallization line region are disposed based on a metallization pitch along a second direction different from the first direction, based on the first one or more via patterns and the second one or more via patterns belonging to a first via layer between the first metallization layer and a drain / source conductive layer in the layout plan, the first one or more via patterns and the second one or more via patterns are disposed based on a first minimum via pitch greater than the metallization pitch, and based on the first one or more via patterns and the second one or more via patterns belonging to a second via layer between the first metallization layer and a gate layer in the layout plan, the first one or more via patterns and the second one or more via patterns are disposed based on a second minimum via pitch greater than the metallization pitch.

[0164] In some embodiments, one or more gate patterns in the gate layer of the layout floorplan are disposed based on a gate pitch along the first direction, the first minimum via pitch is one of at least twice the metallization pitch or at least the gate pitch, and the second minimum via pitch is one of at least twice the metallization pitch or at least the gate pitch.

[0165] In some embodiments, the first layout unit further includes a third one or more via patterns belonging to a third via layer, the third via layer is located between the first metallization line region and a third metallization line region of a second metallization layer above the first metallization line region, the second layout unit further includes a fourth one or more via patterns belonging to the third via layer, and the third one or more via patterns and the fourth one or more via patterns are spaced apart based on a third minimum via pitch that is at least greater than the metallization pitch.

[0166] In some embodiments, the third minimum via pitch is one of at least twice the metallization pitch or at least the gate pitch.

[0167] In some embodiments, the first layout unit further includes a third conductive line pattern of a second metallization layer, the second layout unit further includes a fourth conductive line pattern of the second metallization layer, the third conductive line pattern and the fourth conductive line pattern are aligned along the second direction, and the third conductive line pattern and the fourth conductive line pattern are disposed based on a minimum end-to-end distance along the second direction that is greater than the metallization pitch.

[0168] In some embodiments, the first layout unit and the second layout unit include portions of a cut diffusion upper metal (CMD) pattern for defining the first one or more drain / source conductive structures of the first circuit unit and the second one or more drain / source conductive structures of the second circuit unit, and the CMD pattern has a third zigzag pattern along the unit boundary.

[0169] In some embodiments, the first layout unit and the second layout unit include portions of a cut polysilicon (CPO) pattern for defining the first one or more gate structures of the first circuit unit and the second one or more gate structures of the second circuit unit, and the CPO pattern has a fourth zigzag pattern along the unit boundary.

[0170] In some aspects, a method of generating a layout plan for a semiconductor device includes obtaining, from a plurality of placement locations of the layout plan, a placement location group for indicating a target layout cell of a target circuit cell. Each of the plurality of placement locations of the layout plan has a width corresponding to a gate pitch of the layout plan along a first direction and a height corresponding to a standard cell height of the layout plan along a second direction. The plurality of placement locations includes a first row of placement locations including first placement locations of a first placement type and second placement locations of a second placement type arranged in an alternating fashion along the first direction and usable for placing a standard layout cell of the standard cell height in a nominal form. The plurality of placement locations includes a second row of placement locations including third placement locations of a flipped first placement type and fourth placement locations of a flipped second placement type arranged in an alternating fashion along the first direction and usable for placing the standard layout cell in a flipped form corresponding to an axis mirror of the nominal form along the first direction. A shared space is defined along a boundary between the first row and the second row, the shared space being free of any layout pattern in a first metallization layer of the layout plan. The first placement locations of the placement locations of the first row are contiguous to the fourth placement locations of the placement locations of the second row, and the second placement locations of the placement locations of the first row are contiguous to the third placement locations of the placement locations of the second row. The first placement type indicates that a via pattern disposed at an adjacent of a reverse second direction side of a respective placement location is accommodated under the first metallization layer of the layout plan. The second placement type indicates that any via pattern disposed at an adjacent of the reverse second direction side of a corresponding placement location is prohibited under the first metallization layer of the layout plan. The method includes placing one of a plurality of candidate layout cells associated with the target circuit cell as the target layout cell on the placement location group based on a placement location type of an edge placement location of the placement location group in the reverse first direction. The method further includes storing the layout plan including the layout cell into a memory of a processing device.

[0171] In some embodiments, the plurality of candidate layout cells associated with the target circuit cell includes a candidate layout cell including a first one or more layout regions and a second one or more layout regions arranged in an alternating fashion along the first direction, each of the first one or more layout regions and the second one or more layout regions corresponding to a respective placement location, each of the first one or more layout regions being based on accommodating a via pattern disposed at an adjacent of an opposite side of the candidate layout cell relative to the second direction under a first metallization layer of the layout plan, and each of the second one or more layout regions being based on prohibiting any via pattern disposed at the adjacent of the opposite side of the candidate layout cell relative to the second direction under the first metallization layer of the layout plan.

[0172] In some embodiments, the plurality of candidate placement cells associated with the target circuit cell includes a candidate placement cell that includes a first one or more placement regions and a second one or more placement regions arranged in an alternating fashion along a first direction, each of the first one or more placement regions and the second one or more placement regions corresponding to a respective placement location, each of the first one or more placement regions is based on accommodating placement of a first via pattern adjacent to a first side of the candidate placement cell under a first metallization layer of a layout floorplan and prohibiting placement of any via pattern adjacent to a second side of the candidate placement cell under the first metallization layer of the layout floorplan, each of the second one or more placement regions is based on accommodating placement of a second via pattern adjacent to the second side of the candidate placement cell under the first metallization layer of the layout floorplan and prohibiting placement of any via pattern adjacent to the first side of the candidate placement cell under the first metallization layer of the layout floorplan, and the first side of the candidate placement cell and the second side of the candidate placement cell are opposite sides with respect to a second direction.

[0173] In some embodiments, the cell height of the target placement cell is a standard cell height, or, the cell height of the target placement cell is twice a standard cell height.

[0174] The foregoing summarizes features of several embodiments in order that a person skilled in the art can better understand various aspects of the present disclosure. Those skilled in the art will readily understand that they can readily employ the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and alterations within the scope and spirit of the present disclosure.

Claims

1. A semiconductor device, comprising: The first circuit unit includes one or more conductive lines located in a first metallization line region of the first metallization layer, and includes one or more via structures located below the first metallization layer. as well as The second circuit unit is adjacent to the first circuit unit at the unit boundary between the first circuit unit and the second circuit unit. The second circuit unit includes one or more second conductive lines located in the second metallization line region of the first metallization layer, and includes one or more second via structures located below the first metallization layer. in, The first metallized line region and the second metallized line region are separated by a shared space extending along the cell boundary. Based on the first or more via structures located between the first metallization layer and the first or more drain / source conductive structures of the first circuit unit, and the second or more via structures located between the first metallization layer and the second or more drain / source conductive structures of the second circuit unit, the first or more via structures and the second or more via structures are located within a first region having a first serrated pattern along the cell boundary, and Based on the first one or more via structures located between the first metallization layer and the first one or more gate structures of the first circuit unit, and the second one or more via structures located between the first metallization layer and the second one or more gate structures of the second circuit unit, the first one or more via structures and the second one or more via structures are located in a second region having a second serrated pattern along the cell boundary.

2. The semiconductor device according to claim 1, wherein, The unit boundary extends along a first direction. The first metallized line region and the second metallized line region are configured based on a metallization pitch along a second direction different from the first direction. Based on a first or more via structures located between the first metallization layer and the first or more drain / source conductive structures of the first circuit unit, and a second or more via structures located between the first metallization layer and the second or more drain / source conductive structures of the second circuit unit, the first or more via structures and the second or more via structures are provided based on a first minimum via pitch greater than the metallization pitch, and Based on the first one or more via structures located between the first metallization layer and the first one or more gate structures of the first circuit unit, and the second one or more via structures located between the first metallization layer and the second one or more gate structures of the second circuit unit, the first one or more vias and the second one or more vias are provided based on a second minimum via pitch greater than the metallization pitch.

3. The semiconductor device according to claim 2, wherein, The first or more gate structures and the second or more gate structures are configured based on the gate pitch along the first direction. The first minimum via pitch is one of the following: at least twice the metallization pitch or at least the gate pitch, and The second minimum via pitch is one of the following: at least twice the metallization pitch or at least the gate pitch.

4. The semiconductor device according to claim 2, wherein, The first circuit unit further includes a third or more via structures located between the first metallization line region and the third metallization line region of the second metallization layer above the first metallization layer. The second circuit unit further includes a fourth or more via structures located between the second metallization line region and the fourth metallization line region of the second metallization layer, and The third or more via structures are spaced apart from the fourth or more via structures based on a third minimum via pitch that is at least greater than the metallization pitch.

5. The semiconductor device according to claim 4, wherein, The third minimum via pitch is one of the following: at least twice the metallization pitch or at least the gate pitch.

6. The semiconductor device according to claim 4, wherein, The first circuit unit also includes a third conductive line in the second metallization layer. The second circuit unit also includes a fourth conductive line of the second metallization layer. The third conductive line and the fourth conductive line are aligned along the second direction, and The third and fourth conductive lines are arranged based on a minimum end-to-end distance along the second direction that is greater than the metallization pitch.

7. The semiconductor device according to claim 1, wherein, The first or more drain / source conductive structures and the second or more drain / source conductive structures are spaced apart based on a cut-diffused metal pattern, and The cut diffusion metal pattern has a third serrated pattern along the unit boundary.

8. The semiconductor device according to claim 1, wherein, The first or more gate structures and the second or more gate structures are spaced apart based on diced polysilicon patterns, and The cut polycrystalline silicon pattern has a fourth serrated pattern along the cell boundary.

9. A method for generating a layout plan of a semiconductor device, comprising: A first layout unit is placed in the layout plan view. The first layout unit indicates a first circuit unit, including a first one or more conductive line patterns indicating a first one or more conductive lines in a first metallized line area of ​​a first metallized layer, and including a first one or more via patterns indicating a first one or more via structures below the first metallized layer. A second layout unit is placed in the layout plan view. The second layout unit is adjacent to the first layout unit at the unit boundary between the first layout unit and the first layout unit. The second layout unit indicates a second circuit unit, including a second or more conductive line pattern indicating a second or more conductive lines in a second metallized line area of ​​the first metallized layer, and including a second or more via pattern indicating a second or more via structure below the first metallized layer. as well as The layout plan, including the first layout unit and the second layout unit, is stored in the memory of the processing device. in, The first metallized line region and the second metallized line region are separated by a shared space extending along the cell boundary. Based on the fact that the first or more via patterns and the second or more via patterns belong to the first via layer between the first metallization layer and the drain / source conductive layer in the layout plan, the first or more via patterns and the second or more via patterns are located in a first region having a first serrated pattern along the cell boundary, and Based on the fact that the first or more via patterns and the second or more via patterns belong to the second via layer between the first metallization layer and the gate layer in the layout plan, the first or more via patterns and the second or more via patterns are located in a second region having a second serrated pattern along the cell boundary.

10. A method for generating a layout plan of a semiconductor device, comprising: A set of placement positions for indicating target circuit cells is obtained from a plurality of placement positions of the layout plan, each of the plurality of placement positions of the layout plan having a width along a first direction corresponding to the gate pitch of the layout plan, and a height along a second direction corresponding to the standard cell height of the layout plan, wherein the plurality of placement positions: This includes the placement positions of the first row, including a first placement position of a first placement type and a second placement position of a second placement type arranged alternately along the first direction, and can be used to place standard layout units of standard unit height in nominal form. The placement includes the second row, a third placement of a first placement type arranged alternately along the first direction, and a fourth placement of a second placement type, and can be used to place the standard layout unit in a flipped form, the flipped form corresponding to a mirror image of the nominal form along the first direction. A shared space is defined along the boundary between the first row and the second row, and this shared space contains no layout pattern in the first metallization layer of the layout plan. The first placement position of the first row is adjacent to the fourth placement position of the second row. The second placement position of the first row is adjacent to the third placement position of the second row. The first placement type indicates that a through-hole pattern disposed at an adjacent location on the opposite second direction side of the corresponding placement position is accommodated below the first metallization layer in the layout plan view, and The second placement type indicates that any through-hole patterns are prohibited on the adjacent location on the opposite second direction side of the corresponding placement position below the first metallization layer of the layout plan. Based on the placement position type of the edge placement position in the opposite first direction in the placement position group, one of the multiple candidate layout units associated with the target circuit unit is placed as the target layout unit on the placement position group; and The layout plan view including the layout units is stored in the memory of the processing device.

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