Multi-surface detection anti-vibration method applied to semiconductor substrate slice

Abstract

The invention discloses a multi-surface detection anti-vibration method applied to a semiconductor substrate slice. According to the technical scheme, the multi-surface detection anti-vibration method is characterized by comprising the following steps of S1, low-substrate leakage current detection; s2, surface resistivity detection; s3, parasitic capacitance detection; s4, noise isolation detection; s5, multi-surface anti-vibration testing is carried out; s6, multi-surface anti-vibration analysis is carried out; according to the invention, the defect that only a testing machine is adopted for testing the semiconductor substrate is overcome, and the vibration resistance of the semiconductor is influenced by other performances, so that low-substrate leakage current detection, surface resistivity detection, parasitic capacitance detection and noise isolation detection are carried out on the semiconductor substrate in the scheme; and the anti-vibration performance is comprehensively calculated and analyzed, so that the test result is relatively accurate.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a multi-surface detection and vibration damping method for semiconductor substrates. Background Technology

[0002] Semiconductor materials are the foundation of modern electronic devices, and their quality directly affects the performance and lifespan of these devices. Semiconductor substrate testing is an important task for quality assessment and fault analysis of semiconductor materials. Through semiconductor substrate testing, key indicators such as the material's electrical properties, crystal quality, and substrate thickness can be detected.

[0003] The substrate is the base that supports the epitaxial thin film. Due to the lack of homogeneous substrates, GaN-based LEDs are generally grown on heterogeneous substrates such as sapphire, SiC, and Si. To date, sapphire has become the most cost-effective substrate and is the most widely used. Because GaN has a higher refractive index than sapphire, in order to reduce total emission of light emitted from the LED at the substrate interface, current surface-mount chips generally undergo material epitaxy on patterned substrates to improve light scattering. Common patterned substrate patterns are typically micrometer-scale hexagonal close-packed conical arrays, which can improve the light extraction efficiency of LEDs to over 60%. Research also shows that by using patterned substrates in conjunction with certain growth processes, the extension direction of dislocations in GaN can be controlled, thereby effectively reducing the dislocation density of the GaN epitaxial layer. For a considerable period of time to come, patterned substrates will remain the primary technology used in surface-mount chips.

[0004] Chinese Patent CN104756243B discloses a position detection device that detects the position of a disk-shaped substrate held on a support member capable of moving along a trajectory parallel to the Y-axis. The device is characterized by comprising a camera arranged in an orthogonal XY-axis coordinate system. When the support member holding the disk-shaped substrate is in a predetermined monitoring position, the camera captures an image of only a portion of the periphery of the disk-shaped substrate by ensuring that the intersection point (C) of a straight line and the edge of the disk-shaped substrate enters the field of view, the straight line passing through the disk-shaped substrate... The disk-shaped substrate has a circumferential vertex in the Y-axis direction, with the center of the substrate parallel to the Y-axis. An edge extraction unit extracts the Y-axis coordinate values ​​of adjacent units with distinct density differences in the XY coordinates of the intersection point (C) from the image data of the peripheral portion of the disk-shaped substrate captured by the camera. The XY coordinates of the location at the edge of the disk-shaped substrate within the field of view, away from the extracted intersection point (C), are extracted as edge data. A coordinate detection unit detects the center position coordinates of the disk-shaped substrate based on the edge data extracted by the edge extraction unit.

[0005] The aforementioned patents have some advantages, but also some disadvantages: the testing of semiconductor substrates mostly uses a single testing machine, but the vibration resistance of semiconductors is also affected by other properties. The current solutions lack a scheme that comprehensively considers various properties to test and calculate the vibration resistance, which needs to be improved. Summary of the Invention

[0006] In view of the problems mentioned in the background art, the purpose of this invention is to provide a multi-surface detection vibration resistance method for semiconductor substrates, so as to solve the problems mentioned in the background art.

[0007] The above-mentioned technical objective of the present invention is achieved through the following technical solution: A vibration damping method for multi-surface detection of semiconductor substrates includes the following steps: S1. Low substrate leakage current detection: A laser beam is used to scan the surface of the chip under constant voltage. Part of the laser beam energy is converted into heat energy. If there is a defect in the chip, the temperature at the defect will rise cumulatively, causing changes in the resistance and current of the metal lines. By matching the change area with the scanning position of the laser beam, the defect or failure location can be located. S2. Surface resistivity detection: Four probes with a spacing of 1 mm are pressed simultaneously onto the flat surface of the sample. A constant current source is used to pass a small current to the two outer probes. Then, a high-precision digital multimeter is used to measure the voltage on the two middle probes. Finally, the resistivity of the sample is calculated according to the theoretical formula. S3. Parasitic Capacitance Detection: Select the IGBT test template and set the parasitic capacitance test conditions according to the test requirements; set the display range of the parasitic capacitance test curve; select the parasitic capacitance parameters to be tested; execute the test; S4. Noise isolation detection: Observe the ballistic avalanche phenomenon in nanoscale vertical InSe / BP heterostructures; analyze the random telegraph noise caused by resonant tunneling under low temperature conditions; analyze the graphene superlattice structure grown on hexagonal boron nitride using low temperature and low frequency noise. S5. Multi-surface vibration resistance test: Prepare one set of test specimens for cast iron, aluminum silicon carbide, and aluminum alloy respectively; clamp the above three specimens onto the damping vibration testing machine; set the corresponding back-and-forth vibration frequency; set the corresponding vibration time - 25 seconds; observe the vibration of the three materials when the equipment stops and make relevant records. S6. Multi-surface vibration resistance analysis: The results of multi-surface vibration resistance testing are integrated with low substrate leakage current detection data, surface resistivity detection data, parasitic capacitance detection data and noise isolation detection data to obtain vibration resistance analysis results.

[0008] Preferably, the method also includes microscopic photothermal distribution testing, wherein the microscopic photothermal distribution testing steps are as follows: using an amorphous silicon infrared ULIS detector, the light intensity distribution, diameter, and divergence angle parameters of the light source are measured through algorithms, chips, and image sensing technology; then, the light intensity distribution is measured through a CCD, and the diameter parameter of the light source is calculated through an algorithm, and the relative intensity of the light intensity is measured.

[0009] Preferably, when the leakage point cannot be located, step S1 uses a microscopic photothermal distribution testing system to test the light distribution and thermal distribution of the chip, determines the abnormal location of the light / thermal distribution as the location of the chip leakage, thereby locating the leakage point. Then, SEM characterization test is performed on a precise slice of the leakage point using FIB to analyze the cause of the leakage.

[0010] Preferably, when detecting parasitic capacitance, S3 uses a fault model for simulation, provides waveform vectors, and adopts VCD or WGL format. During testing, timing, level and logic are combined for programming, and the chip input vector is used to detect the output.

[0011] Preferably, when S3 detects parasitic capacitance, if the test point is abnormal, the following operations are performed: the pulse setting parameters are corrected by increasing the pulse width and the measurement time; mutual inductance is reduced by connecting a twisted pair; the oscillation of signal reflection is reduced by selecting the gate series resistor; mutual inductance is reduced by adding an external magnetic ring; and self-oscillation is eliminated by improving the stability of the DUT by connecting a 50-ohm resistor to ground through the gate to absorb the emitted signal.

[0012] Preferably, in step S6, when the semiconductor substrate does not meet the requirements, the ion beam generated by the liquid metal ion source is accelerated by an ion gun, focused, and irradiated onto the sample surface to generate a secondary electron signal and obtain an electron image, or a high-current ion beam is used to peel off surface atoms to process the micro-surface of the semiconductor substrate.

[0013] In summary, the present invention has the following main beneficial effects: This invention overcomes the shortcomings of simply using a testing machine to test semiconductor substrates. Since the vibration resistance of semiconductors is also affected by other properties, this solution performs low substrate leakage current detection, surface resistivity detection, parasitic capacitance detection, and noise isolation detection on the semiconductor substrate; and comprehensively calculates and analyzes the vibration resistance performance, resulting in more accurate test results. Attached Figure Description

[0014] Figure 1 This is a flowchart of the present invention. Detailed Implementation

[0015] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Example 1

[0016] refer to Figure 1 A vibration damping method for multi-surface detection of semiconductor substrates includes the following steps: S1. Low substrate leakage current detection: A laser beam is used to scan the surface of the chip under constant voltage. Part of the laser beam energy is converted into heat energy. If there is a defect in the chip, the temperature at the defect will rise cumulatively, causing changes in the resistance and current of the metal lines. By matching the change area with the scanning position of the laser beam, the defect or failure location can be located. S2. Surface resistivity detection: Four probes with a spacing of 1 mm are pressed simultaneously onto the flat surface of the sample. A constant current source is used to pass a small current to the two outer probes. Then, a high-precision digital multimeter is used to measure the voltage on the two middle probes. Finally, the resistivity of the sample is calculated according to the theoretical formula. S3. Parasitic Capacitance Detection: Select the IGBT test template and set the parasitic capacitance test conditions according to the test requirements; set the display range of the parasitic capacitance test curve; select the parasitic capacitance parameters to be tested; execute the test; S4. Noise isolation detection: Observe the ballistic avalanche phenomenon in nanoscale vertical InSe / BP heterostructures; analyze the random telegraph noise caused by resonant tunneling under low temperature conditions; analyze the graphene superlattice structure grown on hexagonal boron nitride using low temperature and low frequency noise. S5. Multi-surface vibration resistance test: Prepare one set of test specimens for cast iron, aluminum silicon carbide, and aluminum alloy respectively; clamp the above three specimens onto the damping vibration testing machine; set the corresponding back-and-forth vibration frequency; set the corresponding vibration time - 25 seconds; observe the vibration of the three materials when the equipment stops and make relevant records. S6. Multi-surface vibration resistance analysis: The results of multi-surface vibration resistance testing are integrated with low substrate leakage current detection data, surface resistivity detection data, parasitic capacitance detection data and noise isolation detection data to obtain vibration resistance analysis results.

[0017] The test also includes a microscopic photothermal distribution test, which involves using an amorphous silicon infrared ULIS detector and employing algorithms, chips, and image sensing technology to measure the light intensity distribution, diameter, and divergence angle parameters of the light source. The light intensity distribution is then measured using a CCD, and the diameter parameter of the light source is calculated using an algorithm. The relative intensity of the light intensity is then measured.

[0018] When the leakage point cannot be located, S1 uses a microscopic photothermal distribution testing system to test the light and heat distribution of the chip, determines the abnormal location of the light / heat distribution as the location of the chip leakage, and then uses FIB to perform SEM characterization test on a precise slice of the leakage point to analyze the cause of the leakage.

[0019] Specifically, when detecting parasitic capacitance, S3 uses a fault model for simulation, providing waveform vectors in VCD or WGL format. During testing, timing, level, and logic are combined for programming, and the chip input vector is used to detect the output.

[0020] When S3 detects parasitic capacitance, if the test point is abnormal, it performs the following operations: corrects the pulse setting parameters by increasing the pulse width and measurement time; reduces mutual inductance by connecting with twisted pairs; reduces signal reflection oscillation by selecting the gate series resistor; reduces mutual inductance by adding an external magnetic ring; and improves DUT stability to eliminate self-oscillation by connecting the gate to ground with a 50-ohm resistor.

[0021] In step S6, when the semiconductor substrate does not meet the requirements, the ion beam generated by the liquid metal ion source is accelerated by the ion gun, focused and irradiated on the sample surface to generate a secondary electron signal to obtain an electron image, or a high current ion beam is used to peel off the surface atoms to process the micro surface of the semiconductor substrate.

[0022] This invention achieves a capacitance testing accuracy of 1fF / <1% for capacitors <100fF; accurately plots CV curves under different bias voltages; and covers three test items (Cgg / Cgb / Cgsd@VB) in the same test circuit; with an average DUT occupying only 0.25 pads. This invention overcomes the limitations of traditional CBCMs in eliminating charge injection and front-end leakage effects, and solves technical bottlenecks such as excessively large chip area for current capacitor testing, insufficient accuracy in capacitor testing technology, large parasitic capacitance, inability to test front-end capacitors under different bias voltages, and the limitation of testing only one capacitance item per DUT. It is particularly suitable for FEOL capacitor testing using 55nm, 40nm, 28nm, 14nm, and more advanced processes, achieving a testing accuracy of 1fF and simultaneously measuring the CV curves of multiple capacitance test items.

[0023] In this invention, the shortcomings of semiconductor substrate testing are that the testing is mostly done by a single testing machine. Since the vibration resistance of semiconductors is also affected by other properties, this solution performs low substrate leakage current detection, surface resistivity detection, parasitic capacitance detection, and noise isolation detection on the semiconductor substrate; and comprehensively calculates and analyzes the vibration resistance, resulting in more accurate test results.

[0024] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A vibration damping method for multi-surface detection of semiconductor substrates, characterized in that: Includes the following steps: S1. Low substrate leakage current detection: A laser beam is used to scan the surface of the chip under constant voltage. Part of the laser beam energy is converted into heat energy. If there is a defect in the chip, the temperature at the defect will rise cumulatively, causing changes in the resistance and current of the metal lines. By matching the change area with the scanning position of the laser beam, the defect or failure location can be located. S2. Surface resistivity detection: Four probes with a spacing of 1 mm are pressed simultaneously onto the flat surface of the sample. A constant current source is used to pass a small current to the two outer probes. Then, a high-precision digital multimeter is used to measure the voltage on the two middle probes. Finally, the resistivity of the sample is calculated according to the theoretical formula. S3. Parasitic Capacitance Detection: Select the IGBT test template and set the parasitic capacitance test conditions according to the test requirements; Set the display range of the parasitic capacitance test curve; select the parasitic capacitance parameters to be tested; Execute the test; S4. Noise isolation detection: Observe the ballistic avalanche phenomenon in nanoscale vertical InSe / BP heterostructures; analyze the random telegraph noise caused by resonant tunneling under low temperature conditions; analyze the graphene superlattice structure grown on hexagonal boron nitride using low temperature and low frequency noise. S5. Multi-surface vibration resistance test: Prepare one set of test specimens for cast iron, aluminum silicon carbide, and aluminum alloy respectively; clamp the above three specimens onto the damping vibration testing machine; set the corresponding back-and-forth vibration frequency; set the corresponding vibration time - 25 seconds; observe the vibration of the three materials when the equipment stops and make relevant records. S6. Multi-surface vibration resistance analysis: The results of multi-surface vibration resistance testing are integrated with low substrate leakage current detection data, surface resistivity detection data, parasitic capacitance detection data and noise isolation detection data to obtain vibration resistance analysis results.

2. The vibration damping method for multi-surface detection applied to semiconductor substrates according to claim 1, characterized in that: It also includes microscopic photothermal distribution testing, the steps of which are as follows: using an amorphous silicon infrared ULIS detector, through algorithms, chips and image sensing technology, the light intensity distribution, diameter and divergence angle parameters of the light source are measured, then the light intensity distribution is measured by CCD, and the diameter parameter of the light source is calculated by algorithm, and the relative intensity of the light intensity is measured.

3. The vibration damping method for multi-surface detection applied to semiconductor substrates according to claim 1, characterized in that: When the leakage point cannot be located, the S1 method uses a microscopic photothermal distribution testing system to test the light and heat distribution of the chip, determines the abnormal location of the light / heat distribution as the location of the chip leakage, and then uses FIB to perform SEM characterization testing on a precise slice of the leakage point to analyze the cause of the leakage.

4. The vibration damping method for multi-surface detection applied to semiconductor substrates according to claim 1, characterized in that: When detecting parasitic capacitance, the S3 uses a fault model for simulation, providing waveform vectors in VCD or WGL format. During testing, timing, level, and logic are combined for programming, and the chip input vector is used to detect the output.

5. The vibration damping method for multi-surface detection of semiconductor substrates according to claim 1, characterized in that: If the test point is abnormal during parasitic capacitance detection, S3 will perform the following operations: correct the pulse setting parameters by increasing the pulse width and measurement time; reduce mutual inductance by connecting with twisted pairs; reduce signal reflection oscillation by selecting the gate series resistor; reduce mutual inductance by adding an external magnetic ring; and improve DUT stability to eliminate self-oscillation by connecting the gate to ground with a 50-ohm resistor.

6. The vibration damping method for multi-surface detection applied to semiconductor substrates according to claim 1, characterized in that: When the semiconductor substrate does not meet the requirements, S6 accelerates the ion beam generated by the liquid metal ion source through the ion gun, focuses it and irradiates the sample surface to generate a secondary electronic signal to obtain an electronic image, or uses a high-current ion beam to peel off the surface atoms and process the micro surface of the semiconductor substrate.

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