Ultralow-temperature-drift band-gap reference circuit

Abstract

The invention belongs to the technical field of analog integrated circuits, and particularly relates to an ultralow-temperature-drift band-gap reference circuit which comprises a first-order band-gap reference circuit and a high-order temperature compensation circuit. The first-order band-gap reference circuit comprises a starting circuit, a band-gap reference core circuit and an output zero-temperature current circuit; the starting circuit is connected with the band-gap reference core circuit and the output zero-temperature current circuit, the band-gap reference core circuit is connected with the output zero-temperature current circuit, the output zero-temperature current circuit is connected with the high-order temperature compensation circuit, and the high-order temperature compensation circuit is connected with the band-gap reference core circuit; according to the high-order temperature compensation circuit, the full temperature section is divided into four sections, the high-order compensation current is generated by adopting the tube working in the sub-threshold region, and the compensation current in the high-temperature section and the leakage current of the triode are superposed to weaken the temperature drift coefficient, so that the compensation current in the high-temperature section is extracted, the temperature drift coefficient is optimized, and the temperature drift coefficient is reduced. The ultra-low temperature drift performance of the whole process corner is achieved, and the circuit stability and the environmental adaptability are improved.

Description

Technical Field

[0001] This invention belongs to the field of analog integrated circuit technology, and specifically relates to a bandgap reference circuit with ultra-low temperature drift. Background Technology

[0002] Traditional bandgap reference circuits rely on single curvature compensation or base current compensation, resulting in temperature drift coefficients ranging from 10 to 50 ppm / ℃, which is insufficient to meet the requirements of high-precision applications. Existing segmented compensation techniques have not achieved synergistic optimization of the transistor's negative and positive temperature voltages, resulting in insufficient continuity of the compensation range and unstable temperature drift suppression effects. Summary of the Invention

[0003] To address the aforementioned problems in the prior art, this invention employs an ultra-low temperature drift bandgap reference circuit, comprising: a first-order bandgap reference circuit and a higher-order temperature compensation circuit; the first-order bandgap reference circuit includes a startup circuit, a bandgap reference core circuit, and an output zero-temperature current circuit; the startup circuit is connected to the bandgap reference core circuit and the output zero-temperature current circuit, the bandgap reference core circuit is connected to the output zero-temperature current circuit, the output zero-temperature current circuit is connected to the higher-order temperature compensation circuit, and the higher-order temperature compensation circuit is connected to the bandgap reference core circuit.

[0004] The high-order temperature compensation circuit includes: PMOS transistors PM6~PM21, NMOS transistors NM7~NM10, resistor R12, current source, and operational amplifier A2;

[0005] The gates of PMOS transistors PM12, PM14, PM16, PM18, and PM20, the output of operational amplifier A2, and the drain of PMOS transistor PM12 are connected together. The sources of PMOS transistors PM12, PM14, PM16, PM18, and PM20 are connected to the power supply VDD.

[0006] The source of PMOS transistor PM13 is connected to the drain of PMOS transistor PM12; the gates of PMOS transistor PM13, PM15, PM17, PM19, PM21, NMOS transistor NM9, and PM13 are connected together.

[0007] The drain of PMOS transistor PM21, one end of resistor R12, and the non-inverting input of operational amplifier A2 are connected together; the other end of resistor R12, the drain of PMOS transistor PM11, the drain of PMOS transistor PM9, the drain of PMOS transistor PM7, the source of NMOS transistor NM5, the source of NMOS transistor NM6, the source of NMOS transistor NM8, and the source of NMOS transistor NM9 are grounded to GND.

[0008] The source of PMOS transistor PM15 is connected to the drain of PMOS transistor PM14; the source of PMOS transistor PM17 is connected to the drain of PMOS transistor PM16; the source of PMOS transistor PM19 is connected to the drain of PMOS transistor PM18; the source of PMOS transistor PM21 is connected to the drain of PMOS transistor PM20; the sources of PMOS transistors PM6 and PM7, and the drain of PMOS transistor PM15 are connected; the sources of PMOS transistors PM8 and PM9, the drain of PMOS transistor PM17, and the drain of NMOS transistor NM6 are also connected. The drains of PMOS transistors PM10, PM11, and PM19 are connected together. The drain and gate of NMOS transistor NM7 are connected to the gate of NMOS transistor NM9. The drain of NMOS transistor NM7 is connected to the output terminal of the current source. The gates of NMOS transistors NM10, NM8, and NM8, as well as the source of NMOS transistor NM7, are connected together. The gates of NMOS transistors NM5, NM5, and NM6 are connected together.

[0009] The gates of PMOS transistors PM6, PM11, and PM8, as well as the inverting input of operational amplifier A2, are connected to the reference voltage output by the zero-temperature current circuit; the input of the current source is connected to the zero-temperature current output by the zero-temperature current circuit; and the gates of PMOS transistors PM7, PM9, and PM10 are connected to the positive temperature characteristic voltage output by the bandgap reference core circuit.

[0010] Beneficial effects:

[0011] The high-order temperature compensation circuit of this invention divides the entire temperature range into four segments (generating negative temperature current at low temperatures, no compensation current at medium temperatures, generating positive temperature compensation current at higher temperatures, and no compensation current at high temperatures). It uses transistors operating in the subthreshold region to generate high-order compensation current. Furthermore, the compensation current in the high-temperature segment is superimposed on the leakage current of the transistor, which weakens the temperature drift coefficient. Therefore, the compensation current in the high-temperature segment is removed, thereby optimizing the temperature drift coefficient, achieving ultra-low temperature drift performance across the entire process angle, improving circuit stability and environmental adaptability, and meeting the reference voltage requirements of high-precision electronic equipment. Attached Figure Description

[0012] Figure 1 A schematic diagram of a first-order bandgap reference circuit provided in an embodiment of the present invention;

[0013] Figure 2 A schematic diagram of a high-order temperature compensation circuit provided in an embodiment of the present invention;

[0014] Figure 3 Temperature characteristic curves of VBG with high-order compensation for bandgap reference provided in embodiments of the present invention. Detailed Implementation

[0015] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0016] like Figure 1 As shown, the present invention employs an ultra-low temperature drift bandgap reference circuit, comprising: a startup circuit, a bandgap reference core circuit, an output zero-temperature current circuit, and a high-order temperature compensation circuit; the startup circuit is connected to the bandgap reference core circuit, the bandgap reference core circuit is connected to the output zero-temperature current circuit, the output zero-temperature current circuit is connected to the high-order temperature compensation circuit, and the high-order temperature compensation circuit is connected to the bandgap reference core circuit.

[0017] The startup circuit module ensures the circuit leaves the zero state during initialization and shuts off during normal operation. The bandgap reference core module (brokaw structure) generates the reference voltage. The output zero-temperature current module generates the zero-temperature current. and reference voltage.

[0018] like Figure 2 As shown, the high-order temperature compensation circuit includes: PMOS transistors PM6~PM21, NMOS transistors NM7~NM10, resistor R12, current source, and operational amplifier A2;

[0019] The gates of PMOS transistors PM12, PM14, PM16, PM18, and PM20, the output of operational amplifier A2, and the drain of PMOS transistor PM12 are connected together. The sources of PMOS transistors PM12, PM14, PM16, PM18, and PM20 are connected to the power supply VDD.

[0020] The source of PMOS transistor PM13 is connected to the drain of PMOS transistor PM12; the gates of PMOS transistor PM13, PM15, PM17, PM19, PM21, NMOS transistor NM9, and PM13 are connected together.

[0021] The drain of PMOS transistor PM21, one end of resistor R12, and the non-inverting input of operational amplifier A2 are connected together; the other end of resistor R12, the drain of PMOS transistor PM11, the drain of PMOS transistor PM9, the drain of PMOS transistor PM7, the source of NMOS transistor NM5, the source of NMOS transistor NM6, the source of NMOS transistor NM8, and the source of NMOS transistor NM9 are grounded to GND; the inverting input of operational amplifier A2 is connected to VREF1.

[0022] The source of PMOS transistor PM15 is connected to the drain of PMOS transistor PM14; the source of PMOS transistor PM17 is connected to the drain of PMOS transistor PM16; the source of PMOS transistor PM19 is connected to the drain of PMOS transistor PM18; the source of PMOS transistor PM21 is connected to the drain of PMOS transistor PM20; the sources of PMOS transistors PM6 and PM7, and the drain of PMOS transistor PM15 are connected; the sources of PMOS transistors PM8 and PM9, the drain of PMOS transistor PM17, and the drain of NMOS transistor NM6 are also connected. The drains of PMOS transistors PM10, PM11, and PM19 are connected together. The drains and gates of NMOS transistors NM7 and NM9 are connected together. The drain of NMOS transistor NM7 is connected to the output terminal of the current source. The gates of NMOS transistors NM10, NM8, and NM8, as well as the source of NMOS transistor NM7, are connected together. The gates and drains of NMOS transistors NM5 and NM6 are connected together.

[0023] The drains of PMOS transistor PM8 and PMOS transistor PM10 are connected to the same node, which outputs the compensation current for the high-order temperature compensation circuit. .

[0024] The gates of PMOS transistors PM6, PM11, and PM8, as well as the inverting input of operational amplifier A2, are connected to the reference voltage output by the zero-temperature current circuit; specifically, the gate of PMOS transistor PM6 is connected to the reference voltage. The gate connection reference voltage of PMOS transistor PM11 The gate connection reference voltage of PMOS transistor PM8 The inverting input terminal of op-amp A2 is connected to a voltage... ;

[0025] The input terminal of the current source is connected to the zero-temperature current output of the zero-temperature current circuit. The gates of PMOS transistors PM7, PM9, and PM10 are connected to the positive temperature characteristic voltage output by the bandgap reference core circuit. .

[0026] The core circuit of the bandgap reference includes: resistors R1~R5, resistor Rtrimming, clamping operational amplifier A1, NPN transistor Q1, and NPN transistor Q2;

[0027] The base of NPN transistor Q1 is connected to the base of NPN transistor Q2; the collector of NPN transistor Q1 is connected to one end of resistor R4 and the inverting input of clamping operational amplifier A1; the collector of NPN transistor Q2 is connected to one end of resistor R5 and the non-inverting input of clamping operational amplifier A1; the other ends of resistors R4 and R5 are connected to the power supply VDD.

[0028] The emitter of NPN transistor Q2 is connected to one end of resistor R1. The emitter of NPN transistor Q1 and the other end of resistor R1 are connected to one end of resistor R2. Resistors R2, Rtrimming, and R3 are connected in series. The other end of resistor R3 is grounded (GND). The end of resistor Rtrimming connected to resistor R3 is connected to the drain of PMOS transistors PM8 and PM10 (i.e., it connects to the compensation current of the high-order temperature compensation circuit). The terminal where resistors R1 and R2 are connected outputs a positive temperature characteristic voltage. .

[0029] The clamping operational amplifier A1 is used to ensure that the voltages at points A and B are equal, thus guaranteeing that the currents in branches Q1 and Q2 are equal. Resistors R4 and R5 are the same, and the emitter area of ​​NPN transistor Q2 is N times the emitter area of ​​NPN transistor Q1; preferably, N=8.

[0030] The zero-temperature current output circuit includes: PMOS transistors PM2~PM5 and resistors R7~R11;

[0031] The sources of PMOS transistors PM2 and PM4 are connected to the power supply VDD. The gates of PMOS transistors PM2 and PM4 are connected to the output of clamping operational amplifier A1. The drain of PMOS transistor PM2 is connected to the source of PMOS transistor PM3, and the drain of PMOS transistor PM4 is connected to the source of PMOS transistor PM5. The drain of PMOS transistor PM5 outputs a zero-temperature current. The gate of PMOS transistor PM3, the drain of PMOS transistor PM3, the gate of PMOS transistor PM5, and one end of resistor R7 are connected to the base of NPN transistor Q1 (i.e., the zero temperature coefficient voltage VBG output by the bandgap reference core circuit).

[0032] Resistors R7, R8, R9, R10, and R11 are connected in series, with the other end of resistor R11 grounded. The terminal where resistors R7 and R8 are connected outputs a reference voltage. The terminal where resistors R8 and R9 are connected outputs a reference voltage. The terminal where resistors R9 and R10 are connected outputs a reference voltage. The terminal where resistors R10 and R11 are connected outputs a reference voltage. .

[0033] The startup circuit includes: PMOS transistor PM1, NMOS transistors NM1~NM3 and resistor R6;

[0034] The source of PMOS transistor PM1 is connected to the power supply VDD, the gate is connected to one end of resistor R6, the drain is connected to the drain of NMOS transistor NM1, and the other end of resistor R6 is grounded.

[0035] The gate, drain, NM2, and gate of NMOS transistor NM1 are connected to the drain of NMOS transistor NM4; the drain (Start_up) of NMOS transistor NM2 is connected to the gate of PMOS transistor PM2.

[0036] The sources of NMOS transistors NM1, NM2, NM3, and NM4 are grounded to GND; the gate of NMOS transistor NM4 is connected to the base of NPN transistor Q1, and the drain of NMOS transistor NM3 is connected to the collector of NPN transistor Q2.

[0037] Working principle: In the first-order bandgap reference circuit, resistors R4 and R5 are identical. The emitter area of ​​NPN transistor Q1 is N times that of NPN transistor Q2. The magnitude of the PTAT current generated through NPN transistors Q1 and Q2 is... , This is a temperature-proportional thermal voltage; and since resistors R4 and R5 are identical, and the currents in the two branches of NPN transistors Q1 and Q2 are the same, a voltage with a positive temperature characteristic is generated across resistors R2, Rtrimming, and R3. The voltage with this positive temperature characteristic The voltage between the base and emitter of NPN transistor Q1 The voltage with zero temperature coefficient can be obtained by weighted summation. , Voltage with negative temperature characteristics.

[0038] Working principle of high-order temperature compensation circuit:

[0039] Tsividis studied BJT pipes. The relationship between temperature T and temperature was investigated and quantitatively analyzed. The equation for T is as follows:

[0040]

[0041] in, This represents the bandgap voltage at temperature T=0K, where T is the temperature. 298K (25℃), For temperature Voltage with negative temperature characteristics at that time α is a parameter affected by the process, with a value approximately between 3.6 and 4; α is a parameter reflecting the relationship between the bias current of the BJT and temperature. When the bias current is related to temperature, α=1, otherwise α=0.

[0042] As can be seen from the formula, it includes a constant term, a first-order term, and a higher-order term. Therefore, the higher-order compensation circuit needs to generate a higher-order term. Thus, this invention selects a MOSFET operating in the subthreshold region to provide the higher-order term. The current formula for the subthreshold MOSFET is as follows:

[0043]

[0044] in, Drain current, The characteristic current is process-dependent and its expression is: μ is generally the carrier mobility, Cox is the oxide capacitance, and m is the process factor. Gate-source voltage, It is a non-ideal factor. For thermal voltage, the expression is: k is Boltzmann's constant, T is the thermodynamic temperature, and q is the electron charge.

[0045] The design concept of the high-order compensation circuit is to divide the entire temperature range into four segments. Low temperature range: controlled by PMOS transistors PM10 and PM11. When, the current passes through Compensation is performed; Mid-temperature range: controlled by PMOS transistors PM9 and PM11. Current passes through and Flow to GND; Higher temperature range: controlled by PMOS transistors PM8 and PM9, when At that time, the compensation current passes through Compensation is performed; High-temperature section: controlled by PMOS transistors PM6 and PM7, when At that time, the compensation current passes through The high-temperature section is removed without compensation. The specific calculation process is as follows:

[0046]

[0047]

[0048]

[0049]

[0050]

[0051]

[0052]

[0053]

[0054]

[0055]

[0056] Substituting the above formula into the equation, we get:

[0057]

[0058]

[0059]

[0060] in, For resistors The sum of, ~ For current, , These are the coefficients of the first-order and higher-order terms, respectively.

[0061] As can be seen from the above expressions, PMOS transistors PM6, PM7, PM8, PM9, PM10, and PM11, which operate in the subthreshold region, can be used to perform high-order compensation of the bandgap reference.

[0062] Simulation of the temperature characteristic curve of VBG with high-order compensation bandgap reference is as follows: Figure 3 As shown, the high-order temperature compensation circuit of the present invention can perform high-order compensation for the bandgap reference.

[0063] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A bandgap reference circuit with ultra-low temperature drift, characterized in that, include: A first-order bandgap reference circuit and a high-order temperature compensation circuit; the first-order bandgap reference circuit includes a startup circuit, a core bandgap reference circuit, and an output zero-temperature current circuit. The startup circuit is connected to the bandgap reference core circuit and the output zero-temperature current circuit. The bandgap reference core circuit is connected to the output zero-temperature current circuit. The output zero-temperature current circuit is connected to the high-order temperature compensation circuit. The high-order temperature compensation circuit is connected to the bandgap reference core circuit.

2. The ultra-low temperature drift bandgap reference circuit according to claim 1, characterized in that, The high-order temperature compensation circuit includes: PMOS transistors PM6~PM21, NMOS transistors NM7~NM10, resistor R12, current source, and operational amplifier A2; The gates of PMOS transistors PM12, PM14, PM16, PM18, and PM20, the output of operational amplifier A2, and the drain of PMOS transistor PM12 are connected together. The sources of PMOS transistors PM12, PM14, PM16, PM18, and PM20 are connected to the power supply VDD. The source of PMOS transistor PM13 is connected to the drain of PMOS transistor PM12; the gates of PMOS transistor PM13, PM15, PM17, PM19, PM21, NMOS transistor NM9, and PM13 are connected together. The drain of PMOS transistor PM21, one end of resistor R12, and the non-inverting input of operational amplifier A2 are connected together; the other end of resistor R12, the drain of PMOS transistor PM11, the drain of PMOS transistor PM9, the drain of PMOS transistor PM7, the source of NMOS transistor NM5, the source of NMOS transistor NM6, the source of NMOS transistor NM8, and the source of NMOS transistor NM9 are grounded to GND. The source of PMOS transistor PM15 is connected to the drain of PMOS transistor PM14; the source of PMOS transistor PM17 is connected to the drain of PMOS transistor PM16; the source of PMOS transistor PM19 is connected to the drain of PMOS transistor PM18; the source of PMOS transistor PM21 is connected to the drain of PMOS transistor PM20; the sources of PMOS transistors PM6 and PM7, and the drain of PMOS transistor PM15 are connected; the sources of PMOS transistors PM8 and PM9, the drain of PMOS transistor PM17, and the drain of NMOS transistor NM6 are also connected. The drains of PMOS transistors PM10, PM11, and PM19 are connected together. The drain and gate of NMOS transistor NM7 are connected to the gate of NMOS transistor NM9. The drain of NMOS transistor NM7 is connected to the output terminal of the current source. The gates of NMOS transistors NM10, NM8, and NM8, as well as the source of NMOS transistor NM7, are connected together. The gates of NMOS transistors NM5, NM5, and NM6 are connected together. The drains of PMOS transistors PM8 and PM10 are connected to the same node to output the compensation current of the high-order temperature compensation circuit. The gates of PMOS transistors PM6, PM11, and PM8, as well as the inverting input of operational amplifier A2, are connected to the reference voltage output by the zero-temperature current circuit. The input of the current source is connected to the zero-temperature current output by the zero-temperature current circuit. The gates of PMOS transistors PM7, PM9, and PM10 are connected to the positive temperature characteristic voltage output by the bandgap reference core circuit.

3. The ultra-low temperature drift bandgap reference circuit according to claim 2, characterized in that, PMOS transistors PM6, PM7, PM8, PM9, PM10, and PM11 operate in the subthreshold region.

4. The ultra-low temperature drift bandgap reference circuit according to claim 2, characterized in that, The core circuit of the bandgap reference includes: resistors R1~R5, resistor Rtrimming, clamping operational amplifier A1, NPN transistor Q1, and NPN transistor Q2; The base of NPN transistor Q1 is connected to the base of NPN transistor Q2; the collector of NPN transistor Q1 is connected to one end of resistor R4 and the inverting input of clamping operational amplifier A1; the collector of NPN transistor Q2 is connected to one end of resistor R5 and the non-inverting input of clamping operational amplifier A1; the other ends of resistors R4 and R5 are connected to the power supply VDD. The emitter of NPN transistor Q2 is connected to one end of resistor R1. The emitter of NPN transistor Q1 and the other end of resistor R1 are connected to one end of resistor R2. Resistors R2, Rtrimming, and R3 are connected in series. The other end of resistor R3 is grounded to GND. The end of resistor Rtrimming connected to resistor R3 is connected to the compensation current of the high-order temperature compensation circuit.

5. The ultra-low temperature drift bandgap reference circuit according to claim 4, characterized in that, Resistors R4 and R5 are the same.

6. The ultra-low temperature drift bandgap reference circuit according to claim 4, characterized in that, The emitter area of ​​NPN transistor Q2 is N times that of NPN transistor Q1.

7. The ultra-low temperature drift bandgap reference circuit according to claim 4, characterized in that, The zero-temperature current output circuit includes: PMOS transistors PM2~PM5 and resistors R7~R11; The sources of PMOS transistors PM2 and PM4 are connected to the power supply VDD. The gates of PMOS transistors PM2 and PM4 are connected to the output of clamping operational amplifier A1. The drain of PMOS transistor PM2 is connected to the source of PMOS transistor PM3, and the drain of PMOS transistor PM4 is connected to the source of PMOS transistor PM5. The drain of PMOS transistor PM5 outputs a zero-temperature current. The gates of PMOS transistors PM3 and PM3, the gates of PMOS transistor PM5, and one end of resistor R7 are connected to the base of NPN transistor Q1. Resistors R7, R8, R9, R10, and R11 are connected in series, with the other end of resistor R11 grounded. The terminal where resistors R7 and R8 are connected outputs a reference voltage. The terminal where resistors R8 and R9 are connected outputs a reference voltage. The terminal where resistors R9 and R10 are connected outputs a reference voltage. The terminal where resistors R10 and R11 are connected outputs a reference voltage. .

8. The ultra-low temperature drift bandgap reference circuit according to claim 7, characterized in that, Reference voltage Connect the inverting input terminal of op-amp A2, and the reference voltage. Connect the gate of PMOS transistor PM8, reference voltage Connect the gate of PMOS transistor PM11, reference voltage Connect the gate of PMOS transistor PM6.

9. The ultra-low temperature drift bandgap reference circuit according to claim 8, characterized in that, The startup circuit includes: PMOS transistor PM1, NMOS transistors NM1~NM3 and resistor R6; The source of PMOS transistor PM1 is connected to the power supply VDD, the gate is connected to one end of resistor R6, the drain is connected to the drain of NMOS transistor NM1, and the other end of resistor R6 is grounded. The gate, drain, NM2, and gate of NMOS transistor NM1 are connected to the drain of NMOS transistor NM4; the drain of NMOS transistor NM2 is connected to the gate of PMOS transistor PM2. The sources of NMOS transistors NM1, NM2, NM3, and NM4 are grounded to GND; the gate of NMOS transistor NM4 is connected to the base of NPN transistor Q1, and the drain of NMOS transistor NM3 is connected to the collector of NPN transistor Q2.

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