Manufacturing method of high-density circuit board for intelligent computing module
By fabricating conductive copper layers and vias on high-density circuit boards and combining this with multilayer dry film pattern control of the electroplating process, the problem of difficult lead processing and removal was solved, enabling reliable electroplating of gold on high-precision circuit boards and ensuring signal stability and integrity.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-03-06
- Publication Date
- 2026-04-14
AI Technical Summary
In the existing technology for electroplating gold on high-precision circuit boards, the leads are difficult to process and remove, leading to problems such as signal interference. In particular, it is difficult to meet the integrity requirements of the electroplated gold pads in the full gold-clad design.
Instead of designing leads, conductive channels are formed on the board surface by creating a conductive copper layer and outer circuitry in the tooling area. Combined with vias and conductive copper layers, this provides the current basis for gold plating, replacing the function of leads. The electroplating process is controlled by multi-layer dry film patterning to ensure the integrity of the gold plating pads.
This effectively avoids the problems of difficult lead removal and incomplete gold plating pads, ensuring reliable conduction and signal stability of high-precision circuits, and realizing fine gold plating processing of high-density circuit boards.
Smart Images
Figure CN121865526A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of circuit board design and manufacturing, and in particular to a method for manufacturing a high-density circuit board for an intelligent computing module. Background Technology
[0002] For some high-precision circuit boards used in smart electronic products or smart computing modules, the requirements for circuit precision are high. For areas where high-precision components need to be soldered or inserted, there is a design for electroplated gold pads with high precision circuits.
[0003] Existing electroplating gold processing technology requires the creation of leads to the electroplating gold pads. One end is connected to the electroplating gold pad, and the other end is connected to the copper foil in the tool area on the board edge. During electroplating, the clamps of the electroplating equipment hold the tool area on the board edge, and the current is conducted to the electroplating gold pad through the copper foil to form the electroplating conditions.
[0004] However, due to the small spacing between fine lines and the dense distribution of gold-plated pads, it is difficult to meet the space requirements for independently designed leads in blank areas. If leads are designed and manufactured, it is easy to increase the difficulty of processing the circuit pattern and make it difficult to remove the leads after electroplating. When the gold-plated layer of the circuit board is designed to completely cover the gold-plated pads (i.e., "full gold-covered" or "(three sides, one top) four-sided gold-covered" design to improve service life and signal stability), the base copper is usually exposed at the connection point with the gold-plated pads after the leads are removed, making it difficult to meet the requirement of full coverage.
[0005] If the leads are designed to be routed to the inner layer (so that the gold-plated pads meet the requirement of being gold-plated on all four sides), and then routed to the outer layer of the tooling area on the board edge, then blind vias need to be made at the gold-plated pads to connect to the inner layer. However, due to the dense circuitry, the blind vias are also densely fabricated, which is difficult to process. Moreover, after the gold plating is completed, only the leads in the tooling area can be removed, while the blind vias and inner layer leads cannot be removed (that is, the leads can only be cut by removing the tooling area, but the inner layer leads and blind vias cannot be completely removed). This will cause signal interference and other problems in subsequent applications.
[0006] Based on the above problems, there is a need to provide a circuit board manufacturing method for processing fine electroplated gold lines. Summary of the Invention
[0007] This invention aims to solve the problems of difficult processing and removal of leads in the electroplating gold processing of high-density circuit boards with fine lines. It provides a method for manufacturing a high-density circuit board for intelligent computing modules. The circuit board is formed into a processing board according to design data. The processing board includes forming lines, with the area within the forming lines being the effective area and the area outside the forming lines being the tool area. The design data includes electroplating gold pads. Electroplating is performed using electroplating chucks to clamp the tool area in an electroplating device. The clamping position of the electroplating chucks is located in the tool area. The manufacturing method includes the following steps:
[0008] S10: A core board is fabricated according to the design data. The core board includes a first copper layer on one side of the electroplated gold pads and a second copper layer on the other side. Through holes are drilled in the tool area of the core board. Then, the core board is electroplated to form an electroplated layer, and the through holes form conductive holes. Then, surface circuitry is fabricated, including the fabrication of the annular holes for the conductive holes. The entire board is then formed into a circuit pattern board.
[0009] S20: The circuit pattern board is electroplated with copper to form a conductive copper layer, and the whole board is formed into an electroplated copper board. A first dry film is applied to the electroplated copper board, and a first dry film pattern containing a window pattern is made, the first dry film window pattern corresponding to the distribution area of the electroplated gold pads; then the first stripping is performed, and the first dry film pattern is removed, and the whole board is formed into a bare pattern board.
[0010] S30: Apply a second dry film to the bare graphic board and create a second dry film graphic including a windowed pattern of the second dry film, wherein the windowed pattern of the second dry film corresponds to the area of the electroplated gold pad and the clamping position; the entire board is used to form a second dry film graphic board;
[0011] S40: The second dry film pattern board is electroplated with gold, then the second dry film pattern is removed, followed by a second removal of the plating, and after subsequent processing, the circuit board is formed.
[0012] Furthermore, the thicknesses of the first copper layer and the second copper layer are both less than the thicknesses in the design data; the thicknesses of the first copper layer and the second copper layer of the core board after the whole board is electroplated are both equal to the thicknesses in the design data.
[0013] Furthermore, the thickness of the first copper layer is less than the thickness in the corresponding design data; before the whole board is electroplated, an anti-plating dry film pattern layer is formed on the second copper layer; after the whole board is electroplated, the anti-plating dry film pattern layer is removed.
[0014] Furthermore, the copper plating includes sequentially performing copper plating, copper electroplating, and baking processes on the circuit pattern board.
[0015] Furthermore, the baking is performed at a temperature of 55°C to 75°C for 30 to 60 minutes.
[0016] Furthermore, the thickness of the conductive copper layer is 3 μm to 10 μm.
[0017] Furthermore, both the first and second plating removal processes are micro-etching processes.
[0018] Further, fabricating the surface circuitry includes: fabricating interconnected enclosed circuit patterns in the tool area; the annular hole connecting the enclosed circuit patterns; the clamping position located at at least one position on the enclosed circuit patterns; the electroplating chuck clamping and electrically connecting to the clamping position; the clamping position electrically connecting to the enclosed circuit patterns; the enclosed circuit patterns electrically connecting to the conductive copper layer; the conductive copper layer electrically connecting to the surface circuitry; and the surface circuitry electrically connecting to the electroplated gold pads.
[0019] Furthermore, the subsequent processing includes fabricating a solder resist layer on the electroplated gold plate, followed by forming and processing according to the forming line.
[0020] Furthermore, the design data also includes blind holes, which are fabricated simultaneously with the drilling of through holes, and the whole-board electroplating includes filling the blind holes with electroplating.
[0021] The technical solution of this invention does not use leads designed for electroplating gold processing. Instead, it creates a conductive copper layer on the board surface, which, combined with the outer layer circuitry, forms a conductive channel on the board surface, providing the current basis for electroplating gold. This replaces the function of leads in existing technologies and effectively avoids the difficulties in removing leads and forming fully gold-plated pads caused by high-precision circuitry.
[0022] By creating through holes in the tooling area, a through-through effect is achieved through the tooling area on the board edge, providing a more reliable double-sided or multi-layer conductivity guarantee for electroplating gold, and preventing the problem of poor conductivity on a single surface due to the presence of large areas without copper or circuit defects.
[0023] The process involves electroplating copper to form a conductive copper layer, followed by the first dry film window patterning, the first stripping, the second dry film window patterning, and finally electroplating a gold layer. This process utilizes the conductive copper layer and surface circuitry as channels to provide the electroplating current. The overall manufacturing method forms a streamlined and highly precise process with interconnected upstream and downstream steps. Attached Figure Description
[0024] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.
[0025] Figure 1 This is a flowchart illustrating the manufacturing process of the circuit board in this embodiment.
[0026] Figure 2 This is a schematic diagram of the cross-sectional structure of the core plate in this embodiment;
[0027] Figure 3 This is a schematic diagram of the cross-sectional structure of the through-hole plate in this embodiment;
[0028] Figure 4 This is a schematic diagram of the cross-sectional structure of the circuit board in this embodiment;
[0029] Figure 5 This is a schematic diagram of the cross-sectional structure of the electroplated copper plate according to this embodiment;
[0030] Figure 6 This is a schematic diagram of the cross-sectional structure of the first dry film graphic plate in this embodiment;
[0031] Figure 7 This is a schematic diagram of the bare plate cross-section structure in this embodiment;
[0032] Figure 8 This is a schematic diagram of the cross-sectional structure of the second dry film graphic plate in this embodiment;
[0033] Figure 9 This is a schematic diagram of the cross-sectional structure of the electroplated gold plate in this embodiment;
[0034] Figure 10 This is a schematic diagram of the cross-sectional structure of the plating stripping plate according to this embodiment;
[0035] Figure 11 This is a schematic diagram of the cross-sectional structure of the circuit board in this embodiment;
[0036] Figure 12 This is a schematic diagram of the circuit board planar structure according to this embodiment.
[0037] Explanation of icon numbers:
[0038] 10. Forming line; 20. Effective area; 30. Tooling area; 40. Electroplating gold area; 100. Core board; 110. First copper layer; 120. Second copper layer; 130. Inner layer board; 1310. Inner layer circuitry; 200. Through-hole board; 210. Electroplating layer; 220. Through-hole; 2210. Hole ring; 230. Blind hole; 300. Circuit pattern board; 310. Surface circuitry; 400. Electroplated copper plate; 4 10. Conductive copper layer; 500. First dry film pattern board; 510. First dry film pattern; 5110. First dry film windowed pattern; 600. Pattern bare board; 700. Second dry film pattern board; 710. Second dry film pattern; 720. Second dry film windowed pattern; 800. Electroplated gold board; 810. Electroplated gold layer; 900. Stripped plate board; 1000. Circuit board; 1010. Solder mask layer; 1020. Dense solder pads.
[0039] The objectives, features, and advantages of this invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation
[0040] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.
[0041] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indication will also change accordingly.
[0042] Furthermore, in this invention, descriptions involving "first," "second," etc., are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.
[0043] Please see Figure 1 , Figure 1 This is a flowchart illustrating the manufacturing process of the circuit board in this embodiment.
[0044] The method for manufacturing a circuit board 1000 with fine electroplated gold lines provided in this embodiment involves forming a processing board according to design data and processing it. The processing board includes forming lines 10, the area within the forming lines 10 is the effective area 20, and the area outside is the tool area 30. The design data includes electroplating gold pads. Electroplating is performed in an electroplating device by clamping the tool area 30 with an electroplating chuck. The clamping position of the electroplating chuck is located in the tool area 30. The manufacturing method includes... Figure 1 The processing steps are explained in detail below.
[0045] Please see Figures 2 to 4 ; Figure 2 This is a schematic diagram of the cross-sectional structure of the core plate in this embodiment; Figure 3 This is a schematic diagram of the cross-sectional structure of the through-hole plate in this embodiment; Figure 4 This is a schematic diagram of the cross-sectional structure of the circuit board in this embodiment.
[0046] Step S10:
[0047] Core board 100 is manufactured according to the design data (see [reference]). Figure 2 The core board 100 includes a first copper layer 110 with electroplated gold pads on one side and a second copper layer 120 on the other side; the inner layer 130 of the core board 100 can be an insulating dielectric layer or a multilayer board formed by processing, according to the prior art and application requirements.
[0048] Through holes are drilled in the tool area 30 of the core board 100. Then, the core board 100 is electroplated to form an electroplated layer 210. The through holes are transformed into vias 220, and the entire board is formed into a via plate 200 (see [reference]). Figure 3 ); then surface circuitry 310 is fabricated, including the annular ring 2210 for fabricating vias 220; the entire board is then formed into a circuit pattern board 300 (see [reference]). Figure 4 ).
[0049] In this embodiment, a core board 100 is first formed according to existing technology, and then an electroplating layer 210 is formed by electroplating the entire board, which provides a base layer for subsequent electroplating copper processing to form a conductive copper layer 410.
[0050] By creating through holes 220 in the tool area 30, an effective through-through conduction effect is formed, providing a more reliable double-sided or multi-layer conduction guarantee for electroplating gold, and preventing the problem of poor conduction of a single surface line 310 due to the presence of a large area without copper or line defects.
[0051] Through drilling and electroplating of the entire board, the metallization of the through holes (i.e., forming the through holes 220) and the copper thickness of the entire board surface are simultaneously increased (i.e., forming the electroplating layer 210).
[0052] In one embodiment, the thicknesses of the first copper layer 110 and the second copper layer 120 are both less than the thicknesses in the design specifications; the thicknesses of the first copper layer 110 and the second copper layer 120 of the core board 100 after electroplating are both equal to the thicknesses in the design specifications.
[0053] The thickness of the first copper layer 110 and the second copper layer 120 is reduced, and an electroplated layer 210 is formed after electroplating of the whole board. The copper thickness reaches the completed copper thickness in the design data. That is, the copper layer thickness is reduced first, and then the copper thickness requirement is met through electroplating. If both the first copper layer 110 and the second copper layer 120 are designed with electroplated gold pads, then the thickness of both copper layers is reduced first, and then electroplating is performed.
[0054] In one embodiment, the thickness of the first copper layer 110 is less than the thickness in the corresponding design data; before the whole board is electroplated, an anti-plating dry film pattern layer is formed on the second copper layer 120; after the whole board is electroplated, the anti-plating dry film pattern layer is removed.
[0055] If only the first copper layer 110 is designed with gold-plated pads, then an anti-plating dry film can be used to protect the second copper layer 120, and then the first copper layer 110 can be electroplated as a whole board.
[0056] Optionally, the entire plate can be electroplated to form an electroplated layer 210 using a vertical continuous electroplating process. This process employs an insoluble anode and combines a refined electroplating method that adds a copper sulfate solution to the electroplating tank. Compared to traditional electroplating methods, this method can form a copper plating layer with better uniformity, providing a good foundation for subsequent metallization processing.
[0057] In one embodiment, the design data also includes blind holes 230, which are fabricated simultaneously with drilling through holes, and the whole-board electroplating includes filling electroplating of the blind holes 230.
[0058] In the high-density interconnected circuit board 1000, there is generally a blind via 230 design. The blind via 230 can not only meet the design and application requirements, but also provide optional interlayer conduction effect during the processing, forming a conduction channel through the via 220, inner layer circuit 1310 (when the inner layer board 130 is a multilayer board, it has inner layer circuit 1310), blind via 230, surface circuit 310, and electroplated pads.
[0059] Please see Figures 5 to 7 ; Figure 5 This is a schematic diagram of the cross-sectional structure of the electroplated copper plate according to this embodiment; Figure 6 This is a schematic diagram of the cross-sectional structure of the first dry film graphic plate in this embodiment; Figure 7 This is a schematic diagram of the cross-sectional structure of the bare plate in this embodiment.
[0060] Step S20:
[0061] The circuit pattern board 300 is electroplated with copper to form a conductive copper layer 410, and the entire board is formed into an electroplated copper plate 400 (see [reference]). Figure 5 A first dry film is applied to the electroplated copper plate 400, and a first dry film pattern 510 containing a first dry film window pattern 5110 is created to form a first dry film pattern plate 500 (see [reference]). Figure 6 The first dry film window pattern 5110 corresponds to the distribution area of the electroplated gold pads (i.e. Figure 4 The electroplated gold area 40 shown in the diagram); then the first stripping is performed, and the first dry film pattern 510 is removed, forming the entire board into a patterned bare board 600 (see [reference]). Figure 7 ).
[0062] This embodiment utilizes the process flow and structural features to create a conductive copper layer 410, thereby replacing the electroplated gold leads. It eliminates the need to design separate electroplated gold leads on the board, effectively meeting the processing requirements of high-precision circuit electroplating and avoiding problems such as short circuits after electroplating, difficulty in removing leads, and incomplete coverage of the electroplated gold layer 810 caused by designing leads.
[0063] After the conductive copper layer 410 is formed, the conductive copper layer 410 of the electroplated gold area 40 needs to be removed in order to facilitate the subsequent electroplating gold process. Therefore, the conductive copper layer 410 in this area is removed by applying a first dry film to create a first dry film pattern 510 and performing the first stripping.
[0064] Preferably, the thickness of the conductive copper layer is 3μm to 10μm, which can form an effective conductive effect as an alternative to the "lead".
[0065] In one embodiment, copper plating includes sequentially performing copper plating, copper electroplating, and baking processes on the circuit pattern board 300.
[0066] The copper plating process provides a conductive basis for copper plating, and the electroplated copper forms a conductive copper layer 410. It has been verified that baking can effectively prevent the oxidation of the conductive copper layer 410 generated during the electroplating process, thereby avoiding problems such as delamination and peeling of the conductive copper layer 410, and preventing the generation of copper oxide residue after the plating is removed (removal of the conductive copper layer 410), which can lead to problems such as gold plating penetration and short circuits.
[0067] In one embodiment, baking is performed at a temperature of 55°C to 75°C for 20 to 50 minutes.
[0068] Verification has shown that low-temperature baking of the board can not only prevent delamination and peeling, but also prevent the thin conductive copper layer 410 from overheating and bubbling due to excessive baking, and prevent excessive expansion and contraction of the high-precision board during the heating process.
[0069] Please see Figure 8 ; Figure 8 This is a schematic diagram of the cross-sectional structure of the second dry film graphic plate in this embodiment.
[0070] Step S30:
[0071] A second dry film is applied to the bare pattern board 600, and a second dry film pattern 710 containing a second dry film windowed pattern 720 is fabricated. The second dry film windowed pattern 720 corresponds to the area of the electroplated gold pads and the clamping position (if the hole ring 2210 is located at the clamping position, then it corresponds to the hole ring 2210); the entire board is used to form the second dry film pattern board 700 (see [reference]). Figure 8 ).
[0072] The second dry film and the second dry film pattern 710 are made so that the board edge tool area 30 (a part of the area) forms a copper area that is electrically connected to the electroplating equipment, while exposing the area of the electroplating gold pad (i.e., the electroplating gold area 40), providing a board surface pattern base for the electroplating gold processing.
[0073] Preferably, the second dry film is an anti-electrolytic gold dry film.
[0074] Please see Figures 9 to 12 ; Figure 9 This is a schematic diagram of the cross-sectional structure of the electroplated gold plate in this embodiment; Figure 10 This is a schematic diagram of the cross-sectional structure of the plating stripping plate according to this embodiment; Figure 11 This is a schematic diagram of the cross-sectional structure of the circuit board in this embodiment; Figure 12 This is a schematic diagram of the circuit board planar structure according to this embodiment.
[0075] Step S40:
[0076] The second dry film pattern board 700 is electroplated with gold to form an electroplated gold layer 810, and the entire board is formed into an electroplated gold board 800 (see [reference]). Figure 9 Then, the second dry film pattern 710 is removed, followed by a second stripping process to form the stripped plate 900 (see [link]). Figure 10 After subsequent processing, circuit board 1000 is formed (see below). Figure 11 and Figure 12 ).
[0077] The circuit board 1000 is fabricated to form fine lines with electroplated gold, namely dense solder pads 1020.
[0078] Electroplating is performed on the fabricated board surface. An electroplated gold layer 810 is formed in the area of the electroplated gold pads (i.e., electroplated gold area 40). After the second dry film pattern 710 is removed, the conductive copper layer 410 is further removed, and then the circuit board 1000 is fabricated.
[0079] Preferably, both the first and second plating removal processes are performed using micro-etching, with the second plating removal being an alkaline etching process.
[0080] The conductive copper layer 410 is removed using rapid etching. In the first removal, the conductive copper layer 410 is replaced by an electroplated layer 210. By adjusting and controlling the micro-etching parameters (including chemical concentration, etching speed, etching time, etching spray volume, etc.), the conductive copper layer 410 is removed quickly without significantly affecting the electroplated layer 210. In the second removal, since the electroplated gold area 40 has already formed an electroplated gold layer 810, and the conductive copper layer 410 in other areas is replaced by an electroplated layer 210, the conductive copper layer 410 can also be removed quickly using micro-etching. The second removal uses alkaline etching, which can effectively prevent acid etching from causing gold surface corrosion to the electroplated gold layer 810.
[0081] In one embodiment, fabricating the surface circuit 310 includes fabricating an interconnected enclosed circuit pattern (not shown in the figures) onto the tool area 30, with the annular hole 2210 connecting the enclosed circuit pattern; the clamping position being located at at least one position on the enclosed circuit pattern; the electroplating chuck clamping and electrically connecting to the clamping position, the clamping position being electrically connected to the enclosed circuit pattern, the enclosed circuit pattern being electrically connected to the conductive copper layer 410, the conductive copper layer 410 being electrically connected to the surface circuit 310, and the surface circuit 310 being electrically connected to the electroplated gold pads.
[0082] An enclosed circuit pattern is created in the tool area 30, and the hole ring 2210 connects the enclosed circuit pattern to form a continuous conductive circuit pattern structure. During the gold plating process, a continuous conductive effect can be formed no matter which point the electroplating chuck clamps in the tool area 30. Furthermore, the conductivity of the board surface is achieved through the conductive copper layer 410, providing a current basis for the gold plating area 40.
[0083] In one embodiment, the subsequent processing includes fabricating a solder resist layer 1010 on the electroplated gold plate 800, followed by forming and processing along the forming line 10.
[0084] By fabricating a solder mask layer 1010 and removing the tooling area 30, a circuit board 1000 is formed.
[0085] The above are merely preferred embodiments of the present invention and do not limit the scope of the patent. Any equivalent structural transformations made using the contents of the specification and drawings of the present invention under the inventive concept of the present invention, or direct / indirect applications in other related technical fields, are included within the scope of patent protection of the present invention.
Claims
1. A method for manufacturing a high-density circuit board for an intelligent computing module, wherein the circuit board is formed into a processing board according to design data and processed, the processing board includes forming lines, the area within the forming lines is an effective area, and the area outside the forming lines is a tool area, the design data includes gold plating pads, the gold plating is performed by using a gold plating chuck to clamp the tool area in a gold plating device, the clamping position of the gold plating chuck is located in the tool area, characterized in that... The manufacturing method includes the following steps: S10: A core board is formed according to the design data. The core board includes a first copper layer on one side of the electroplated gold pad and a second copper layer on the other side. Through holes are drilled in the tool area of the core board, and then the core board is electroplated to form an electroplated layer, and the through holes form through holes; Next, surface wiring is fabricated, including fabricating the annular ring for the vias; The entire board is used to form the circuit pattern board; S20: The circuit pattern board is electroplated with copper to form a conductive copper layer, and the entire board is formed into an electroplated copper plate. A first dry film is applied to the electroplated copper plate, and a first dry film pattern containing a window pattern is created, wherein the first dry film window pattern corresponds to the distribution area of the electroplated gold pads. After the first stripping is performed, the first dry film pattern is removed, and the whole board is formed into a bare pattern board. S30: Apply a second dry film to the bare graphic board and create a second dry film graphic including a windowed pattern of the second dry film, wherein the windowed pattern of the second dry film corresponds to the area of the electroplated gold pad and the clamping position; the entire board is used to form a second dry film graphic board; S40: The second dry film pattern board is electroplated with gold, then the second dry film pattern is removed, followed by a second removal of the plating, and after subsequent processing, the circuit board is formed.
2. The method for manufacturing a high-density circuit board for an intelligent computing module according to claim 1, characterized in that, The thicknesses of the first copper layer and the second copper layer are both less than the thicknesses in the design data; the thicknesses of the first copper layer and the second copper layer of the core board after the whole board is electroplated are both equal to the thicknesses in the design data.
3. The method for manufacturing a high-density circuit board for an intelligent computing module according to claim 1, characterized in that, The thickness of the first copper layer is less than the thickness in the corresponding design data; before the whole board is electroplated, an anti-electroplating dry film pattern layer is formed on the second copper layer; after the whole board is electroplated, the anti-electroplating dry film pattern layer is removed.
4. The method for manufacturing a high-density circuit board for an intelligent computing module according to claim 1, characterized in that, The copper plating process includes sequentially performing copper plating, copper electroplating, and baking on the circuit board.
5. The method for manufacturing a high-density circuit board for an intelligent computing module according to claim 4, characterized in that, The baking process involves baking at a temperature of 55°C to 75°C for 30 to 60 minutes.
6. The method for manufacturing a high-density circuit board for an intelligent computing module according to claim 1, characterized in that, The thickness of the conductive copper layer is 3 μm to 10 μm.
7. The method for manufacturing a high-density circuit board for an intelligent computing module according to claim 1, characterized in that, Both the first and second plating removal processes are micro-etching processes.
8. The method for manufacturing a high-density circuit board for an intelligent computing module according to claim 1, characterized in that, Fabricating the surface circuitry includes: creating interconnected enclosed circuit patterns in the tool area; the annular hole connecting the enclosed circuit patterns; the clamping position located at at least one position on the enclosed circuit patterns; the electroplating chuck clamping and electrically connecting to the clamping position; the clamping position electrically connecting to the enclosed circuit patterns; the enclosed circuit patterns electrically connecting to the conductive copper layer; the conductive copper layer electrically connecting to the surface circuitry; and the surface circuitry electrically connecting to the electroplated gold pads.
9. A method for manufacturing a high-density circuit board for an intelligent computing module according to claim 1, characterized in that, The subsequent processing includes fabricating a solder resist layer on the electroplated gold plate, followed by forming and processing according to the forming line.
10. A method for manufacturing a high-density circuit board for an intelligent computing module according to claim 1, characterized in that, The design data also includes blind holes, which are fabricated simultaneously with the drilling of through holes, and the whole-board electroplating includes filling the blind holes with electroplating.