Multilayer electronic component

Abstract

The present disclosure provides a multilayer electronic component. The multilayer electronic component includes a body having dielectric layers and internal electrodes alternately arranged with the dielectric layers in a first direction. The body further includes a first surface and a second surface opposite to each other in a first direction, and a third surface and a fourth surface connected to the first surface and the second surface and opposite to each other in a second direction. An external electrode is provided, the external electrode including a connection portion provided on the third surface and the fourth surface, and a band portion extending from the connection portion to a portion of the first surface. A bump electrode is disposed on the tape portion of the outer electrode. A solder layer including a Sn-based solder including one or more of Sb, Ag, and Cu is disposed between the tape portion of the external electrode and the bump electrode. The solder layer extends to a surface of the bump electrode in the second direction and the connection portion of the external electrode.

Description

[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2024-0139988, filed on October 15, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to a multilayer electronic component. Background Technology

[0003] Multilayer ceramic capacitors (MLCCs), a type of multilayer electronic component, have become important surface-mount components used in industries such as communications, computers, home appliances, and automobiles due to their small size and guaranteed high capacitance. Specifically, MLCCs are key passive components used in various electrical and electronic devices, as well as information and communication devices, such as mobile phones, computers, and digital TVs. Furthermore, with the increasing use of MLCCs in automotive and infotainment systems, the demand for high reliability, high strength characteristics, and miniaturization is growing.

[0004] Because the dielectric layer included in a multilayer ceramic capacitor has piezoelectricity and electrostriction, piezoelectricity may occur between the internal electrodes when a direct current (DC) or alternating current (AC) voltage is applied to the multilayer ceramic capacitor, thereby causing vibration.

[0005] These vibrations can be transmitted through the external electrodes of the multilayer ceramic capacitor to the printed circuit board mounted on it, thus producing vibrational sound. This vibrational sound can correspond to audible frequencies in the range of 20Hz to 20000Hz, which may be unpleasant to humans, and such unpleasant vibrational sound can be referred to as acoustic noise.

[0006] Traditionally, methods for reducing acoustic noise have included different thicknesses for the upper and lower covers of the capacitor, attaching a ceramic-containing intermediary to the lower part of the capacitor, or attaching metal bumps to the lower part of the capacitor.

[0007] In the case of methods for attaching metal bumps to the lower part of a capacitor, it is known to use high-temperature solder to attach the external electrode and the metal bumps, and ordinary solder can be used to attach the substrate and electronic components.

[0008] In products with attached metal bumps (where high-temperature solder is only present between the external electrode and the metal bumps), the Sn plating that provides mountability may flow downwards due to the additional soldering process, resulting in a thinner upper portion of the Sn plating compared to that of a standard product. Consequently, when the Ni plating thins or cracks, it can act as a pathway for moisture penetration, potentially leading to reduced reliability. Summary of the Invention

[0009] One aspect of this disclosure is to provide a multilayer electronic component with excellent reliability.

[0010] Another aspect of this disclosure is to prevent installation defects from occurring.

[0011] However, the purpose of this disclosure is not limited to the foregoing, and can be more readily understood in the process of explaining specific embodiments of this disclosure.

[0012] A multilayer electronic component according to embodiments of the present disclosure may include: a body including a dielectric layer and inner electrodes disposed alternately with the dielectric layer in a first direction, and including a first surface and a second surface opposite to each other in the first direction, a third surface and a fourth surface connected to the first surface and the second surface and opposite to each other in the second direction, and a fifth surface and a sixth surface connected to the first surface and the fourth surface and opposite to each other in the third direction; an outer electrode including a connection portion disposed on the third surface and the fourth surface and a strip portion extending from the connection portion to a portion of the first surface; a bump electrode disposed on the strip portion of the outer electrode, and wherein a solder layer includes a Sn-based solder comprising one or more of Sb, Ag, and Cu, the solder layer being disposed between the strip portion of the outer electrode and the bump electrode, and extending to the surface of the bump electrode in the second direction and the connection portion of the outer electrode. Attached Figure Description

[0013] The above and other aspects, features and advantages of this disclosure will become clearer from the following detailed embodiments, taken in conjunction with the accompanying drawings, in which: Figure 1 This is a perspective view showing a multilayer electronic assembly according to an embodiment of the present disclosure.

[0014] Figure 2 yes Figure 1 A three-dimensional view of the bottom of the multi-layered electronic components.

[0015] Figure 3 It is along Figure 1 A cross-sectional view of a multilayer electronic component taken by line I-I'.

[0016] Figure 4 It is along Figure 1 A cross-sectional view of a multilayer electronic component taken from line II-II'.

[0017] Figure 5 This is an exploded perspective view showing the main body of a multilayer electronic component according to an embodiment of the present disclosure.

[0018] Figure 6yes Figure 3 A magnified view of region K1.

[0019] Figure 7 The lower surface of the bump electrode is schematically shown.

[0020] Figure 8 According to another embodiment of this disclosure Figure 3 A magnified view of region K1. Detailed Implementation

[0021] In the following description, embodiments of the present disclosure will be illustrated with reference to the accompanying drawings. However, the present disclosure may be exemplified in many different forms and should not be construed as being limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Therefore, for clarity of description, the shape and size of elements in the drawings may be exaggerated, and elements indicated by the same reference numerals in the drawings are the same elements.

[0022] In the accompanying drawings, irrelevant descriptions will be omitted to clearly depict this disclosure, and thicknesses may be enlarged to clearly represent multiple layers and regions. The same reference numerals will be used to describe the same elements having the same function within the scope of the same concept. Throughout the specification, unless otherwise expressly stated, when a component is referred to as "comprising" or "including," it means that it may also include other components, rather than excluding them.

[0023] In the accompanying drawings, the first direction may refer to the thickness direction, the second direction may refer to the length direction, and the third direction may refer to the width direction.

[0024] Figure 1 This is a perspective view showing a multilayer electronic assembly 100 according to an embodiment of the present disclosure.

[0025] Figure 2 yes Figure 1 A three-dimensional view of the bottom of the multi-layered electronic components.

[0026] Figure 3 It is along Figure 1 A cross-sectional view of a multilayer electronic component taken by line I-I'.

[0027] Figure 4 It is along Figure 1 A cross-sectional view of a multilayer electronic component taken from line II-II'.

[0028] Figure 5 This is an exploded perspective view showing the main body of a multilayer electronic assembly according to an embodiment of the present disclosure.

[0029] Figure 6 yes Figure 3 A magnified view of region K1.

[0030] In the following text, reference will be made to Figures 1 to 6 A multilayer electronic assembly 100 according to embodiments of the present disclosure is described in detail.

[0031] According to embodiments of the present disclosure, a multilayer electronic component 100 may include: a body 110 including a dielectric layer 111 and inner electrodes 121 and 122 alternately disposed with respect to the dielectric layer 111 in a first direction; the body 110 having a first surface 1 and a second surface 2 opposite to each other in the first direction, a third surface 3 and a fourth surface 4 connected to the first surface 1 and the second surface 2 and opposite to each other in the second direction, and a fifth surface 5 and a sixth surface 6 connected to the first surface to the fourth surface and opposite to each other in the third direction; outer electrodes 131 and 132 including a connection portion CP disposed on the third surface and the fourth surface and a strip portion BP extending from the connection portion to a portion of the first surface; bump electrodes 141 and 142 disposed on the strip portion of the outer electrodes; and solder layers 151 and 152 including a Sn-based solder comprising one or more of Sb, Ag, and Cu, the solder layers 151 and 152 being disposed between the strip portion of the outer electrodes and the bump electrodes, and extending to the surface of the bump electrodes in the second direction and the connection portion of the outer electrodes. Optionally, solder layers 151 and 152 may extend to the connection portion of the outer electrode and the two surfaces of the bump electrode that are opposite each other in the second direction and the two surfaces that are opposite each other in the third direction.

[0032] The body 110 may have dielectric layers 111 and internal electrodes 121 and 122 stacked therein alternately.

[0033] The main body 110 is not limited to a specific shape, and may have a hexahedral shape or a shape similar to a hexahedron, such as... Figure 1 and Figure 2 As shown in the diagram. Because the ceramic powder particles included in the body 110 can shrink during the sintering process, the body 110 may not have a hexahedral shape with perfectly straight lines. However, the body 110 may have a generally hexahedral shape.

[0034] The main body 110 may have a first surface 1 and a second surface 2 that are opposite to each other in a first direction, a third surface 3 and a fourth surface 4 that are connected to the first surface 1 and the second surface 2 and are opposite to each other in a second direction, and a fifth surface 5 and a sixth surface 6 that are connected to the first surface 1 and the second surface 2, connected to the third surface 3 and the fourth surface 4 and are opposite to each other in a third direction.

[0035] In an embodiment, the main body 110 may include a 1-3 corner connecting the first surface 1 and the third surface 3, a 1-4 corner connecting the first surface 1 and the fourth surface 4, a 2-3 corner connecting the second surface 2 and the third surface 3, and a 2-4 corner connecting the second surface 2 and the fourth surface 4. The 1-3 corner and the 2-3 corner may have a centrally contracting form toward the third surface 3 toward the main body 110 in a first direction, and the 1-4 corner and the 2-4 corner may have a centrally contracting form toward the fourth surface 4 toward the main body 110 in a first direction.

[0036] Since the inner electrodes 121 and 122 are not stacked on the edge region of the dielectric layer 111, a step difference may occur due to the thickness of the inner electrodes 121 and 122. When viewed from the first or second surface, the corners connecting the first surface with the third to sixth surfaces and / or the corners connecting the second surface with the third to sixth surfaces may have a central contraction towards the body 110 in the first direction. Alternatively, due to shrinkage behavior during the sintering process of the body, when viewed from the first or second surface, the corners connecting the first surface 1 with the third surface 3, the second surface 4, the third surface 5, and the fourth surface 6 and / or the corners connecting the second surface 2 with the third surface 3, the second surface 4, the third surface 5, and the fourth surface 6 may have a central contraction towards the body 110 in the first direction. Optionally, to prevent defects such as breakage, the corners of each surface of the connecting body 110 can be rounded by performing an additional process, wherein the corners connecting the first surface with the third to sixth surfaces and / or the corners connecting the second surface with the third to sixth surfaces can be rounded.

[0037] The corners may include corners 1-3 connecting the first and third surfaces, corners 1-4 connecting the first and fourth surfaces, corners 2-3 connecting the second and third surfaces, and corners 2-4 connecting the second and fourth surfaces. Additionally, corners may include corners 1-5 connecting the first and fifth surfaces, corners 1-6 connecting the first and sixth surfaces, corners 2-5 connecting the second and fifth surfaces, and corners 2-6 connecting the second and sixth surfaces. The first to sixth surfaces of the body 110 may be generally flat surfaces, and non-flat areas may be considered corners. In the following text, the extension of each surface may refer to a line extending from the flat portion of each surface.

[0038] In addition, in order to suppress the step difference caused by the inner electrodes 121 and 122, after stacking, the stacked body is cut so that the inner electrodes are exposed on two surfaces of the capacitance forming portion Ac in the third direction (width direction), and then a single dielectric layer or two or more dielectric layers are stacked on the two surfaces of the capacitance forming portion Ac in the third direction (width direction) to form the edge portions 114 and 115. In this case, the corners connecting the first surface to the fifth and sixth surfaces and the corners connecting the second surface to the fifth and sixth surfaces may not have a contracted form.

[0039] The plurality of dielectric layers 111 forming the main body 110 may be in a sintered state, and the adjacent dielectric layers 111 may be integrated with each other, making it difficult to distinguish the boundaries between the adjacent dielectric layers 111 without using a scanning electron microscope (SEM).

[0040] According to an embodiment of the present disclosure, the raw material for forming the dielectric layer 111 is not particularly limited as long as a sufficient electrostatic capacitance can be obtained using it. For example, a barium titanate-based material, a lead composite perovskite-based material, or a strontium titanate-based material can be used. The barium titanate-based material may include BaTiO3-based ceramic powder, and the BaTiO3-based ceramic powder may be, for example, (Ba 1-x Ca x )TiO3 (0 < x < 1), Ba(Ti 1-y Ca y )O3 (0 < y < 1), (Ba 1-x Ca x )(Ti 1-y Zr y )O3 (0 < x < 1, 0 < y < 1) or Ba(Ti 1-y Zr y )O3 (0 < y < 1), etc.

[0041] For the purpose of the present disclosure, the material for forming the dielectric layer 111 may include various ceramic additives, organic solvents, binders, dispersants, etc. added to powder particles (such as barium titanate (BaTiO3) powder particles, etc.).

[0042] The main body 110 may include: a capacitance forming portion Ac in which a capacitance is formed by alternately arranging the first inner electrode 121 and the second inner electrode 122 facing each other with the dielectric layer 111 interposed therebetween; and covering portions 112 and 113 formed on the upper and lower portions of the capacitance forming portion Ac in the first direction.

[0043] Furthermore, the capacitor forming part Ac is the part that contributes to the capacitor forming, and it can be formed by repeatedly stacking a plurality of first internal electrodes 121 and second internal electrodes 122 with a dielectric layer 111 between the first internal electrodes 121 and the second internal electrodes 122.

[0044] Cover portions 112 and 113 may include an upper cover portion 112 disposed on the upper part of the capacitor forming portion Ac in the first direction and a lower cover portion 113 disposed on the lower part of the capacitor forming portion Ac in the first direction.

[0045] The upper cover portion 112 and the lower cover portion 113 can be formed by stacking a single dielectric layer or two or more dielectric layers on the upper and lower surfaces of the capacitor forming portion Ac in the thickness direction, respectively, and the upper cover portion 112 and the lower cover portion 113 can help to substantially prevent damage to the internal electrode due to physical stress or chemical stress.

[0046] The upper cover 112 and the lower cover 113 may not include the inner electrode and may include the same material as the dielectric layer 111.

[0047] In other words, the upper cover 112 and the lower cover 113 may include ceramic materials, such as barium titanate (BaTiO3) based ceramic materials.

[0048] Additionally, edge portions 114 and 115 may be provided on the side surface of the capacitor forming portion Ac.

[0049] Edge portions 114 and 115 may include a first edge portion 114 disposed on one side surface of the capacitor forming portion Ac in the width direction and a second edge portion 115 disposed on the other side surface of the capacitor forming portion Ac in the width direction. That is, edge portions 114 and 115 may be disposed on both side surfaces of the capacitor forming portion Ac in the width direction.

[0050] like Figure 4 As shown, the edges 114 and 115 may refer to the region between the two ends of the first inner electrode 121 and the second inner electrode 122 and the outer surface of the body 110 in the width-thickness direction of the cross section of the body 110.

[0051] Edges 114 and 115 help to substantially prevent damage to the internal electrodes due to physical or chemical stress.

[0052] Edges 114 and 115 can be formed by applying conductive paste to the area of ​​the ceramic green sheet other than the area where the edge will be formed, to form an inner electrode.

[0053] In addition, in order to suppress the step difference caused by the inner electrodes 121 and 122, after stacking, the stack body can be cut so that the inner electrodes are exposed on the two surfaces of the capacitor forming part Ac in the third direction (width direction). Then, a single dielectric layer or two or more dielectric layers can be stacked on the two surfaces of the capacitor forming part Ac in the third direction (width direction) to form the edge parts 114 and 115.

[0054] The internal electrodes 121 and 122 may be stacked alternately with the dielectric layer 111.

[0055] The inner electrodes 121 and 122 may include a first inner electrode 121 and a second inner electrode 122. The first inner electrode 121 and the second inner electrode 122 are alternately arranged opposite each other, and a dielectric layer 111 is disposed between the first inner electrode 121 and the second inner electrode 122, and the first inner electrode 121 and the second inner electrode 122 may be exposed on the third surface 3 and the fourth surface 4 of the body 110, respectively.

[0056] Reference Figure 3 The first inner electrode 121 may be spaced apart from the fourth surface 4 and exposed through the third surface 3, and the second inner electrode 122 may be spaced apart from the third surface 3 and exposed through the fourth surface 4. The first outer electrode 131 may be disposed on the third surface 3 of the body and connected to the first inner electrode 121, and the second outer electrode 132 may be disposed on the fourth surface 4 of the body and connected to the second inner electrode 122.

[0057] That is, the first inner electrode 121 can be connected to the first outer electrode 131 but not to the second outer electrode 132, and the second inner electrode 122 can be connected to the second outer electrode 132 but not to the first outer electrode 131. Therefore, the first inner electrode 121 can be formed at a certain distance from the fourth surface 4, and the second inner electrode 122 can be formed at a certain distance from the third surface 3.

[0058] In this case, the first inner electrode 121 and the second inner electrode 122 can be electrically isolated from each other by a dielectric layer 111 disposed between the first inner electrode 121 and the second inner electrode 122.

[0059] The main body 110 can be formed by alternately stacking ceramic green sheets printed with conductive paste for the first internal electrode 121 and ceramic green sheets printed with conductive paste for the second internal electrode 122, and then firing them.

[0060] There are no particular restrictions on the materials used to form the internal electrodes 121 and 122, and any material with excellent conductivity can be used.

[0061] For example, internal electrodes 121 and 122 may include one or more of nickel (Ni), copper (Cu), palladium (Pd), silver (Ag), gold (Au), platinum (Pt), tin (Sn), tungsten (W), titanium (Ti), and alloys thereof.

[0062] Alternatively, the internal electrodes 121 and 122 can be formed by printing a conductive paste for the internal electrodes, including one or more of nickel (Ni), copper (Cu), palladium (Pd), silver (Ag), gold (Au), platinum (Pt), tin (Sn), tungsten (W), titanium (Ti), and alloys thereof, onto a ceramic green sheet. The printing method for the conductive paste for the internal electrodes may include screen printing or gravure printing, but this disclosure is not limited thereto.

[0063] The external electrodes 131 and 132 may include a connecting portion CP disposed on the third and fourth surfaces, and a strip portion BP extending from the connecting portion to a portion of the first surface. (See reference...) Figure 3 The area between the extension line E1 on the first surface and the extension line E2 on the second surface of the external electrodes 131 and 132 can be referred to as the connecting part CP, and the area below the extension line E1 on the first surface of the external electrodes 131 and 132 can be referred to as the strip part BP.

[0064] Furthermore, the belt portion BP is not limited to being disposed on the first surface, but can be configured to extend from the connecting portion to one or more of the second, fifth, and sixth surfaces.

[0065] The external electrodes 131 and 132 may include a first external electrode 131 and a second external electrode 132. The first external electrode 131 may be disposed on a third surface and connected to a first internal electrode 121, and the second external electrode 132 may be disposed on a fourth surface and connected to a second internal electrode 122.

[0066] Bump electrodes 141 and 142 may be disposed on the strip portion BP of the outer electrode. Bump electrodes 141 and 142 may help reduce or absorb vibrations transmitted from the substrate to the multilayer electronic components and may help suppress acoustic noise.

[0067] The bump electrodes 141 and 142 may include a first bump electrode 141 and a second bump electrode 142. The first bump electrode 141 may be disposed on the strip portion of the first external electrode 131 and may be electrically connected to the first external electrode 131, and the second bump electrode 142 may be disposed on the strip portion of the second external electrode 132 and may be electrically connected to the second external electrode 132.

[0068] Solder layers 151 and 152 facilitate bonding of external electrodes 131 and 132 to bump electrodes 141 and 142, respectively. Furthermore, when attaching multilayer electronic components to a substrate using conventional solder, solder layers 151 and 152 help prevent the Sn plating layers 131c and 132c and / or the bump Sn plating layers 141c and 142c from flowing downwards.

[0069] Solder layers 151 and 152 may include Sn-based solder, which includes one or more of Sb, Ag, and Cu. When the Sn-based solder contains one or more of Sb, Ag, and Cu, the melting point of the Sn-based solder may be 200°C or higher, and solder layers 151 and 152 may not melt when the multilayer electronic components are attached to the substrate using ordinary solder, thus helping to maintain the bonding between the external electrodes 131 and 132 and the bump electrodes 141 and 142.

[0070] According to embodiments of this disclosure, the Sn-based solder can be one or more of Sn-Sb-based solder, Sn-Ag-based solder, Sn-Cu-based solder, and Sn-Ag-Cu-based solder.

[0071] In addition, there are no particular restrictions on the content of Sb, Ag and Cu included in Sn-based solders, and they can be added appropriately according to the intended use and environment.

[0072] For example, in the case of Sn-Ag based solder, when the Sn content is 96.5 wt% and the Ag content is 3.5 wt%, a high melting point solder with a melting point of about 221 °C can be used, and in the case of Sn-Cu based solder, when the Sn content is 99.3 wt% and the Cu content is 0.7 wt%, a high melting point solder with a melting point of about 227 °C can be used.

[0073] Solder layers 151 and 152 may be disposed between the strip portion BP of the outer electrodes 131 and 132 and the bump electrodes 141 and 142, and may extend to the surfaces of the bump electrodes 141 and 142 in the second direction and the connection portion CP of the outer electrodes 131 and 132. According to embodiments of the present disclosure, since solder layers 151 and 152 extend to the surfaces of the bump electrodes 141 and 142 in the second direction and the connection portion CP of the outer electrodes 131 and 132, downward flow of the Sn plating layers 131c and 132c and / or the bump Sn plating layers 141c and 142c can be prevented when the multilayer electronic assembly is fixed to the substrate using ordinary solder. Furthermore, the outer electrodes 131 and 132 can be more firmly bonded to the bump electrodes 141 and 142, and the hermetic seal of the multilayer electronic assembly 100 can be enhanced.

[0074] When the solder layers 151 and 152 are provided only between the belt portions BP of the outer electrodes 131 and 132 and the bump electrodes 141 and 142, there is a concern about mounting defects occurring due to the downward flow of the Sn coatings 131c and 132c and / or the bump Sn coatings 141c and 142c not being prevented when fixing the multilayer electronic component to the substrate by using ordinary solder.

[0075] In an embodiment, the ends of the solder layers 151 and 152 provided on the connection portion may be provided between the extension line E1 of the first surface and the extension line E2 of the second surface. That is, the solder layers 151 and 152 may not need to cover the entire connection portion CP of the outer electrode, and even if the solder layers 151 and 152 only cover a part of the connection portion CP, the outer electrodes 131 and 132 can be firmly connected to the bump electrodes 141 and 142 while preventing the downward flow of the Sn coating.

[0076] In an embodiment, the following relationship can be satisfied: H1 < H2 < T / 2, where the average distance from the first surface to the innermost electrode closest to the first surface in the first direction is H1, the average distance from the extension line E1 of the first surface to the end of the solder layer provided on the connection portion in the first direction is H2, and the dimension of the main body in the first direction is T.

[0077] When H2 is greater than or equal to T / 2, in the case of the same amount of solder, the effect of improving the firm bonding of the outer electrodes 131 and 132 to the bump electrodes 141 and 142 while preventing the downward flow of the Sn coating may be insufficient.

[0078] By satisfying the condition H1 < H2, the effect of firmly bonding the outer electrodes 131 and 132 to the bump electrodes 141 and 142 while preventing the downward flow of the Sn coating can be more reliably ensured.

[0079] However, it is not intended to exclude the case where H2 is less than H1, and even when H2 is less than H1, the effect of firmly bonding the outer electrodes 131 and 132 to the bump electrodes 141 and 142 while preventing the downward flow of the Sn coating can be ensured, so that H1 ≥ H2 can be satisfied according to the embodiments of the present disclosure.

[0080] H1 and H2 can be the average values ​​measured from cross-sections cut from the central portion of the body 110 in the first and second directions in the third direction. H1 can be the average value of the distance between the inner electrode closest to the first surface 1 and the first surface 1 in the cross-section measured at a specific point in the second direction, and H2 can be a value measured based on the end of the solder layer disposed at the connection portion, and can be the average value of the value measured from the side of the first outer electrode 131 and the value measured from the side of the second outer electrode 132. In this case, the extension line E1 of the first surface, which serves as the reference for measuring H1 and H2, can be the same.

[0081] Furthermore, in the cross-section of the central portion of the main body 110 cut from the third direction upward in the first and second directions, the dimension T of the main body 110 in the first direction can be the average distance between the extension line E1 of the first surface and the extension line E2 of the second surface in the first direction.

[0082] In an embodiment, the area of ​​the solder layers 151 and 152 extending to the surface of the bump electrode in the second direction can be set to 50% or more of the area of ​​the surface of the bump electrode in the second direction. Therefore, the effect of firmly bonding the outer electrodes 131 and 132 to the bump electrodes 141 and 142 can be more reliably ensured while preventing the Sn plating from flowing downwards.

[0083] Additionally, solder layers 151 and 152 may extend to the lower surface of the bump electrode in the first direction. However, when solder layers 151 and 152 extend to the lower surface of the bump electrode in the first direction, it may be difficult to ensure the bonding strength between the multilayer electronic components and the substrate when using ordinary solder to fix the multilayer electronic components to the substrate, as solder layers 151 and 152 may not dissolve well in the ordinary solder. This may result in installation defects.

[0084] Therefore, in an embodiment, solder layers 151 and 152 may be configured to extend to a portion of the lower surface of the bump electrode in a first direction.

[0085] Reference Figure 7 , Figure 7 The lower surface of the bump electrode is schematically shown. More preferably, based on the total area of ​​the lower surface of the bump electrode 141 in the first direction, the area of ​​the region of the lower surface of the bump electrode 141 covered by the solder layer 151 in the first direction can be 10% or less. Therefore, the outer electrodes 131 and 132 can be firmly bonded to the bump electrodes 141 and 142 while preventing the Sn plating layer from flowing downward, and the bonding strength between the multilayer electronic components and the substrate can also be reliably ensured.

[0086] In other words, it is desirable to have a minimum solder layer on the lower surface of the bump electrode that contacts the substrate, and more preferably, the solder layer may not be provided on the lower surface of the bump electrode.

[0087] The method for controlling the arrangement of solder layers 151 and 152 is not particularly limited. Furthermore, in the heat treatment process for bonding external electrodes 131 and 132 to bump electrodes 141 and 142 using solder layers 151 and 152, the diffusion degree of solder layers 151 and 152 can be controlled by adjusting the heat treatment temperature, the material and amount of the solder layers, etc., thereby controlling the arrangement of solder layers 151 and 152. Additionally, by attaching a high-heat-resistant adhesive film for masking to the lower surfaces of bump electrodes 141 and 142 before heat treatment, the penetration of molten solder layers 151 and 152 to the lower surfaces of bump electrodes 141 and 142 can be more reliably prevented. The high-heat-resistant adhesive film attached to the lower surfaces of bump electrodes 141 and 142 can be removed after heat treatment.

[0088] In addition, at least a portion of the solder layer can be arranged in the form of islands.

[0089] Reference Figure 8 , Figure 8 According to another embodiment Figure 3 The enlarged view of region K1 shows that the solder layer 151' can be set discontinuously, or it can be set in the form of islands with regions interrupted in the middle.

[0090] However, in order to securely connect the outer electrodes 131 and 132 to the bump electrodes 141 and 142, it may be desirable to provide the solder layer 151 in the region between the strip portion of the outer electrode and the bump electrode in the form of a layer.

[0091] In addition, the external electrodes 131 and 132 can be formed using any material such as metal, as long as they are conductive, and the specific material can be determined by taking into account electrical properties, structural stability, etc., and the external electrodes 131 and 132 can also have a multilayer structure.

[0092] For example, the first external electrode 131 may include an electrode layer 131a disposed on the body 110 and plating layers 131b and 131c formed on the electrode layer.

[0093] For a more specific example of electrode layer 131a, the electrode layer may be a sintered electrode comprising a conductive metal and glass or a resin-based electrode comprising a conductive metal and resin.

[0094] Furthermore, the electrode layer 131a may have a form in which a sintered electrode and a resin-based electrode are sequentially formed on the body. Alternatively, the electrode layer may be formed by transferring a sheet including a conductive metal onto the body, or by transferring a sheet including a conductive metal onto a sintered electrode.

[0095] Materials with excellent electrical conductivity can be used as conductive metals included in electrode layer 131a, but are not particularly limited thereto. For example, the conductive metal can be one or more of nickel (Ni), copper (Cu), and alloys thereof.

[0096] Platings 131b and 131c can help improve mounting characteristics. There are no particular restrictions on the type of platings 131b and 131c, which can be one or more of Ni, Sn, Pd and their alloys, and can be formed in multiple layers.

[0097] In an embodiment, the first external electrode 131 may be connected to the first internal electrode 121, and may include an electrode layer 131a comprising Cu and glass, a Ni plating layer 131b disposed on the electrode layer, and a Sn plating layer 131c disposed on the Ni plating layer.

[0098] The bump electrodes 141 and 142 can be formed from any conductive material (such as metal), and the specific material can be determined by taking into account electrical properties, structural stability, etc., and can also have a multilayer structure.

[0099] For example, the bump electrode 141 may include a bump core 141a disposed at the center of the bump electrode and bump plating layers 141b and 141c disposed on the bump core.

[0100] In an embodiment, the bump electrode 141 may include: a bump core 141a disposed at the center of the bump electrode and comprising Cu; a bump Ni plating layer 141b disposed on the bump core 141a; and a bump Sn plating layer 141c disposed on the bump Ni plating layer 141b. Additionally, the bump electrode 142 may have a structure similar to that of the bump electrode 141 described above.

[0101] In an embodiment, the solder layer 151 may be configured to contact the Sn plating layer 131c and the bump Sn plating layer 141c.

[0102] Although the above description is based on the structure of the first external electrode 131 and the bump electrode 141, the second external electrode 132 and the bump electrode 142 may have a structure similar to that of the first external electrode 131 and the bump electrode 141.

[0103] One of the many effects of this disclosure is to improve the reliability of multilayer electronic components by controlling the arrangement of the solder layer connecting the bump electrodes and the strip.

[0104] One of the many effects of this disclosure is to suppress the occurrence of mounting defects when mounting multilayer electronic components on a substrate.

[0105] Although embodiments of the present disclosure have been described in detail above, the present disclosure is not limited to the above embodiments and drawings, and is intended to be limited by the appended claims. Therefore, within the scope of the technical spirit of the present disclosure described in the claims, those skilled in the art will be able to make various substitutions, modifications and alterations, which also fall within the scope of the present disclosure.

[0106] Furthermore, the expression "one embodiment" as used in this disclosure does not mean the same embodiment and is provided to emphasize and describe different unique features. However, the one embodiment presented above does not preclude implementation in combination with features of another embodiment. For example, even if a matter described in one particular embodiment is not described in another embodiment, it may be understood as a description relating to another embodiment, unless there is a description that is contrary to or contradictory to the matter in the other embodiment.

[0107] The terminology used in this disclosure is for describing one embodiment only and is not intended to limit the disclosure. In this context, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0108] While exemplary embodiments have been shown and described above, it will be readily understood by those skilled in the art that modifications and variations may be made without departing from the scope of the invention as defined by the appended claims.

Claims

1. A multilayer electronic component, comprising: The body includes a dielectric layer and internal electrodes disposed alternately with the dielectric layer in a first direction, and includes a first surface and a second surface opposite to each other in the first direction, a third surface and a fourth surface connected to the first surface and the second surface and opposite to each other in the second direction, and a fifth surface and a sixth surface connected to the first surface to the fourth surface and opposite to each other in the third direction. The external electrode includes a connecting portion disposed on the third surface and the fourth surface, and a strip extending from the connecting portion to a portion of the first surface; and A bump electrode is disposed on the strip portion of the outer electrode. The solder layer includes a Sn-based solder comprising one or more of Sb, Ag, and Cu. The solder layer is disposed between the strip portion of the outer electrode and the bump electrode, and extends to the surface of the bump electrode in the second direction and the connection portion of the outer electrode.

2. The multilayer electronic component according to claim 1, wherein, The Sn-based solder is selected from one or more of the group consisting of Sn-Sb-based solder, Sn-Ag-based solder, Sn-Cu-based solder, and Sn-Ag-Cu-based solder.

3. The multilayer electronic component according to claim 1, wherein, The end of the solder layer disposed on the connection portion is located between the extension line of the first surface and the extension line of the second surface.

4. The multi-layer electronic component according to claim 1 satisfies H1 < H2 < T / 2, where H1 is the average distance from the first surface to the inner electrode closest to the first surface in the first direction, H2 is the average distance from the extension line of the first surface to the end of the solder layer disposed on the connection in the first direction, and T is the dimension of the body in the first direction.

5. The multilayer electronic component according to claim 1, wherein H1 ≥ H2, H1 is the average distance from the first surface to the inner electrode closest to the first surface in the first direction. Wherein, H2 is the average distance from the extension of the first surface in the first direction to the end of the solder layer disposed on the connection portion.

6. The multilayer electronic assembly according to claim 1, wherein, The area of ​​the solder layer extending to the surface of the bump electrode in the second direction is set to 50% or more of the area of ​​the surface of the bump electrode in the second direction.

7. The multilayer electronic assembly according to claim 1, wherein, The solder layer extends to a portion of the lower surface of the bump electrode in the first direction.

8. The multilayer electronic component according to claim 7, wherein, Based on the total area of ​​the lower surface of the bump electrode, the area of ​​the region of the lower surface of the bump electrode covered by the solder layer in the first direction is 10% or less.

9. The multilayer electronic assembly according to claim 1, wherein, At least a portion of the solder layer is arranged in an island-like pattern.

10. The multilayer electronic component according to claim 9, wherein, The solder layer is disposed in a layered manner in the region between the strip portion of the outer electrode and the bump electrode.

11. The multilayer electronic assembly according to claim 1, wherein, The external electrode includes: an electrode layer connected to the internal electrode and comprising Cu and glass; a Ni plating layer disposed on the electrode layer; and a Sn plating layer disposed on the Ni plating layer.

12. The multilayer electronic assembly according to claim 11, wherein, The bump electrode includes: a bump core containing Cu and disposed at the center of the bump electrode; a bump Ni plating layer disposed on the bump core; and a bump Sn plating layer disposed on the bump Ni plating layer.

13. The multilayer electronic assembly according to claim 12, wherein, The solder layer is configured to contact the Sn plating layer and the bump Sn plating layer.

14. The multilayer electronic assembly according to claim 1, wherein, The solder layer comprises the Sn-based solder having a melting point of 200°C or higher.

15. The multilayer electronic assembly according to claim 1, wherein, The solder layer also extends to the two surfaces of the bump electrode that are opposite each other in the third direction.

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