Formation method of semiconductor structure
By using a protective layer as a second-side process support in RC-IGBT chip manufacturing, the process flow is simplified, the problems of adhesive residue and high fragmentation rate are solved, and more efficient production is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI HUAHONG GRACE SEMICON MFG CORP
- Filing Date
- 2026-01-20
- Publication Date
- 2026-04-17
AI Technical Summary
The existing RC-IGBT chip manufacturing process is complex, has problems such as adhesive residue and high breakage rate, and has a long process cycle.
Using a protective layer as the mechanical structure support for the second-side process of the substrate simplifies the second-side process flow, avoids adhesive residue, and thins the substrate through chemical mechanical polishing or wet etching, thereby simplifying the process flow and improving production efficiency.
The process flow for the second side of the substrate is simplified, adhesive residue is avoided, the breakage rate is reduced, the process cycle is shortened, production efficiency is improved, and costs are reduced.
Smart Images
Figure CN121888618A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and more particularly to a method for forming a semiconductor structure. Background Technology
[0002] RC-IGBT (reverse conducting IGBT) is a technology that integrates an insulated gate bipolar transistor (IGBT) and a diode (FRD) on the same chip. It achieves bidirectional conduction by incorporating a fast recovery diode and is widely used in power electronic devices to improve power density and reduce size.
[0003] RC-IGBT represents the future direction of highly integrated power semiconductor technology. Through ingenious chip-level design, it combines the functions of two chips in traditional solutions into one, achieving a perfect balance of miniaturization, low cost, and high performance. However, the design and manufacturing process of the chip itself becomes more complex; therefore, the manufacturing process of RC-IGBT chips needs to be optimized. Summary of the Invention
[0004] The technical problem solved by this invention is to provide a method for forming a semiconductor structure to optimize the manufacturing process of RC-IGBT chips.
[0005] To address the aforementioned technical problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a first device region and a second device region, the substrate including a first surface and a second surface opposite to each other, and having a first doped region therein; forming a first device structure in the first device region, the first device structure including a gate structure located in the first device region and an emitter located in the first device region; forming a second device structure in the second device region, the second device structure including an anode, the emitter and the anode being located on the first surface; forming a protective layer on the first surface of the substrate, the thickness of the protective layer being higher than the top surface of the emitter and the anode; thinning the second surface of the substrate using the protective layer as structural support; after thinning the second surface of the substrate, forming a collector in the first device region; and forming a cathode in the second device region, the collector and the cathode being located on the second surface.
[0006] Optionally, the method for forming a protective layer on the first surface of the substrate includes: applying a protective material layer to the first surface of the substrate; and thermally curing the protective material layer to form the protective layer.
[0007] Optionally, the protective layer may be made of an organic material, including polyimide.
[0008] Optionally, forming the first device structure further includes: forming a body region within the first device region, the first surface exposing the surface of the body region, the conductivity type of the body region being opposite to the conductivity type of the first doped region, the gate structure extending from the first surface through the body region to the first doped region; and forming an emitter in the first device region.
[0009] Optionally, forming a second device structure in the second device region further includes: forming an anode region in the second device region, the first surface exposing the surface of the anode region, the conductivity type of the anode region being opposite to the conductivity type of the first doped region; forming an anode in the second device region, the emitter and the anode being located on the first surface.
[0010] Optionally, forming an emitter in the first device region and an anode in the second device region includes: forming an emitter region within the body region, the emitter region being adjacent to the gate structure, the conductivity type of the emitter region being opposite to that of the body region; forming a first electrode layer on the emitter region, the first electrode layer being electrically connected to the emitter region, the first electrode layer further extending to the second device region and being electrically connected to the anode region, the emitter including the emitter region and the first electrode layer located on the emitter region, and the anode including an anode region and the first electrode layer located on the anode region.
[0011] Optionally, the thickness of the protective layer is higher than the top surfaces of the emitter and the anode, including: the height difference between the top surface of the protective layer and the top surface of the first electrode layer is at least the thickness of the first electrode layer.
[0012] Optionally, the ion doping concentration in the emission region is greater than the ion doping concentration in the first doping region.
[0013] Optionally, it further includes: forming a body contact region within the body region, the first surface exposing the body contact region, the conductivity type of the body contact region being the same as the conductivity type of the body region, and the ion doping concentration in the body contact region being greater than the ion doping concentration in the body region.
[0014] Optionally, before forming a protective layer on the first surface of the substrate, the method further includes: forming a first metal layer on the body contact region, the first metal layer being electrically connected to the body contact region; and forming a second metal layer on the gate structure, the second metal layer being electrically connected to the gate structure.
[0015] Optionally, forming a collector in the first device region and a cathode in the second device region includes: forming a collector region within a first doped region of the first device region, wherein the conductivity type of the collector region is opposite to that of the first doped region; forming a cathode region within a first doped region of the second device region, wherein the conductivity type of the cathode region is the same as that of the first doped region; forming a second electrode layer on the collector region and the cathode region, wherein the second electrode layer is electrically connected to the collector region and the cathode region, wherein the collector includes a collector region and a second electrode layer located on the collector region, and the cathode includes a cathode region and a second electrode layer located on the cathode region.
[0016] Optionally, the ion doping concentration in the current collector region is greater than the ion doping concentration in the first doped region; the ion doping concentration in the cathode region is greater than the ion doping concentration in the first doped region.
[0017] Optionally, before forming the collector region and cathode region within the first doped region, the method further includes: forming a buffer zone within the first doped region, the buffer zone being located between the collector region and cathode region and the first doped region, the conductivity type of the buffer zone being the same as that of the first doped region, and the ion doping concentration within the buffer zone being greater than the ion doping concentration within the first doped region and less than the ion doping concentration within the collector region.
[0018] Optionally, the method of forming the gate structure includes: forming a gate trench in a first device region, the gate trench extending from a first surface of the substrate through the body region to a first doped region; forming a gate dielectric layer on the sidewall surface and bottom surface of the gate trench; and forming a gate layer on the gate dielectric layer.
[0019] Optionally, the body region and the anode region are formed simultaneously, and the ion doping concentration in the body region is the same as the ion doping concentration in the anode region.
[0020] Optionally, the ion doping concentration in the body region is different from the ion doping concentration in the anode region.
[0021] Optionally, the conductivity type of the first doped region includes N-type, and the conductivity type of the body region includes P-type.
[0022] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:
[0023] The semiconductor structure formation method of the present invention uses a protective layer as a mechanical structural support for the second-side process of the substrate. After the second-side process of the substrate, it can be removed or not, thereby simplifying the second-side process flow of the substrate, avoiding the problem of introducing adhesive residue, and reducing the breakage rate. When the protective layer is not removed, it can reduce costs and increase efficiency, while shortening the process cycle and improving production efficiency. Attached Figure Description
[0024] Figures 1 to 7 This is a schematic diagram of the formation process of the semiconductor structure in an embodiment of the present invention. Detailed Implementation
[0025] As described in the background section, there is a need to optimize the manufacturing process of RC-IGBT chips.
[0026] Specifically, after the front-side processing of the wafer is completed, the back-side processing is required. The back-side processing includes wafer back-side thinning, photolithography, implantation, and resist removal. Therefore, bonding and debonding of glass substrates on the front side are necessary to restore the wafer to a thicker state and provide mechanical support during these processes. Other protective layer designs exist to replace glass substrates, but these all involve varying degrees of cost. Furthermore, removing the bonded glass substrate can easily lead to adhesive residue and stress cracking issues.
[0027] To address the aforementioned issues, the present invention provides a method for forming a semiconductor structure. This method employs a protective layer as the mechanical structural support for the second-side substrate process. This protective layer can be removed or not removed after the second-side substrate process, thereby simplifying the second-side substrate process flow, avoiding the introduction of adhesive residue, reducing the breakage rate, reducing costs and increasing efficiency when the protective layer is not removed, and shortening the process cycle and improving production efficiency.
[0028] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0029] Figures 1 to 7 This is a schematic diagram of the formation process of the semiconductor structure in an embodiment of the present invention.
[0030] Please refer to Figure 1 A substrate 100 is provided, the substrate 100 includes a first device region I and a second device region II, the substrate 100 includes a first surface S1 and a second surface S2 opposite to each other, and the substrate 100 has a first doped region 101.
[0031] The first doped region 101 has a conductivity type including N-type or P-type, and the first doped region 101 contains N-type ions or P-type ions. The N-type ions include phosphorus ions, arsenic ions or antimony ions, and the P-type ions include boron ions, boron-fluorine ions or indium ions.
[0032] In this embodiment, the conductivity type of the first doped region 101 includes N-type.
[0033] In this embodiment, the substrate 200 is made of silicon.
[0034] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.
[0035] Next, a first device structure is formed in the first device region I. The first device structure includes a gate structure 104 located in the first device region I and an emitter located in the first device region I. A second device structure is formed in the second device region II. The second device structure includes an anode, and the emitter and the anode are located on the first surface S1. The formation process of the gate structure 104, the emitter, and the anode is described in [reference needed]. Figures 1 to 4 .
[0036] Please continue to refer to this. Figure 1 A body region 102 is formed in the first device region I, and the first surface S1 exposes the surface of the body region 102. The conductivity type of the body region 102 is opposite to that of the first doped region 101. An anode region 103 is formed in the second device region II, and the first surface S1 exposes the surface of the anode region 103. The conductivity type of the anode region 103 is opposite to that of the first doped region 101.
[0037] The conductivity type of the body region 102 includes N-type or P-type, and the body region 102 contains N-type ions or P-type ions. The N-type ions include phosphorus ions, arsenic ions or antimony ions, and the P-type ions include boron ions, boron-fluorine ions or indium ions.
[0038] In this embodiment, the conductivity type of the body region 102 includes P-type.
[0039] The conductivity type of the anode region 103 includes N-type or P-type, and the anode region 103 contains N-type ions or P-type ions. The N-type ions include phosphorus ions, arsenic ions or antimony ions, and the P-type ions include boron ions, boron-fluorine ions or indium ions.
[0040] In this embodiment, the conductivity type of the anode region 103 includes P-type.
[0041] In this embodiment, the anode region 103 and the body region 102 are formed simultaneously in one process. The types and concentrations of doped ions in the anode region 103 and the body region 102 are the same, and the depths of the anode region 103 and the body region 102 are also the same.
[0042] In other embodiments, the ion doping concentration in the body region is different from the ion doping concentration in the anode region.
[0043] The formation process of the anode region 103 and the body region 102 includes an ion implantation process.
[0044] Please continue to refer to this. Figure 1 A gate structure 104 is formed in the first device region I, and the gate structure 104 extends from the first surface S1 through the body region 102 to the first doped region 101.
[0045] The method of forming the gate structure 104 includes: forming a gate trench (not shown) in a first device region I, the gate trench extending from a first surface S1 of a substrate 100 through the body region 102 to a first doped region 101; forming a gate dielectric material layer on the sidewall surface and bottom surface of the gate trench and on the surface of the first surface S1 of the substrate 100; forming a gate material layer on the gate dielectric material layer; planarizing the gate material layer and the gate dielectric material layer until the surface of the first surface S1 of the substrate 100 is exposed; forming a gate structure 104 in the gate trench, the gate structure 104 including a gate dielectric layer 1041 on the sidewall surface and bottom surface of the gate trench, and a gate layer 1042 located on the gate dielectric layer 1041, the gate layer 1042 filling the gate trench.
[0046] In this embodiment, the material of the gate dielectric layer 1041 includes silicon oxide or a low-K (K less than 3.9) material; the material of the gate layer 1042 includes polysilicon.
[0047] In this embodiment, the depth of the gate structure 104 is greater than the depth of the body region 102.
[0048] In another embodiment, a gate structure is first formed in a first device region, a body region is then formed in the first device region, and an anode region is formed in the second device region.
[0049] Please refer to Figures 2 to 4 An emitter is formed in the first device region I; an anode is formed in the second device region II, and the emitter and the anode are located on the first surface S1.
[0050] Please refer to Figure 2An emitter region 105 is formed within the body region 102. The emitter region 105 is adjacent to the gate structure 104. The conductivity type of the emitter region 105 is opposite to that of the body region 102.
[0051] The conductivity type of the emission region 105 includes N-type or P-type, and the emission region 105 contains N-type ions or P-type ions. The N-type ions include phosphorus ions, arsenic ions or antimony ions, and the P-type ions include boron ions, boron fluoride ions or indium ions.
[0052] In this embodiment, the conductivity type of the emission region 105 includes N-type.
[0053] The process for forming the emitter region 105 includes ion implantation.
[0054] In this embodiment, the ion doping concentration in the emission region 105 is greater than the ion doping concentration in the first doping region 101.
[0055] Please continue to refer to this. Figure 2 A body contact region 106 is formed within the body region 102, and the first surface S1 exposes the body contact region 106. The conductivity type of the body contact region 106 is the same as that of the body region 102, and the ion doping concentration in the body contact region 106 is greater than that in the body region 102.
[0056] The body contact area 106 is adjacent to the emission area 105.
[0057] The conductivity type of the body contact region 106 includes N-type or P-type, and the body contact region 106 contains N-type ions or P-type ions. The N-type ions include phosphorus ions, arsenic ions or antimony ions, and the P-type ions include boron ions, boron-fluorine ions or indium ions.
[0058] In this embodiment, the conductivity type of the body contact area 106 includes P-type.
[0059] The process for forming the body contact region 106 includes an ion implantation process.
[0060] Please refer to Figure 3 and Figure 4 , Figure 3 It is a 3D image. Figure 4 for Figure 3 A cross-sectional view along the AA1 direction shows an isolation layer 107 formed on the gate structure 104.
[0061] The isolation layer 107 is used to protect the surface of the gate structure 104 and to electrically isolate it from the subsequently formed first electrode layer.
[0062] The material of the isolation layer 107 includes a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride.
[0063] In this embodiment, the material of the isolation layer 107 includes silicon nitride.
[0064] Please continue to refer to this. Figure 3 and Figure 4 A first electrode layer 108 is formed on the emitter region 105. The first electrode layer 108 is electrically connected to the emitter region 105. The first electrode layer 108 also extends to the second device region II and is electrically connected to the anode region 103. The first electrode layer 108 is electrically isolated from the gate structure 104 through the isolation layer 107.
[0065] The emitter includes an emitter region 105 and a first electrode layer 108 located on the emitter region 105; the anode includes an anode region 103 and a first electrode layer 108 located on the anode region 103.
[0066] The material of the first electrode layer 108 includes a metal or a metal nitride; the metal includes one or more combinations of copper, aluminum, tungsten, cobalt, nickel and tantalum; the metal nitride includes one or more combinations of tantalum nitride and titanium nitride.
[0067] In this embodiment, the material of the first electrode layer 108 includes copper.
[0068] In this embodiment, the method further includes: forming a first metal layer (not shown) on the body contact region 106, the first metal layer being electrically connected to the body contact region 106; and forming a second metal layer (not shown) on the gate structure 104, the second metal layer being electrically connected to the gate structure 104.
[0069] In this embodiment, the first metal layer, the second metal layer, and the first electrode layer 108 are formed simultaneously in one process, and the first metal layer, the second metal layer, and the first electrode layer 108 have the same material and thickness.
[0070] In other embodiments, the first metal layer, the second metal layer, and the first electrode layer may be formed in different steps, and the materials and thicknesses of the first metal layer, the second metal layer, and the first electrode layer may be different.
[0071] The first metal layer is electrically connected to the body region 102 through the body contact region 106. The ion concentration in the body contact layer 106 is relatively high, thereby the contact resistance between the first metal layer and the body contact region 106 is relatively low.
[0072] Please refer to Figure 5 A protective layer 109 is formed on the first surface S1 of the substrate 100, and the thickness of the protective layer 109 is higher than the top surfaces of the emitter and the anode.
[0073] In this embodiment, the thickness of the protective layer 109 is higher than the top surfaces of the emitter and the anode, including: the height difference between the top surface of the protective layer 109 and the top surface of the first electrode layer 108 is at least the thickness of the first electrode layer 108.
[0074] The protective layer 109 is thick enough so that it can achieve greater strength after thermosetting. The protective layer 109 is strong enough to provide stronger support for the substrate 100 and is less prone to breakage during back-side processing of the substrate 100.
[0075] In this embodiment, the thickness of the protective layer 109 is also higher than the top surface of the first metal layer and the top surface of the second metal layer.
[0076] The method for forming a protective layer 109 on the first surface S1 of the substrate 100 includes: applying a protective material layer (not shown) to the first surface S1 of the substrate 100; and thermally curing the protective material layer to form the protective layer 109.
[0077] In this embodiment, the material of the protective layer 109 includes an organic material, which includes polyimide (PI).
[0078] In other embodiments, the organic material also includes bismaleimide resin (BMI), silaneyne resin (PSA), copolymers of silaneyne resin and polyimide, benzoxazole resin (such as PBOA, PBON), or polytriazole resin (PTA).
[0079] The protective layer 109 has good chemical resistance and high temperature resistance, making it suitable for various applications. Specifically, when the protective layer 109 is used as a structural support in the fabrication process of the second surface S2 of the substrate 100, its good chemical resistance and high temperature resistance provide stable structural support, ensuring that deformation and other problems are less likely to occur during the fabrication process of the second surface S2 of the substrate 100.
[0080] In this embodiment, the protective layer 109 has a high temperature resistance range greater than 300 degrees Celsius.
[0081] Please refer to Figure 6 With the protective layer 109 as structural support, the second surface S2 of the substrate 100 is thinned.
[0082] The process for thinning the second surface S2 of the substrate 100 includes chemical mechanical polishing or wet etching.
[0083] Please continue to refer to this. Figure 6 After thinning the second surface S2 of the substrate 100, a collector electrode is formed in the first device region I; a cathode electrode is formed in the second device region II, with the collector electrode and the cathode located on the second surface.
[0084] The method of forming a collector in the first device region I and a cathode in the second device region II includes: forming a collector region 111 in a first doped region 101 in the first device region I, wherein the conductivity type of the collector region 111 is opposite to that of the first doped region 101; forming a cathode region 112 in the first doped region 101 in the second device region II, wherein the conductivity type of the cathode region 112 is the same as that of the first doped region 101; and forming a second electrode layer 113 on the collector region 111 and the cathode region 112, wherein the second electrode layer 113 is electrically connected to the collector region 111 and the cathode region 112.
[0085] In this embodiment, the collector includes a collector region 111 and a second electrode layer 113 located on the collector region 111, and the cathode includes a cathode region 112 and a second electrode layer 113 located on the cathode region 112.
[0086] The conductivity type of the current collector 111 includes N-type or P-type, and the current collector 111 contains N-type ions or P-type ions. The N-type ions include phosphorus ions, arsenic ions or antimony ions, and the P-type ions include boron ions, boron-fluorine ions or indium ions.
[0087] In this embodiment, the conductivity type of the current collector 111 includes P-type.
[0088] In this embodiment, the ion doping concentration in the collector region 111 is greater than the ion doping concentration in the first doping region 101.
[0089] The cathode region 112 has an N-type or P-type conductivity, and contains N-type or P-type ions. The N-type ions include phosphorus ions, arsenic ions, or antimony ions, and the P-type ions include boron ions, boron-fluorine ions, or indium ions.
[0090] In this embodiment, the conductivity type of the cathode region 112 includes N-type.
[0091] In this embodiment, the ion doping concentration in the cathode region 112 is greater than the ion doping concentration in the first doping region 101.
[0092] The material of the second electrode layer 113 includes a metal or a metal nitride; the metal includes one or more combinations of copper, aluminum, tungsten, cobalt, nickel and tantalum; the metal nitride includes one or more combinations of tantalum nitride and titanium nitride.
[0093] In this embodiment, the material of the second electrode layer 113 includes copper.
[0094] Please continue to refer to this. Figure 6 Before forming the collector region 111 and the cathode region 112 in the first doped region 101, the method further includes: forming a buffer zone 110 in the first doped region 101, wherein the buffer zone 110 is located between the collector region 111 and the cathode region 112 and the first doped region 101.
[0095] In this embodiment, the conductivity type of the buffer 110 is the same as that of the first doped region 101.
[0096] The conductivity type of the buffer 110 includes N-type or P-type, and the buffer 110 contains N-type ions or P-type ions. The N-type ions include phosphorus ions, arsenic ions or antimony ions, and the P-type ions include boron ions, boron-fluorine ions or indium ions.
[0097] In this embodiment, the conductivity type of the buffer 110 includes N-type.
[0098] In this embodiment, the ion doping concentration in the buffer 110 is greater than the ion doping concentration in the first doped region 101, but less than the ion doping concentration in the collector region 111. The buffer 110 serves as an ion concentration transition between the first doped region 101 and the collector region 111, resulting in a gradient change in ion concentration, which is beneficial for the depletion of the first device structure formed in the first device region I in the first doped region 101.
[0099] In other embodiments, the buffer may not be formed.
[0100] Please refer to Figure 7 Remove the protective layer 109 to form the semiconductor structure.
[0101] In this embodiment, the process of removing the protective layer 109 includes a wet etching process, which uses a corresponding solvent to remove the protective layer 109 based on the principle of polarity dissolution, thereby removing the protective layer 109 cleanly with minimal damage to the semiconductor structure.
[0102] In other embodiments, the protective layer can be retained as part of the semiconductor structure for subsequent process fabrication. Please refer to the specific structure for details. Figure 6 As stated above.
[0103] The semiconductor structure includes: a first device structure located in the first device region I and a second device structure located in the second device region II.
[0104] The first device structure is an insulated gate bipolar transistor (IGBT), and the second device structure is a diode (FRD). The semiconductor structure constitutes an RC-IGBT.
[0105] RC-IGBTs connect the collector of an insulated-gate bipolar transistor (IGBT) to the cathode of a diode and the emitter to the anode of the diode, forming a structure with alternating P-type and N-type semiconductors. When forward-biased, current flows through the IGBT region; when reverse-biased, the built-in diode conducts the current.
[0106] The collector of the insulated gate bipolar transistor is connected to the cathode of the diode, and the emitter is connected to the anode of the diode. Specifically, the emitter is connected to the anode of the diode by simultaneously connecting the first electrode layer 108 to the emitter region 105 and the anode region 103; the collector is connected to the cathode of the diode by simultaneously connecting the second electrode layer 113 to the collector region 111 and the cathode region 112.
[0107] The protective layer 109 is used as the mechanical structure support for the S2 process of the second surface of the substrate 100. It can be removed or not after the S2 process of the second surface of the substrate 100, thereby simplifying the S2 process flow of the second surface of the substrate 100, avoiding the problem of introducing adhesive residue, reducing the fragmentation rate, reducing costs and increasing efficiency when the protective layer is not removed, and shortening the process cycle and improving production efficiency.
[0108] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a first device region and a second device region, the substrate including a first surface and a second surface opposite to each other, and the substrate having a first doped region; A first device structure is formed in the first device region, the first device structure comprising: a gate structure located in the first device region and an emitter located in the first device region; A second device structure is formed in the second device region, the second device structure including an anode, and the emitter and the anode are located on the first surface; A protective layer is formed on the first surface of the substrate, the thickness of which is greater than the top surfaces of the emitter and the anode; Using the protective layer as structural support, the second surface of the substrate is thinned; After thinning the second side of the substrate, a collector electrode is formed in the first device region; A cathode is formed in the second device region, and the collector and the cathode are located on the second surface.
2. The method for forming a semiconductor structure as described in claim 1, characterized in that, A method for forming a protective layer on a first surface of the substrate includes: applying a protective material layer to the first surface of the substrate; and thermally curing the protective material layer to form the protective layer.
3. The method for forming a semiconductor structure as described in claim 2, characterized in that, The protective layer is made of organic materials, including polyimide.
4. The method for forming a semiconductor structure as described in claim 1, characterized in that, Forming the first device structure further includes: forming a body region within the first device region, the first surface exposing the surface of the body region, the conductivity type of the body region being opposite to the conductivity type of the first doped region, the gate structure extending from the first surface through the body region to the first doped region; and forming an emitter in the first device region.
5. The method for forming a semiconductor structure as described in claim 4, characterized in that, The second device structure is formed in the second device region, further comprising: forming an anode region in the second device region, wherein the first surface exposes the surface of the anode region, and the conductivity type of the anode region is opposite to the conductivity type of the first doped region; forming an anode in the second device region, wherein the emitter and the anode are located on the first surface.
6. The method for forming a semiconductor structure as described in claim 5, characterized in that, The method of forming an emitter in the first device region and an anode in the second device region includes: forming an emitter region within the body region, the emitter region being adjacent to the gate structure, and the conductivity type of the emitter region being opposite to that of the body region; forming a first electrode layer on the emitter region, the first electrode layer being electrically connected to the emitter region, the first electrode layer further extending to the second device region and being electrically connected to the anode region, the emitter including the emitter region and the first electrode layer located on the emitter region, and the anode including an anode region and the first electrode layer located on the anode region.
7. The method for forming a semiconductor structure as described in claim 6, characterized in that, The thickness of the protective layer is higher than the top surfaces of the emitter and the anode, including: the height difference between the top surface of the protective layer and the top surface of the first electrode layer is at least the thickness of the first electrode layer.
8. The method for forming a semiconductor structure as described in claim 6, characterized in that, The ion doping concentration in the emission region is greater than the ion doping concentration in the first doping region.
9. The method for forming a semiconductor structure as described in claim 6, characterized in that, Also includes: A body contact region is formed within the body region, the first surface exposes the body contact region, the conductivity type of the body contact region is the same as the conductivity type of the body region, and the ion doping concentration in the body contact region is greater than the ion doping concentration in the body region.
10. The method for forming a semiconductor structure as described in claim 9, characterized in that, Before forming a protective layer on the first surface of the substrate, the method further includes: forming a first metal layer on the body contact region, the first metal layer being electrically connected to the body contact region; and forming a second metal layer on the gate structure, the second metal layer being electrically connected to the gate structure.
11. The method for forming a semiconductor structure as described in claim 1, characterized in that, Forming a collector in the first device region and a cathode in the second device region includes: forming a collector region within a first doped region of the first device region, wherein the conductivity type of the collector region is opposite to that of the first doped region; forming a cathode region within a first doped region of the second device region, wherein the conductivity type of the cathode region is the same as that of the first doped region; forming a second electrode layer on the collector region and the cathode region, wherein the second electrode layer is electrically connected to the collector region and the cathode region, wherein the collector includes a collector region and a second electrode layer located on the collector region, and the cathode includes a cathode region and a second electrode layer located on the cathode region.
12. The method for forming a semiconductor structure as described in claim 11, characterized in that, The ion doping concentration in the current collector region is greater than the ion doping concentration in the first doping region; the ion doping concentration in the cathode region is greater than the ion doping concentration in the first doping region.
13. The method for forming a semiconductor structure as described in claim 11, characterized in that, Before forming the collector region and cathode region within the first doped region, the method further includes: forming a buffer zone within the first doped region, the buffer zone being located between the collector region and cathode region and the first doped region, the conductivity type of the buffer zone being the same as that of the first doped region, and the ion doping concentration within the buffer zone being greater than the ion doping concentration within the first doped region and less than the ion doping concentration within the collector region.
14. The method for forming a semiconductor structure as described in claim 4, characterized in that, The method of forming the gate structure includes: forming a gate trench in a first device region, the gate trench extending from a first surface of a substrate through the body region to a first doped region; forming a gate dielectric layer on the sidewall surface and bottom surface of the gate trench; and forming a gate layer on the gate dielectric layer.
15. The method for forming a semiconductor structure as described in claim 4, characterized in that, The body region and the anode region are formed simultaneously, and the ion doping concentration in the body region is the same as the ion doping concentration in the anode region.
16. The method for forming a semiconductor structure as described in claim 4, characterized in that, The ion doping concentration in the body region is different from the ion doping concentration in the anode region.
17. The method for forming a semiconductor structure as described in claim 4, characterized in that, The conductivity type of the first doped region includes N-type, and the conductivity type of the bulk region includes P-type.