Driving circuit, power conversion circuit and driving method

Abstract

The invention provides a driving circuit, a power conversion circuit and a driving method, and belongs to the technical field of electronic circuits. The driving circuit comprises a driving unit and a resistor. The driving unit is used for providing a driving signal. The first end of the resistor is electrically connected to the control end of a switch, and the second end of the resistor is used for receiving the driving signal. Wherein the resistance value of the resistor is matched with the duty ratio of the driving signal, so that the switch is in a constant current region in the starting stage. According to the embodiment of the invention, the resistor is matched with the duty ratio of the driving signal, so that the switch is in a constant-current region in the starting stage, the starting current of the switch is limited, and the safety is ensured.

Description

Technical Field

[0001] This disclosure relates to the field of electronic circuit technology, and in particular to a driving circuit, a power conversion circuit, and a driving method. Background Technology

[0002] In traditional soft-start processes, the switching transistor typically operates in the variable resistance region. In this operating state, the rate of voltage change (dv / dt) across the transistor is high, leading to a significant increase in startup current, posing a potential risk to the reliability of the switching device itself and the overall system. With the significant increase in power density, the switching frequency also increases, making the aforementioned problems particularly prominent in applications requiring high efficiency and high power density, thus limiting the further widespread application of this topology in related fields. Summary of the Invention

[0003] This disclosure provides a driving circuit, a power conversion circuit, and a driving method that can limit the starting current during the switching start-up phase, thereby improving safety.

[0004] This disclosure provides a driving circuit, including: a driving unit for providing a driving signal; a resistor, the first end of which is electrically connected to the control terminal of a switch, and the second end of which is used to receive the driving signal; wherein, by coordinating the resistance value of the resistor and the duty cycle of the driving signal, the switch is in a constant current region during the startup phase.

[0005] This disclosure provides a power conversion circuit, including a first power converter. The first power converter includes a first switching unit, wherein at least one switch in the first switching unit is driven by a driving circuit described in any embodiment of this disclosure.

[0006] This disclosure provides a driving method, including: providing a driving signal; transmitting the driving signal to the control terminal of a switch through a resistor; and ensuring that the switch is in a constant current region during the startup phase by coordinating the resistance value of the resistor and the duty cycle of the driving signal.

[0007] The driving circuit provided in this embodiment adds a resistor between the switch and the driving unit, and through the coordination of the resistor and the duty cycle of the driving signal provided by the driving unit to the switch, the switch is in a constant current region during the startup phase, thereby limiting the startup current of the switch during the startup phase and improving the safety of the switch. Attached Figure Description

[0008] Figure 1 A schematic diagram of the drive circuit in an exemplary embodiment of this disclosure is shown.

[0009] Figure 2A schematic diagram of the power conversion circuit in an exemplary embodiment of this disclosure is shown.

[0010] Figure 3 A schematic diagram of the power conversion circuit in another exemplary embodiment of this disclosure is shown.

[0011] Figure 4 This diagram illustrates the soft-start phase in an exemplary embodiment of the present disclosure.

[0012] Figure 5 The diagram illustrates a switch in an exemplary embodiment of this disclosure with different drive resistors.

[0013] Figure 6 This diagram illustrates the duty cycle of the drive signal at different stages in an exemplary embodiment of this disclosure.

[0014] Figure 7 This diagram illustrates the duty cycle of the drive signal at different stages in another exemplary embodiment of this disclosure.

[0015] Figure 8 This diagram illustrates the duty cycle of the drive signal at different stages in yet another exemplary embodiment of this disclosure.

[0016] Figure 9 This diagram illustrates the duty cycle of the drive signal at different stages in yet another exemplary embodiment of the present disclosure.

[0017] Figure 10 A schematic diagram of the power conversion circuit in yet another exemplary embodiment of this disclosure is shown.

[0018] Figure 11 A schematic diagram of PWM compensation in an exemplary embodiment of this disclosure is shown.

[0019] Figure 12 A flowchart illustrating the driving method in an exemplary embodiment of this disclosure is shown. Detailed Implementation

[0020] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0021] Furthermore, the accompanying drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0022] It should be understood that the steps described in the method embodiments of this disclosure may be performed in different orders and / or in parallel. Furthermore, the method embodiments may include additional steps and / or omit the steps shown. The scope of this disclosure is not limited in this respect.

[0023] It should be noted that the concepts of "first" and "second" mentioned in this disclosure are used only to distinguish different devices, modules or units, and are not used to limit the order of functions performed by these devices, modules or units or their interdependencies.

[0024] It should be noted that the terms "a" and "a plurality of" used in this disclosure are illustrative rather than restrictive, and those skilled in the art should understand that, unless otherwise expressly indicated in the context, they should be understood as "one or more".

[0025] With the significant increase in power density of power modules, the switching frequency also increases. Furthermore, since some power modules have fixed-frequency output and fixed gain, the gain cannot be adjusted by changing the switching frequency. Therefore, even with a small duty cycle during the soft-start phase, the switches / transistors in the power module exhibit a high rate of voltage change (dv / dt), resulting in a large startup current for the switching transistors, which poses a certain risk. This disclosure proposes a drive circuit that controls the duty cycle of the switch drive signal and a suitable drive resistor (i.e., the resistor described below). This is used to control the switching transistor, so that it operates in the constant current region during the soft start phase, thereby limiting the starting current.

[0026] like Figure 1 As shown, the driving circuit 100 provided in this embodiment includes a driving unit / driving chip 110 and resistors. The drive unit 110 is used to provide drive signals. Resistor The first terminal is electrically connected to the control terminal of a switch S, and the resistor The second end is used to receive the drive signal.

[0027] For example, the drive unit 110 includes a power supply terminal VDD, a reference voltage terminal VREF, an input positive terminal IN+, an input negative terminal IN-, a first output terminal OTH, and a second output terminal OUTL. Resistors The second terminal is electrically connected to the first output terminal OUTH of the drive unit 110 to receive the drive signal output by it for driving the switch S.

[0028] Among them, through resistor The combination of the resistance value and the duty cycle of the drive signal ensures that switch S is in the constant current region during the startup phase.

[0029] Figure 1 The driving circuit 100 shown also includes a resistor R off Its first end is electrically connected to the control terminal of switch S, and its second end is electrically connected to the second output terminal OUTL of drive unit 110. The signal output from the second output terminal OUTL is used to turn off switch S. off Used to discharge when switch S is turned off.

[0030] For example, during the startup phase, through the resistor The duty cycle of the drive signal ensures that the source-drain voltage Vds of switch S is greater than the pinch-off voltage VP, thus placing switch S in the constant current region during the startup phase. The pinch-off voltage VP is equal to the gate-source voltage of switch S. The difference between Vds and the threshold voltage Vgsth (also expressed as Vth) of switch S. That is, when switch S is in the constant current region, Vds > VP, VP = -Vgsth.

[0031] For example, switch S includes a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). For example, switch S includes an N-channel enhancement-mode MOSFET. According to the characteristic curve of an N-channel enhancement-mode MOSFET, its operating region is defined by the drain-source voltage Vds and the gate-source voltage Vds. Jointly decided, when Vds < When Vth = -Vth, switch S is in the variable resistance region. When Vds = -Vth, switch S is in the pre-pinch-off trajectory. When Vds > When -Vth, switch S is in the constant current region.

[0032] For example, switch S includes a gate, a source, and a drain. The control terminal of switch S is its gate, the first terminal of switch S is its drain, and the second terminal is its source.

[0033] For example, during the startup phase, through the resistor The combination of the resistance value and the duty cycle of the drive signal causes the peak value of the gate-source voltage of switch S to be... The ratio of the voltage to the threshold voltage Vgsth of switch S is within a preset range so that switch S is in the constant current region.

[0034] In this embodiment of the disclosure, the peak value of the gate-source voltage of switch S refers to the highest point of the voltage waveform actually measured at the gate-source terminal of switch S during any switching cycle in the dynamic switching process (turn-on process or turn-off process). The peak values ​​of the gate-source voltage in different switching cycles may be equal or unequal, but they are all lower than the absolute maximum rated value of switch S.

[0035] For example, the preset range is between 1 and 1.8, that is... / Vgsth=1~1.8. This is to ensure the peak gate-source voltage of switch S is... Slightly higher than its threshold voltage Vgsth, so that it is in the constant current region and avoids entering the variable resistance region.

[0036] For example, the preset range is between 1.17 and 1.47, that is... / Vgsth=1.17~1.47.

[0037] For example, when the threshold voltage Vgsth of switch S is 1.7V, during the startup phase, the peak value of the gate-source voltage of switch S is controlled. It is between 2V and 2.5V.

[0038] When switch S operates in the constant current region, its conduction current is mainly determined by its gate voltage. The control allows the maximum current that switch S can carry to be nearly constant, thus limiting the starting current during startup without affecting stable operation during steady-state operation.

[0039] like Figure 5 The figure shows the gate voltage (also known as the gate-source voltage) of switch S. Schematic diagrams for different driving resistors, i.e., resistors with different resistance values. Gate voltage under The diagram shows that Vgs_Ron_small represents the state of switch S with a small resistance. Gate voltage under Vgs_Ron_big indicates that switch S is in a larger resistance. Gate voltage under When the resistance Increasing this value will reduce EMI (Electromagnetic Interference). Vdriver_out represents the drive signal provided to the gate of switch S. Vout represents the output voltage of the power conversion circuit when switch S is used as a switch in the power conversion circuit, and Vo represents the target value that the output voltage Vout is expected to achieve.

[0040] refer to Figure 5 During the startup phase, specifically between time t1 and time t3, the duty cycle of the drive signal Vdriver_out emitted by the driver chip is very small. Therefore, in the resistor... When the resistance is small, the gate voltage of switch S is... The rising slope is relatively large, and the peak value of the gate-source voltage of switch S is large. When the value is relatively large, for example, when Vgsth is 1.7V, Reaching 5-7V allows switch S to operate in the variable resistance region, with switch S fully conducting. At this point, Vds of switch S is close to 0V, resulting in a large starting current. This embodiment of the disclosure increases the resistance... The resistance value is such that, due to the very small duty cycle of the drive signal Vdriver_out during the startup phase, the gate voltage of switch S is... Slow rise, peak gate-source voltage of switch S The voltage is slightly higher than the threshold voltage Vgsth between the first time t1 and the third time t3 (e.g., Vgsth is 1.7V). (2-2.5V), so that switch S operates in the constant current region, at which time Vds of switch S is greater than -Vgsth reduces the starting current of switch S. Specifically, when... When the voltage is less than Vgsth, switch S is in the cutoff region (also known as the off region), and switch S is turned off. Between the first time t1 and the third time t3, the output voltage Vout gradually increases.

[0041] It is understandable that, between the first time t1 and the third time t3, the duty cycle of the driving signal Vdriver_out can be a fixed, small value (e.g., 3%, or 1.5%, which can be determined according to the actual scenario, and this disclosure does not limit this); or, the duty cycle can increase linearly or non-linearly, as long as the switch S can still operate in the constant current region even when it increases to the maximum duty cycle between the first time t1 and the third time t3. In this embodiment, by gradually increasing the duty cycle of the driving signal Vdriver_out between the first time t1 and the third time t3, the conduction speed of the switch S can be accelerated.

[0042] Continue to refer to Figure 5Between the third time t3 and the fourth time t4, the duty cycle of the driving signal Vdriver_out gradually increases to 50%, and then can maintain a constant duty cycle of 50%.

[0043] For example, for switch S to enter the constant current region, two conditions must be met: the duty cycle of the drive signal is small, and the resistance... The resistance is relatively large, thus reducing the starting current of switch S and slowing down the conduction speed of switch S. This operation allows switch S to operate in the constant current region, utilizing the drain current in this region... The controlled and essentially constant characteristics effectively limit the inrush current. Since the loss of switch S is proportional to Vds, the drain-source voltage Vds of switch S is relatively high in the constant current region, resulting in relatively large conduction losses. Therefore, in this embodiment, switch S is controlled to operate in the constant current region during the soft-start / start-up phase, i.e., from t1 to t3. When the soft-start phase ends (after t3), the duty cycle of the drive signal is rapidly increased to the value required for normal operation (e.g., 50%), causing switch S to fully enter the variable resistance region. In this region, Vds decreases significantly, thereby greatly reducing losses and allowing switch S to enter a highly efficient and normal operating state.

[0044] Exemplarily, the drive signal has a first frequency and a first period. Exemplarily, the first frequency refers to the switching frequency of switch S, and the first period refers to the switching period of switch S. In embodiments of this disclosure, switch S and the power conversion circuit applying switch S are fixed-frequency, i.e., the gain of the power conversion circuit is not adjusted by adjusting the switching frequency.

[0045] For example, in this embodiment of the present disclosure, the duty cycle of the drive signal is first fixed, and then the resistance is determined based on the fixed duty cycle of the drive signal. The resistance value; then, based on the determined resistance... The resistance value is adjusted to change the duty cycle of the drive signal so that switch S is in the constant current region during the startup phase.

[0046] For example, the driving time of the drive signal is determined to be a set value; the peak value of the gate-source voltage of switch S during the startup phase is determined. Determine the amplitude of the drive signal; based on the set value and the peak value of the gate-source voltage of switch S during the startup phase. And the amplitude of the driving signal, to determine the resistance. The resistance value.

[0047] For example, resistor (can also be expressed as) , The method for determining the resistance value of (, ...) is as follows: First, obtain the gate parasitic resistance and input capacitance of switch S; then, based on the set value of the drive time and the peak value of the gate-source voltage of switch S during the startup phase... The amplitude of the drive signal, the gate parasitic resistance of switch S, and the input capacitance are used to determine the resistance. The resistance value.

[0048] In this embodiment of the disclosure, The calculation and switching characteristics are related. Therefore, as Figure 2 and Figure 3 As shown, different switches, such as switches S1, S2, S3, and S4, can each have their own corresponding resistors. The resistance values ​​are expressed as follows: , , , The resistance value of each can be determined using the following method.

[0049] Specifically, the resistance can be determined according to the following gate charging formula. Resistance value: (1) (2) in, This represents the peak value of the gate-source voltage of switch S during the startup phase. Indicates the amplitude of the driving signal. This indicates the set value of the drive time. It is a time constant. This indicates the resistance. This represents the gate parasitic resistance of switch S. This represents the input capacitance of switch S.

[0050] For example, the set value The conduction time corresponding to the minimum duty cycle of the drive signal during the startup phase. =D min ×TS, D min TS represents the minimum duty cycle of the drive signal, and TS represents the switching period. This ensures that at any point during the startup phase, switch S can be reliably driven to the gate voltage required to enter the constant current region, thus guaranteeing a smooth startup. Of course, this disclosure is not limited thereto. It can also be set based on experience (such as D=3%) or other constraints.

[0051] For example, let the driving voltage be (i.e., the amplitude of the drive voltage Vdriver_out provided by the driver chip), drive time Gate parasitic resistance of switch S The input capacitor of switch S Then the gate voltage of switch S Changes over time and driving voltage The relationship can be expressed by the following formula: (3) Therefore, to ensure that switch S operates in the constant current region, the source-drain voltage Vds of switch S must be greater than VP (pinch-off voltage). Where VP = -Vgsth. According to the above formula, the resistance... Together with the duty cycle D (which determines the effective charging time), it determines... The rising slope and peak value of the switch S are used to control its operating area. This is achieved through precise configuration. With the given resistance value, this embodiment can control switch S as a controllable constant current source during the soft-start phase. During the soft-start of the power conversion circuit, by actively limiting the rise rate and peak value of the gate voltage, excessive voltage overshoot and current surge caused by circuit parasitic parameters can be effectively suppressed, thereby achieving reliable soft-start.

[0052] Determine the resistance based on the foregoing content. After determining the resistance value, this disclosure performs soft start by adjusting the duty cycle D of the drive signal. The specific control strategy is as follows: First, to ensure control effectiveness, the upper limit of the duty cycle D needs to be determined. Based on the target gate-source voltage peak value... Drive voltage and the determined resistance Gate parasitic resistance Input capacitor Parameters, using gate charging formulas (1) and (2) and ton=D max ×TS can be used to deduce the maximum allowable value D of the duty cycle during the startup phase. max The D max This is the critical condition that ensures switch S operates in the constant current region without entering the fully on state (variable resistance region). Subsequently, during the soft-start phase, the control circuit limits the duty cycle D of the drive signal to D0. min With D max Dynamic adjustments can be made between them (e.g., making D change from D). min (Initially increases linearly). In this way, the gate voltage build-up process can be precisely controlled, ensuring that switch S remains in the constant current region during soft start-up, thereby smoothly limiting the inrush current and achieving reliable soft start-up.

[0053] The core advantage of this method lies in: the hardware parameters (resistance) are optimized. Once determined, the duty cycle, a single variable, can be adjusted through digital or analog control circuits to achieve a complex, adaptive soft-start curve, balancing design flexibility and reliability.

[0054] For example, suppose Set to 2.5V. Once determined using the aforementioned method, substitute the values ​​into the formula above to calculate the maximum duty cycle D of switch S operating in the constant current region. max Then, the minimum duty cycle D during the startup phase over time. min and D max Adjust the duty cycle D to make the switch work in the constant current region.

[0055] For example, such as Figure 4 As shown, the startup phase can also be called the soft-start phase. The startup phase includes a first phase from the first time t1 to the second time t2, and a second phase from the second time t2 to the third time t3.

[0056] For example, the judgment point at the second time t2 can be that the output voltage Vout reaches a second predetermined percentage (first target value) of the target value Vo, for example... Figure 4 The example used is 90%, but this disclosure is not limited to this and can be set according to the actual circuit. The judgment point at the third time t3 can be that the output voltage Vout reaches the target value Vo.

[0057] Figures 6 to 9 In the diagram, the horizontal axis represents time t, and the vertical axis represents the duty cycle D of the driving signal. For example, as shown... Figure 6 As shown, the duty cycle of the drive signal increases at a greater rate in the second stage than in the first stage; that is, the rising slope of the second stage is greater than that of the first stage. This embodiment of the disclosure ensures the safety of the switch during the startup phase by making the duty cycle increase more slowly in the first stage, and by accelerating the increase rate of the duty cycle in the second stage, it speeds up the switch's turn-on speed and reduces losses. Alternatively, as... Figure 9 As shown, in the first and second stages, the duty cycle of the drive signal is maintained at a first predetermined value (e.g., 1.5%, but this disclosure is not limited to this and is only for illustrative purposes).

[0058] For example, the duration of the first stage is greater than the duration of the second stage. That is, the duration of t2 minus t1 is greater than the duration of t3 minus t2. This embodiment of the disclosure ensures the safety of the switch during the startup phase by making the first stage last longer; and by making the second stage shorter, it can shorten the conduction time of the switch and reduce losses.

[0059] For example, in the first stage, the duty cycle of the drive signal increases linearly or non-linearly from a second predetermined value (e.g., 1.5%, but this disclosure is not limited thereto, it is just an example) to a third predetermined value (e.g., 2.523%, but this disclosure is not limited thereto, it is just an example); in the second stage, the duty cycle of the drive signal increases linearly or non-linearly from the third predetermined value to a fourth predetermined value (e.g., 3.773%, but this disclosure is not limited thereto, it is just an example).

[0060] In this embodiment of the disclosure, the first predetermined value and the second predetermined value may be equal or unequal.

[0061] For example, in the first and second phases, the drive signal is in burst mode.

[0062] In this embodiment, the burst mode is the opposite of the continuous mode. The continuous mode refers to continuously providing drive signals to the switch according to the switching cycle. For example, the first switching cycle provides a first drive signal with a duty cycle, the second switching cycle provides a second drive signal with a duty cycle, and the first and second switching cycles are adjacent without interruption, and so on for other switching cycles. The burst mode, on the other hand, means that the drive signal is not continuously emitted in every switching cycle, but is intermittently turned on and off. There is a period between adjacent switching cycles during which no drive signal is provided to the switch, i.e., the switch is completely turned off (dormant). Each switching cycle includes one or more switching cycles, i.e., intermittent restarting of the switch operation. By placing the drive signals of the first and second stages in burst mode, and by intermittently putting the switch in a dormant state, this embodiment can macroscopically control the energy injected into the switch, allowing the output voltage sufficient time to slowly rise, avoiding continuous power surges, thereby reducing the startup current and ensuring safety.

[0063] For example, such as Figures 4 to 9 As shown, the startup phase also includes a third phase from the third time t3 to the fourth time t4.

[0064] For example, such as Figure 6 and Figure 9 As shown, the duty cycle of the drive signal increases at a greater rate in the third stage than in the second stage, and reaches 50% in the third stage. This embodiment of the present disclosure controls the duty cycle of the drive signal to rapidly increase to 50% between t3 and t4, thereby accelerating the switching speed and reducing losses.

[0065] Figure 6In this embodiment, the duty cycle of the drive signal Vdriver_out gradually increases from the constant current region to the variable resistance region. This ensures a sufficiently small duty cycle in the constant current region, reducing the switch's startup current, and accelerates the transition to the variable resistance region, reducing losses. Once the switch is in the variable resistance region, the duty cycle of the drive signal reaches 50% to meet normal operating requirements.

[0066] For example, such as Figure 9 As shown, at the third time t3, the duty cycle of the drive signal increases from a first predetermined value (e.g., 1.5%) to a fifth predetermined value (e.g., 15%). Alternatively, as... Figures 6 to 8 As shown, at the third time t3, the duty cycle of the drive signal increases from a fourth predetermined value (e.g., 3.773%) to a fifth predetermined value (e.g., 15%). The sudden change in the duty cycle of the drive signal at the third time t3 does not affect the stability of the output because the output voltage Vout has already reached the target value Vo. The closed-loop control system has sufficient dynamic suppression capability to effectively absorb the transient disturbances caused by the step change in the duty cycle.

[0067] For example, such as Figures 6 to 9 As shown, in the third stage, the duty cycle of the drive signal increases from the fifth predetermined value (15%) to 50%.

[0068] For example, such as Figures 6 to 9 As shown, the duty cycle of the drive signal is maintained at 50% in the fourth stage. The fourth stage begins at the fourth time t4.

[0069] For example, such as Figures 6 to 9 As shown, in the third and fourth stages, switch S is in the variable resistance region.

[0070] For example, in the third and fourth stages, the drive signal is in a continuous mode.

[0071] For example, such as Figures 6 to 9 As shown, the duration of the third stage is shorter than the durations of the first and second stages. In this embodiment of the disclosure, by shortening the duration of the third stage, the switching speed can be increased and power loss reduced.

[0072] For example, the duration of the third phase is a first predetermined percentage of the duration of the first phase and the second phase. For example, the first predetermined percentage is 5% to 10%.

[0073] In this embodiment of the disclosure, the second predetermined value is less than the third predetermined value, the third predetermined value is less than the fourth predetermined value, the fourth predetermined value is less than the fifth predetermined value, and the fifth predetermined value is less than 50%. The first predetermined value is less than the fifth predetermined value.

[0074] In this embodiment, by increasing the gate drive resistance of the switch and providing a very small duty cycle in the first and second stages, the turn-on speed of the switch can be slowed down, so that the switch is in the constant current region, allowing the output voltage to build up slowly in the first and second stages, reducing the startup current. As the output voltage gradually builds up, in the third stage, by accelerating the growth rate of the duty cycle of the drive signal, the switch is made to operate in the variable resistance region, thereby reducing the switch's Vds and drain current Id, reducing the generated conduction losses and heat. When the output voltage approaches the target value, it smoothly and without impact switches from a small duty cycle and constant current region current-limiting state to a steady-state target duty cycle (e.g., 50% duty cycle) determined by closed-loop feedback and the normal operating state of full conduction.

[0075] In high-frequency, high-power-density scenarios, traditional frequency-modulated soft-start faces challenges. This disclosure addresses these challenges by selecting appropriate drive resistors (affecting switching speed) and peak gate-source voltage, preventing the MOSFET switch from entering a fully low-resistance conduction state during turn-on and instead ensuring it operates in the constant-current region. Furthermore, by controlling the duty cycle, a smaller duty cycle is applied during the startup phase, directly reducing the energy pulse width injected per switching cycle and thus limiting the injected energy. In the constant-current region, the MOSFET functions similarly to a current source controlled by the gate voltage, with the Id current remaining essentially constant as the Vds voltage changes. At this point, although the drain-source voltage Vds is high, the current Id is essentially controlled by the gate voltage. The clamping action achieves active clamping rather than passively limiting the starting current, thus fundamentally preventing current runaway.

[0076] This disclosure provides a drive circuit for a switch, which enables the switch to operate in a constant current region during the startup phase. The drive circuit includes a drive resistor, a drive signal connected in series with the gate of the switch, and the switch has a threshold voltage (also known as the on-state voltage drop) Vgsth. The drive signal has a duty cycle in each switching cycle. By setting the values ​​of the drive resistor and / or the duty cycle, the switch is ensured to operate in the constant current region during the startup phase. When the switch operates in the constant current region, the source-drain voltage Vds > VP (pinch-off voltage), where VP = -Vgsth. VP is determined by the switching characteristics.

[0077] like Figure 2 and Figure 3As shown, this disclosure also provides a power conversion circuit 200, including a first power converter 210. The first power converter 210 includes a first switching unit 211, at least one switch in the first switching unit 211 being driven by a driving circuit as described in any embodiment of this disclosure. Figure 2 and Figure 3 In the embodiments, it is assumed that all switches in the first switching unit 211 are driven by the driving circuit provided in any embodiment of the present disclosure.

[0078] For example, the first power converter 210 includes an LLC resonant converter (which may be represented as DCX_LLC) operating in DC transformer mode.

[0079] In the field of power conversion, converting direct current (DC) of one voltage to DC of another to provide power to a load (i.e., DC-DC conversion) is a power conversion requirement. Among these, the inductor-inductor-capacitor (LLC) resonant converter is a type of DC / DC conversion circuit. LLC refers to a high-frequency soft-switching topology composed of a resonant inductor (Lr), a magnetizing inductor (Lm), and a resonant capacitor (C). Figure 2 and Figure 3 In this embodiment, the resonant inductor can be implemented using the leakage inductance of the transformer T, and the magnetizing inductance is the inductance of the primary winding of the transformer T itself. Therefore, both can be integrated into the transformer T. However, this disclosure is not limited to this, and the resonant inductor can also be independent of the transformer T.

[0080] Soft-switching technology is easily implemented in LLC resonant converters, reducing losses in the power switches (e.g., S1 to S4) of the switching unit in the circuit. Furthermore, LLC resonant converters are easily upscaled to higher frequencies, reducing the size of magnetic components. Therefore, LLC resonant converters offer advantages such as higher conversion efficiency and higher power density.

[0081] When the LLC resonant converter is operating in steady state, the frequency of the power switches in the LLC resonant converter is close to the natural resonant frequency of the resonant slot, and the duty cycle of the drive signals of each power switch is close to 50%. When the LLC resonant converter is operating in the startup phase, it is required that the output voltage Vout of the output capacitor Cout smoothly reach the target value Vo in a short period of time, so as to quickly complete the startup phase and avoid damage to the power switches.

[0082] DCX stands for DC Transformer, referring to a DC-DC converter that operates at a fixed frequency and has a fixed voltage transformation ratio. DCX_LLC is an LLC resonant converter operating in DC transformer mode. Its primary function is to provide electrical isolation and fixed voltage transformation, rather than regulating the output voltage. It utilizes the resonant principle to achieve voltage transformation and isolation at a fixed frequency and high efficiency. Operating near its resonant frequency, it leverages its flat gain region and employs soft-switching technology ZVS / ZCS to achieve high efficiency and high power density. DCX_LLC can be applied to data center power supplies, such as for bus conversion from 48V to 12V or lower voltages, enabling efficient server power supply. It can also be applied to electric vehicle onboard power supplies, such as converting high-voltage battery voltage (e.g., 400V) to low-voltage (e.g., 12V / 24V) to power onboard equipment.

[0083] With the significant increase in power density of power modules, the switching frequency also increases. Since DCX_LLC is a fixed-frequency output with fixed gain, the gain cannot be adjusted by regulating the switching frequency. Therefore, during traditional DCX_LLC soft-start, the switch operates in the variable resistance region. Even with a small duty cycle, the switch exhibits a high voltage change rate (dv / dt) during turn-off and turn-on. This high dv / dt can couple to the gate through the Miller capacitance of the MOSFET, potentially causing false turn-on or interacting with parasitic parameters of the circuit, generating high-frequency oscillations and spike currents. At this time, the current in the resonant cavity may not be effectively suppressed by frequency modulation, resulting in a large instantaneous current, posing a certain risk. This disclosure proposes a method to control the switch by controlling the duty cycle and a suitable drive resistor, allowing it to operate in the constant current region during the soft-start phase, thereby limiting the start-up current. Therefore, this disclosure relates to a soft-start (Vo build-up process) scheme for DCX_LLC.

[0084] In this embodiment, the soft-start of the DCX_LLC refers to the smooth and controllable establishment of the output voltage Vout and current through a specific control strategy when the power is turned on, in order to avoid impacting the circuit. This process is not the DCX_LLC actively adjusting the voltage itself, but rather to cope with an inherent challenge: the huge inrush current (surge current) at startup. The core of the DCX_LLC is a fixed frequency and a fixed voltage ratio, the purpose of which is to transfer energy efficiently and simply. However, this brings a startup problem: at startup, the output capacitor Cout is in a fully discharged state, equivalent to a short circuit. If the switching frequency of the DCX_LLC is immediately set to the optimal resonant point, its inherent high gain characteristics will inject a huge current into the output capacitor instantaneously, which may damage the switch and the capacitor. Therefore, the primary goal of the DCX_LLC soft-start is to suppress the startup inrush current and protect the circuit components.

[0085] For example, the first switching unit includes a full-bridge switching unit or a half-bridge switching unit.

[0086] For example, such as Figure 2 As shown, the first switching unit 211 includes a full-bridge switching unit. The full-bridge switching unit includes: a first switch S1 and a third switch S3 connected in series between the first input terminal and the second input terminal of the first power converter 210; and a second switch S2 and a fourth switch S4 connected in series between the first input terminal and the second input terminal of the first power converter 210. The control terminals of the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4 are electrically connected to a first resistor R. on1 Second resistor R on2 Third resistor R on3 and the fourth resistor R on4 The first terminal; the first resistor R on1 Second resistor R on2 Third resistor R on3 and the fourth resistor R on4 The second terminal is used to receive the first drive signal PWM1, the second drive signal PWM2, the third drive signal PWM3, and the fourth drive signal PWM4, respectively. The first drive signal PWM1 and the fourth drive signal PWM4 are in phase, while the first drive signal PWM1 and the second drive signal PWM2 are out of phase.

[0087] In this embodiment of the disclosure, the first resistor R on1 Second resistor R on2 Third resistor R on3 Fourth resistor R on4 The resistance values ​​are determined based on the characteristics of the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4, respectively. For specific determination methods, please refer to the resistance R of switch S mentioned above. on The determination method will not be elaborated here. A soft-start mode with a gradually increasing duty cycle of the drive signal, combined with at least one drive resistor connected in series with each switch, can achieve a better soft-start.

[0088] In this embodiment, by selecting appropriate drive resistors R for the primary-side switching transistors S1 to S4... on1 R on2 R on3 R on4 By slowly increasing the drive signal, the duty cycles of PWM1, PWM2, PWM3, and PWM4 are gradually increased, thus... The rising edge rises slowly, ensuring that S1 to S4 operate in the constant current region. In the constant current region, the output current Id of the switching transistors S1 to S4 is independent of the input voltage Vin, so it can achieve current clamping during the startup process under high current input conditions.

[0089] For example, the first drive signal PWM1 and the fourth drive signal PWM4 have the same duty cycle, and the second drive signal PWM2 and the third drive signal PWM3 have the same duty cycle.

[0090] Figure 2 In this embodiment, the first input terminal and the second input terminal of the first power converter 210 are respectively connected to the positive terminal and the negative terminal of the input voltage Vin. The first output terminal and the second output terminal of the first power converter 210 are respectively connected to the positive terminal and the negative terminal of the output voltage Vout.

[0091] In this embodiment of the present disclosure, the first power converter 210 further includes a rectifier unit connected to the secondary winding of the transformer T. Figure 2 and Figure 3 In this embodiment, the rectifier unit is a full-bridge circuit including switches S5, S6, S7 and S8, but this disclosure does not limit the specific circuit structure of the rectifier unit.

[0092] It should be noted that, although Figure 2 In this embodiment, four switches S1 to S4 in the first switching unit 211 each have their own driving unit 110, but this disclosure is not limited to this. In other embodiments, the four switches S1 to S4 may have three driving units, two driving units, or even one driving unit, with some switches sharing the same driving unit. Different switches with the same timing sequence may share one driving unit 110. Alternatively, different switches with different timing sequences may share one driving unit 110. For example, switches S1 and S3 may share the same driving unit 110, and switches S2 and S4 may share another driving unit 110. In some applications, by combining software control, one driving unit 110 can generate different timing pulses to serve as driving signals for different switches.

[0093] For example, the first switching unit includes a half-bridge switching unit. The half-bridge switching unit includes a first switch and a third switch connected in series between a first input terminal and a second input terminal of the first power converter. The control terminals of the first switch and the third switch are electrically connected to the first terminals of a first resistor and a third resistor, respectively; the second terminals of the first resistor and the third resistor are respectively used to receive a first drive signal and a third drive signal; the first drive signal and the third drive signal are inverted.

[0094] For example, the first drive signal and the third drive signal have the same duty cycle but opposite phase.

[0095] In this embodiment of the present disclosure, the first power converter 210 includes, in addition to, the following: Figure 2 The full-bridge DC-DC converter shown can also be used as follows: Figure 3As shown, it includes a half-bridge DC-DC converter, that is, the first switching unit 211 includes a half-bridge switching unit, that is, the primary side can also be a half-bridge. Figure 3 Other aspects of the embodiments can be found in the above embodiments, and will not be repeated here.

[0096] The soft-start solution provided in this disclosure can also be applied to, for example, Figure 3 The half-bridge DC-DC converter shown is described above. At least one of the switches S1 and S3 in the half-bridge switching unit uses the aforementioned drive circuit.

[0097] In this embodiment of the disclosure, the primary-side switching transistor (e.g., during the soft-start phase) Figure 2 S1 to S4 in the middle, or Figure 3 The duty cycle of the drive signals S1 and S3 is small (less than 50%), therefore, a suitable drive resistor should be selected. (include Figure 2 In to ,or Figure 3 In and The resistance value allows the duty cycle of the drive signal emitted by the drive unit to increase slowly. The voltage rise slope is achieved through (Control) provides a drive signal to the primary-side switch, causing it to operate in the constant current region during the soft-start phase. For example, the primary-side switch can be brought into the constant current region directly during the first duty cycle of the first switching cycle. The rise time is short and the rise slope is slow, therefore the peak value that can be reached during the conduction time is... The duty cycle is relatively low. In addition, the duty cycle of the control drive signal is gradually increased, which allows the primary-side switch to move from the constant current region to the variable resistance region (after t3) relatively quickly, preventing excessive losses in the constant current region.

[0098] In this embodiment of the disclosure, the primary-side switch and the secondary-side switch (e.g.) Figure 2 and Figure 3 The initial duty cycle and expansion speed (i.e., the growth rate of the duty cycle) of S5 to S8 are relatively small until the output voltage Vout reaches the target value Vo, i.e., steady state t3.

[0099] In this embodiment, the secondary-side switch does not require a drive resistor. The secondary-side switch turns on when the primary-side switch reaches 90% Vo or reaches Vo. The secondary-side switch is turned on after the primary-side switch has been soft-started, and the duty cycle of the secondary-side switch is slightly smaller than that of the primary-side switch to begin rectification.

[0100] For example, the power conversion circuit 200 further includes a controller (not shown in the figure), configured to turn off the drive unit 110 when the output voltage Vout of the first power converter 210 is greater than an output reference voltage, and to turn on the drive unit 110 when the output voltage Vo of the first power converter 210 is less than or equal to the output reference voltage. This embodiment of the present disclosure uses the controller to determine whether the output voltage Vout is greater than the output reference voltage, thereby intermittently turning off the corresponding primary-side switch to achieve a burst mode.

[0101] For example, the startup phase includes a first phase from a first time t1 to a second time t2. In this first phase, the output voltage Vout of the first power converter 210 rises from 0V to a second predetermined percentage of the target value Vo. This second predetermined percentage of the target value Vo is the same as the first target value, and the magnitude of the first target value is the product of the target value Vo and the second predetermined percentage. For example, as... Figure 4 As shown, the second predetermined percentage is 90%. The first target value is equal to 90% Vo.

[0102] Figure 4 The horizontal axis represents time t, and the vertical axis represents the output voltage Vout, with the desired target value for the output voltage being Vo. For example, Figure 4 For the soft-start scheme applied to DCX_LLC, the soft-start is divided into 4 stages: t1-t2 is the Ramp up stage, t2-t3 is the Transient stage, t3-t4 is the steady state 1 stage, and after t4 is the steady state 2 stage.

[0103] The ramp-up phase, also known as the soft-start phase, is the main stage of soft start. Its goal is to allow the output voltage to rise smoothly, linearly / non-linearly, or in a controlled manner from 0V to near the target value. The duty cycle gradually increases from its minimum value Dmin or remains constant to control the rise rate of the output voltage, effectively suppressing inrush current and voltage overshoot, ensuring a safe and smooth startup process. During the ramp-up phase, the primary-side switches initially have a very small duty cycle; S1 and S4 have the same duty cycle, as do S2 and S3. The duty cycle then slowly increases until time t2. The secondary-side switches S5-S8 are not driven. During the ramp-up phase, the primary-side switches operate in burst mode.

[0104] The Transient phase is a transient transition period or transient switching period. Its goal is to smoothly and stably switch from the startup control mode to the steady-state normal operating mode. It begins when the output voltage reaches a preset threshold (e.g., 90% of the target value Vo) at time t2. During the Transient phase, the primary-side switches operate in burst mode. During this phase, the duty cycle of the primary-side switches continues to slowly increase from the final stage of the Ramp-up phase. S1 and S4 have the same duty cycle, as do S2 and S3. The secondary-side switches S5-S8 initially have very small duty cycles. S5 and S8 turn on after S2 and S3 with a delay, while S6 and S7 turn on after S1 and S4 with a delay. Afterward, the duty cycles slowly increase until time t3, at which point the duty cycles of both primary-side switches S1-S4 and secondary-side switches S5-S8 are relatively small.

[0105] The steady-state phase 1 is relatively short, lasting approximately 5%–10% of the ramp-up and / or transient phases. During this phase, the system switches from burst mode to continuous mode. The primary-side switches S1–S4 and the secondary-side switches S5–S8 rapidly increase their duty cycles from the end of the transient phase to nearly 50% (full duty cycle minus dead time), causing Vo to reach the target value and completing the main startup process.

[0106] In steady-state stage 2, the duty cycle is maintained at 50%, the system enters steady-state operation, the output voltage and current are kept in dynamic balance, the efficiency and thermal performance are optimal, and the soft-start process ends.

[0107] For example, the period of the drive signal is a first period. In this embodiment of the disclosure, the switching frequency of the primary-side switch is fixed.

[0108] For example, such as Figure 6 As shown, at the first time t1, the duty cycle of the drive signal is a second predetermined value (e.g., 1.5%).

[0109] For example, in the first stage, the duty cycle of the drive signal increases from a second predetermined value (e.g., 1.5%) to a third predetermined value (e.g., 2.523%) according to a first duty cycle function.

[0110] like Figure 6 As shown, the first duty cycle function is a linear function, and the duty cycle changes linearly. Its duty cycle can be expressed as duty(t) = 1.5% + A × t, where A is the slope of the duty cycle increase, for example, A = 0.00025 / 4400, t = 180ms / TS, and TS is the switching period, for example, TS = 1000ns. The specific values ​​here are only for illustrative purposes and this disclosure is not limited to them.

[0111] like Figure 9As shown, when the duty cycle remains constant in the first stage, A=0.

[0112] For example, in the first stage, for every first preset number (e.g., 4400 switching cycles) of the first cycle, the duty cycle of the drive signal increases by a first preset value (e.g., 250 ps) until it increases from the second predetermined value to the third predetermined value; or, the duty cycle of the drive signal remains at the first predetermined value.

[0113] For example, there can be multiple different slopes in the same phase. For example, such as Figure 7 As shown, the first duty cycle function in the first stage can be multiple piecewise functions, including two or more linearly varying functions. Figure 7 Taking the first duty cycle function of the first stage as an example, which contains two piecewise linear functions, where t1 to t 12 Let t be a linear function. 12 The function from t1 to t2 is another linear function, but this disclosure is not limited thereto. Exemplarily, from t1 to t2... 12 The duration between them is greater than t 12 The duration between t1 and t2. For example, the time from t1 to t2. 12 The rising slope of the linear function is less than t 12 The rising slope of the linear function up to t2.

[0114] For example, the controller is further configured to: set the initial value of the output reference voltage to 0, and gradually increase the output reference voltage by a step size until it increases to a voltage threshold related to the input voltage Vin of the first power converter 210.

[0115] For example, the length of the first cycle is increased by a step every second preset number (e.g., 200 switching cycles) until it reaches a voltage threshold related to the input voltage Vin of the first power converter 210. The second preset number is less than the first preset number.

[0116] For example, the initial value of the output reference voltage Vref is set to 0, and the step length of Vref is increased every 200us until it reaches 0.004×Vin+16.1mV.

[0117] For example, the startup phase further includes a second phase from a second time t2 to a third time t3. In the second phase, the output voltage Vout of the first power converter 210 rises from a second predetermined percentage (a first target value) of the target value to the target value Vo.

[0118] For example, the period of the drive signal is a first period; at the second moment, the duty cycle of the drive signal is a third predetermined value; in the second stage, the duty cycle of the drive signal increases from the third predetermined value to a fourth predetermined value according to a second duty cycle function.

[0119] like Figure 6 As shown, the second duty cycle function is a linear function, and the duty cycle changes linearly.

[0120] For example, the second stage may also include multiple piecewise functions, including two or more functions with linear variations. For instance, such as... Figure 8 As shown, taking the second duty cycle function of the second stage, which contains two piecewise linear functions, as an example, where t2 to t 23 Let t be a linear function. 23 The function from t2 to t3 is another linear function, but this disclosure is not limited thereto. Exemplarily, the function from t2 to t3 is... 23 The duration between them is greater than t 23 The duration between t2 and t3. For example, the time between t2 and t3. 23 The rising slope of the linear function is less than t 23 The rising slope of the linear function up to t3.

[0121] For example, the controller is further configured to: gradually increase the output reference voltage by a step size until it reaches the target value; and when the output voltage of the first power converter is detected to be equal to the target value, increase the duty cycle of the drive signal from a fourth predetermined value or a first predetermined value to a fifth predetermined value.

[0122] For example, in the second stage, every third preset number (400 switching cycles) of the first cycle, the duty cycle of the drive signal increases by a first preset value until it increases from the third preset value to a fourth preset value; or, the duty cycle of the drive signal remains at the first preset value; wherein the third preset number is less than the first preset number.

[0123] For example, the controller is further configured to: starting from the voltage threshold, increase the first cycle length by a step step for every second preset number of the first cycles until it reaches the target value; when the output voltage of the first power converter is detected to be equal to the target value, increase the duty cycle of the drive signal from a fourth predetermined value or a first predetermined value to a fifth predetermined value; wherein the second preset number is less than the third preset number.

[0124] For example, the startup phase further includes a third phase from the third time point to the fourth time point. In the third phase, the fifth predetermined value is increased to 50% according to a third duty cycle function.

[0125] like Figure 6 As shown, the third duty cycle function is a linear function, and the duty cycle changes linearly.

[0126] For example, the third stage may also include multiple piecewise functions, including two or more functions with linear variations.

[0127] For example, in the third stage, starting from the fifth predetermined value, for every fourth predetermined number (e.g., 200 switching cycles) of the first cycle, the duty cycle of the drive signal increases by a second predetermined value until it increases from the fifth predetermined value to 50%; wherein the fourth predetermined number is less than the third predetermined number, and the second predetermined value is greater than the first predetermined value.

[0128] For example, the duty cycle of the drive signal is maintained at 50% in the fourth stage; the fourth stage begins at the fourth time t4.

[0129] For example, the power conversion circuit 200 further includes a negative feedback circuit (not shown in the figure), used to detect the drain current of the switch during the startup phase, and control the reduction of the duty cycle of the drive signal when the drain current of the switch is detected to be greater than a current threshold. This embodiment of the disclosure uses a negative feedback circuit to ensure that the switch is in the constant current region during the startup phase as much as possible, and does not accidentally enter the variable resistance region.

[0130] To prevent the switch from accidentally entering the variable resistance region between t1 and t3, a negative feedback circuit can be added. For example, the drain current Id of the switch can be monitored in real time. If the drain current exceeds a preset current threshold, the duty cycle can be reduced slightly. This current threshold can be determined based on the boundary between the variable resistance region and the constant current region.

[0131] For example, such as Figure 10 As shown, the power conversion circuit 200 also includes a second power converter 220. The second power converter 220 includes a second switching unit 221. Figure 10 Taking a full-bridge DC-DC converter as an example, where both the second switching unit 221 and the first switching unit 211 are full-bridge DC-DC converters. Figure 10 As shown, the second switching unit 221 includes primary-side switching transistors S9 and S1. 10 S 11 and S 12 The second power converter 220 also includes a rectifier unit. Figure 10 Taking a full-bridge rectifier unit as an example, it includes the secondary-side switching transistor S. 13 S 14 S 15 and S 16 .

[0132] For example, the primary-side switch is a MOSFET device. For example, the primary-side switch is a gallium nitride (GaN) transistor.

[0133] At least one switch in the second switching unit 221 is driven by a driving circuit as described in any embodiment of this disclosure.

[0134] like Figure 10 As shown, the first input terminal of the first switching unit 211 is electrically connected to the positive terminal of the input voltage Vin, and the second input terminal is electrically connected to the first input terminal of the second switching unit 221; the second input terminal of the second switching unit 221 is electrically connected to the negative terminal of the input voltage Vin. The output terminals of the first power converter 210 and the second power converter 220 are connected in parallel.

[0135] For example, the power conversion circuit 200 consists of two LLC primary windings connected in series and secondary windings connected in parallel. Figure 10 Taking a full-bridge DC-DC converter with a series primary winding and parallel secondary winding topology as an example. Because the primary windings are series-connected, the current must be identical. Ideally, the parameters of each MOSFET in the first and second switching units would be the same. For example, if the four MOSFETs (S1, S4, S9, S...)... 12 Completely identical, and If they are completely identical, then they will generate exactly the same drain current Id in the constant current region. Thus, in a series circuit, the currents are naturally equal, the two transistors share the voltage equally, and the system is stable.

[0136] However, in reality, no two MOSFETs have exactly the same parameters. Different MOSFETs have manufacturing tolerances, which leads to variations in the characteristics of the same... Under voltage conditions, the desired current (Id_want) differs for each switch. For example, if the transconductance of S1 / S4 is slightly higher than that of S9 / S... 12 Under the same driving conditions, the conduction current of S1 / S4 is larger. However, since switches S1 and S4 are connected in series, according to Kirchhoff's current law, the actual current flowing through S1, S4 and S9 is smaller. 12 The current must be strictly equal to I_actual. To meet this constraint, the system will automatically adjust through voltage redistribution. Switches with higher transconductance are more likely to turn on, forcing their drain-source voltage Vds to increase to limit the current; while switches with lower transconductance reduce their drain-source voltage Vds to handle a larger voltage drop. This unbalanced voltage distribution will directly lead to a decrease in the half-bus voltage (V... BUS An offset has occurred.

[0137] The reason for the above-mentioned uneven voltage phenomenon is that the drain current Id in the constant current region is not only related to the voltage distribution. It is related to Vds. In the constant current region, the MOSFET current Id is not completely unaffected by Vds; its characteristic curve rises slightly as Vds increases (early effect). The higher Vds, the better the current Id of the MOSFET at the same current-carrying capacity. Below this, Id will increase slightly. The formula for the constant current region is: (4) in For transconductance parameters, Indicates the carrier mobility of the switch. This represents the gate oxide capacitance per unit area of ​​the switch. Indicates the width of the channel of the switch. Indicates the length of the switch channel; The modulation coefficient is the channel length of the switch.

[0138] Therefore, in order to reduce the currents of S1 and S4 from their "desired" higher values ​​to the actual I_actual, the circuit will actively reduce Vds1 of S1 and S4, and in order to increase the currents of S9 and S... 12 The current is increased from the "desired" lower value to the same I_actual, and the circuit will increase S9, S 12 The Vds2 value creates an uneven voltage distribution, thus causing V to... BUS It is not equal to half of Vin.

[0139] For example, the power conversion circuit 200 further includes a controller, which is used to acquire the half-bus voltage V at the second input terminal of the first switching unit 211 and the first input terminal of the second switching unit 221. BUS If the half-bus voltage V BUS If the voltage is greater than half of the input voltage Vin, then the duty cycle of the drive signal for the switch in the second switching unit 221 is compensated; if the half bus voltage V BUS If the voltage is less than half of the input voltage Vin, the duty cycle of the drive signal for the switch in the first switching unit 211 is compensated.

[0140] like Figure 11 As shown, taking an MCU controller as an example, to solve V BUS The problem of uneven voltage distribution first needs to be addressed by considering the input voltages Vin and V. BUS Isolation sampling is performed, and the sampled signal is transmitted to the MCU. The MCU processes the sampled signal and calculates V. BUS The deviation from Vin / 2 is ΔV = V BUS –Vin / 2, used as a feedback error signal to determine the degree of bias; if V BUSIf the current is greater than 1 / 2Vin, it indicates that the current flowing through the switch of the second power converter 220 is relatively small, resulting in weak conduction capability and insufficient voltage drop. Therefore, its conduction time needs to be extended. This requires compensation of the PWM of the switch of the second power converter 220, for example, by increasing the compensation by 250ps for each interrupt time (here, interrupt time refers to the interrupt time of the driver chip / driver unit), until V... BUS The voltage recovers to 1 / 2Vin; if V BUS If the current is less than 1 / 2Vin, it means that the current that can flow through the switch of the first power converter 210 is relatively small, the conduction capability is weak, and the voltage drop is insufficient. Therefore, its conduction time needs to be extended. This requires compensation of the PWM of the switch of the first power converter 210, with the compensation level increasing by 250ps for each interrupt time, until V... BUS The voltage recovers to 1 / 2Vin. The compensated PWM makes the half-bus voltage V... BUS No longer biased.

[0141] The following specific examples illustrate the embodiments provided in this disclosure. Figure 10 The full-bridge circuit shown is a series primary and parallel secondary circuit, illustrated using a little duty softstart scheme.

[0142] Assuming the frequency fs (here referring to the switching frequency / first frequency; in this embodiment, the switching frequency is always fixed and remains unchanged) is 1MHz (corresponding to a switching period TS = 1000ns), the scheme provided in this embodiment is applied to a fixed-frequency topology. Ignoring dead time, a 50% duty cycle is 500ns, and the soft-start time (t1-t3) is 200ms (2 × 1000ns). ns).

[0143] The ramp-up phase t1-t2 lasts for 180ms. The drive signals for switches S1, S4, and S9 are PWM1, PWM4, PWM9, and PWM9 respectively. 12 PWM drive signal 12 All outputs are at a fixed frequency, fs = 1MHz, with an initial duty cycle assumed to be 15ns (i.e., 1.5% duty cycle). The PWM output is in burst mode; PWM is off when Vout > Vref, and PWM output is on when Vout ≤ Vref, for example, every 4400... The duty cycle is increased by 250 ps (0.25 ns, i.e., the duty cycle D increases by 0.025% each time). This 250 ps (0.025%) increase in duty cycle is the adjustment amount for each update. At each 4.4 ms update interval, the controller increases the high-level on-time (i.e., "pulse width") of the PWM pulse by 250 ps, ​​ensuring accurate energy injection.

[0144] During the ramp-up phase t1-t2, the duty cycle increases by 1.023%, therefore, as Figure 6 As shown, the duty cycle increased from 1.5% to 2.523%. That is... Figure 6 In this embodiment, if the duty cycle increases linearly in the first stage, then in the ramp-up t1-t2 180ms stage, the duty cycle will increase to 2.523%. In other embodiments, the duty cycle in this stage can also remain constant (e.g., ...). Figure 9 (Example) or it may be non-linearly increased. The drive signal PWM2 for switch S2, the drive signal PWM3 for switch S3, and the switch S... 10 PWM drive signal 10 Switch S 11 PWM drive signal 11 With PWM1, PWM4, PWM9, PWM 12 Phase shift 180°, rise rate same as PWM1, PWM4, PWM9, PWM 12 .

[0145] During the ramp-up t1-t2 phase, the initial value of Vref is set to 0, and every 200... The voltage Vref increases in a stepwise manner over a fixed period, with the first step increasing in length each fixed period until it reaches 0.004 × Vin + 16.1 mV. This strategy achieves a smooth and controllable start-up of the output voltage Vout by precisely controlling the rise trajectory of Vref.

[0146] The Vref update cycle is 200µs, significantly longer than the 1µs switching cycle; it is 200 times longer. Approximately 200 switching cycles are provided for closed-loop tracking for each Vref step, ensuring the control loop has sufficient time to complete the current / voltage response and avoiding overshoot or oscillation caused by sudden command changes. If the update cycle is too fast (e.g., 10µs), the loop response will lag, the system will lose stability, and may even lead to startup failure.

[0147] The ramp-up phase (t1-t2) is relatively long (e.g., 180ms). Vref increases in steps with a period of 200μs, and is updated approximately 900 times throughout the entire startup process, forming a high-density, low-step voltage reference trajectory. This design makes the rise of the output voltage Vout present a nearly continuous and smooth ramp, completely avoiding the voltage jumps, current surges, and electromagnetic interference caused by traditional stepped startup.

[0148] Furthermore, 200µs corresponds to a 5kHz update frequency. This frequency is significantly lower than the system's switching frequency (1MHz) but higher than the expected bandwidth of the output voltage loop. This ensures that changes in Vref can be smoothly tracked by the system as a "track command" without triggering high-frequency resonance or oscillations. 200µs is a user-friendly time interval for digital controllers (such as DSPs). It can be easily triggered by a timer interrupt, giving the controller ample time to perform other tasks (such as protection detection).

[0149] This disclosure provides a precise, digitally controlled DCX_LLC soft-start scheme that achieves soft-start by adjusting the duty cycle. At a fixed 1MHz high frequency, digital control allows the output voltage to rise smoothly and controllably from 0V to the target value Vo, while strictly limiting energy injection in each switching cycle to avoid startup current surges. Macroscopic energy control is achieved through a burst mode, using the output voltage Vout as feedback and comparing it to a slowly rising Vref. When Vout ≤ Vref, PWM is activated, outputting a burst of pulses to charge the output capacitor; when Vout > Vref, PWM is immediately deactivated, charging stops, and Vout is allowed to decrease due to load consumption. This ensures the output voltage is tightly clamped to the trajectory of Vref, macroscopically preventing overshoot. Microscopic pulse control is achieved by controlling the slope of the duty cycle D. During each burst period, the width of the PWM pulse itself (duty cycle) starts from a very small value and increases extremely slowly. The initial duty cycle of 1.5% is an extremely narrow and safe pulse with minimal energy injection. The duty cycle increases by 250 ps (0.025%) every 4400 switching cycles (4.4 ms). This is the duty cycle update cycle; the controller does not change the duty cycle in every switching cycle, but adjusts it only once every 4400 switching cycles, demonstrating the high precision and slow speed of digital control. A 250 ps adjustment step is achievable for digital controllers (such as DSPs), enabling smooth, shock-free startup. During the ramp-up phase (t1-t2) (assuming a duration of 180 ms), the total duty cycle increase is (180 ms / 4.4 ms) × 0.025% ≈ 1.023%. Therefore, it increases from an initial 1.5% to approximately 2.523%. Because the width of each pulse increases extremely slowly, the single-cycle energy injected into the resonant cavity and output capacitor is strictly limited. Even during burst-on, the energy of each pulse is strictly limited and increases very slowly, fundamentally preventing the primary-side switch from entering the variable resistance region. This disclosed embodiment achieves open-loop, predictable control of startup current and output voltage through burst switching, duty cycle slope, and Vref trajectory. It avoids complex current sampling and fast protection loops, instead ensuring safety through precisely calculated time sequences. Using a digital controller, a high-risk process is broken down into a series of extremely small, safe steps for execution, resulting in high reliability.

[0150] like Figure 6 As shown, the transient t2-t3 phase is assumed to last for 20ms. PWM1, PWM4, PWM9, PWM 12The output voltage reaches 90% Vo and enters the Transient t2-t3 stage. The frequency is 1MHz, and the duty cycle increases by 250ps every 400us (0.4ms), meaning the duty cycle increases by 1.25% within the 20ms Transient t2-t3 period. PWM2, PWM3, PWM 10 PWM 11 With PWM1, PWM4, PWM9, PWM 12 Phase shift 180°, rise rate same as PWM1, PWM4, PWM9, PWM 12 Vref continues to increase during the ramp-up phase, increasing by one step every 200µs until Vout = Vref, i.e., at time t3, the duty cycle jumps from approximately 3.773% to 15%. This jump does not refer to a linear increase in the duty cycle instantaneously, but rather to an instantaneous switch in the control mode of the entire system at time t3 when the condition Vout = Vref is met. Before t3, the duty cycle is strictly controlled by open-loop, slow soft-start timing logic. At time t3, the system determines that the output voltage has accurately established and tracked the target trajectory Vref. At this point, the soft-start logic is disabled, and control is transferred to a closed-loop controller designed for steady-state operation. The goal of this steady-state controller (voltage-mode or current-mode PWM) is to maintain a stable, higher output voltage (e.g., the Vo ultimately required by the system). To achieve this new goal, it calculates a new, higher duty cycle command of 15% and outputs it immediately. This 15% is the result of the steady-state operating point calculation, not a gradual increase from 3.773%.

[0151] During the ramp-up phase, the output capacitor is fully discharged, which is equivalent to a short circuit and poses the highest risk. Therefore, a very small duty cycle of 1.5% and a very slow increase (0.025% every 4.4ms) are used to avoid triggering the danger. In the transient phase, the output voltage has been initially established, and the output capacitor is no longer a short circuit, but the target value has not yet been reached. The duty cycle growth rate is appropriately accelerated (increased to 0.025% every 0.4ms), with the goal of approaching the target value faster while ensuring safety. At time t3, the output voltage has reached the final target value, and the system is ready for steady state. The duty cycle is directly switched to the optimal operating point (15%), pursuing the highest efficiency (soft switching) and best performance in steady state.

[0152] The steady-state t3-t4 phase is assumed to be 7ms. PWM1, PWM4, PWM9, PWM 12Fixed-frequency output, fs=1MHz, initial duty cycle 150ns (i.e., initial duty cycle 15%), increasing by 10ns every 0.2ms, i.e., increasing the duty cycle by 1% each time, for a total of 7ms / 0.2ms=35 times, therefore, increasing by 35%, from 15% to 50%. PWM2, PWM3, PWM 10 PWM 11 With PWM1, PWM4, PWM9, PWM 12 Phase shift 180°, deployment speed same as PWM1, PWM4, PWM9, PWM 12 .

[0153] Steady-state stage 2, PWM1, PWM4, PWM9, PWM 12 Fixed frequency output, fs=1MHz, duty cycle 50%. PWM2, PWM3, PWM 10 PWM 11 With PWM1, PWM4, PWM9, PWM 12 Phase shift 180°, rise rate same as PWM1, PWM4, PWM9, PWM 12 .

[0154] For example, the primary-side switching transistor used in the embodiments of this disclosure =518pF, =0.3Ω, Vgsth=1.7V, the amplitude of the driving voltage of the driver chip =5V. To ensure this primary-side switching transistor operates in the constant current region, it is... The voltage is controlled between 2V and 2.5V. According to the formula above, we can obtain... The resistance value ranges from 41Ω to 56Ω. For example, Take 40Ω.

[0155] like Figure 9 As shown, still based on Figure 10 The example shown is a full-bridge circuit with the primary side in series and the secondary side in parallel. Assume the frequency fs is 1MHz (switching period TS = 1000ns), applied to a fixed-frequency topology. Ignoring dead time, the 50% duty cycle is 500ns, and the soft-start time (t1-t3) is 200ms (2 × 1000ns). ns).

[0156] Assume the ramp-up time t1-t2 is 180ms. PWM1, PWM4, PWM9, PWM 12Fixed-frequency output, fs=1MHz, initial duty cycle of 15ns (i.e., 1.5% duty cycle), PWM output in burst mode. PWM is off when Vout>Vref; PWM output is on when Vout≤Vref. Duty remains constant during this phase. PWM2, PWM3, PWM... 10 PWM 11 With PWM1, PWM4, PWM9, PWM 12 Phase shift 180°, deployment speed same as PWM1, PWM4, PWM9, PWM 12 Set the initial value of Vref to 0, and increment it every 200. Vref increases the first step length until it reaches 0.004×Vin+16.1mV.

[0157] The transient t2-t3 phase is assumed to last 20ms. PWM1, PWM4, PWM9, PWM 12 The output voltage reaches 90% Vo and enters the Transient t2-t3 stage. The frequency is 1MHz, and the duty cycle remains unchanged. PWM2, PWM3, PWM 10 PWM 11 With PWM1, PWM4, PWM9, PWM 12 The phase shifts by 180°. Vref then continues to increase by ramping up until Vout = Vref, that is, at time t3, duty will increase to 15%.

[0158] The steady-state t3-t4 phase is assumed to be 7ms. PWM1, PWM4, PWM9, PWM 12 Fixed-frequency output, fs=1MHz, initial duty cycle 150ns (i.e., initial duty cycle 15%), increasing by 10ns every 0.2ms to 50%. PWM2, PWM3, PWM 10 PWM 11 With PWM1, PWM4, PWM9, PWM 12 Phase shift 180°, deployment speed same as PWM1, PWM4, PWM9, PWM 12 .

[0159] Steady-state stage 2, PWM1, PWM4, PWM9, PWM 12 Fixed frequency output, fs=1MHz, duty cycle 50%. PWM2, PWM3, PWM 10 PWM 11 With PWM1, PWM4, PWM9, PWM 12 Phase shift 180°, deployment speed same as PWM1, PWM4, PWM9, PWM 12 .

[0160] Figure 12 A flowchart illustrating a driving method in an exemplary embodiment of this disclosure is shown. Figure 12 As shown, the driving method provided in this embodiment includes the following steps.

[0161] In S110, drive signals are provided.

[0162] In S120, the drive signal is transmitted to the control terminal of the switch via a resistor.

[0163] In S130, the switch is kept in the constant current region during the startup phase by the combination of the resistance value of the resistor and the duty cycle of the drive signal.

[0164] The method provided in this disclosure further includes: determining the driving time of the driving signal as a set value, the set value corresponding to the on-time corresponding to the minimum duty cycle of the driving signal during the startup phase; determining the peak value of the gate-source voltage of the switch during the startup phase; determining the amplitude of the driving signal; and determining the resistance value of the resistor based on the set value of the driving time of the driving signal and the amplitude of the driving signal, as well as the peak value of the gate-source voltage of the switch during the startup phase, the gate parasitic resistance of the switch, and the input capacitance. The determination of the resistance value can be achieved through analog circuits, software, or a combination of hardware and software.

[0165] Figure 12 Other aspects of the embodiments can be found in the embodiments described above.

[0166] Furthermore, embodiments of this disclosure also provide a power supply device, including the power conversion circuit described in any embodiment of this disclosure.

[0167] For example, the power supply device includes multiple power conversion circuits connected in parallel.

[0168] Furthermore, embodiments of this disclosure also provide a power supply system, the power supply system including the power conversion circuit described in any embodiment of this disclosure; and one or more voltage regulation modules. The input terminal of the power conversion circuit is connected to the output terminal of the voltage regulation module, or the output terminal of the power conversion circuit is connected to the input terminal of the voltage regulation module.

[0169] A standalone DCX-LLC cannot regulate voltage. In practical systems, it can be combined with upstream or downstream voltage regulation modules (such as Buck or Boost converters) to form a two-stage architecture, enabling wide-range voltage regulation.

[0170] Furthermore, embodiments of this disclosure also provide a computer device, including: a power distribution system for providing an input voltage; one or more power systems as described in any embodiment of this disclosure, connected to the power distribution system to receive the input voltage; and one or more processors connected to a corresponding power system to receive the output voltage.

[0171] The computer equipment in this disclosure includes any electronic device such as a computer, tablet, mobile phone, wearable smart device, server, VR, AR, etc.

[0172] From the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions according to the embodiments of this disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, terminal device, or network device, etc.) to execute the solutions according to the embodiments of this disclosure.

[0173] In exemplary embodiments of this disclosure, a computer-readable storage medium is also provided, which may be a readable signal medium or a readable storage medium. A program product capable of implementing the methods described above is stored thereon. In some possible implementations, various aspects of this disclosure may also be implemented as a program product including program code, which, when run on a terminal device, causes the terminal device to perform the steps of the various exemplary embodiments of this disclosure described in the "Detailed Description" section above.

[0174] In this disclosure, a computer-readable storage medium may include a data signal propagated in baseband or as part of a carrier wave, carrying readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A readable signal medium may also be any readable medium other than a readable storage medium, capable of transmitting, propagating, or transmitting a program for use by or in connection with an instruction execution system, apparatus, or device.

[0175] In exemplary embodiments of this disclosure, a computer program product is also provided, comprising a computer program or computer instructions, which are loaded and executed by a processor to enable a computer to perform the steps of the various exemplary embodiments of this disclosure described in the foregoing “Detailed Description” section of this specification.

[0176] Furthermore, although the steps of the method in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or a step may be broken down into multiple steps.

[0177] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein.

Claims

1. A driving circuit, characterized in that, include: The drive unit is used to provide drive signals; A resistor, the first end of which is electrically connected to the control terminal of a switch, and the second end of which is used to receive the drive signal; Specifically, by coordinating the resistance value of the resistor and the duty cycle of the drive signal, the switch is kept in a constant current region during the startup phase.

2. The driving circuit according to claim 1, characterized in that, The resistance value is determined based on the set value and amplitude of the drive signal's drive time, as well as the peak value of the gate-source voltage, gate parasitic resistance, and input capacitance of the switch during the startup phase; the set value corresponds to the on-time corresponding to the minimum duty cycle of the drive signal during the startup phase.

3. The driving circuit according to claim 1, characterized in that, During the startup phase, the source-drain voltage of the switch is made greater than the pinch-off voltage by the combination of the resistance value of the resistor and the duty cycle of the drive signal, so that the switch is in the constant current region during the startup phase. The pinch-off voltage is equal to the difference between the gate-source voltage of the switch and the threshold voltage of the switch.

4. The driving circuit according to claim 1, characterized in that, During the startup phase, the ratio of the peak value of the gate-source voltage of the switch to the threshold voltage of the switch is kept within a preset range by coordinating the resistance value of the resistor and the duty cycle of the drive signal, so that the switch is in the constant current region.

5. The driving circuit according to claim 4, characterized in that, The preset range is between 1 and 1.

8.

6. The driving circuit according to claim 4, characterized in that, When the threshold voltage of the switch is 1.7V, during the startup phase, the peak value of the gate-source voltage of the switch is controlled to be between 2V and 2.5V.

7. The driving circuit according to claim 1, characterized in that, The driving signal has a first frequency and a first period.

8. The driving circuit according to claim 1, characterized in that, While keeping the resistance value constant, the duty cycle of the drive signal during the startup phase is controlled to keep the switch in the constant current region.

9. The driving circuit according to claim 8, characterized in that, Based on the peak value of the gate-source voltage of the switch during the startup phase, the amplitude of the drive signal, and the resistance value of the resistor, determine the maximum duty cycle value of the drive signal during the startup phase. During the startup phase, the duty cycle of the drive signal is less than or equal to the maximum duty cycle value of the drive signal during the startup phase.

10. The driving circuit according to claim 1, characterized in that, The startup phase includes a first phase from a first time point to a second time point, and a second phase from the second time point to a third time point; The duty cycle of the drive signal increases at a greater rate in the second stage than it increases at the first stage; or, in both the first and second stages, it remains at a first predetermined value.

11. The driving circuit according to claim 10, characterized in that, The duration of the first phase is longer than the duration of the second phase.

12. The driving circuit according to claim 10, characterized in that, In the first stage, the duty cycle of the driving signal increases linearly or non-linearly from a second predetermined value to a third predetermined value; In the second stage, the duty cycle of the drive signal increases linearly or non-linearly from the third predetermined value to the fourth predetermined value.

13. The driving circuit according to claim 10, characterized in that, The startup phase also includes a third phase from the third time point to the fourth time point; the duty cycle of the drive signal increases at a greater rate in the third phase than it increases at the second phase, and increases to 50% in the third phase.

14. The driving circuit according to claim 13, characterized in that, At the third time point, the duty cycle of the drive signal is increased from a first predetermined value or a fourth predetermined value to a fifth predetermined value; In the third stage, the duty cycle of the drive signal increases from the fifth predetermined value to 50%.

15. The driving circuit according to claim 13, characterized in that, The duty cycle of the drive signal is maintained at 50% in the fourth stage; The fourth phase begins at the fourth moment.

16. The driving circuit according to claim 15, characterized in that, In the third and fourth stages, the switch is in the variable resistance region.

17. The driving circuit according to claim 13, characterized in that, The duration of the third phase is shorter than the duration of the first and second phases.

18. The driving circuit according to claim 13, characterized in that, The duration of the third phase is a first predetermined percentage of the duration of the first and second phases.

19. The driving circuit according to claim 1, characterized in that, The switch includes a MOSFET.

20. A power conversion circuit, characterized in that, include: A first power converter, comprising: A first switching unit, wherein at least one switch in the first switching unit is driven by a driving circuit as described in any one of claims 1 to 19.

21. The power conversion circuit according to claim 20, characterized in that, Also includes: The controller is configured to shut down the drive unit when the output voltage of the first power converter is greater than an output reference voltage; When the output voltage of the first power converter is less than or equal to the output reference voltage, the drive unit is turned on.

22. The power conversion circuit according to claim 21, characterized in that, The startup phase includes a first phase from a first moment to a second moment; In the first stage, the output voltage of the first power converter rises from 0V to a first target value, the first target value being the product of a target value and a second predetermined percentage.

23. The power conversion circuit according to claim 22, characterized in that, The period of the driving signal is the first period; At the first moment, the duty cycle of the drive signal is a second predetermined value; In the first stage, the duty cycle of the drive signal increases from the second predetermined value to the third predetermined value according to the first duty cycle function.

24. The power conversion circuit according to claim 21, characterized in that, The controller is further configured to: set the initial value of the output reference voltage to 0, and gradually increase the output reference voltage by a step size until it increases to a voltage threshold related to the input voltage of the first power converter.

25. The power conversion circuit according to claim 22, characterized in that, The startup phase also includes a second phase from the second time point to the third time point; In the second stage, the output voltage of the first power converter rises from the first target value to the target value.

26. The power conversion circuit according to claim 25, characterized in that, The period of the driving signal is the first period; At the second moment, the duty cycle of the drive signal is a third predetermined value; In the second stage, the duty cycle of the drive signal increases from the third predetermined value to the fourth predetermined value according to the second duty cycle function.

27. The power conversion circuit according to claim 26, characterized in that, The controller is further configured to: gradually increase the output reference voltage by a step length until it reaches the target value; and when the output voltage of the first power converter is detected to be equal to the target value, increase the duty cycle of the drive signal from a fourth predetermined value or a first predetermined value to a fifth predetermined value.

28. The power conversion circuit according to claim 27, characterized in that, The startup phase also includes a third phase from the third time point to the fourth time point; in the third phase, the fifth predetermined value is increased to 50% according to the third duty cycle function.

29. The power conversion circuit according to claim 28, characterized in that, The duty cycle of the drive signal is maintained at 50% in the fourth stage; The fourth phase begins at the fourth moment.

30. The power conversion circuit according to claim 20, characterized in that, The first switching unit includes a full-bridge switching unit or a half-bridge switching unit.

31. The power conversion circuit according to claim 20, characterized in that, Also includes: A negative feedback circuit is used to detect the drain current of the switch during the startup phase, and when the drain current of the switch is detected to be greater than a current threshold, control the reduction of the duty cycle of the drive signal.

32. The power conversion circuit according to claim 20, characterized in that, Also includes: The second power converter includes: A second switching unit, wherein at least one switch in the second switching unit is driven by a driving circuit as described in any one of claims 1 to 19; The first input terminal of the first switching unit is electrically connected to the positive terminal of the input voltage, and the second input terminal of the first switching unit is electrically connected to the first input terminal of the second switching unit; the second input terminal of the second switching unit is electrically connected to the negative terminal of the input voltage. The output terminal of the first power converter is connected in parallel with the output terminal of the second power converter.

33. The power conversion circuit according to claim 32, characterized in that, Also includes: The controller is used to acquire the half-bus voltage of the second input terminal of the first switching unit or the first input terminal of the second switching unit; If the half-bus voltage is greater than half of the input voltage, the duty cycle of the drive signal of the switch in the second switching unit is compensated. If the half-bus voltage is less than half of the input voltage, the duty cycle of the drive signal of the switch in the first switching unit is compensated.

34. A driving method, characterized in that, include: Provide drive signals; The drive signal is transmitted to the control terminal of the switch via a resistor; By coordinating the resistance value of the resistor and the duty cycle of the drive signal, the switch is kept in the constant current region during the startup phase.

35. The driving method according to claim 34, characterized in that, The resistance value is determined based on the set value and amplitude of the drive signal's drive time, as well as the peak value of the gate-source voltage, gate parasitic resistance, and input capacitance of the switch during the startup phase; the set value corresponds to the on-time corresponding to the minimum duty cycle of the drive signal during the startup phase.

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