Embedded system memory management method and system and electronic equipment thereof

Abstract

The invention provides an embedded system memory management method and system and electronic equipment thereof. The method comprises the following steps: carrying out initialization processing on a to-be-managed embedded system memory; in the running process of the embedded system memory, data distribution and space release are carried out on the embedded system memory according to the received application request and release request; regularly triggering statistical check on each parameter of the embedded system memory to generate a corresponding parameter triggering result; and judging whether each parameter triggering result meets a triggering adjustment condition or not, and adjusting the parameters meeting the triggering adjustment condition. The problem that an existing embedded system memory management method cannot give consideration to concurrency efficiency and fragment control can be solved.

Description

Technical Field

[0001] This invention relates to the field of embedded development technology, and more specifically, to an embedded system memory management method, system, and electronic device thereof. Background Technology

[0002] For IoT devices such as automotive electronic control units (ECUs), their embedded systems are often in resource-constrained application scenarios, so these embedded systems typically do not receive support from standard operating systems or complete C runtime libraries (Libc).

[0003] For resource-constrained embedded systems, memory management is particularly critical. Existing memory management methods for such embedded systems include static pre-partitioning, fixed-size memory pools, and buddy system algorithms. However, while these existing methods can manage memory to a certain extent, they cannot automatically adjust the memory structure in a timely manner during actual use, and they also struggle to balance concurrency efficiency with fragmentation control.

[0004] Therefore, there is an urgent need for an automatic memory management method for embedded systems that can balance concurrency efficiency and fragmentation control. Summary of the Invention

[0005] In view of the above problems, the purpose of this invention is to provide an embedded system memory management method, system and electronic device to solve the problem that existing embedded system memory management methods cannot simultaneously achieve concurrency efficiency and fragmentation control.

[0006] The embedded system memory management method provided by this invention includes: Initialize the memory of the embedded system to be managed; During the operation of the embedded system memory, data allocation and space release are performed on the embedded system memory according to the received application requests and release requests, respectively; and statistical checks are periodically triggered on various parameters of the embedded system memory to generate corresponding parameter trigger results. Determine whether the triggering results of each parameter meet the triggering adjustment conditions, and adjust the parameters that meet the triggering adjustment conditions.

[0007] Alternatively, the process of allocating data to the embedded system memory according to the application request includes: Determine the size of the request data in the application request and align the request data in the application request; The aligned request data is inserted into the corresponding memory location according to the requested size.

[0008] Alternatively, the process of inserting the aligned request data into the corresponding memory location according to the request size includes: Based on the requested size, the free block list is traversed starting from the head of the linked list in the embedded system memory to determine the candidate insertion gap group; Based on preset selection rules, the final insertion gap is determined from the candidate insertion gap group, and the request data is inserted into the final insertion gap.

[0009] In addition, an alternative approach is that the process of inserting the aligned request data into the corresponding memory location according to the request size further includes: If no candidate insertion slot is found in the free block list, the request data is inserted at the end of the free block list.

[0010] Alternatively, the process of releasing the embedded system memory based on the received release request includes: The linked list of the embedded system memory is traversed according to the release request to determine the entry to be released corresponding to the release request; The entries to be released are cleared.

[0011] Alternatively, an alternative approach is to adjust the parameters that meet the trigger adjustment conditions, including the following steps: The parameters that meet the trigger adjustment conditions are simulated and adjusted using at least two preset adjustment strategies, and the net benefit of the parameters that meet the trigger adjustment conditions under each adjustment strategy is calculated. The adjustment strategy that yields the greatest net benefit is selected to adjust the parameters that meet the trigger adjustment conditions.

[0012] Alternatively, the process for calculating the net return of each adjustment strategy may include: Calculate the benefits and costs of the parameters that meet the trigger adjustment conditions under each adjustment strategy; The benefits and costs are calculated based on a preset net benefit formula to determine the net benefit of the parameter that meets the trigger adjustment condition under each adjustment strategy.

[0013] In addition, alternative solutions include subspace fission, subspace merging, boundary fine-tuning, block migration, and idle structure reconstruction.

[0014] On the other hand, the present invention also provides an embedded system memory management system, including an initialization module, an allocation and release module, a statistical check module, and an adjustment module; wherein, The initialization module is used to initialize the memory of the embedded system to be managed; The allocation and release module is used to allocate data and release space in the embedded system memory according to the received application request and release request during the operation of the embedded system memory. The statistical inspection module is used to periodically trigger statistical inspections on various parameters of the embedded system memory during the operation of the embedded system memory, so as to generate corresponding parameter triggering results. The adjustment module is used to determine whether the triggering results of each parameter meet the triggering adjustment conditions, and to adjust the parameters that meet the triggering adjustment conditions.

[0015] In another aspect, the present invention also provides an electronic device, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that the processor, when executing the computer program, implements the steps of the embedded system memory management method as described above.

[0016] Compared with the prior art, the embedded system memory management method, system, and electronic device provided by the present invention have the following advantages: During the operation of the embedded system memory, data allocation and space release are performed on the embedded system memory according to the received application and release requests, respectively; and various parameters of the embedded system memory are periodically triggered for statistical checks to generate corresponding parameter trigger results; it is determined whether the trigger results of each parameter meet the trigger adjustment conditions, and the parameters that meet the trigger adjustment conditions are adjusted; the memory structure can be automatically adjusted in a timely manner, and both concurrency efficiency and fragmentation control can be achieved.

[0017] To achieve the foregoing and related objectives, one or more aspects of the invention include the features which will be described in detail below and specifically pointed out in the claims. The following description and accompanying drawings illustrate certain exemplary aspects of the invention. However, these aspects indicate only a few of the various ways in which the principles of the invention can be used. Furthermore, the invention is intended to include all such aspects and their equivalents. Attached Figure Description

[0018] Other objects and results of the invention will become more apparent and readily understood with reference to the following description taken in conjunction with the accompanying drawings and the contents of the claims, and with a more complete understanding of the invention. In the drawings: Figure 1 A flowchart of an embedded system memory management method provided according to an embodiment of the present invention; Figure 2 A flowchart related to initialization provided according to an embodiment of the present invention; Figure 3 A flowchart related to data allocation provided according to embodiments of the present invention; Figure 4 A flowchart related to space release provided according to an embodiment of the present invention; Figure 5 This is a flowchart illustrating the relevant process for triggering adjustments according to an embodiment of the present invention; Figure 6 This is an internal logic block diagram of an embedded system memory management system provided according to an embodiment of the present invention; Figure 7 An internal logic block diagram of an electronic device provided according to an embodiment of the present invention. Detailed Implementation

[0019] In the following description, numerous specific details are set forth for illustrative purposes and to provide a thorough understanding of one or more embodiments. However, it will be apparent that these embodiments may also be implemented without these specific details. In other instances, well-known structures and devices are shown in block diagram form for ease of description of one or more embodiments.

[0020] The embodiments of this invention can be applied to electronic devices such as computer systems / servers, which can operate with a wide range of other general-purpose or special-purpose computing system environments or configurations. Examples of well-known computing systems, environments, and / or configurations suitable for use with electronic devices such as computer systems / servers include, but are not limited to: personal computer systems, server computer systems, thick clients, handheld or laptop devices, microprocessor-based systems, set-top boxes, programmable consumer electronics, networked personal computers, minicomputer systems, mainframe computer systems, and distributed cloud computing environments including any of the above systems, etc.

[0021] Computer systems / servers and other electronic devices can be described in the general context of computer-executable instructions executed by the computer system. Typically, program modules can include routines, programs, object programs, components, logic, data structures, etc., which perform specific tasks or implement specific abstract data types. Computer systems / servers and other electronic devices can be implemented in distributed cloud computing environments, where tasks are executed by remote processing devices linked through communication networks. In distributed cloud computing environments, program modules can reside on local or remote computing system storage media, including storage devices.

[0022] It should be understood that the terminology used in this invention is merely for describing particular embodiments and is not intended to limit the invention. Furthermore, with respect to numerical ranges in this invention, it should be understood that each intermediate value between the upper and lower limits of the range is also specifically disclosed. Every smaller range between any stated value or intermediate value within a stated range, and any other stated value or intermediate value within said range, is also included in this invention. The upper and lower limits of these smaller ranges may be independently included or excluded from the range.

[0023] Various modifications and variations can be made to the specific embodiments described in this specification without departing from the scope or spirit of the invention, as will be apparent to those skilled in the art. Other embodiments derived from this specification will also be readily apparent to those skilled in the art. This application specification and embodiments are merely exemplary.

[0024] In the following description, numerous specific details are set forth for illustrative purposes and to provide a thorough understanding of one or more embodiments. However, it will be apparent that these embodiments may also be implemented without these specific details.

[0025] The following details the specific process of the embedded system memory management method provided by this invention. Figure 2 A flowchart of an embedded system memory management method according to an embodiment of the present invention is shown, by... Figure 1 It can be seen that the embedded system memory management method provided by the present invention includes: S110: Initialize the memory of the embedded system to be managed.

[0026] Specifically, such as Figure 2 As shown, in the managed embedded system startup or dedicated initialization interface, such as in InitMemory(void In `base_addr, uint32_ttotal_size`, the block descriptor table (e.g., `Blocks[MAX_BLOCKS]`, each entry contains fields such as `address`, `size`, and `next_index`) is initialized and cleared. Each entry can be cleared to zero through initialization. Then, an initial free block entry is inserted, such as: `blocks[0]={address=base_addr, size=total_size, next_index=-1}`. Next, the boundaries are recorded and alignment rules are set, such as `memory_start=base_addr`, `memory_end=base_addr+total_size`, and the alignment size is set (e.g., 4 bytes / 8 bytes). Finally, the statistics / log / error code structure is initialized (e.g., request count, release count, fragmentation accumulation, log buffer, error flag variable, etc.).

[0027] S120: During the operation of the embedded system memory, data allocation and space release are performed on the embedded system memory according to the received application request and release request, respectively.

[0028] Specifically, the process of allocating data to the embedded system memory according to the application request includes: determining the size of the request data and aligning the request data; and inserting the aligned request data into the corresponding memory location according to the request size.

[0029] More specifically, the process of inserting the aligned request data into the corresponding memory location according to the request size includes: traversing the free block list starting from the head of the linked list of the embedded system memory based on the request size to determine a candidate insertion gap group; determining the final insertion gap from the candidate insertion gap group based on a preset selection rule, and inserting the request data into the final insertion gap; furthermore, if no candidate insertion gap is found in the free block list, the request data is inserted at the tail of the free block list.

[0030] In one specific embodiment of the present invention, such as Figure 3 As shown, during the operation of the embedded system memory, when a request is received, the size of the requested data is determined. Then, the requested data is first rounded up to the alignment boundary (for example, if aligned to 4 bytes, then aligned=(s+3)&(~3)). Then, the free block list is traversed from the head of the linked list (linked according to next_index), pre=head_index is set, and then cur=blocks[pre].next_index is set. For each pair (pre,cur), the gap spare=blocks[cur].address−(blocks[pre].address+blocks[pre].size) is calculated. If spare≥aligned, it is determined that there is a place where a space can be inserted. In actual operation, multiple candidate space gaps can be recorded to form a candidate space gap group. Finally, based on a preset rule (e.g., spare is the smallest but still ≥aligned), the best fit gap is selected from the candidate space gap group as the final space gap, which is used as the insertion point.

[0031] It should be noted that if no insertion point is found in the middle block, the request data is considered to be inserted at the end of the chain, with the tail gap = memory_end - (blocks[last].address + blocks[last].size). If there is a tail gap, a new block is inserted at the tail, and the request data is stored in the new block. When inserting a new block, a free entry idx is allocated from the free block entry pool. Let blocks[idx].address=blocks[pre].address+blocks[pre].size, blocks[idx].size=aligned, blocks[idx].next_index=blocks[pre].next_index, blocks[pre].next_index=idx.

[0032] After the requested data is inserted, update the request count, hit rate statistics, and logs, and then return the new block address to the caller.

[0033] Furthermore, the process of releasing memory in the embedded system based on the received release request includes: The linked list of the embedded system memory is traversed according to the release request to determine the entry to be released corresponding to the release request; the entry to be released is then cleared.

[0034] In one specific embodiment of the present invention, such as Figure 4 As shown, after receiving a release request, the managed embedded system traverses the linked list based on the release pointer ptr to find the entry where blocks[idx].address == ptr (i.e., the entry corresponding to the release pointer ptr). If not found, it is considered an illegal release, and an error code / log flag is set. If found, it is joined with the predecessor pre entry, pre.next_index = blocks[idx].next_index, and the entry is recycled into the free entry pool for reuse. Specifically, memset(ptr, 0, blocks[idx].size) or other zeroing operations can be performed to recycle the entry. In addition, it can also check whether it can be physically merged with the successor block of pre or other free blocks. If merging is possible, blocks[pre].size += size_next and the join is skipped.

[0035] After the release request is processed, update the release count, number of free blocks, fragmentation statistics, and log / error codes.

[0036] S130: Periodically trigger statistical checks on various parameters of the embedded system memory to generate corresponding parameter trigger results; S140: Determine whether each parameter trigger result meets the trigger adjustment conditions, and adjust the parameters that meet the trigger adjustment conditions.

[0037] Specifically, the process of adjusting the parameters that meet the trigger adjustment conditions includes: performing simulated adjustment on the parameters that meet the trigger adjustment conditions through at least two preset adjustment strategies, and calculating the net benefits of the parameters that meet the trigger adjustment conditions under each adjustment strategy; selecting the adjustment strategy with the maximum net benefit to adjust the parameters that meet the trigger adjustment conditions.

[0038] More specifically, the process of calculating the net benefits of each adjustment strategy includes: calculating the benefits and costs of the parameters that meet the trigger adjustment conditions under each adjustment strategy; calculating the benefits and costs based on a preset net benefit formula to determine the net benefits of the parameters that meet the trigger adjustment conditions under each adjustment strategy.

[0039] It should be noted that as Figure 5 shown, during the actual operation of the embedded system memory, each malloc / free operation requires updating the corresponding statistical variables; for example, the application times, release times of each entry / sub-pool / global, the current number of free blocks / size distribution of free blocks, fragmentation metrics (such as the ratio of the largest continuous free block to the total free blocks, the average size of free blocks), hit rate / hole hit rate / split times / borrow times, etc.

[0040] Then, periodically (such as every N operations or every cycle of T time), trigger statistical checks are performed on the parameters of the embedded system memory to determine whether each parameter meets the corresponding adjustment conditions (such as hit rate < R_min, free rate > E_max, fragmentation deviation > ΔF_thresh, the number of consecutive unadjusted times exceeds the threshold, etc.). If there are some parameters that meet the trigger adjustment conditions, these parameters enter the prediction / decision-making stage.

[0041] In the prediction / decision-making stage, for each parameter, several possible adjustment strategies (such as fission / merger / boundary fine-tuning / block migration, etc.) are simulated for it, and then the benefits (such as fragmentation reduction, utilization improvement) and costs (block relocation, structure reconstruction, pause / delay overhead, etc.) of this parameter under each strategy are calculated (such as estimated); if the net benefit of a certain adjustment strategy of this parameter > λ × cost (λ is the threshold coefficient), then select this adjustment strategy as the final actual adjustment to be executed; otherwise, skip the adjustment; for a certain parameter, if there are multiple adjustment strategies with net benefits > λ × cost (λ is the threshold coefficient), then select the adjustment strategy with the maximum net benefit to adjust this parameter; after the adjustment is completed, update the statistics / log / error code / cooling mechanism, etc.

[0042] In a preferred embodiment of the present invention, the adjustment strategy includes subspace fission, subspace merging, boundary fine-tuning, block migration, and free structure reconstruction; wherein, subspace fission refers to dividing a large space / subregion into two subregions / subpools; subspace merging refers to merging two free regions / subpools; boundary fine-tuning refers to slightly moving the boundary point up or down along the subpool boundary; block migration / reassignment refers to address migration / reassignment processing for free blocks / blocks that may cross boundaries due to boundary changes; free structure reconstruction refers to rebuilding its linked list / fast list / cache structure after the subpool / region structure is adjusted; it should be noted that in the above adjustment measurement process, there may be overhead such as block data migration, pointer update, free entry reconstruction, log recording, and state refresh.

[0043] It should be noted that for the memory of the embedded system to be managed, each processing core / each task group can be configured with a local sub-pool / local free list / fast path structure, and common allocation / release operations are preferentially performed locally; however, if the local sub-pool resources are insufficient, cross-core / cross-pool borrowing / splitting processing can be used. Furthermore, lock-free / atomic operations / CAS / lightweight spinlocks are used in fast paths (small block allocation / release) to reduce synchronization overhead and blocking; exclusive locks / critical section protection are used in adjustment / repartitioning paths; additionally, for interrupt / ISR contexts, dedicated lock-free / safe paths can be designed without using blocking lock mechanisms. Finally, if the embedded system to be managed has priority task constraints, priority scheduling / inheritance / priority inversion avoidance mechanisms can be added to the allocation / release process.

[0044] As can be seen from the above specific embodiments, the embedded system memory management method provided by the present invention has at least the following advantages: 1. Enhanced runtime adaptability: Existing solutions typically determine the pool structure during the initialization phase, making it difficult to adjust as the runtime load changes. The solution provided by this invention can monitor application / release statistics in real time during system operation and automatically perform sub-pool fission / merging / boundary fine-tuning / block migration when trigger conditions are met. 2. Lower fragmentation rate and higher memory utilization: Existing solutions mainly rely on initial partitioning and static fission to control fragmentation, which reduces efficiency when the load shifts; the solution provided by this invention effectively reduces the waste of idle fragments and improves the overall utilization rate through interleaving allocation + borrowing / splitting mechanism + online reconstruction. 3. Main path performance remains stable; despite the adjustment mechanism, most allocation / release operations still follow the lightweight path (insertion / splitting / fast table / lock-free mechanism), ensuring stable allocation / release response time and preventing the main process from being affected by the adjustment mechanism; 4. Adjustment cost controllable and jitter protection mechanism: The solution provided by this invention performs simulation / prediction, calculates net benefit and cost before triggering adjustment, and sets a cooling / jitter control mechanism to ensure that adjustment has benefits without frequent oscillations; 5. Excellent concurrency and multi-core adaptation: Existing static solutions are prone to lock contention and high latency in multi-task / multi-core environments; the solution provided by this invention designs a local sub-pool / fast path / lock-free / light synchronization mechanism and supports cross-core / cross-pool borrowing, which significantly reduces concurrency conflicts and improves throughput. 6. Enhanced diagnostic / error feedback capabilities: Existing solutions have limited disclosure regarding error / log / diagnostic mechanisms; the solution provided by this invention adds error codes / status flags / log recording mechanisms to the allocation / release / adjustment paths, improving system debuggability and reliability; 7. High flexibility and configurability: The solution provided by this invention makes various strategies (trigger threshold, cooldown time, whether to split / borrow, adjustment frequency, etc.) configurable, making it easy to optimize and adapt to different hardware platforms / load scenarios.

[0045] The embedded system memory management system 400 provided by this invention can be installed in electronic devices. Depending on the functions implemented, such as... Figure 6 As shown, the embedded system memory management system 400 may include: an initialization module 410, an allocation and release module 420, a statistics check module 430, and an adjustment module 440. The modules described in this invention mainly refer to a series of computer program segments that can be executed by the processor of an electronic device and perform a fixed function, and are stored in the memory of the electronic device.

[0046] In this embodiment, the functions of each module / unit are as follows: Initialization module 410 is used to initialize the memory of the embedded system to be managed. The allocation and release module 420 is used to allocate data and release space in the embedded system memory according to the received application request and release request during the operation of the embedded system memory. The statistical inspection module 430 is used to periodically trigger statistical inspections on various parameters of the embedded system memory during the operation of the embedded system memory, so as to generate corresponding parameter triggering results. The adjustment module 440 is used to determine whether the triggering results of each parameter meet the triggering adjustment conditions, and to adjust the parameters that meet the triggering adjustment conditions.

[0047] It should be noted that the above embodiments of the embedded system memory management system and the embedded system memory management method can be used for reference, and will not be elaborated further here.

[0048] Figure 7 This is a schematic diagram of the structure of an electronic device that implements the embedded system memory management system of the present invention.

[0049] like Figure 7 As shown, the electronic device 1 may include a processor 10, a memory 11 and a bus, and may also include a computer program, such as an embedded system memory management program 12, stored in the memory 11 and capable of running on the processor 10.

[0050] The memory 11 includes at least one type of readable storage medium, including flash memory, portable hard drive, multimedia card, card-type memory (e.g., SD or DX memory), magnetic memory, magnetic disk, optical disk, etc. In some embodiments, the memory 11 can be an internal storage unit of the electronic device 1, such as the portable hard drive of the electronic device 1. In other embodiments, the memory 11 can also be an external storage device of the electronic device 1. Furthermore, the memory 11 can include both internal and external storage units of the electronic device 1. The memory 11 can be used not only to store application software and various types of data installed on the electronic device 1, such as program code, but also to temporarily store data that has been output or will be output.

[0051] In some embodiments, the processor 10 may be composed of integrated circuits, such as a single packaged integrated circuit or multiple integrated circuits with the same or different functions, including combinations of one or more central processing units (CPUs), microprocessors, digital processing chips, graphics processors, and various control chips. The processor 10 is the control unit of the electronic device, connecting various components of the entire electronic device through various interfaces and lines. It executes programs or modules (such as embedded system memory management programs) stored in the memory 11, and calls data stored in the memory 11 to perform various functions of the electronic device 1 and process data.

[0052] The bus can be a Peripheral Component Interconnect Standard (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This bus can be divided into an address bus, a data bus, a control bus, etc. The bus is configured to enable communication between the memory 11 and at least one processor 10, etc.

[0053] Figure 7 Only electronic devices with components are shown; it will be understood by those skilled in the art that... Figure 7 The structure shown does not constitute a limitation on the electronic device 1, and may include fewer or more components than shown, or combine certain components, or have different component arrangements.

[0054] For example, although not shown, the electronic device 1 may also include a power supply (such as a battery) to power the various components. Preferably, the power supply can be logically connected to the at least one processor 10 through a power management device, thereby enabling functions such as charging management, discharging management, and power consumption management. The power supply may also include one or more DC or AC power supplies, recharging devices, power fault detection circuits, power converters or inverters, power status indicators, and other arbitrary components. The electronic device 1 may also include various sensors, Bluetooth modules, Wi-Fi modules, etc., which will not be described in detail here.

[0055] Furthermore, the electronic device 1 may also include a network interface. Optionally, the network interface may include a wired interface and / or a wireless interface (such as a Wi-Fi interface, a Bluetooth interface, etc.), which is typically used to establish communication connections between the electronic device 1 and other electronic devices.

[0056] Optionally, the electronic device 1 may further include a user interface, which may be a display, an input unit (such as a keyboard), or, optionally, a standard wired interface or a wireless interface. In some embodiments, the display may be an LED display, a liquid crystal display, a touch-sensitive liquid crystal display, or an organic light-emitting diode touchscreen, etc. The display may also be appropriately referred to as a screen or display unit, used to display information processed in the electronic device 1 and to display a visual user interface.

[0057] It should be understood that the embodiments described are for illustrative purposes only and do not limit the scope of protection of the present invention.

[0058] The embedded system memory management program 12 stored in the memory 11 of the electronic device 1 is a combination of multiple instructions. When run in the processor 10, it can implement the embedded system memory management method.

[0059] Furthermore, if the modules / units integrated in the electronic device 1 are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. The computer-readable medium may include: any entity or device capable of carrying the computer program code, a recording medium, a USB flash drive, a portable hard drive, a magnetic disk, an optical disk, a computer memory, or a read-only memory.

[0060] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, apparatus, article, or method that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, apparatus, article, or method. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, apparatus, article, or method that includes that element.

[0061] As per the above reference Figures 1 to 7 The embedded system memory management method and system according to the present invention are described by way of example. However, those skilled in the art should understand that various modifications can be made to the embedded system memory management method and system proposed in the present invention without departing from the scope of the invention. Therefore, the scope of protection of the present invention should be determined by the contents of the appended claims.

Claims

1. A memory management method for an embedded system, characterized in that, include: Initialize the memory of the embedded system to be managed; Based on the received application and release requests, the memory of the initialized embedded system is allocated data and released space respectively; and the various parameters of the embedded system memory are periodically triggered and statistically checked to generate corresponding parameter trigger results. Determine whether the triggering results of each parameter meet the triggering adjustment conditions, and adjust the parameters that meet the triggering adjustment conditions.

2. The embedded system memory management method as described in claim 1, characterized in that, The process of allocating data to the embedded system memory according to the application request includes: Determine the size of the request data in the application request and align the request data in the application request; The aligned request data is inserted into the corresponding memory location according to the requested size.

3. The embedded system memory management method as described in claim 2, characterized in that, The process of inserting the aligned request data into the corresponding memory location according to the request size includes: Based on the requested size, the free block list is traversed starting from the head of the linked list in the embedded system memory to determine the candidate insertion gap group; Based on preset selection rules, the final insertion gap is determined from the candidate insertion gap group, and the request data is inserted into the final insertion gap.

4. The embedded system memory management method as described in claim 3, characterized in that, The process of inserting the aligned request data into the corresponding memory location according to the request size also includes: If no candidate insertion slot is found in the free block list, the request data is inserted at the end of the free block list.

5. The embedded system memory management method as described in claim 4, characterized in that, The process of releasing memory space in the embedded system based on the received release request includes: The linked list of the embedded system memory is traversed according to the release request to determine the entry to be released corresponding to the release request; The entries to be released are cleared.

6. The embedded system memory management method as described in claim 5, characterized in that, The process of adjusting parameters that meet the trigger adjustment conditions includes: The parameters that meet the trigger adjustment conditions are simulated and adjusted using at least two preset adjustment strategies, and the net benefit of the parameters that meet the trigger adjustment conditions under each adjustment strategy is calculated. The adjustment strategy that yields the greatest net benefit is selected to adjust the parameters that meet the trigger adjustment conditions.

7. The embedded system memory management method as described in claim 6, characterized in that, The process of calculating the net return of each adjustment strategy includes: Calculate the benefits and costs of the parameters that meet the trigger adjustment conditions under each adjustment strategy; The benefits and costs are calculated based on a preset net benefit formula to determine the net benefit of the parameter that meets the trigger adjustment condition under each adjustment strategy.

8. The embedded system memory management method as described in claim 7, characterized in that, The adjustment strategies include subspace fission, subspace merging, boundary fine-tuning, block migration, and idle structure reconstruction.

9. An embedded system memory management system, characterized in that, It includes an initialization module, an allocation and release module, a statistical check module, and an adjustment module; among which, The initialization module is used to initialize the memory of the embedded system to be managed; The allocation and release module is used to allocate data and release space in the embedded system memory according to the received application request and release request during the operation of the embedded system memory. The statistical inspection module is used to periodically trigger statistical inspections on various parameters of the embedded system memory during the operation of the embedded system memory, so as to generate corresponding parameter triggering results. The adjustment module is used to determine whether the triggering results of each parameter meet the triggering adjustment conditions, and to adjust the parameters that meet the triggering adjustment conditions.

10. An electronic device, comprising: A memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, when the processor executes the computer program, it implements the steps of the embedded system memory management method as described in any one of claims 1 to 8.

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