Instruction transmitting system and method, electronic equipment and chip

Abstract

The invention discloses an instruction transmitting system and method, a chip and electronic equipment, and belongs to the technical field of processors. The system comprises a distribution module, a determination module and a selection module. The distribution module is used for distributing a first instruction to the storage unit, the first instruction is used for indicating execution of operation on the multiple source operands, the storage unit is used for storing the preparation state of each source operand, and the preparation state represents whether the corresponding source operands are prepared or not. And the determination module is used for determining that the preparation state of any source operand represents that any source operand is prepared under the condition that any source operand is stored in the first source register. And the selection module is used for transmitting the first instruction in the storage unit to the processor under the condition that each preparation state represents that the corresponding source operand is prepared. The system transmits the instruction to the processor only when each source operand is stored in the source register, so that the processor can immediately process the instruction, and the processing efficiency is improved.

Description

Technical Field

[0001] This application relates to the field of processor technology, and in particular to an instruction issuing system, method, electronic device, and chip. Background Technology

[0002] With the development of processor technology, the performance requirements for processors are becoming increasingly demanding, and processor performance is closely related to its processing efficiency. Specifically, a processor can process instructions issued to it by the instruction dispatch system in the order they are issued.

[0003] However, if the instruction issue order is not properly arranged, the processor will have to wait a significant amount of time to process the instructions. For example, since instructions are used to instruct the processing of source operands, if an instruction has been issued but its source operands are not yet ready, the processor must wait for the source operands to become ready before it can process the instruction. This will affect the processor's processing efficiency and lead to a decrease in processor performance. Summary of the Invention

[0004] This application provides an instruction issuing system, method, electronic device, and chip that can improve the processing efficiency of the processor, thereby improving the performance of the processor. The technical solution includes the following contents.

[0005] In a first aspect, a command issuing system is provided, the system comprising an allocation module, a determination module, and a selection module;

[0006] The allocation module is used to allocate a first instruction to a storage unit. The first instruction is used to instruct the execution of operations on multiple source operands. The storage unit is used to store the preparation status of each source operand. The preparation status indicates whether the corresponding source operand is ready.

[0007] The determining module is used to determine the preparation state of any source operand, indicating that the source operand has been prepared, when any source operand is stored in the first source register.

[0008] The selection module is used to send the first instruction from the memory unit to the processor when each preparation state indicates that the corresponding source operand is ready.

[0009] Secondly, a command issuing method is provided, the method comprising:

[0010] The first instruction is assigned to the storage unit, which is used to instruct the operation to be performed on multiple source operands. The storage unit is used to store the preparation status of each source operand, and the preparation status indicates whether the corresponding source operand is ready.

[0011] When any one source operand is stored in the first source register, determining the preparation state of the source operand indicates that the source operand has been prepared.

[0012] When each preparation state indicates that the corresponding source operand is ready, the first instruction in the memory cell is sent to the processor.

[0013] In one possible implementation, the method further includes:

[0014] Obtain the second instruction, modify the second instruction to obtain the first instruction;

[0015] Wherein, the first instruction is used to instruct the destination operand to be stored in a first destination register, the second instruction is used to instruct the destination operand to be stored in a second destination register, the destination operand is the result of the operation of the plurality of source operands, the first destination register does not store data before storing the destination operand, and the second destination register stores data of other instructions besides the second instruction.

[0016] In one possible implementation, the first source register, the first destination register, and the second destination register are all physical registers, the first source register corresponds to the first source number, the first destination register corresponds to the first destination number, and the second destination register corresponds to the second destination number;

[0017] The modification of the second instruction to obtain the first instruction includes:

[0018] Obtain the second instruction, which includes a plurality of second source numbers and a third destination number, wherein the plurality of second source numbers and the third destination number correspond to different logic registers;

[0019] Obtain the first destination number and write the first destination number into the number mapping table, which is used to store the number mapping relationship between the logical register and the physical register.

[0020] Based on the second instruction and the number mapping table, determine the first source number corresponding to each second source number and the second destination number corresponding to the third destination number, modify the second destination number to the first destination number, and determine the first instruction based on each first source number and the first destination number.

[0021] In one possible implementation, the method further includes:

[0022] Select the first destination number that is at the top of the numbering queue, which is used to store the numbers of physical registers that do not contain data in sequence.

[0023] In one possible implementation, the method further includes:

[0024] Obtain the number to be used, and push the number to be used into the number queue after the last number. The number to be used is the number of the physical register to which the data is to be released.

[0025] In one possible implementation, the storage unit is further used to store the first source number corresponding to each first source register; the method further includes:

[0026] Get the register number;

[0027] If the register number exists in each of the first source numbers, it is determined that the source operand has been stored in the first source register corresponding to the register number.

[0028] In one possible implementation, the method further includes:

[0029] Record the first elapsed time after the third instruction is transmitted, the third instruction being used to instruct the computation to obtain any one of the source operands;

[0030] If the first time is not less than the first threshold, obtain the register number corresponding to any one of the source operands.

[0031] Thirdly, a chip is provided, the chip including the instruction issuing system described in the first aspect, the instruction issuing system being used to execute the instruction issuing method described in the second aspect.

[0032] Fourthly, an electronic device is provided, the electronic device comprising the chip described in the third aspect above.

[0033] Fifthly, a computer-readable storage medium is provided, wherein at least one computer program is stored therein, the at least one computer program being loaded and executed by a processor to enable an electronic device to implement the instruction issuing method described in the second aspect above.

[0034] In a sixth aspect, a computer program is provided, said computer program being at least one, wherein the at least one computer program is loaded and executed by a processor to enable an electronic device to implement the instruction issuing method described in the second aspect above.

[0035] In a seventh aspect, a computer program product is also provided, wherein at least one computer program is stored therein, the at least one computer program being loaded and executed by a processor to enable an electronic device to implement the instruction issuing method described in the second aspect above.

[0036] The technical solution provided in this application brings at least the following beneficial effects:

[0037] In the technical solution provided in this application, the selection module only issues the first instruction to the processor after all source operands are ready. Since all source operands have already been stored in the first source register when the processor receives the first instruction, the processor does not need to wait and can process the instruction immediately, resulting in higher processing efficiency and improved processor performance. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 This is a schematic diagram of a computer system provided in an embodiment of this application;

[0040] Figure 2 This is a schematic diagram of a command issuing system provided in an embodiment of this application;

[0041] Figure 3 This is a schematic diagram of a table entry provided in an embodiment of this application;

[0042] Figure 4 This is a schematic diagram of an instruction issuance provided in an embodiment of this application;

[0043] Figure 5 This is a schematic diagram of another command issuing system provided in an embodiment of this application;

[0044] Figure 6 This is a schematic diagram of the architecture of a renaming module provided in an embodiment of this application;

[0045] Figure 7 This is a schematic diagram of another command issuing system provided in an embodiment of this application;

[0046] Figure 8 This is a flowchart illustrating a command issuance method provided in an embodiment of this application;

[0047] Figure 9 This is a schematic diagram of a command issuing method provided in an embodiment of this application;

[0048] Figure 10 This is an architecture diagram of an instruction issuing system provided in an embodiment of this application;

[0049] Figure 11This is a schematic diagram of the structure of a terminal device provided in an embodiment of this application;

[0050] Figure 12 This is a schematic diagram of the structure of a server provided in an embodiment of this application. Detailed Implementation

[0051] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0052] It should be noted that the terms "first," "second," etc., used in this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0053] First, the abbreviations and key terms involved in the embodiments of this application are defined.

[0054] Source operands: The data required for the operation.

[0055] Destination operand: The result of the operation.

[0056] Very Long Instruction Word (VLIW): Also known as a Very Long Instruction Set Architecture, it is a type of instruction set. An instruction set consists of multiple instructions that instruct the computation of at least two source operands to obtain a destination operand. Any two instructions can involve the same data. For example, a source operand of instruction one may be the destination operand of instruction two, or a source operand of instruction one may be a source operand of instruction two. In practical applications, the data involved in any two instructions can also be different. VLIW enables instruction-level parallelism. By chaining multiple instructions together, the processor can process multiple instructions in parallel, achieving instruction-level parallelism, increasing the number of instructions processed per clock cycle, and improving instruction processing speed.

[0057] Micro-operations (Uop): Instructions that enable the processor to perform the lowest-level operations (i.e., micro-operations). For example, micro-operations are used to instruct the reading of data from memory, the writing of data to a register, or the performance of operations such as addition, subtraction, multiplication, and division.

[0058] Source Register: Used to store source operands.

[0059] Destination Register: Used to store the destination operand.

[0060] Physical registers: These are the actual registers located inside a chip, used to temporarily store information such as instructions, data, and addresses. Chips include central processing units (CPUs) and artificial intelligence (AI) processors.

[0061] Logical register: A register used in an instruction to store source or destination operands. Each logical register can be mapped to a physical register.

[0062] Write-After-Write (WAW) dependency: If instruction one instructs to write data to a register, and instruction two instructs to write another data to the same register, then instruction two is equivalent to modifying the result of instruction one's operation, and there is a write-after-write dependency between instruction one and instruction two. For example, instruction one: VADD V2, V1, V0; instruction two: VSUB V2, V4, V3. Instruction one adds the source operand in logical register V1 to the source operand in logical register V0, resulting in the destination operand in logical register V2. Instruction two subtracts the source operand in logical register V4 from the source operand in logical register V3, resulting in the destination operand in logical register V2. Because the destination operand of instruction one is modified to the destination operand of instruction two, there is a write-after-write dependency between instruction one and instruction two.

[0063] Write After Read (WAR): If instruction one instructs to read data into a register, and instruction two instructs to write another data into that register, then instruction two is equivalent to modifying the data required for the operation by instruction one, and a write-after-read dependency exists between instruction one and instruction two. For example, instruction one: VADD V2, V1, V0; instruction two: VSUB V0, V4, V3. Instruction one represents adding the source operand in logical register V1 to the source operand in logical register V0, resulting in the destination operand in logical register V2. Instruction two represents subtracting the source operand in logical register V4 from the source operand in logical register V3, resulting in the destination operand in logical register V0. Because the source operand of instruction one is modified to the destination operand of instruction two, a write-after-read dependency exists between instruction one and instruction two.

[0064] Read After Write (RAW) dependency: If instruction one instructs writes data to a register, and instruction two instructs read data from that register, then instruction two is equivalent to reading the result of instruction one's operation. There is a read-after-write dependency between instructions one and two. For example, instruction one: VMUL V2, V1, V0; instruction two: VADD V4, V3, V2. Instruction one multiplies the source operand in logical register V1 with the source operand in logical register V0 to obtain the destination operand in logical register V2. Instruction two adds the source operand in logical register V3 with the source operand in logical register V2 to obtain the destination operand in logical register V4. Since the destination operand of instruction one is the source operand of instruction two, there is a read-after-write dependency between instructions one and two.

[0065] Instruction cavitation: During instruction execution, if there is a pause or delay due to certain reasons, a blank time period (i.e., pause time or delay time) is generated, forming a "cavitation".

[0066] In the field of processor technology, an instruction dispatch system can issue instructions to the processor in the order they are issued, so that the processor can process them. If the instruction dispatch order is not properly arranged, the processor will have to wait a long time to process the instructions. For example, consider the following two instructions.

[0067] Command 1: VADDV4, V3, V2

[0068] Instruction 2: VMUL V2, V1, V0

[0069] Instruction 1 is a vector addition instruction, used to instruct the completion of the vector operation V4 = V3 + V2. Instruction 2 is a vector multiplication instruction, used to instruct the completion of the vector operation V2 = V1 × V0. Therefore, Instruction 1 depends on the result of Instruction 2. When instructions are issued to the processor in the order they are issued, Instruction 1 is issued first. At this time, although the processor receives Instruction 1, it cannot process it, resulting in an instruction bubbling phenomenon. Then, Instruction 2 is issued. The processor receives and processes Instruction 2. At this time, the source operand of Instruction 1 (i.e., the data in logic register V2) is ready, and the processor processes Instruction 1. In other words, the processor receives Instruction 1 before Instruction 2, but it needs to wait for Instruction 2 to be processed before it can process Instruction 1; that is, the processor needs to wait a considerable amount of time to process Instruction 1.

[0070] Because processors can experience instruction cavitation, their processing efficiency is low, thus reducing their performance. To address this, this application provides an instruction issuing system designed to at least solve these technical problems.

[0071] like Figure 1 As shown, Figure 1 This is a schematic diagram of a computer system provided in an embodiment of this application. The computer system includes a terminal device 101 and a server 102, which are connected via a wireless network or a wired network. The terminal device 101 has a client installed and running, and the server 102 provides background services to the client. This embodiment does not limit the type of client. For example, the client can be an instant messaging client, a media playback client, a game client, etc. The target object 103 interacts with the client to achieve instant messaging, playback of music or video media, game play, etc.

[0072] In this embodiment, at least one of the terminal device 101 and the server 102 includes a chip. The chip is responsible for executing programs, and during program execution, it can generate instructions, execute instructions, process data, etc. This application does not limit the type of chip; for example, the chip can be a graphics processing unit (GPU) chip, an artificial intelligence chip, etc. The chip includes an instruction issuing system and a processor. The instruction issuing system is used to issue instructions to the processor so that the processor can execute the instructions. The content of the instruction issuing system has been described below and will not be repeated here.

[0073] In one possible implementation, server 102 undertakes the primary computational work, while terminal device 101 undertakes the secondary computational work. Alternatively, server 102 undertakes the secondary computational work, while terminal device 101 undertakes the primary computational work. Or, terminal device 101 and server 102 collaborate on computation using a distributed computing architecture.

[0074] Optionally, the terminal device 101 can be any electronic device product capable of human-computer interaction with the user through one or more methods such as a keyboard, touchpad, remote control, voice interaction, or handwriting device. For example, the terminal device 101 can be a smartphone, tablet computer, laptop computer, desktop computer, smart speaker, smartwatch, PC (Personal Computer), mobile phone, PDA (Personal Digital Assistant), wearable device, PPC (Pocket PC), smart car system, smart TV, etc.

[0075] Terminal device 101 can refer to one of a plurality of terminal devices. This embodiment uses terminal device 101 as an example. Those skilled in the art will know that the number of terminal devices 101 can be more or less. For example, there may be only one terminal device 101, or there may be dozens or hundreds of terminal devices 101, or more. This application embodiment does not limit the number or type of terminal devices 101.

[0076] Server 102 can be a single server, a server cluster consisting of multiple servers, or any of the following: a cloud computing platform or a virtualization center. This embodiment of the application does not limit this. Server 102 communicates directly or indirectly with terminal device 101 via a wired or wireless network. Server 102 has data receiving, data processing, and data sending functions. Of course, server 102 may also have other functions, which are not limited in this embodiment of the application.

[0077] Those skilled in the art should understand that the terminal device 101 and server 102 described above are merely illustrative examples. Other existing or future terminal devices or servers that are applicable to this application should also be included within the scope of protection of this application, and are hereby incorporated by reference.

[0078] like Figure 2 As shown, Figure 2 This is a schematic diagram of a command issuing system provided in an embodiment of this application. The command issuing system includes an allocation module 10, a determination module 20, and a selection module 30. Exemplarily, the command issuing system can be a circuit inside a chip, and the allocation module 10 can be any of a sub-circuit, component, or transistor within that circuit. Similarly, the determination module 20 and the selection module 30 can both be any of a sub-circuit, component, or transistor.

[0079] Figure 2 In the structural diagrams of the embodiments below, black circles are used to identify input terminals, and white circles are used to identify output terminals. See also Figure 2The input terminal of the allocation module 10 is used to receive instructions. The source of the instructions is not limited here. For example, a module for processing scalar instructions can send instructions to the allocation module 10, or the renaming module mentioned below can also send instructions to the allocation module 10. The output terminal of the allocation module 10 is connected to the storage unit, and the allocation module 10 is used to store instructions into the storage unit. The input terminal of the determination module 20 is used to receive a wake-up signal. The source of the wake-up signal is not limited here. For example, the allocation module 10 can send a wake-up signal to the determination module 20, or the delay module mentioned below can also send a wake-up signal to the determination module 20. The output terminal of the determination module 20 is connected to the storage unit, and the determination module 20 is used to modify the information stored in the storage unit. The input terminal of the selection module 30 is connected to the storage unit, and the selection module 30 is used to read the instructions stored in the storage unit and send the instructions to the processor through its output terminal. The various modules involved in the instruction issuing system of this application embodiment are described in detail below.

[0080] The allocation module 10 is used to allocate a first instruction to a storage unit. The first instruction is used to instruct the execution of operations on multiple source operands. The storage unit is used to store the preparation status of each source operand. The preparation status indicates whether the corresponding source operand is ready.

[0081] A storage unit is a structure used to store data and can take many forms, such as a queue, a data pool, or an entry. An entry is a storage architecture used to store instruction-related information. For example, an entry stores the instruction type, indicating operations such as addition, subtraction, multiplication, division, comparison, and sorting. An entry also stores the source register number and the destination register number; the source register number indicates the source register containing the source operand, and the destination register number indicates the destination register containing the destination operand.

[0082] In this example, the storage unit can store the readiness status of the source operand. The storage format of the readiness status is related to the representation of the storage unit. Taking a table entry as an example, the table entry is used to store the first field of the source operand, which indicates whether the source operand is ready. In the following text, the "ready" field in the table entry is the first field. Optionally, the first field can be a first identifier, for example, the first field being 1, indicating that the source operand is ready; or the first field can be a second identifier, for example, the first field being 0, indicating that the source operand is not ready.

[0083] In practical applications, entries may also include other information. For example, an entry may also store a second field, which indicates whether the data in the register is a source operand or a destination operand. In the following text, the "valid" field in the entry refers to the second field. Optionally, the second field may be a third identifier; for example, a second field value of 1 indicates that the data in the register is a source operand. Alternatively, the second field may be a fourth identifier; for example, a second field value of 0 indicates that the data in the register is a destination operand.

[0084] like Figure 3 As shown, Figure 3 This is a schematic diagram of an entry provided in an embodiment of this application. "uop" represents the instruction type. "pvs0" represents the physical register number of a source operand, "ready0" represents whether the source operand is ready to complete, and "valid0" represents the source operand. "pvs1" represents the physical register number of another source operand, "ready1" represents whether the source operand is ready to complete, and "valid1" represents the source operand. "pvd" represents the physical register number of the destination operand, and "valid2" represents the destination operand. Optionally, both the source and destination operands are vectors; therefore, "pvs" represents the Physical Vector Source Register, and "pvd" represents the Physical Vector Destination Register.

[0085] In this embodiment, the allocation module 10 can obtain a first instruction and allocate it to a free entry in the table. After the first instruction is allocated to a free entry, the entry stores information about the first instruction. The first instruction is an arithmetic instruction used to instruct the execution of an operation on multiple source operands to obtain a destination operand; the type of operation is not limited here. For example, the first instruction could be: VSUB V7, V6, V5, which means V7 = V6 - V5.

[0086] The determination module 20 is used to determine the preparation status of any source operand when any source operand is stored in the first source register, indicating that the source operand has been prepared.

[0087] Taking a storage unit as an entry as an example, each source operand corresponds to a first field segment, and an entry includes multiple first field segments. When the allocation module 10 allocates the first instruction to an entry, the first field segment corresponding to each source operand in the entry indicates that the corresponding source operand is not yet ready. After any source operand is stored in the first source register, the determination module 20 modifies the first field segment corresponding to the source operand so that the first field segment indicates that the corresponding source operand is ready.

[0088] Select module 30 is used to send the first instruction from the memory unit to the processor when each preparation state indicates that the corresponding source operand is ready.

[0089] Continuing with the example of a storage unit being a table entry, the first instruction corresponds to multiple source operands, and each source operand corresponds to a first field. Only when each first field indicates that its corresponding source operand is ready, does the selection module 20 issue the first instruction from the table entry to the processor. After the first instruction is issued, the table entry is idle and can be used to store the next instruction. Because all source operands are ready when the first instruction is issued, the processor does not need to wait and can process the first instruction immediately, avoiding instruction bouncy and thus improving the processor's processing efficiency.

[0090] It is understandable that instruction issuing systems in related technologies issue instructions in the order they arrive, with earlier instructions issued first and later instructions issued later, which is sequential issuance. However, the embodiments of this application do not focus on the order of instructions, but only on whether the source operands of each instruction are ready. Therefore, there are cases where earlier instructions are issued later and later instructions are issued first, which is out-of-order issuance. Because the instruction issuing system of the embodiments of this application issues each instruction in an out-of-order manner, it decouples the write-after-read dependencies between instructions, allowing instructions to be executed immediately once issued, thus improving instruction execution efficiency.

[0091] For example, if instruction one is: VMUL V2, V1, V0, and instruction two is: VADD V4, V3, V2, then there is a write-after-read dependency between instruction one and instruction two. Assign instruction one to table entry 0 and instruction two to table entry 1, as follows: Figure 4 As shown in (1) of the table. In entry 0, "ready0=1" indicates that one source operand has been stored in register V0, and "ready1=1" indicates that another source operand has been stored in register V1. Since instruction one meets the issue conditions, instruction one can be issued. Since instruction one has not yet been processed, there is no destination operand in register V2. In entry 1, "ready0=0" indicates that one source operand has not been stored in register V2, and "ready1=1" indicates that another source operand has been stored in register V3. Since instruction two does not meet the issue conditions, instruction two cannot be issued.

[0092] After several time cycles, instruction one is processed. At this time, register V2 stores the destination operand of instruction one, and register V2 can be changed from "ready0 = 0" to "ready0 = 1". For example... Figure 4As shown in (2), since instruction one has already been issued, entry 0 does not store information about instruction one. In entry 1, "ready0=1" indicates that one source operand has been stored in register V2, and "ready1=1" indicates that another source operand has been stored in register V3. Since instruction two meets the issue conditions, instruction two can be issued. In addition, "validi=1" indicates that the data in the register is a source operand; "validi=0" indicates that the data in the register is a destination operand, and i takes the value 0, 1, or 2.

[0093] As described above, there is a write-after-read dependency between Instruction 1 and Instruction 2. If Instruction 1 and Instruction 2 are issued sequentially, the processor must wait for Instruction 1 to complete before executing Instruction 2, resulting in instruction bubbling during the execution of Instruction 2. However, in this embodiment, Instruction 1 and Instruction 2 are issued out of order. When Instruction 2 is issued, the source operand is already prepared, so the processor does not need to wait and can process Instruction 2 immediately, preventing instruction bubbling. Furthermore, since the source operand of Instruction 2 is already prepared, it is equivalent to having already processed the destination operand of Instruction 1, making Instruction 2 no longer dependent on Instruction 1, thus decoupling the write-after-read dependency between instructions.

[0094] In one possible implementation, such as Figure 5 As shown, the instruction issuing system in this embodiment of the application further includes a renaming module 40. The input terminal of the renaming module 40 is used to receive instructions; the source of the instructions is not limited here. For example, a module used to process scalar instructions can send instructions to the renaming module 40. The output terminal of the renaming module 40 is connected to the input terminal of the allocation module 10, and the renaming module 40 is used to transmit instructions to the allocation module 10.

[0095] The renaming module 40 is used to obtain the second instruction, modify the second instruction to obtain the first instruction, and transmit the first instruction to the allocation module 10.

[0096] The first instruction is used to instruct the destination operand to be stored in the first destination register, and the second instruction is used to instruct the destination operand to be stored in the second destination register. The destination operand is the result of the operation of multiple source operands. The first destination register does not contain any data before storing the destination operand, and the second destination register stores the data of other instructions except the second instruction.

[0097] In this embodiment, write-after-write dependencies or read-after-write dependencies may exist between instructions, and these two types of dependencies are pseudo-dependencies. The reason for pseudo-dependencies is that the processor includes a finite number of registers; for example, a vector processor includes 32 vector registers. Due to the limited number of registers, the compiler needs to reuse some registers. In one case, the compiler repeatedly writes data to a certain register, resulting in a write-after-write dependency. Based on this, by modifying the register where data is written using the renaming module 40, the write-after-write dependency between instructions can be decoupled. In another case, the compiler reads data into a certain register and then writes data back into that register, resulting in a read-after-write dependency. Based on this, by modifying the register where data is written using the renaming module 40, the read-after-write dependency between instructions can be decoupled.

[0098] For example, in Example 1, Instruction 1 is: VADD V2, V1, V0; Instruction 2 is: VSUB V2, V4, V3. Since both Instruction 1 and Instruction 2 write the destination operand to the destination register V2, there is a write-after-write dependency between them. If the destination register of Instruction 2 is changed from V2 to V5, so that Instruction 1 writes the destination operand to the destination register V2 and Instruction 2 writes the destination operand to the destination register V5, the write-after-write dependency can be decoupled.

[0099] For example, in Example 2, Instruction 1 is: VADD V2, V1, V0; Instruction 2 is: VSUB V0, V4, V3. Since Instruction 1 needs to read the source operand into source register V0, and Instruction 2 needs to write the destination operand into destination register V0, there is a read-after-write dependency between Instruction 1 and Instruction 2. If the destination register of Instruction 2 is changed from V0 to V5, so that Instruction 1 reads the source operand into source register V0, and Instruction 2 writes the destination operand into destination register V5, the read-after-write dependency can be decoupled.

[0100] In summary, the renaming module 40 obtains a second instruction. This second instruction instructs the operation on multiple source operands to obtain a destination operand. The second instruction also instructs the source register storing the source operands and the destination register storing the destination operand. For ease of description, the destination register of the second instruction is referred to as the second destination register. If the second destination register stores data from other instructions, the renaming module 40 obtains a first instruction by modifying the second instruction. The first instruction instructs the operation on multiple source operands to obtain a destination operand. The first instruction also instructs the source register storing the source operands and the destination register storing the destination operand. For ease of description, the destination register of the first instruction is referred to as the first destination register. In other words, by modifying the second instruction, the second destination register can be changed to a first destination register that does not store data.

[0101] For example, in Example 1 above, the destination register V2 of Instruction 2 stores the destination operand of Instruction 1. In this case, the renaming module 40 modifies Instruction 2 to change the destination register V2 to a destination register V5 that does not store data. Similarly, in Example 2 above, the destination register V0 of Instruction 2 stores the source operand of Instruction 1. In this case, the renaming module 40 modifies Instruction 2 to change the destination register V0 to a destination register V5 that does not store data.

[0102] By modifying the destination register of the instruction through the renaming module 40, write-after-write or read-after-write dependencies between instructions are decoupled, so that instructions can be issued independently without having to read before writing or write before writing, thereby reducing waiting time and improving instruction processing efficiency.

[0103] In practical applications, the renaming module 40 can acquire a modification signal, which indicates whether to modify the second instruction. If the second destination register already contains data, the modification signal indicates that the second instruction should be modified; if the second destination register does not contain data, the modification signal indicates that the second instruction should not be modified. The renaming module 40 modifies or does not modify the second instruction based on the modification signal. Alternatively, regardless of whether the second destination register already contains data, the renaming module 40 can directly modify the second instruction to ensure that the first destination register is definitely empty.

[0104] In an exemplary embodiment, the first source register, the first destination register, and the second destination register are all physical registers. The first source register corresponds to the first source number, the first destination register corresponds to the first destination number, and the second destination register corresponds to the second destination number. Figure 6 As shown, the renaming module 40 includes a writing unit 401 and a reading unit 402.

[0105] The write unit 401 is used to obtain a second instruction, which includes multiple second source numbers and a third destination number, and the multiple second source numbers and the third destination number correspond to different logic registers.

[0106] The write unit 401 is also used to obtain the first destination number and write the first destination number into the number mapping table. The number mapping table is used to store the number mapping relationship between logical registers and physical registers.

[0107] The reading unit 402 is used to determine the first source number corresponding to each second source number and the second destination number corresponding to the third destination number according to the second instruction and the number mapping table, modify the second destination number to the first destination number, and determine the first instruction based on each first source number and the first destination number.

[0108] The second instruction includes multiple second source numbers, which are the numbers of the logical registers corresponding to the source operands. The second instruction also includes a third destination number, which is the number of the logical register corresponding to the destination operand. For example, in the instruction VSUB V7, V6, V5, V7 is the third destination number, and V6 and V5 are two second source numbers.

[0109] After obtaining the second instruction, the write unit 401 can also obtain the first destination number. The first destination number is the number of the first destination register, which is a physical register that does not store data. The write unit 401 writes the first destination number into a number mapping table. The number mapping table stores the number mapping relationship between the second source number and the first source number (hereinafter referred to as the first relationship), and the number mapping relationship between the third destination number and the second destination number (hereinafter referred to as the second relationship). Based on the second relationship, the write unit 401 writes the first destination number into the number mapping table to establish the number mapping relationship between the third destination number and the first destination number (hereinafter referred to as the third relationship). The first source number is the number of the first source register, which is a physical register. The second destination number is the number of the second destination register, which is also a physical register.

[0110] In other words, the number mapping table originally stores the first relationship between the second source number lvs and the first source number pvs, and the second relationship between the third destination number lvd and the second destination number pvd2. The writing unit 401 can write the third relationship between the third destination number lvd and the first destination number pvd1 into the number mapping table.

[0111] Optionally, the number of number mapping relationships stored in the number mapping table is not less than the number of logical memory units. For example, assuming there are 32 logical registers, the number mapping table can store 32 number mapping relationships, which correspond to 32 logical registers and their corresponding physical registers. The number of physical registers is not less than the number of logical registers; for example, there are 64 physical registers.

[0112] The reading unit 402 can acquire a second instruction. The second instruction includes multiple second source numbers. The reading unit 402 can determine the corresponding first source number based on the number mapping table and each second source number; for example, based on the first relationship and the second source number lvs, the first source number pvs is determined. The second instruction also includes a third destination number. The reading unit 402 can determine the corresponding first destination number and second destination number based on the number mapping table and the third destination number; for example, based on the second relationship and the third destination number lvd, the second destination number pvd2 is determined, and based on the third relationship and the third destination number lvd, the first destination number pvd1 is determined. The reading unit 402 modifies the second destination number to the first destination number, thereby determining the first instruction. The first instruction includes each first source number and the first destination number.

[0113] Optionally, the first instruction also includes a second destination number, where the first destination number is the number of the physical register that actually stores the destination operand, and the second destination number is the number of the physical register that originally indicated the location of the destination operand. By modifying the second destination number to the first destination number, the physical register storing the destination operand is modified, thus changing the second destination register to the first destination register.

[0114] like Figure 6 As shown, the write unit 401 obtains the second instruction and the first destination number new_pvd, and writes the first destination number new_pvd into the number mapping table. The read unit 402 obtains the first source number corresponding to the second source number based on the second instruction and the number mapping table. The first source number includes pvs0, pvs1 to pvs n-1 The reading unit 402 can also obtain the second destination number old_pvd and the first destination number new_pvd corresponding to the third destination number based on the second instruction and the number mapping table, and modify the second destination number old_pvd to the first destination number new_pvd. Based on the first source numbers pvs0, pvs1 to pvs... n-1 The first instruction is determined by the first destination number new_pvd.

[0115] Optionally, the renaming module 40 also includes a pop-up unit 403. The pop-up unit 403 is used to select the first destination number that is at the top of the sorted sequence from the number queue and send the first destination number to the writing unit 401. The number queue is used to store the numbers of physical registers that do not contain data in sequence.

[0116] In this embodiment, a numbered queue is used to store the numbers of at least one free register, where a free register is a physical register that does not store data. The numbers in the numbered queue are ordered sequentially, and the ordering method is not limited here. For example, the free register number can be determined according to the time when the physical register released data.

[0117] The write unit 401 can send a pop signal to the pop unit 403, which indicates that a number should be popped from the number queue. Based on the pop signal, the pop unit 403 selects the number of the free register that is at the top of the number queue; this number is the first destination number. Then, the pop unit 403 sends the first destination number to the write unit 401. Optionally, after selecting the first destination number, the pop unit 403 can delete the first destination number from the number queue; each time a number is deleted, the order of all numbers in the number queue shifts forward by one position.

[0118] like Figure 6 As shown, assuming the first destination number "new_pvd" is at the beginning of the number queue, the pop unit 403 selects the first destination number "new_pvd" from the number queue and sends it to the write unit 401. Alternatively, the pop unit 403 can delete the first destination number "new_pvd" from the number queue and shift the order of the remaining numbers in the number queue one position forward.

[0119] By storing the numbers of free registers in a numbered queue, free registers are managed in an orderly manner, allowing for quick identification of available registers when needed. The orderly use of free registers is achieved by selecting the first or last number in the sorted sequence.

[0120] Optionally, such as Figure 6 As shown, the renaming module 40 also includes a push unit 404. The push unit 404 is used to obtain the number to be used and push the number to be used into the number queue after the last number. The number to be used is the number of the physical register to which the data is being released.

[0121] For each physical register, after the physical register releases its stored data, it becomes an idle register. At this time, the push unit 404 can obtain the number of the idle register, which is the number to be used. The push unit 404 pushes the number to be used into the number queue, sorted after the last number. Figure 6 As shown, the push unit 404 obtains the number to be used "wb_old_pvd" and pushes the number to be used "wb_old_pvd" to the end of the number queue.

[0122] By pushing the numbers of free registers into a number queue, timely management of free registers is achieved, allowing for quick identification of free registers when needed. Pushing the numbers to the end of the number queue eliminates the need to change the order of existing numbers; newly pushed numbers are simply placed after existing ones, reducing complexity.

[0123] In practical applications, the writing unit 401 acquires at least one second instruction. Assume that the writing unit 401 acquires an instruction packet containing multiple second instructions. This instruction packet may carry a target parameter, which indicates k third destination numbers that need to be modified, where k is a positive integer. The writing unit 401 sends a pop signal carrying k to the pop unit 403. The pop unit 403 selects the top k first destination numbers from the number queue based on the pop signal and sends these k first destination numbers to the writing unit 401. The writing unit 401 writes the k first destination numbers into a number mapping table. The reading unit 402 can acquire the instruction packet. For any second instruction, the reading unit 402 determines the first source number and the second destination number based on the second instruction and the number mapping table. If the second instruction includes a third destination number that needs to be modified, the reading unit 402 also determines the first destination number based on the second instruction and the number mapping table, modifies the second destination number to the first destination number, and obtains the first instruction. If the second instruction does not include a third destination number that needs to be modified, the reading unit 402 does not modify the second instruction.

[0124] Assuming the instruction packet includes n second source numbers, the read unit 402 can obtain n first source numbers. If the instruction packet includes m third destination numbers, the read unit 402 can obtain m second destination numbers and k first destination numbers, where the k first destination numbers can overwrite the k second destination numbers. Here, m, n, and k are all positive integers, and m is not less than k. The first and second destination numbers flow through the pipeline with the instructions. After the instruction is completed, the result is stored in the destination area, and the first and second destination registers can release data, becoming free registers. At this time, the push unit 404 pushes the numbers of the free registers into the number queue for use by subsequent instructions.

[0125] Optionally, the second instruction is a vector operation instruction, meaning the instruction issuing system in this embodiment is in a vector pipeline, which follows the scalar pipeline. Instructions in the vector pipeline will always be executed. Therefore, once the first destination number is popped from the number queue, it will definitely be used so that the write unit 401 writes the first destination number into the number mapping table. This eliminates the need for the system to perform a recovery operation on the number queue and number mapping table, which helps reduce chip area.

[0126] In one possible implementation, the storage unit is also used to store the first source number corresponding to each first source register.

[0127] Module 20 is also used to obtain the register number.

[0128] The determination module 20 is also used to determine, when a register number exists in each of the first source numbers, that the source operand has been stored in the first source register corresponding to the register number.

[0129] This application does not limit the method of obtaining the register number. One possible method is shown below. In this example, as... Figure 7 As shown, the command transmission system also includes a delay module 50. The input terminal of the delay module 50 is connected to the output terminal of the selection module 30, which transmits timing commands to the delay module 50. The output terminal of the delay module 50 is connected to the input terminal of the determination module 20, which transmits a wake-up signal to the determination module.

[0130] The delay module 50 is used to record the first elapsed time after the third instruction is issued, and the third instruction is used to indicate that any source operand is obtained through computation. The delay module 50 is also used to transmit the register number corresponding to any source operand to the determination module 20 if the first elapsed time is not less than a first threshold.

[0131] Before the selection module 30 issues the first instruction, it can also issue a third instruction. This third instruction instructs the execution of an operation on the source operand to obtain the destination operand. If the destination operand of the third instruction is any of the source operands of the first instruction, a write-after-read dependency exists between the third and first instructions. The processor must process the third instruction before processing the first instruction. Therefore, after the selection module 30 issues the third instruction, it sends a timing instruction to the delay module 50 to start timing; the timing duration is the first time.

[0132] The third instruction corresponds to a first threshold, which is not less than the time elapsed from the issuance of the third instruction to its completion. The method for determining the first threshold is not limited here. For example, based on human experience, if the time elapsed from the issuance of the third instruction to its completion is less than 15 clock cycles, then the first threshold is greater than or equal to 15 clock cycles. Alternatively, thresholds for multiple instruction types can be preset; for example, the threshold for single-cycle execution instructions is 0, the threshold for vector sorting (VSORT) instructions is 5 clock cycles, the threshold for vector multiplication (VMUL) instructions is 1 clock cycle, and so on. If the third instruction belongs to a certain instruction type, the threshold for that type of instruction is determined as the first threshold. If the first time is not less than the first threshold, the delay module 50 transmits the register number to the determination module 20. This number is the number of the destination register corresponding to the third instruction, used to actually store the destination operand.

[0133] Optionally, the delay module 50 generates a wake-up signal carrying a register number. The delay module 50 transmits the wake-up signal to the determination module 20 so that the determination module 20 can obtain the register number. Figure 4 As shown, the destination register corresponding to the instruction in entry 0 is the source register corresponding to the instruction in entry 1. After the instruction in entry 0 is sent, the wake-up signal carries the register number wakeup_idx, and wakeup_idx = V2. V2 is the number of the destination register in entry 0, and also the number of the source register in entry 1.

[0134] When the determination module 20 receives a wake-up signal, it compares the register number in the wake-up signal with the register numbers in the table entries. The register numbers in the table entries include the first source numbers. If the register number in the wake-up signal matches a certain first source number, the determination module 20 determines that the source operand has been stored in the first source register corresponding to the first source number. At this time, the determination module 20 adjusts the first field corresponding to the first source register so that the first field represents that the corresponding source operand is ready.

[0135] For example, the delay module 50 sends a wake-up signal valu_vstore_wakeup to the determination module 20. The wake-up signal valu_vstore_wakeup carries the register number wakeup_idx that needs to be woken up. After receiving the wake-up signal, the determination module 20 compares wakeup_idx with each first source number pvs in the table. If wakeup_idx is equal to a certain pvs, then the first field ready corresponding to this pvs is set to 1. Here, ready being 1 indicates that the source operand is ready.

[0136] As mentioned above, there is a write-after-read dependency between the third instruction and the first instruction. In this example, after the third instruction is issued, a first time interval elapses, and since this first time interval is not less than a first threshold, the third instruction has been processed, and the destination operand of the third instruction is obtained. This destination operand is the source operand of the first instruction, and at this point, the first instruction has not yet been issued. In this way, the write-after-read dependency between the third instruction and the first instruction is decoupled, so that the processing of the first instruction no longer depends on the third instruction. Afterwards, the selection module 30 issues the first instruction to the processor. Since the source operand of the first instruction is already prepared, the processor does not need to wait and can immediately process the first instruction, improving instruction processing efficiency.

[0137] In practical applications, there are other ways to generate wake-up signals. For example, the system itself requires a certain time threshold to store the source operand of the first instruction into the first source register; this time threshold is called the second threshold. Based on this, the allocation module 10 starts timing after allocating the first instruction to the table entry, or the system includes a timer that starts timing when the table entry receives the first instruction. When the timing is not less than the second threshold, a wake-up signal is generated and sent to the determination module 20. The wake-up signal carries a register number, which is the number of the first source register of the first instruction. The determination module 20 adjusts the first field based on the register number.

[0138] For example, the allocation module 10 or the timer sends a wake-up signal vload_wakeup to the determination module 20. The wake-up signal vload_wakeup carries the register number wakeup_idx. After receiving the wake-up signal, the determination module 20 compares wakeup_idx with each first source number pvs in the table. If wakeup_idx equals a certain pvs, then the first field ready corresponding to this pvs is set to 1. Here, ready being 1 indicates that the source operand is ready.

[0139] The determination module 20 compares the register number in the wake-up signal with the first source number in the table entry, and adjusts the first field segment corresponding to the first source number that passes the comparison to an identifier indicating that the corresponding source operand is ready. This achieves accurate wake-up of the first field segment, reduces the possibility of errors, and improves system performance. Based on this, the determination module 20 can be referred to as the wake-up module in the following text.

[0140] In practical applications, when the allocation module 10 allocates the first instruction to an entry in the pipeline, if there is no free entry, the allocation module 10 backpressures the pipeline to reduce the instruction flow rate, balance the instruction flow rate and issue rate, and improve system performance. Once the selection module 30 issues the first instruction, it will not be stalled in subsequent pipeline stages; instead, the processor will immediately process the first instruction, improving instruction processing efficiency. That is, in the vector pipeline, vector operation instructions will only generate backpressure at the allocation module 10.

[0141] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, data stored, data displayed, etc.) and signals involved in this application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant regions.

[0142] In the above system, the selection module only issues the first instruction to the processor when all source operands are ready. Since the source operands are already stored in the first source register when the processor receives the first instruction, the processor does not need to wait and can process the instruction immediately, resulting in higher processing efficiency and improved processor performance.

[0143] like Figure 8 As shown, Figure 8 This is a flowchart illustrating a command issuance method provided in an embodiment of this application. This command issuance method can be applied to... Figure 1 In the command issuance system shown, the command is executed by the terminal device or the server. For example... Figure 8 As shown, the instruction issuing method of this application embodiment includes the following steps.

[0144] In step 801, a first instruction is allocated to a storage unit. The first instruction is used to instruct the operation to be performed on multiple source operands. The storage unit is used to store the preparation status of each source operand. The preparation status indicates whether the corresponding source operand is ready.

[0145] In step 802, if any source operand is stored in the first source register, the preparation status of any source operand is determined to indicate that any source operand has been prepared.

[0146] In step 803, if each preparation state indicates that the corresponding source operand is ready, the first instruction in the memory cell is sent to the processor.

[0147] In one possible implementation, the method further includes: obtaining a second instruction and modifying the second instruction to obtain a first instruction;

[0148] The first instruction is used to instruct the destination operand to be stored in the first destination register, and the second instruction is used to instruct the destination operand to be stored in the second destination register. The destination operand is the result of the operation of multiple source operands. The first destination register does not contain any data before storing the destination operand, and the second destination register stores the data of other instructions except the second instruction.

[0149] In one possible implementation, the first source register, the first destination register, and the second destination register are all physical registers, with the first source register corresponding to the first source number, the first destination register corresponding to the first destination number, and the second destination register corresponding to the second destination number.

[0150] Modifying the second instruction to obtain the first instruction includes:

[0151] Obtain the second instruction, which includes multiple second source numbers and a third destination number, with the multiple second source numbers and the third destination number corresponding to different logic registers;

[0152] Obtain the first destination number and write it into the number mapping table. The number mapping table is used to store the number mapping relationship between logical registers and physical registers.

[0153] Based on the second instruction and the number mapping table, determine the first source number corresponding to each second source number and the second destination number corresponding to the third destination number, modify the second destination number to the first destination number, and determine the first instruction based on each first source number and the first destination number.

[0154] In one possible implementation, the method further includes: selecting the first destination number that is at the top of the sorted sequence from the numbering queue, which is used to store the numbers of physical registers that do not contain data in sequence.

[0155] In one possible implementation, the method further includes: obtaining the number to be used, pushing the number to be used into a number queue after the last number, wherein the number to be used is the number of the physical register from which the data is released.

[0156] In one possible implementation, the storage unit is further used to store the first source number corresponding to each first source register; the method further includes:

[0157] Get the register number;

[0158] If a register number exists in each of the first source numbers, it is determined that the source operand has been stored in the first source register corresponding to the register number.

[0159] In one possible implementation, the method also includes:

[0160] Record the first elapsed time after the third instruction is transmitted. The third instruction is used to indicate the operation to obtain any source operand.

[0161] If the value is not less than the first threshold at the first moment, obtain the register number corresponding to any source operand.

[0162] It should be understood that the above methods are executed by the command issuing system and belong to the same concept. For details of the specific implementation process, please refer to the description of the system embodiment, which will not be repeated here.

[0163] In the above method, the selection module only issues the first instruction to the processor when all source operands are ready. Since the source operands are already stored in the first source register when the processor receives the first instruction, the processor does not need to wait and can process the instruction immediately, resulting in higher processing efficiency and improved processor performance.

[0164] The above describes the instruction issuing system of this application from the perspective of modules and method steps. The system will now be described systematically and comprehensively. The instruction issuing system of this application can be applied to terminal devices or servers. The instructions issued by the system include vector operation instructions, scalar operation instructions, etc. Figure 9 As shown, the steps for the command transmission system to transmit commands include steps 901 to 907 as shown below.

[0165] In step 901, the renaming module obtains the second instruction, modifies the second instruction to obtain the first instruction, and sends the first instruction to the allocation module.

[0166] like Figure 10 The renaming module can send a first instruction to the allocation module. Optionally, the architecture of the renaming module is as follows: Figure 6 As shown, the implementation method of step 901 can be found in the description of the renaming module above, and will not be repeated here.

[0167] In step 902, the allocation module allocates the first instruction to an idle entry.

[0168] like Figure 10 As shown, the allocation module can determine a free entry from entries 0 to n-1. For example, if the free entry is entry 0, the allocation module will allocate the first instruction to entry 0. The first instruction includes first source numbers pvs0 to pvs2, and entry 0 stores each first source number. Each first source number corresponds to a first field segment ready and a second field segment valid. The first field segment ready indicates whether the source operand is stored in the first source register corresponding to the first source number, and the second field segment valid indicates that the data in the first source register corresponding to the first source number is the source operand. Entry 0 also stores the type uop of the first instruction. For example, the type uop of the first instruction is any one of vector addition operation VADD, vector subtraction operation VSUB, vector multiplication operation VMUL, or vector sorting operation VSORT. The implementation of step 902 can be found in the description of the allocation module above, and will not be repeated here.

[0169] Step 903: The wake-up module obtains the first wake-up signal, which is a signal generated after the source operand is loaded into the first source register.

[0170] like Figure 10 As shown, the wake-up module can receive the first wake-up signal. The implementation method of step 903 can be found in the description of the wake-up module above, and will not be repeated here.

[0171] Step 904: The wake-up module acquires the second wake-up signal, which is a signal generated by the delay module.

[0172] like Figure 10 As shown, the delay module can send a second wake-up signal to the wake-up module. The implementation of step 904 can be found in the description of the wake-up module above, and will not be repeated here.

[0173] Step 905: The wake-up module sets the first field corresponding to the register number in the table entry to the first identifier according to the register number carried by the wake-up signal.

[0174] like Figure 10 As shown, the wake-up module can receive a first wake-up signal, which includes a register number, such as the number of the first source register corresponding to the first instruction. The wake-up module can also receive a second wake-up signal, which also includes a register number, such as the number of the destination register corresponding to other instructions. The wake-up module compares the register number with the first source numbers pvs0 to pvs2 in entry 0. If a source number matches a register number, the corresponding first field segment is set to the first identifier, and the comparison process ends. For example, if the first source number pvs0 in entry 0 matches a register number, the first field segment ready0 in entry 0 is set to the first identifier. If the first source numbers pvs0 to pvs2 in entry 0 do not match a register number, the wake-up module continues the comparison process, comparing the register number with the first source numbers pvs0 to pvs2 in entry 1. This continues until a first source number matching a register number is found from entries 0 to n-1, and the corresponding first field segment is set to the first identifier. The first field segment is a first identifier indicating that the source operand has been stored in the first source register. The implementation of step 905 can be found in the description of the wake-up module above, and will not be repeated here.

[0175] In step 906, if each of the first field segments in the table entry is a first identifier, the selection module sends the first instruction in the table entry to the processor.

[0176] like Figure 10 As shown, the selection module can view entries 0 through n-1. If any entry, such as the first field segment ready0 through the first field segment ready2 in entry 0, is a first identifier, the selection module sends the first instruction from entry 0 to the processor. The implementation of step 906 can be found in the description of the selection module above, and will not be repeated here.

[0177] In step 907, the delay module records the time elapsed after the first command is transmitted. If the time reaches a threshold, a second wake-up signal is generated.

[0178] like Figure 10As shown, after the first instruction is transmitted, the delay module starts timing. If the time reaches a threshold, the delay module generates a second wake-up signal and sends it to the wake-up module. The second wake-up signal includes the number of the first destination register corresponding to the first instruction, which is used to actually store the destination operand. Upon receiving the second wake-up signal, the wake-up module executes subsequent steps based on the register number, which will not be elaborated further here. The implementation of step 907 can be found in the description of the delay module above, and will not be elaborated further here.

[0179] The instruction dispatch system of this application only dispatches instructions to the processor when all source operands of the instruction have been stored in the source register. This avoids processor waiting time, reduces instruction bubbling, and allows instructions to be executed by the processor immediately, thereby improving instruction processing efficiency and thus improving processor performance.

[0180] Figure 11 A structural block diagram of a terminal device 1100 provided in an exemplary embodiment of this application is shown. The terminal device 1100 includes a processor 1101 and a memory 1102. The processor 1101 is connected to an instruction issuing system, which is used to execute an instruction issuing method. The processor 1101 can receive and process instructions issued by the instruction issuing system.

[0181] Processor 1101 may include one or more processing cores, such as a quad-core processor, an octa-core processor, etc. Processor 1101 may be implemented using at least one hardware form selected from DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). Processor 1101 may also include a main processor and a coprocessor. The main processor, also known as a CPU (Central Processing Unit), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, processor 1101 may integrate a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content required to be displayed on the screen. In some embodiments, processor 1101 may also include an AI (Artificial Intelligence) processor, which is used to handle computational operations related to machine learning.

[0182] The memory 1102 may include one or more computer-readable storage media, which may be non-transitory. The memory 1102 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In some embodiments, the non-transitory computer-readable storage media in the memory 1102 are used to store at least one computer program, which is executed by the processor 1101 to implement the instruction issuance method provided in the method embodiments of this application.

[0183] In some embodiments, the terminal device 1100 may also optionally include: a peripheral device interface 1103 and at least one peripheral device. The processor 1101, memory 1102, and peripheral device interface 1103 can be connected via a bus or signal line. Each peripheral device can be connected to the peripheral device interface 1103 via a bus, signal line, or circuit board. Specifically, the peripheral device includes at least one of: a radio frequency circuit 1104, a display screen 1105, a camera assembly 1106, an audio circuit 1107, and a power supply 1108.

[0184] Peripheral device interface 1103 can be used to connect at least one I / O (Input / Output) related peripheral device to processor 1101 and memory 1102. In some embodiments, processor 1101, memory 1102 and peripheral device interface 1103 are integrated on the same chip or circuit board; in some other embodiments, any one or two of processor 1101, memory 1102 and peripheral device interface 1103 can be implemented on separate chips or circuit boards, which is not limited in this embodiment.

[0185] The radio frequency (RF) circuit 1104 is used to receive and transmit RF (Radio Frequency) signals, also known as electromagnetic signals. The RF circuit 1104 communicates with communication networks and other communication devices via electromagnetic signals. The RF circuit 1104 converts electrical signals into electromagnetic signals for transmission, or converts received electromagnetic signals back into electrical signals. Optionally, the RF circuit 1104 includes: an antenna system, an RF transceiver, one or more amplifiers, a tuner, an oscillator, a digital signal processor, a codec chipset, a user identity module card, etc. The RF circuit 1104 can communicate with other terminals via at least one wireless communication protocol. This wireless communication protocol includes, but is not limited to: the World Wide Web, metropolitan area networks, intranets, various generations of mobile communication networks (2G, 3G, 4G, and 5G), wireless local area networks, and / or WiFi (Wireless Fidelity) networks. In some embodiments, the RF circuit 1104 may also include circuitry related to NFC (Near Field Communication), which is not limited in this application.

[0186] Display screen 1105 is used to display a UI (User Interface). This UI may include graphics, text, icons, videos, and any combination thereof. When display screen 1105 is a touch display screen, it also has the ability to collect touch signals on or above its surface. These touch signals can be input as control signals to processor 1101 for processing. In this case, display screen 1105 can also be used to provide virtual buttons and / or a virtual keyboard, also known as soft buttons and / or a soft keyboard. In some embodiments, there may be one display screen 1105, disposed on the front panel of terminal device 1100; in other embodiments, there may be at least two display screens, disposed on different surfaces of terminal device 1100 or in a folded design; in still other embodiments, display screen 1105 may be a flexible display screen, disposed on a curved or folded surface of terminal device 1100. Furthermore, display screen 1105 may be configured as a non-rectangular, irregular shape, i.e., a non-rectangular screen. The display screen 1105 can be made of materials such as LCD (Liquid Crystal Display) and OLED (Organic Light-Emitting Diode).

[0187] The camera assembly 1106 is used to acquire images or videos. Optionally, the camera assembly 1106 includes a front-facing camera and a rear-facing camera. Typically, the front-facing camera is located on the front panel of the terminal, and the rear-facing camera is located on the back of the terminal. In some embodiments, there are at least two rear-facing cameras, which are any one of a main camera, a depth-sensing camera, a wide-angle camera, and a telephoto camera, to achieve background blurring by fusion of the main camera and the depth-sensing camera, panoramic shooting by fusion of the main camera and the wide-angle camera, VR (Virtual Reality) shooting, or other fusion shooting functions. In some embodiments, the camera assembly 1106 may also include a flash. The flash can be a single-color temperature flash or a dual-color temperature flash. A dual-color temperature flash refers to a combination of a warm-light flash and a cool-light flash, which can be used for light compensation at different color temperatures.

[0188] The audio circuit 1107 may include a microphone and a speaker. The microphone is used to collect sound waves from the user and the environment, converting the sound waves into electrical signals that are input to the processor 1101 for processing, or input to the radio frequency circuit 1104 for voice communication. For stereo sound acquisition or noise reduction purposes, multiple microphones may be used, each located at a different part of the terminal device 1100. The microphone may also be an array microphone or an omnidirectional microphone. The speaker is used to convert electrical signals from the processor 1101 or the radio frequency circuit 1104 into sound waves. The speaker may be a conventional diaphragm speaker or a piezoelectric ceramic speaker. When the speaker is a piezoelectric ceramic speaker, it can convert electrical signals not only into audible sound waves but also into inaudible sound waves for purposes such as distance measurement. In some embodiments, the audio circuit 1107 may also include a headphone jack.

[0189] Power supply 1108 is used to supply power to the various components in terminal device 1100. Power supply 1108 can be AC ​​power, DC power, a disposable battery, or a rechargeable battery. When power supply 1108 includes a rechargeable battery, the rechargeable battery can be a wired rechargeable battery or a wireless rechargeable battery. A wired rechargeable battery is a battery that is charged via a wired line, and a wireless rechargeable battery is a battery that is charged via a wireless coil. The rechargeable battery can also be used to support fast charging technology.

[0190] In some embodiments, the terminal device 1100 further includes one or more sensors 1109. The one or more sensors 1109 include, but are not limited to: an acceleration sensor 1111, a gyroscope sensor 1112, a pressure sensor 1113, an optical sensor 1114, and a proximity sensor 1115.

[0191] Accelerometer 1111 can detect the magnitude of acceleration along the three coordinate axes of a coordinate system established by terminal device 1100. For example, accelerometer 1111 can be used to detect the components of gravitational acceleration along the three coordinate axes. Processor 1101 can control display screen 1105 to display the user interface in either a landscape or portrait view based on the gravitational acceleration signal acquired by accelerometer 1111. Accelerometer 1111 can also be used for games or for acquiring user motion data.

[0192] The gyroscope sensor 1112 can detect the orientation and rotation angle of the terminal device 1100. The gyroscope sensor 1112 can work in conjunction with the accelerometer sensor 1111 to collect the user's 3D movements on the terminal device 1100. Based on the data collected by the gyroscope sensor 1112, the processor 1101 can perform the following functions: motion sensing (e.g., changing the UI based on the user's tilt), image stabilization during shooting, game control, and inertial navigation.

[0193] The pressure sensor 1113 can be disposed on the side bezel of the terminal device 1100 and / or on the lower layer of the display screen 1105. When the pressure sensor 1113 is disposed on the side bezel of the terminal device 1100, it can detect the user's grip signal on the terminal device 1100, and the processor 1101 can perform left / right hand recognition or quick operation based on the grip signal collected by the pressure sensor 1113. When the pressure sensor 1113 is disposed on the lower layer of the display screen 1105, the processor 1101 can control the operable controls on the UI interface based on the user's pressure operation on the display screen 1105. The operable controls include at least one of button controls, scroll bar controls, icon controls, and menu controls.

[0194] Optical sensor 1114 is used to collect ambient light intensity. In one embodiment, processor 1101 can control the display brightness of display screen 1105 based on the ambient light intensity collected by optical sensor 1114. Specifically, when the ambient light intensity is high, the display brightness of display screen 1105 is increased; when the ambient light intensity is low, the display brightness of display screen 1105 is decreased. In another embodiment, processor 1101 can also dynamically adjust the shooting parameters of camera assembly 1106 based on the ambient light intensity collected by optical sensor 1114.

[0195] The proximity sensor 1115, also known as a distance sensor, is typically located on the front panel of the terminal device 1100. The proximity sensor 1115 is used to detect the distance between the user and the front of the terminal device 1100. In one embodiment, when the proximity sensor 1115 detects that the distance between the user and the front of the terminal device 1100 is gradually decreasing, the processor 1101 controls the display screen 1105 to switch from a screen-on state to a screen-off state; when the proximity sensor 1115 detects that the distance between the user and the front of the terminal device 1100 is gradually increasing, the processor 1101 controls the display screen 1105 to switch from a screen-off state to a screen-on state.

[0196] Those skilled in the art will understand that Figure 11 The structure shown does not constitute a limitation on the terminal device 1100, and may include more or fewer components than shown, or combine certain components, or use different component arrangements.

[0197] Figure 12 This is a schematic diagram of the server structure provided in the embodiments of this application. The server 1200 can vary considerably due to different configurations or performance, and may include one or more processors 1201 and one or more memories 1202. The processor 1201 is connected to an instruction issuing system, which is used to execute instruction issuing methods. The processor 1201 can receive and process instructions issued by the instruction issuing system. The one or more memories 1202 store at least one computer program, which is loaded and executed by the one or more processors 1201 to implement the instruction issuing methods provided in the various method embodiments described above. For example, the processor 1201 is a CPU. Of course, the server 1200 may also have wired or wireless network interfaces, a keyboard, and input / output interfaces for input and output. The server 1200 may also include other components for implementing device functions, which will not be elaborated here. The terminal devices and servers mentioned above belong to electronic devices.

[0198] In an exemplary embodiment, a chip is provided, the chip including any of the above-described instruction issuing systems, the instruction issuing system being used to execute any of the above-described instruction issuing methods.

[0199] In an exemplary embodiment, a computer-readable storage medium is also provided, which stores at least one computer program that is loaded and executed by a processor to enable an electronic device to implement any of the above-described instruction issuing methods.

[0200] Optionally, the aforementioned computer-readable storage medium may be a read-only memory (ROM), a random access memory (RAM), a compact disc read-only memory (CD-ROM), magnetic tape, floppy disk, and optical data storage device, etc.

[0201] In an exemplary embodiment, a computer program is also provided, which is at least one such computer program, loaded and executed by a processor to enable an electronic device to implement any of the above-described instruction issuing methods.

[0202] In an exemplary embodiment, a computer program product is also provided, which stores at least one computer program that is loaded and executed by a processor to enable an electronic device to implement any of the above-described instruction issuing methods.

[0203] It should be understood that "multiple" as used in this article refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0204] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0205] The above description is merely an exemplary embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the principles of this application should be included within the protection scope of this application.

Claims

1. A command issuing system, characterized in that, The system includes an allocation module, a determination module, and a selection module; The allocation module is used to allocate a first instruction to a storage unit. The first instruction is used to instruct the execution of operations on multiple source operands. The storage unit is used to store the preparation status of each source operand. The preparation status indicates whether the corresponding source operand is ready. The determining module is used to determine the preparation state of any source operand, indicating that the source operand has been prepared, when any source operand is stored in the first source register. The selection module is used to send the first instruction from the memory unit to the processor when each preparation state indicates that the corresponding source operand is ready.

2. The system according to claim 1, characterized in that, The system also includes a renaming module; The renaming module is used to obtain a second instruction, modify the second instruction to obtain the first instruction, and transmit the first instruction to the allocation module; Wherein, the first instruction is used to instruct the destination operand to be stored in a first destination register, the second instruction is used to instruct the destination operand to be stored in a second destination register, the destination operand is the result of the operation of the plurality of source operands, the first destination register does not store data before storing the destination operand, and the second destination register stores data of other instructions besides the second instruction.

3. The system according to claim 2, characterized in that, The first source register, the first destination register, and the second destination register are all physical registers. The first source register corresponds to the first source number, the first destination register corresponds to the first destination number, and the second destination register corresponds to the second destination number. The renaming module includes a writing unit and a reading unit. The writing unit is used to acquire the second instruction, which includes multiple second source numbers and a third destination number, and the multiple second source numbers and the third destination number correspond to different logic registers. The writing unit is further configured to obtain the first destination number and write the first destination number into a number mapping table, wherein the number mapping table is used to store the number mapping relationship between the logical register and the physical register; The reading unit is configured to determine, according to the second instruction and the number mapping table, the first source number corresponding to each second source number and the second destination number corresponding to the third destination number, modify the second destination number to the first destination number, and determine the first instruction based on each first source number and the first destination number.

4. The system according to claim 3, characterized in that, The renaming module also includes a pop-up unit; The pop-up unit is used to select the first destination number that is at the top of the number queue and send the first destination number to the writing unit. The number queue is used to store the numbers of physical registers that do not contain data in sequence.

5. The system according to claim 3, characterized in that, The renaming module also includes a push-in unit; The push unit is used to obtain the number to be used and push the number to be used into the number queue after the last number. The number to be used is the number of the physical register to which the data is to be released.

6. The system according to any one of claims 1 to 5, characterized in that, The storage unit is also used to store the first source number corresponding to each first source register; The determining module is also used to obtain the register number; The determining module is further configured to determine, when the register number exists in each of the first source numbers, that the source operand has been stored in the first source register corresponding to the register number.

7. The system according to claim 6, characterized in that, The system also includes a delay module; The delay module is used to record the first elapsed time after the third instruction is transmitted, and the third instruction is used to instruct the calculation to obtain the arbitrary source operand; The delay module is further configured to transmit the register number corresponding to any one source operand to the determining module when the first time is not less than a first threshold.

8. A method for issuing commands, characterized in that, The method includes: The first instruction is assigned to the storage unit, which is used to instruct the operation to be performed on multiple source operands. The storage unit is used to store the preparation status of each source operand, and the preparation status indicates whether the corresponding source operand is ready. When any one source operand is stored in the first source register, determining the preparation state of the source operand indicates that the source operand has been prepared. When each preparation state indicates that the corresponding source operand is ready, the first instruction in the memory cell is sent to the processor.

9. A chip, characterized in that, The chip includes an instruction issuing system as described in any one of claims 1 to 7, the instruction issuing system being used to execute the instruction issuing method as described in claim 8.

10. An electronic device, characterized in that, The electronic device includes the chip as described in claim 9.

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