Column memory array structure, chip, image sensor and imaging equipment

Abstract

The invention provides a column memory array structure, a chip, an image sensor and imaging equipment. The column memory array structure comprises a column memory circuit array, a control logic circuit and at least one reading circuit which are electrically connected, the column storage circuit array comprises at least two column storage array sub-partitions, and the control logic circuit comprises at least one sub-control logic circuit. Each sub-control logic circuit corresponds to one or more column storage array sub-partitions, and the projection of the sub-control logic circuit on the plane where the column memory array structure is located is located in the region where the corresponding column storage array sub-partition is located; the projection of the reading circuit on the plane where the column memory array structure is located is located in the area where the column memory array structure is located. According to the invention, the area of the column memory array structure can be reduced, the power consumption can be obviously reduced, and the data reading time can be greatly reduced.

Description

Technical Field

[0001] This invention relates to the field of image processing technology, and in particular to a column memory array structure, chip, image sensor and imaging device. Background Technology

[0002] Please see Figure 1 , Figure 1 A schematic block diagram of a column memory array structure in related technologies is given. From Figure 1 As can be seen, the column memory array structure in the related technology mainly includes a column memory circuit array 101, a control logic circuit 102 disposed on the side of the column memory circuit array 101, and a readout circuit 103. The working principle of the column memory array structure in the related technology is roughly as follows: Under the control of the control logic circuit 102, the readout circuit 103 reads data from the column memory circuit array 101 column by column for subsequent processing by relevant modules (e.g., sending the read image data to an image processor for face recognition, object recognition, etc.).

[0003] It should be noted that the information disclosed in the background section of this invention is intended only to enhance the understanding of the general background of this invention, and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0004] The purpose of this invention is to provide a column memory array structure, chip, image sensor, and imaging device. This invention can not only reduce the area of ​​the column memory array structure and significantly reduce power consumption, but also greatly reduce the data readout time. Compared with the scheme in which the control logic circuit and readout circuit are located on the side of the column memory circuit array, the column memory array structure provided by this invention has higher performance.

[0005] To achieve the above objectives, the present invention provides the following technical solution: a column memory array structure, comprising an electrically connected column memory circuit array, a control logic circuit, and at least one readout circuit; the column memory circuit array includes at least two column memory array sub-partitions, the control logic circuit includes at least one sub-control logic circuit, each sub-control logic circuit corresponding to one or more column memory array sub-partitions, and the projection of the sub-control logic circuit on the plane of the column memory array structure lies within the region of the corresponding column memory array sub-partition; the projection of the readout circuit on the plane of the column memory array structure lies within the region of the column memory array structure.

[0006] Optionally, the sub-control logic circuit is arranged along the column direction of the column storage array sub-partition, and the readout circuit is arranged along the row direction of the column storage array sub-partition.

[0007] Optionally, the column storage circuit array includes a first column storage array sub-partition and a second column storage array sub-partition, the control logic circuit includes a first sub-control logic circuit and a second sub-control logic circuit, the first sub-control logic circuit corresponds to the first column storage array sub-partition, the second sub-control logic circuit corresponds to the second column storage array sub-partition, and the readout circuit is located between the first column storage array sub-partition and the second column storage array sub-partition.

[0008] Optionally, the first column storage array sub-partition and the second column storage array sub-partition have the same number of storage units.

[0009] Optionally, the column storage circuit array includes 2N column storage array sub-partitions, each column storage array sub-partition including one or more memory banks; the control logic circuit includes 2N sub-control logic circuits, the column memory array structure includes 2N read circuits, the sub-control logic circuits and the read circuits are all one-to-one with the column storage array sub-partitions, and the read circuits are adjacent to their corresponding column storage array sub-partitions, where N>1.

[0010] Optionally, along the column direction of the column storage circuit array, the readout circuit and the column storage array sub-partitions are symmetrically arranged about the centerline of the column storage circuit array.

[0011] Optionally, the sub-control logic circuit and the readout circuit are further configured to work together according to the received readout instruction to read out data from all the column storage array sub-partitions simultaneously.

[0012] To achieve the above objectives, the present invention also provides a chip on which the column memory array structure described in any of the preceding claims is integrated.

[0013] To achieve the above objectives, the present invention also provides an image sensor, which includes the column memory array structure described in any of the above claims or the chip described above.

[0014] To achieve the above objectives, the present invention also provides an imaging device, which includes the column memory array structure described in any of the above claims, or the chip described above, or the image sensor described above.

[0015] Compared with existing technologies, the column memory array structure, chip, image sensor, and imaging device provided by this invention have the following advantages: The column memory array structure provided by this invention, by adopting a design in which the control logic circuit includes at least one sub-control logic circuit, each sub-control logic circuit corresponds to one or more column memory array sub-partitions, and the projection of the sub-control logic circuit on the plane of the column memory array structure is located in the region of its corresponding column memory array sub-partition, and the projection of the readout circuit on the plane of the column memory array structure is located in the region of the column memory array structure (e.g., between the column memory array sub-partitions), can reduce the area of ​​the column memory array structure; on the other hand, it can also effectively reduce the load on the control lines, thereby significantly reducing power consumption and reducing the performance requirements of the driving devices, thus greatly reducing costs; furthermore, it also lays a good foundation for simultaneously reading data from each column memory array sub-partition, thereby greatly reducing the data readout time; compared with the scheme where the control logic circuit and readout circuit are located on the side of the column memory array, the column memory array structure provided by this invention has higher performance.

[0016] Since the chip, image sensor, and imaging device provided by this invention belong to the same inventive concept as the column memory array structure provided by this invention, the chip, image sensor, and imaging device provided by this invention have at least all the advantages of the column memory array structure provided by this invention. For details on the beneficial effects of the chip, image sensor, and imaging device provided by this invention, please refer to the above description of the beneficial effects of the column memory array structure provided by this invention, which will not be repeated here. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the circuit structure of a column memory array structure used in the prior art for column memory.

[0018] Figure 2 This is a block diagram of the column memory array structure provided in Embodiment 1 of the present invention.

[0019] Figure 3 This is a schematic diagram of the column memory array structure provided in the first embodiment of the present invention.

[0020] Figure 4 This is a schematic diagram of the column memory array structure provided in the second embodiment of the present invention.

[0021] The reference numerals in the attached figures are explained as follows:

[0022] Column storage circuit arrays - 101, 100; column storage array sub-partition - 110; first column storage array sub-partition - 111; second column storage array sub-partition - 112; control logic circuits - 102, 200; sub-control logic circuit - 210; first sub-control logic circuit - 211; second sub-control logic circuit - 212; readout circuits 103, 300. Detailed Implementation

[0023] The following detailed description, in conjunction with the accompanying drawings, further illustrates the column memory array structure, chip, image sensor, and imaging device proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use non-precise proportions, used only to facilitate and clearly illustrate the embodiments of this invention. Please refer to the drawings to make the objectives, features, and advantages of this invention more apparent and understandable. It should be understood that the structures, proportions, sizes, etc., depicted in the accompanying drawings are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed in the specification, and are not intended to limit the implementation conditions of this invention. Any modifications to the structure, changes in proportions, or adjustments to the size, provided that the effects and objectives achieved by this invention are the same or similar, should still fall within the scope of the technical content disclosed in this invention. Specific design features of the invention disclosed herein, including, for example, specific dimensions, orientations, positions, and shapes, will be determined in part by the specific application and usage environment. Furthermore, in the embodiments described below, the same reference numerals are sometimes used across different drawings to denote the same parts or parts with the same function, omitting repeated descriptions. In this specification, similar reference numerals and letters are used to denote similar items; therefore, once an item is defined in one figure, it need not be discussed further in subsequent figures. Furthermore, if the methods described herein involve a series of steps, and the order of these steps presented herein is not necessarily the only possible order in which they can be performed, some of the described steps may be omitted and / or other steps not described herein may be added to the method.

[0024] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. The singular forms "a," "an," and "the" include plural objects; the term "or" is generally used to include "and / or"; the term "several" is generally used to include "at least one"; the term "at least two" is generally used to include "two or more"; and the term "multiple" is generally used to include "at least two." Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. They may also include elements inherent to such a process, method, article, or apparatus.

[0025] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0026] It should be understood that when a component is referred to as "connected," "connected to," or "coupled to" other components, it may be directly connected to other components, or there may be intermediary components. Conversely, when a component is referred to as "directly connected" or "directly connected to" other components, there are no intermediary components.

[0027] The core idea of ​​this invention is to provide a column memory array structure, chip, image sensor and imaging device for column memory. This invention can not only reduce the area of ​​the column memory array structure and significantly reduce power consumption, but also greatly reduce the data readout time. Compared with the scheme in which the control logic circuit and readout circuit are located on the side of the column memory circuit array, the column memory array structure provided by this invention has higher performance.

[0028] It should be noted that the column memory array structure and chip provided by this invention can be applied to the image sensor and imaging device provided by this invention. The image sensor provided by this invention can be applied to the imaging device provided by this invention. It should be understood that the term "imaging device" or "imaging equipment" or other similar terms as used herein include general imaging devices, such as, but not limited to, cameras, camcorders, mobile phones, tablet computers, learning machines, and medical imaging devices with image sensors.

[0029] Example 1

[0030] To achieve the above-mentioned goals, this embodiment provides a column memory array structure for column memory. For an example, please refer to... Figure 2 , Figure 2 This is a block diagram illustrating the column memory array structure provided in this embodiment. Figure 2 As can be seen, the column memory array structure provided by the present invention includes an electrically connected column memory circuit array 100, a control logic circuit 200, and at least one readout circuit 300 (DATA IO); the column memory circuit array 100 includes at least two column memory array sub-partitions 110 (… Figure 2 Taking N column storage array sub-partitions 110 as an example (where N is an integer greater than 2), the control logic circuit 200 includes at least one sub-control logic circuit 210 (…). Figure 2 The example includes N column memory array sub-partitions 110 (where N is an integer greater than 2). Each of the sub-control logic circuits 210 corresponds to one or more of the column memory array sub-partitions 110, and the projection of the sub-control logic circuit 210 on the plane where the column memory array structure 100 is located is located within the region where the corresponding column memory array sub-partition 110 is located; the projection of the readout circuit 300 on the plane where the column memory array structure 100 is located is located within the region where the column memory array structure 100 is located.

[0031] Therefore, the column memory array structure provided by the present invention, by adopting a design in which the control logic circuit 200 includes at least one sub-control logic circuit 210, each sub-control logic circuit 210 corresponds to one or more column memory array sub-partitions 110, and the projection of the sub-control logic circuit 210 on the plane of the column memory array structure is located in the region of the corresponding column memory array sub-partition 110, and the projection of the readout circuit 300 on the plane of the column memory array structure is located in the region of the column memory array structure (e.g., between the column memory array sub-partitions 110), can reduce the area of ​​the column memory array structure on the one hand; on the other hand, it can also effectively reduce the load on the control lines, thereby significantly reducing power consumption and reducing the performance requirements of the driving devices, thereby greatly reducing costs; furthermore, it also lays a good foundation for simultaneously reading data from each column memory array sub-partition 110, thereby greatly reducing the data readout time; and the scheme of placing the control logic circuit and the readout circuit on the side of the column memory circuit array (see [reference]). Figure 1 Compared to other methods, the column memory array structure provided by this invention has higher performance.

[0032] It should be noted that the present invention does not limit the specific implementation of each of the sub-control logic circuits 210 corresponding to one or more column storage array sub-partitions 110. For example, in some embodiments, each of the sub-control logic circuits 210 corresponds to multiple column storage array sub-partitions 110, and the number of column storage array sub-partitions 110 corresponding to each of the sub-control logic circuits 210 may be the same or different; in other embodiments, some of the sub-control logic circuits 210 may correspond to one column storage array sub-partition 110, and other sub-control logic circuits 210 may correspond to multiple column storage array sub-partitions 110; in other embodiments, each of the sub-control logic circuits 210 may correspond to one column storage array sub-partition 110. For ease of understanding and explanation, this article uses the example of having multiple sub-control logic circuits 210 and a one-to-one correspondence between the sub-control logic circuits 210 and the column storage array sub-partitions 110 for description. Furthermore, the projection of the sub-control logic circuit 210 onto the plane where the column memory array structure 100 is located is situated within the region where the corresponding column memory array sub-partition 110 is located. This can be achieved as follows: for a sub-control logic circuit 210 corresponding to one column memory array sub-partition 110, its projection onto the plane where the column memory array structure 100 is located is situated within the region where the corresponding column memory array sub-partition 110 is located; for a sub-control logic circuit 210 corresponding to multiple column memory array sub-partitions 110, its projection onto the plane where the column memory array structure 100 is located is situated within the region formed by the multiple corresponding column memory array sub-partitions 110.

[0033] It should also be noted that the projection of the readout circuit 300 onto the plane of the column memory array structure 100 is located within the area of ​​the column memory array structure 100. This can be achieved by the readout circuit 300 being positioned between the column memory array sub-partitions 110 or by the readout circuit 300 being positioned on the side of the corresponding column memory array sub-partition 110. For example, when there are two column memory array sub-partitions 110 and only one readout circuit 300, the readout circuit 300 is located between the two column memory array sub-partitions 110 (for example, see the following...). Figure 3When there are two readout circuits 300: In some exemplary embodiments, the column memory array sub-partitions 110 and the readout circuits 300 may be spaced apart; in other embodiments, the readout circuits 300 are located on the outer side of the corresponding column memory array sub-partitions 110 (i.e., within the column memory array structure 100, along the column direction of the column memory array structure 100, two column memory array sub-partitions 110 are located in the middle, and two readout circuits 300 are located on both sides); in still other embodiments, the readout circuits 300 are located on the inner side of the corresponding column memory array sub-partitions 110 (i.e., within the column memory array structure 100, along the column direction of the column memory array structure 100, two column memory array sub-partitions 110 are located on both sides, and two readout circuits 300 are located in the middle).

[0034] It should be noted that although this article uses the application of the column memory array structure in an image sensor as an example, it is obvious that the present invention does not limit the application scenarios of the column memory array structure. For more detailed information, please refer to the relevant content on the application of the column memory array structure known to those skilled in the art.

[0035] Exemplary, in some exemplary embodiments, the sub-control logic circuit 210 and the readout circuit 300 are further configured to work together according to a received readout instruction to simultaneously read data from all the column memory array sub-partitions 110. This significantly reduces data readout time, thereby further improving the performance of the column memory array structure provided by the present invention.

[0036] It should be noted that the present invention does not impose excessive limitations on the specific content of the read instruction. For example, the read instruction may include, but is not limited to, the address of the data to be read in the column storage array sub-partition 110.

[0037] For example, please continue to see Figure 2 ,like Figure 2 As shown, in some exemplary embodiments, the sub-control logic circuit 210 is along the column direction of the column storage array sub-partition 110 ( Figure 2 The readout circuit 300 is positioned along the row direction of the column storage array sub-partition 110 (as shown in the left-right direction). Figure 2 The vertical direction shown is used for setting the sub-control logic circuit 210 along the column direction of the column storage array sub-partition 110 and the read circuit 300 along the row direction of the column storage array sub-partition 110. This not only reduces the area of ​​the column memory array structure, but also makes the layout more reasonable and easier to implement.

[0038] It should be noted that those skilled in the art should understand that the present invention does not limit the number of column storage array sub-partitions 110 and sub-control logic circuits 210, and the number of column storage array sub-partitions 110 and sub-control logic circuits 210 can be two, three or more. Furthermore, the present invention does not limit the number of banks in each column storage array sub-partition 110, and each column storage array sub-partition 110 may include one bank or multiple banks. For easier understanding and explanation of the present invention, this document uses the example of a column storage circuit array 100 having 2N banks, and the first embodiment described below uses the example of a column storage circuit array 100 having two column storage array sub-partitions 110, while the second embodiment described below uses the example of a column storage circuit array 100 having 2N column storage array sub-partitions 110, where N is an integer greater than 1.

[0039] <First Implementation Method>

[0040] For example, please see Figure 3 , Figure 3 This is a schematic diagram of the column memory array structure provided in the first embodiment of this invention. Figure 3 As shown, in some exemplary embodiments, the column storage circuit array 100 includes a first column storage array sub-partition 111 and a second column storage array sub-partition 112, the control logic circuit 200 includes a first sub-control logic circuit 211 and a second sub-control logic circuit 212, the first sub-control logic circuit 211 corresponds to the first column storage array sub-partition 111, the second sub-control logic circuit 212 corresponds to the second column storage array sub-partition 112, and the readout circuit 300 is located between the first column storage array sub-partition 111 and the second column storage array sub-partition 112.

[0041] Therefore, the column memory array structure provided by the present invention, by employing a design in which the column memory circuit array 100 includes a first column memory array sub-partition 111 and a second column memory array sub-partition 112, the control logic circuit 200 includes a first sub-control logic circuit 211 and a second sub-control logic circuit 212, and the readout circuit 300 is disposed between the first column memory array sub-partition 111 and the second column memory array sub-partition 112, compared with the scheme in which the control logic circuit and the readout circuit are disposed on the side of the column memory circuit array (see [reference]). Figure 1 Compared to the previous method, it not only reduces the data readout time to half, but also has a clear structure and is easy to implement.

[0042] In some exemplary embodiments, the first column memory array sub-partition 111 and the second column memory array sub-partition 112 have the same number of banks. Therefore, by adopting a design where the first column memory array sub-partition 111 and the second column memory array sub-partition 112 have the same number of banks, the first sub-control logic circuit 211 and the second sub-control logic circuit 212 can have the same structure, thereby facilitating the implementation of the first sub-control logic circuit 211 and the second sub-control logic circuit 212, and further improving the performance of the column memory array structure provided by the present invention. For example, as... Figure 3 As shown, in this embodiment, the number of banks in both the first column storage array sub-partition 111 and the second column storage array sub-partition 112 is N. It is understood that although this example uses the same number of banks in both sub-partitions 111 and 112, this is clearly not a limitation of the invention. The invention does not impose any limitation on the number of banks in both sub-partitions 111 and 112. In other embodiments, the number of banks in both sub-partitions 111 and 112 may also be different.

[0043] By comparison Figure 1 and Figure 3 It can be known that: Figure 1 The control logic circuit 102 and readout circuit 103 shown are arranged on the side of the column memory array 101, and the length of the load line on the control line is the entire column width of the column memory array 101. Figure 1 (Illustrated with blue dashed arrows marked "DATA"), while the column memory array structure provided in this embodiment, such as... Figure 3 As shown, the length of the load line on the control line is half the column width of the entire column memory array 100. Figure 3 The blue arrows ("DATA LEFT" and "DATA RIGHT") are used to illustrate this.

[0044] <Second Implementation Method>

[0045] The column memory array structure provided in this embodiment differs from that provided in the first embodiment in the number of column memory array sub-partitions 110, sub-control logic circuits 210, and readout circuits 300. To avoid redundancy, only the differences from the first embodiment will be described below. For parts not mentioned in this embodiment, please refer to the relevant descriptions of the first embodiment for an adaptive understanding. For example, please refer to... Figure 4 , Figure 4 This is a schematic diagram of the column memory array structure provided in the second embodiment of this invention. Figure 4 As shown, in some exemplary embodiments, the column storage circuit array 100 includes 2N column storage array sub-partitions 110, each column storage array sub-partition 110 including a bank; the control logic circuit 200 includes 2N sub-control logic circuits 210, and the readout circuit 300 includes 2N readout circuits 300. Each sub-control logic circuit 210 and each readout circuit 300 corresponds one-to-one with a column storage array sub-partition 110, and each readout circuit 300 is adjacent to its corresponding column storage array sub-partition 110. Therefore, by employing a design where each sub-control logic circuit 210 and each readout circuit 300 corresponds one-to-one with a column storage array sub-partition 110 and is adjacent to its corresponding column storage array sub-partition 110, the present invention can further reduce the load on the control lines, thereby further reducing power consumption, and further reducing data readout time. For example, a scheme where the control logic circuit and the readout circuit are located on the side of the column storage circuit array (see [reference]). Figure 1 Compared to the previous embodiment, the data readout time of the column memory array structure provided in this embodiment is reduced to 1 / 2N of the original.

[0046] For example, please continue to see Figure 4 ,like Figure 4 As shown, in some exemplary embodiments, along the column direction of the column storage circuit array 100 (exemplarily, Figure 4 The readout circuit 300 and the column storage array sub-partition 110 are both about the center line of the column storage circuit array 100 (in the left-right direction shown). Figure 4 (Used as a red dashed line for illustration) Symmetrical arrangement. Thus, by adopting a design in which the readout circuit 300 and the column storage array sub-partition 110 are symmetrically arranged about the centerline of the column storage circuit array 100 along the column direction of the column storage circuit array 100, not only can the performance of the column memory array structure provided by the present invention be further improved, but the layout is also more reasonable and easier to implement.

[0047] Specifically, such as Figure 4As shown, readout circuit 0 corresponds to column storage array sub-partition 0, readout circuit 1 corresponds to column storage array sub-partition 1, ..., readout circuit N-1 corresponds to column storage array sub-partition N-1, readout circuit N corresponds to column storage array sub-partition N, ..., readout circuit 2N-1 corresponds to column storage array sub-partition 2N-1; furthermore, along the column direction of the column storage circuit array 100, column storage array sub-partition 0 and column storage array sub-partition 2N-1 are symmetrical about the centerline of the column storage circuit array 100, and readout circuit 0 and... The readout circuit 2N-1 is symmetrical about the center line of the column storage circuit array 100; the column storage array sub-partition 1 and the column storage array sub-partition 2N-2 are symmetrical about the center line of the column storage circuit array 100; the readout circuit 1 and the readout circuit 2N-2 are symmetrical about the center line of the column storage circuit array 100; ..., the column storage array sub-partition N-1 and the column storage array sub-partition N are symmetrical about the center line of the column storage circuit array 100; and the readout circuit N-1 and the readout circuit N are symmetrical about the center line of the column storage circuit array 100.

[0048] It should be noted that, Figure 4 The arrangement shown, where the readout circuit 300 and the column storage array sub-partition 110 are symmetrically arranged about the centerline of the column storage circuit array 100 along the column direction, is merely an illustrative example of a preferred embodiment and not a limitation of the present invention. The present invention does not impose excessive limitations on the positional relationship between the readout circuit 300 and the column storage array sub-partition 110. Exemplarily, in other embodiments, the readout circuit 300 and the column storage array sub-partition 110 may not be symmetrically arranged about the centerline of the column storage circuit array 100 along the column direction, as long as the readout circuit 300 is adjacent to its corresponding column storage array sub-partition 110.

[0049] Example 2

[0050] This embodiment provides a chip on which a column memory array structure is integrated. The column memory array structure is any of the column memory array structures provided in any of the embodiments herein.

[0051] This invention does not limit the manufacturing process or application field of the chip. For example, the chip may be, but is not limited to, a 7nm chip, a 14nm chip, and a 28nm chip; the chip may be, but is not limited to, automotive chips, consumer electronics chips, and medical chips, etc.

[0052] Example 3

[0053] This embodiment provides an image sensor. In some exemplary embodiments, the image sensor includes a column memory array structure provided in any of the embodiments herein; in other exemplary embodiments, the image sensor includes a chip provided in the above embodiments.

[0054] Furthermore, the image sensor provided in this embodiment may further include an image processor. The image processor is used to extract and optimize image information from the data read from the column memory array structure (raw image data acquired by the image sensor (such as a CMOS or CCD sensor),) and output the image to an application for display, storage, or further processing. The optimization of image information includes, but is not limited to, noise reduction, other processing (e.g., white balance), mosaic rearrangement, and color adjustment. For more detailed information about image sensors, please refer to the relevant technical adaptations known to those skilled in the art; due to space limitations, these will not be elaborated upon herein.

[0055] Another embodiment of the present invention provides an imaging device. In some exemplary embodiments, the imaging device includes a column memory array structure provided in any of the embodiments herein; in other exemplary embodiments, the imaging device includes a chip provided in the above embodiments; and in still other exemplary embodiments, the imaging device includes an image sensor provided in the above embodiments.

[0056] More specifically, the imaging device provided in this embodiment, in addition to at least a processor, may further include a display component, a communication component, a sensor component, a power supply component, a multimedia component, and an input / output interface, depending on actual needs. The display component, column memory array structure, communication component, sensor component, power supply component, multimedia component, and input / output interface are all connected to the processor. The processor may be a central processing unit (CPU), a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a digital signal processing (DSP) chip, etc. Other communication components, sensor components, power supply components, multimedia components, etc., can be implemented using general-purpose components; due to space limitations, they will not be described in detail here. For more detailed information, please refer to the relevant technical adaptation understanding known to those skilled in the art.

[0057] Since the chip, image sensor, and imaging device provided by this invention belong to the same inventive concept as the column memory array structure provided by this invention, the chip, image sensor, and imaging device provided by this invention have at least all the advantages of the column memory array structure provided by this invention. For details on the beneficial effects of the chip, image sensor, and imaging device provided by this invention, please refer to the above description of the beneficial effects of the column memory array structure provided by this invention, which will not be repeated here.

[0058] Compared with existing technologies, the column memory array structure, chip, image sensor, and imaging device provided by this invention have the following advantages: The column memory array structure provided by this invention, by adopting a design in which the control logic circuit includes at least one sub-control logic circuit, each sub-control logic circuit corresponds to one or more column memory array sub-partitions, and the projection of the sub-control logic circuit on the plane of the column memory array structure is located in the region of its corresponding column memory array sub-partition, and the projection of the readout circuit on the plane of the column memory array structure is located in the region of the column memory array structure (e.g., between the column memory array sub-partitions), can reduce the area of ​​the column memory array structure; on the other hand, it can also effectively reduce the load on the control lines, thereby significantly reducing power consumption and reducing the performance requirements of the driving devices, thus greatly reducing costs; furthermore, it also lays a good foundation for simultaneously reading data from each column memory array sub-partition, thereby greatly reducing the data readout time; compared with the scheme where the control logic circuit and readout circuit are located on the side of the column memory array, the column memory array structure provided by this invention has higher performance.

[0059] It should be noted that the apparatus and methods disclosed in the embodiments herein can also be implemented in other ways. The apparatus embodiments described above are merely illustrative; for example, the flowcharts and block diagrams in the accompanying drawings show the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments herein. In this regard, each block in a flowchart or block diagram may represent a module, program, or part of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system to perform the specified function or action, or can be implemented using a combination of dedicated hardware and computer instructions.

[0060] In addition, the functional modules in the various embodiments of this article can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0061] The above description is merely a description of preferred embodiments of the column memory array structure, chip, image sensor, and imaging device provided by the present invention, and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure are within the protection scope of the present invention. Obviously, those skilled in the art can make various modifications and variations to the present invention without departing from the spirit and scope of the present invention. Therefore, if these modifications and variations fall within the scope of the present invention and its equivalents, the present invention also intends to include these modifications and variations.

Claims

1. A columnar memory array structure, characterized in that, The column memory array structure includes an electrically connected column memory circuit array, a control logic circuit, and at least one readout circuit; the column memory circuit array includes at least two column memory array sub-partitions, the control logic circuit includes at least one sub-control logic circuit, each sub-control logic circuit corresponds to one or more column memory array sub-partitions, and the projection of the sub-control logic circuit on the plane where the column memory array structure is located is located within the region of the column memory array sub-partition corresponding to it; the projection of the readout circuit on the plane where the column memory array structure is located is located within the region of the column memory array structure.

2. The column memory array structure according to claim 1, characterized in that, The sub-control logic circuit is arranged along the column direction of the column storage array sub-partition, and the readout circuit is arranged along the row direction of the column storage array sub-partition.

3. The column memory array structure according to claim 1, characterized in that, The column storage circuit array includes a first column storage array sub-partition and a second column storage array sub-partition. The control logic circuit includes a first sub-control logic circuit and a second sub-control logic circuit. The first sub-control logic circuit corresponds to the first column storage array sub-partition, and the second sub-control logic circuit corresponds to the second column storage array sub-partition. The readout circuit is located between the first column storage array sub-partition and the second column storage array sub-partition.

4. The column memory array structure according to claim 3, characterized in that, The first column storage array sub-partition and the second column storage array sub-partition have the same number of storage units.

5. The column memory array structure according to claim 1, characterized in that, The column storage circuit array includes 2N column storage array sub-partitions, each column storage array sub-partition including one or more memory cells; the control logic circuit includes 2N sub-control logic circuits, the column memory array structure includes 2N readout circuits, the sub-control logic circuits and the readout circuits are all one-to-one with the column storage array sub-partitions, and the readout circuits are adjacent to their corresponding column storage array sub-partitions, N>1.

6. The column memory array structure according to claim 5, characterized in that, Along the column direction of the column storage circuit array, the readout circuit and the column storage array sub-partitions are symmetrically arranged about the centerline of the column storage circuit array.

7. The column memory array structure according to any one of claims 1 to 6, characterized in that, The sub-control logic circuit and the readout circuit are further configured to work together according to the received readout instruction to read out the data in all the column storage array sub-partitions simultaneously.

8. A chip, characterized in that, It integrates a column memory array structure as described in any one of claims 1 to 7.

9. An image sensor, characterized in that, Includes the column memory array structure as described in any one of claims 1 to 7 or the chip as described in claim 8.

10. An imaging device, characterized in that, Includes the column memory array structure as described in any one of claims 1 to 7, or the chip as described in claim 9.

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