High-slew-rate operational amplifier
By combining a medium-gain amplification main circuit, a differential input voltage determination circuit, and a self-biased current mirror circuit, the problems of static power consumption and increased area of the high-voltage slew rate operational amplifier are solved, thereby achieving an increase in slew rate and a reduction in power consumption.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BEIJING MXTRONICS CORP
- Filing Date
- 2025-12-26
- Publication Date
- 2026-05-01
AI Technical Summary
Existing high-voltage slew rate operational amplifiers suffer from increased static power consumption and large area complexity.
The circuit employs a medium-gain amplifier main circuit, a differential input voltage determination circuit, and a self-biased current mirror circuit. The current output by the differential input voltage determination circuit is mirrored and injected into the medium-gain amplifier main circuit by the self-biased current mirror circuit, thereby increasing the slew rate and avoiding the generation of additional current when the input signal difference is small.
It effectively improves the slew rate of the operational amplifier, reduces power consumption, and lowers the area and complexity, making it suitable for working scenarios with different input signal voltage differences.
Smart Images
Figure CN121966477A_ABST
Abstract
Description
A high-voltage slew rate operational amplifier Technical Field
[0001] This invention belongs to the field of analog integrated circuit design technology, and particularly relates to a high-voltage slew rate operational amplifier. Background Technology
[0002] Operational amplifiers are widely used in various integrated circuits due to their high amplification factor. The slew rate of an operational amplifier refers to the average rate at which the amplifier's output voltage changes over time when the input is a step signal; slew rate is an important performance indicator for operational amplifiers.
[0003] The current of an operational amplifier (op-amp) has a significant impact on its slew rate. Current technologies often employ an additional comparator to determine the existence of an input differential voltage difference, controlling the current mirror bias voltage to inject additional current into the op-amp to improve its slew rate. The main problems with this method are: it requires the power supply voltage to continuously provide quiescent current to the comparator, resulting in additional power consumption; and the op-amp input can have two states—the voltage at the positive input terminal is greater than or less than the voltage at the negative input terminal—requiring two comparators, significantly increasing the op-amp's area and complexity. Summary of the Invention
[0004] The technical problem solved by this invention is to overcome the shortcomings of the prior art and provide a high-voltage slew rate operational amplifier, which aims to solve the problems of increased static power consumption, significantly increased area and complexity of traditional high-voltage slew rate operational amplifiers.
[0005] To address the aforementioned technical problems, this invention discloses a high-voltage slew rate operational amplifier, comprising: a medium-gain amplification main circuit for performing common-source cascode gain amplification on input signals VP and VM, and outputting gain-amplified output signals OUT and OUTN; wherein, input signals VP and VM are a pair of differential input signals; and output signals OUT and OUTN are a pair of differential output signals; a differential input voltage determination circuit for comparing the voltage difference between input signals VP and VM with the sum of the threshold voltages of NMOS and PMOS transistors, and outputting a current; and a self-biased current mirror circuit for self-biasing the current output by the differential input voltage determination circuit, mirroring and replicating the current output, and injecting additional current into the medium-gain amplification main circuit.
[0006] In the aforementioned high-slew rate operational amplifier, the medium-gain amplification main circuit includes: NMOS transistors Mn1, Mn2, Mn3, Mn4, and Mn5, PMOS transistors Mp1, Mp2, Mp3, and Mp4, and a common-mode feedback circuit. Specifically, the gate of NMOS transistor Mn1 is connected to the input signal VP, and its drain is connected to the source of NMOS transistor Mn3; the gate of NMOS transistor Mn2 is connected to the input signal VM, and its drain is connected to the source of NMOS transistor Mn4; the sources of NMOS transistors Mn1 and Mn2 are simultaneously connected to the drain of NMOS transistor Mn5; the gates of NMOS transistors Mn3 and Mn4 are simultaneously connected to the common-gate bias voltage Vn2; and the drain of NMOS transistor Mn3... The drain of PMOS transistor Mp3 is connected to the output signal OUTN; the drain of NMOS transistor Mn4 and the drain of PMOS transistor Mp4 are connected to the output signal OUT; the source of PMOS transistor Mp1 is connected to the power supply voltage, and its drain is connected to the source of PMOS transistor Mp3; the source of PMOS transistor Mp2 is connected to the power supply voltage, and its drain is connected to the source of PMOS transistor Mp4; the gates of PMOS transistors Mp1 and Mp2 are connected to the common-source bias voltage Vp1; the gates of PMOS transistors Mp3 and Mp4 are connected to the common-gate bias voltage Vp2; the input of the common-mode feedback circuit is connected to the output signals OUT and OUTN; the current source bias voltage Vn1 output by the common-mode feedback circuit is connected to the gate of NMOS transistor Mn5, and the source of NMOS transistor Mn5 is grounded.
[0007] In the aforementioned high-slew rate operational amplifier, the differential input voltage determination circuit includes: NMOS transistors Mn6, Mn7, Mp5, and Mp6; wherein, the gate of NMOS transistor Mn6 is connected to the input signal VP, its source is connected to the source of PMOS transistor Mp5, and its drain is connected to the drain of PMOS transistor Mp7; the gate of PMOS transistor Mp5 is connected to the input signal VM, and its drain is grounded; the gate of NMOS transistor Mn7 is connected to the input signal VM, its source is connected to the source of PMOS transistor Mp6, and its drain is connected to the drain of PMOS transistor Mp7; the gate of PMOS transistor Mp6 is connected to the input signal VP, and its drain is grounded.
[0008] In the aforementioned high-slew rate operational amplifier, when the voltage difference between the input signals VP and VM is not less than the sum of the threshold voltages of the NMOS and PMOS transistors, the differential input voltage determination circuit outputs current, and the current flows into the input terminal of the self-biased current mirror circuit; when the voltage difference between the input signals VP and VM is less than the sum of the threshold voltages of the NMOS and PMOS transistors, the differential input voltage determination circuit does not output current, and no current flows into the input terminal of the self-biased current mirror circuit.
[0009] In the aforementioned high-voltage slew rate operational amplifier, the self-biased current mirror circuit includes: PMOS transistors Mp7, Mp8, and Mp9; wherein, the source of PMOS transistor Mp7 is connected to the power supply voltage, the gate is connected to the self-biased voltage Vcon, and the drain is connected to the drain of NMOS transistors Mn6 and Mn7 respectively; the source of PMOS transistor Mp8 is connected to the power supply voltage, the gate is connected to the self-biased voltage Vcon, and the drain is connected to the output signal OUT; the source of PMOS transistor Mp9 is connected to the power supply voltage, the gate is connected to the self-biased voltage Vcon, and the drain is connected to the output signal OUTN.
[0010] In the aforementioned high-slew rate operational amplifier, when current flows into the input terminal of the self-biased current mirror circuit, PMOS transistor Mp7 self-biases according to the magnitude of the current flowing in, generating a self-biased voltage Vcon. By adjusting PMOS transistors Mp8 and Mp9 through the self-biased voltage Vcon, the mirrored current output is injected into the medium-gain amplifier main circuit to increase the slew rate of the operational amplifier. When no current flows into the input terminal of the self-biased current mirror circuit, the self-biased voltage Vcon remains at a high level, and the self-biased current mirror circuit has no current output to the medium-gain amplifier main circuit. The slew rate of the operational amplifier remains unchanged and no additional static power consumption is generated.
[0011] The present invention has the following advantages: (1) The present invention discloses a high slew rate operational amplifier. When the input signal difference is large, an additional current is injected into the operational amplifier, which effectively improves the slew rate of the operational amplifier. When the input signal difference is small, the original slew rate of the operational amplifier meets the output voltage requirements of the operational amplifier and no additional current is generated, ensuring that the operational amplifier is more targeted to various working scenarios with different input signal voltage differences.
[0012] (2) This invention discloses a high-voltage slew rate operational amplifier, which uses a PMOS transistor and an NMOS transistor connected to the source to form a differential input voltage determination circuit. This differential input voltage determination circuit does not generate current when the operational amplifier has no input voltage or the input differential voltage is small, thus reducing power consumption. Compared with using two comparators as the determination circuit, the increased operational amplifier area and complexity are greatly reduced. Attached Figure Description
[0013] Figure 1 is a circuit diagram of a high-voltage slew rate operational amplifier according to an embodiment of the present invention; Figure 2 is a schematic diagram of the output signal OUT when both input signals VP and VM are connected to a fixed DC level according to an embodiment of the present invention; Figure 3 is a schematic diagram of the output signal OUT when input signal VM is connected to a fixed DC level, input signal VP is connected to a fixed DC level and a pulse voltage with a height of 1V according to an embodiment of the present invention; Figure 4 is a schematic diagram of the current at the power supply voltage of a conventional operational amplifier and the current at the power supply voltage of the high-voltage slew rate operational amplifier according to an embodiment of the present invention before and after the operational amplifier is input with a 1V pulse differential signal. Detailed Implementation
[0014] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments disclosed in the present invention will be described in further detail below with reference to the accompanying drawings.
[0015] One of the core ideas of this invention is to propose a high-slew rate operational amplifier, which uses a source-connected PMOS and NMOS transistors to form a differential input voltage determination circuit to determine the input voltage difference when the positive input voltage is greater than the negative input voltage and when the positive input voltage is less than the negative input voltage. When the input voltage difference is small, no current is generated, and the self-biased current mirror circuit does not inject current into the medium-gain amplification main circuit, thus generating no additional static power consumption. When the input voltage difference is large, current is generated, and the self-biased current mirror circuit injects current into the medium-gain amplification main circuit, thereby increasing the slew rate of the operational amplifier.
[0016] Referring to Figure 1, in this embodiment, the high-voltage slew rate operational amplifier includes: a medium-gain amplification main circuit, used for common-source cascode gain amplification of input signals VP and VM, and output gain amplification output signals OUT and OUTN; wherein, input signals VP (differential positive input signal) and VM (differential negative input signal) are a pair of differential input signals; and output signals OUT (positive output signal) and OUTN (negative output signal) are a pair of differential output signals.
[0017] The differential input voltage determination circuit is used to compare the voltage difference between the input signals VP and VM with the sum of the threshold voltages of the NMOS and PMOS transistors, and output the current.
[0018] The self-biased current mirror circuit is used to self-bias the current output by the differential input voltage determination circuit, and to mirror and replicate the current output to inject additional current into the medium gain amplifier main circuit.
[0019] In this embodiment, the medium-gain amplifier main circuit mainly includes: NMOS transistors Mn1, Mn2, Mn3, Mn4, and Mn5, PMOS transistors Mp1, Mp2, Mp3, and Mp4, and a common-mode feedback circuit. Specifically, the gate of NMOS transistor Mn1 is connected to the input signal VP, and its drain is connected to the source of NMOS transistor Mn3; the gate of NMOS transistor Mn2 is connected to the input signal VM, and its drain is connected to the source of NMOS transistor Mn4; the sources of NMOS transistors Mn1 and Mn2 are simultaneously connected to the drain of NMOS transistor Mn5; the gates of NMOS transistors Mn3 and Mn4 are simultaneously connected to the common-gate bias voltage Vn2; the drains of NMOS transistors Mn3 and Mp3 are simultaneously connected to the output signal OUTN; and the drains of NMOS transistors Mn4 and Mp4 are simultaneously connected to the output signal OUT. The source of PMOS transistor Mp1 is connected to the power supply voltage, and its drain is connected to the source of PMOS transistor Mp3; the source of PMOS transistor Mp2 is connected to the power supply voltage, and its drain is connected to the source of PMOS transistor Mp4; the gates of PMOS transistors Mp1 and Mp2 are simultaneously connected to the common-source bias voltage Vp1; the gates of PMOS transistors Mp3 and Mp4 are connected to the common-gate bias voltage Vp2; the input of the common-mode feedback circuit is connected to the output signals OUT and OUTN; the current source bias voltage Vn1 output by the common-mode feedback circuit is connected to the gate of NMOS transistor Mn5, and the source of NMOS transistor Mn5 is grounded.
[0020] Input signals VP and VM are connected to NMOS transistor Mn1 and PMOS transistor Mn2 respectively for common-source cascode gain amplification, and output gain amplified output signals OUT and OUTN.
[0021] The amplification structure and current source structure of the medium-gain amplifier main circuit both adopt a common-source, common-gate structure. On the one hand, this can significantly increase the output impedance of the operational amplifier, thereby increasing the operational amplifier gain. On the other hand, the common-source, common-gate current source structure can enhance the power supply rejection ratio of the operational amplifier, reducing its sensitivity to power supply noise. Operational amplifiers lack an inherent mechanism to control the common-mode level. Factors such as transistor offset, process variations, and temperature drift can cause the output common-mode level to shift, even leading to the common-mode level approaching the power supply and ground, resulting in signal distortion or saturation. In this invention, the output signals OUT and OUTN are connected to a common-mode feedback circuit. The common-mode feedback circuit detects the output common-mode level and stabilizes it at a specified value by adjusting the current source bias voltage Vn1.
[0022] In this embodiment, the differential input voltage determination circuit mainly includes: NMOS transistors Mn6, Mn7, Mp5, and Mp6. Specifically, the gate of NMOS transistor Mn6 is connected to the input signal VP, its source is connected to the source of PMOS transistor Mp5, and its drain is connected to the drain of PMOS transistor Mp7; the gate of PMOS transistor Mp5 is connected to the input signal VM, and its drain is grounded; the gate of NMOS transistor Mn7 is connected to the input signal VM, its source is connected to the source of PMOS transistor Mp6, and its drain is connected to the drain of PMOS transistor Mp7; the gate of PMOS transistor Mp6 is connected to the input signal VP, and its drain is grounded. NMOS transistors Mn6, Mn7, Mp5, and Mp6 are low-threshold transistors.
[0023] When the voltage difference between input signal VP and input signal VM is not less than the sum of the threshold voltages of the NMOS transistor and the PMOS transistor: 1) When V P >V M And V P -V M When Vthp ≥ Vthn, PMOS transistor Mp5 and NMOS transistor Mn6 conduct and generate current, and V P -V M The larger the voltage, the greater the current generated. PMOS transistor Mp6 and NMOS transistor Mn7 are turned off and do not generate current; the differential input voltage determination circuit outputs current, and the current flows into the input terminal of the self-biased current mirror circuit; 2) When V M >V P And V M -V P When Vthp ≥ Vthn, PMOS transistor Mp6 and NMOS transistor Mn7 conduct and generate current, and V M -V P The larger the voltage, the greater the current generated. PMOS transistor Mp5 and NMOS transistor Mn6 are turned off and do not generate current; the differential input voltage determination circuit outputs current, which flows into the input terminal of the bias current mirror circuit. Where V... P V represents the input signal voltage VP. M This represents the input signal VM voltage, V thp V represents the sum of the threshold voltages of PMOS transistors Mp5 and Mp6. thn This represents the sum of the threshold voltages of NMOS transistors Mn6 and Mn7.
[0024] When the voltage difference between input signal VP and input signal VM is less than the sum of the threshold voltages of the NMOS transistor and the PMOS transistor, i.e. |V P -V M | <V thp +V thnWhen PMOS transistors Mp5 and Mn6 are turned off and do not generate current, PMOS transistors Mp6 and Mn7 are turned off and do not generate current, the differential input voltage determination circuit does not output current, and no current flows into the input terminal of the self-biased current mirror circuit.
[0025] In this embodiment, the self-biased current mirror circuit mainly includes: PMOS transistors Mp7, Mp8, and Mp9. Specifically, the source of PMOS transistor Mp7 is connected to the power supply voltage, its gate is connected to the self-biased voltage Vcon, and its drain is connected to the drains of NMOS transistors Mn6 and Mn7, respectively. The source of PMOS transistor Mp8 is connected to the power supply voltage, its gate is connected to the self-biased voltage Vcon, and its drain is connected to the output signal OUT. The source of PMOS transistor Mp9 is connected to the power supply voltage, its gate is connected to the self-biased voltage Vcon, and its drain is connected to the output signal OUTN.
[0026] When current flows into the input of the self-biased current mirror circuit, PMOS transistor Mp7 generates a self-biased voltage Vcon based on the magnitude of the current. By adjusting PMOS transistors Mp8 and Mp9 through the self-biased voltage Vcon, the mirrored current output is injected into the medium-gain amplifier main circuit to improve the slew rate of the operational amplifier.
[0027] When no current flows into the input of the self-biased current mirror circuit, the self-biased voltage Vcon remains high, and PMOS transistors Mp7, Mp8, and Mp9 remain off, generating no current. The self-biased current mirror circuit has no current output to the medium-gain amplifier main circuit, the slew rate of the operational amplifier remains unchanged, and no additional static power consumption is generated.
[0028] In this embodiment, when both input signals VP and VM are connected to a fixed DC level, the curve of the output signal OUT is shown in Figure 2. Taking two points on the rising segment of the curve and calculating the slope, the slew rate of the operational amplifier is 72.67 MV / s. When input signal VM is connected to a fixed DC level and input signal VP is connected to a fixed DC level and a pulse voltage with a height of 1V, the curve of the output signal OUT is shown in Figure 3. Taking two points on the rising segment of the curve and calculating the slope, the slew rate of the operational amplifier is 170.76 MV / s. It can be seen that the slew rate of the operational amplifier is significantly improved.
[0029] In this embodiment, as shown in Figure 4, the input signal VP is a DC level 1.5V pulse input signal that rises 1V in 5μs. The A_VDD1 curve represents the current at the power supply voltage of a conventional operational amplifier without an input voltage difference determination circuit and a self-biased current mirror, while the A_VDD2 curve represents the current at the power supply voltage of the high-voltage slew rate operational amplifier described in this invention. As shown in Figure 4, when the operational amplifier has no large input differential signal, the current at the power supply voltage of the high-voltage slew rate operational amplifier described in this invention is the same as that of the conventional operational amplifier without an input voltage difference determination circuit and a self-biased current mirror, and no additional static power consumption is generated. When the operational amplifier receives a large differential signal at 5μs, the differential input voltage determination circuit generates current and injects additional current into the medium-gain amplification main circuit through the self-biased current mirror circuit. At this time, the current at the power supply voltage of the high-voltage slew rate operational amplifier described in this invention is greater than that of the conventional operational amplifier without an input voltage difference determination circuit and a self-biased current mirror, resulting in additional power consumption.
[0030] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.
[0031] The contents not described in detail in this specification are common knowledge to those skilled in the art.
Claims
1. A high-voltage slew rate operational amplifier, characterized in that, include: The medium-gain amplifier main circuit is used to perform common-source cascode gain amplification on the input signals VP and VM, and output amplified gain output signals OUT and OUTN. VP and VM are a pair of differential input signals; OUT and OUTN are a pair of differential output signals. A differential input voltage determination circuit is used to compare the voltage difference between VP and VM with the sum of the threshold voltages of the NMOS and PMOS transistors, and output current. A self-biased current mirror circuit is used to self-bias the current output from the differential input voltage determination circuit, mirroring and replicating the current output to inject additional current into the medium-gain amplifier main circuit.
2. The high-slew rate operational amplifier according to claim 1, characterized in that, The medium-gain amplifier main circuit includes: NMOS transistors Mn1, Mn2, Mn3, Mn4, and Mn5, PMOS transistors Mp1, Mp2, Mp3, and Mp4, and a common-mode feedback circuit. Specifically, the gate of NMOS transistor Mn1 is connected to the input signal VP, and its drain is connected to the source of NMOS transistor Mn3; the gate of NMOS transistor Mn2 is connected to the input signal VM, and its drain is connected to the source of NMOS transistor Mn4; the sources of NMOS transistors Mn1 and Mn2 are simultaneously connected to the drain of NMOS transistor Mn5; the gates of NMOS transistors Mn3 and Mn4 are simultaneously connected to the common-gate bias voltage Vn2; and the drain of NMOS transistor Mn3 is connected to the common-gate bias voltage Vn2. The drain of p3 is simultaneously connected to the output signal OUTN; the drains of NMOS transistor Mn4 and PMOS transistor Mp4 are simultaneously connected to the output signal OUT; the source of PMOS transistor Mp1 is connected to the power supply voltage, and its drain is connected to the source of PMOS transistor Mp3; the source of PMOS transistor Mp2 is connected to the power supply voltage, and its drain is connected to the source of PMOS transistor Mp4; the gates of PMOS transistors Mp1 and Mp2 are simultaneously connected to the common-source bias voltage Vp1; the gates of PMOS transistors Mp3 and Mp4 are connected to the common-gate bias voltage Vp2; the input of the common-mode feedback circuit is connected to the output signals OUT and OUTN; the current source bias voltage Vn1 output by the common-mode feedback circuit is connected to the gate of NMOS transistor Mn5, and the source of NMOS transistor Mn5 is grounded.
3. The high-voltage slew rate operational amplifier according to claim 1, characterized in that, The differential input voltage determination circuit includes: NMOS transistors Mn6, Mn7, Mp5, and Mp6; wherein, the gate of NMOS transistor Mn6 is connected to the input signal VP, its source is connected to the source of PMOS transistor Mp5, and its drain is connected to the drain of PMOS transistor Mp7; the gate of PMOS transistor Mp5 is connected to the input signal VM, and its drain is grounded; the gate of NMOS transistor Mn7 is connected to the input signal VM, its source is connected to the source of PMOS transistor Mp6, and its drain is connected to the drain of PMOS transistor Mp7; the gate of PMOS transistor Mp6 is connected to the input signal VP, and its drain is grounded.
4. The high-slew rate operational amplifier according to claim 3, characterized in that, When the voltage difference between input signals VP and VM is not less than the sum of the threshold voltages of the NMOS and PMOS transistors, the differential input voltage determination circuit outputs current, and the current flows into the input terminal of the self-biased current mirror circuit; when the voltage difference between input signals VP and VM is less than the sum of the threshold voltages of the NMOS and PMOS transistors, the differential input voltage determination circuit does not output current, and no current flows into the input terminal of the self-biased current mirror circuit.
5. The high-voltage slew rate operational amplifier according to claim 1, characterized in that, The self-biased current mirror circuit includes: PMOS transistors Mp7, Mp8, and Mp9; wherein, the source of PMOS transistor Mp7 is connected to the power supply voltage, the gate is connected to the self-biased voltage Vcon, and the drain is connected to the drain of NMOS transistors Mn6 and Mn7 respectively; the source of PMOS transistor Mp8 is connected to the power supply voltage, the gate is connected to the self-biased voltage Vcon, and the drain is connected to the output signal OUT; the source of PMOS transistor Mp9 is connected to the power supply voltage, the gate is connected to the self-biased voltage Vcon, and the drain is connected to the output signal OUTN.
6. The high-slew rate operational amplifier according to claim 5, characterized in that, When current flows into the input of the self-biased current mirror circuit, PMOS transistor Mp7 self-biases according to the magnitude of the current, generating a self-biased voltage Vcon. By adjusting PMOS transistors Mp8 and Mp9 through the self-biased voltage Vcon, the mirrored current output is injected into the medium-gain amplifier main circuit to improve the slew rate of the operational amplifier. When no current flows into the input of the self-biased current mirror circuit, the self-biased voltage Vcon remains high, and the self-biased current mirror circuit has no current output to the medium-gain amplifier main circuit. The slew rate of the operational amplifier remains unchanged and no additional static power consumption is generated.