Display device, electronic device, and method of manufacturing the display device

Abstract

The invention relates to a display device, an electronic device, and a method of manufacturing the display device. The display device may include a display extending at least partially in a first direction and a second direction crossing the first direction; a window on the display in a third direction crossing the first direction and the second direction; a connection circuit board connected to the display at a first side of the display; a main circuit board on a rear surface of the display in a fourth direction opposite to the third direction and connected to the connection circuit board; and a cover portion overlapping the connection circuit board and the main circuit board, in which a first side of the cover portion is in contact with a lower surface of the window in the fourth direction.

Description

Display device, electronic device, and method of manufacturing the display device

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2024-0150557, filed with the Korean Intellectual Property Office on October 30, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Some embodiments of this disclosure relate to a display device, an electronic device, and a method of manufacturing the display device. More specifically, some embodiments of this disclosure relate to a display device, an electronic device, and a method of manufacturing the display device with improved reliability. Background Technology

[0003] Display devices that provide images to users, such as televisions, monitors, smartphones, and tablet computers, may include display panels that display images. Various display panels, such as liquid crystal display panels, organic light-emitting display panels, electrowetting display panels, and electrophoretic display panels, are being developed.

[0004] The circuit board can be connected to the display panel via pads. As an example, the pads of the circuit board, the pads of the display panel, and the pads of the interconnecting circuit boards may need to be fully and completely connected to ensure that control signals and image signals are transmitted to the display panel without distortion.

[0005] The information disclosed in this background section is technical information that was known or derived by the inventor before or during the implementation of embodiments of this application, or acquired during the implementation of embodiments. Therefore, the information disclosed in this background section may include information that does not constitute prior art known to the public. Summary of the Invention

[0006] According to some embodiments of the present disclosure, a display device and an electronic device including the display device can be provided, wherein the driver chip of the display device can be protected from the influence of external static electricity. According to some embodiments of the present disclosure, a method for manufacturing the display device can be provided.

[0007] According to some embodiments of this disclosure, a display device may be provided and includes: a display extending at least partially in a first direction and a second direction intersecting the first direction; a window on the display in a third direction intersecting the first and second directions; a connecting circuit board connected to the display on a first side of the display; a main circuit board on a rear surface of the display in a fourth direction opposite to the third direction and connected to the connecting circuit board; and a cover portion overlapping the connecting circuit board and the main circuit board, wherein the first side of the cover portion contacts the lower surface of the window in the fourth direction.

[0008] According to some embodiments of this disclosure, an electronic device may be provided and includes: a housing; an electronic module within the housing; and a display device overlapping the electronic module, the display device including: a display extending at least partially in a first direction and a second direction intersecting the first direction; a window on the display in a third direction intersecting the first and second directions; a connecting circuit board electrically connected to the display on a first side of the display; a main circuit board on a rear surface of the display in a fourth direction opposite to the third direction and connected to the connecting circuit board; and a cover portion overlapping the connecting circuit board and the main circuit board, wherein a first side of the cover portion contacts the lower surface of the window in the fourth direction.

[0009] According to some embodiments of this disclosure, a method of manufacturing a display device may be provided and includes: connecting a display and a main circuit board to a connecting circuit board, wherein the display extends at least partially in a first direction and a second direction intersecting the first direction, the main circuit board is on a rear surface of the display, and the connection includes: connecting the connecting circuit board and the display on one side of the display; and bending the connecting circuit board, wherein the bent connecting circuit board connects the display to the main circuit board; the method may further include: placing a window upward on the display in a third direction intersecting the first and second directions; and placing a cover portion such that the cover portion overlaps with the connecting circuit board and the main circuit board.

[0010] According to some embodiments of this disclosure, the display device may include a cover portion that contacts the lower surface of the window and the lower surface of a cover plate beneath the display module to cover the driver chip. The cover portion can protect the driver chip from external static electricity. Therefore, the reliability of the display device can be improved.

[0011] According to some embodiments of this disclosure, a method for manufacturing a display device can be provided, which may include: after performing a process for forming a window, forming a cover portion that can be attached to the lower surface of the window and the lower surface of a cover plate. In this case, even if defects are detected in the cover portion, it becomes easier to separate the cover portion from the window and the cover plate, and it also becomes easier to reattach the cover portion to the window and the cover plate. Accordingly, the manufacturing yield of the display device can be improved. Attached Figure Description

[0012] Figure 1 is a combined perspective view of an electronic device according to an embodiment of the present disclosure.

[0013] Figure 2 is an exploded perspective view of an electronic device according to an embodiment of the present disclosure.

[0014] Figure 3 is a cross-sectional view of a display module according to an embodiment of the present disclosure.

[0015] Figure 4 is a plan view of a display panel according to an embodiment of the present disclosure.

[0016] Figure 5 is a plan view of an input sensing unit according to an embodiment of the present disclosure.

[0017] Figure 6 is a cross-sectional view of a display module according to an embodiment of the present disclosure.

[0018] Figure 7A is a cross-sectional view of a display device according to an embodiment of the present disclosure.

[0019] Figure 7B is a cross-sectional view of a display device according to an embodiment of the present disclosure.

[0020] Figure 8 is a cross-sectional view of a display device according to an embodiment of the present disclosure.

[0021] Figures 9A to 9E are process diagrams of a method for manufacturing a display device according to an embodiment of the present disclosure. Detailed Implementation

[0022] The embodiments of this disclosure can be modified in various ways and implemented in many different forms, and therefore, non-limiting exemplary embodiments will be described in detail below and illustrated in the accompanying drawings. However, the embodiments of this disclosure are not limited to the specific exemplary embodiments. All modifications, equivalents, and / or substitutions to the embodiments of this disclosure are included within the spirit and scope of this disclosure.

[0023] In this disclosure, it will be understood that when an element (or region, layer or portion) is referred to as being “on”, “connected to” or “linked to” another element or layer, the element may be directly on, directly connected to or directly linked to the other element or layer, or there may be intervening elements or layers.

[0024] The same reference numerals refer to the same elements throughout the drawings. In order to effectively describe the technical content, the thickness, scale, and dimensions of parts may be exaggerated in the drawings.

[0025] As used herein, the term “and / or” includes any and all combinations of one or more of the listed items.

[0026] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements are not limited by these terms. These terms are used only to distinguish one element from another. Thus, the first element discussed below may be referred to as the second element without departing from the teachings of this disclosure. As used herein, the singular forms “a” and “the (described)” are intended to also include the plural forms, unless the context clearly indicates otherwise.

[0027] For ease of description, spatial relative terms such as “below,” “under,” “down,” “above,” and “up” are used herein to describe the relationship of one element or feature relative to another element or feature as shown in the accompanying drawings.

[0028] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms such as those defined in common dictionaries shall be understood to have meanings consistent with their meanings in the context of the relevant field and shall not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0029] It will be further understood that, when used in this specification, the term "comprising" (or "including") indicates the presence of the stated features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or groups thereof.

[0030] As used herein, the phrase “at least one of…” following a list of elements modifies the entire list of elements and does not modify any individual element in the list. For example, the phrase “at least one of a, b, and c” should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c. It should be understood that the term “substantially” used herein with respect to thickness, width, material composition, percentage, range, orientation, etc., is intended to mean approximately or approximate, rather than precisely. For example, the terms “about” or “substantially” as used herein indicate that a small margin of error may exist, such as less than 1% of the stated amount.

[0031] In the following description, non-limiting exemplary embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0032] Figure 1 is an assembled perspective view of an electronic device according to an embodiment of the present disclosure. Figure 2 is an exploded perspective view of an electronic device according to an embodiment of the present disclosure.

[0033] Referring to Figures 1 and 2, the electronic device ED can display an image IM and sense external input TC in response to the activation of an electrical signal. As examples, the electronic device ED may include devices such as monitors, mobile phones, tablet computers, navigation units, gaming units, etc. However, these are merely examples, and the electronic device ED is not limited to any particular device. As a non-limiting example, a mobile phone will be described as an electronic device ED.

[0034] When viewed in a plane, the electronic device ED can have a rectangular shape having a long side extending in a first direction DR1 and a short side extending in a second direction DR2 intersecting the first direction DR1. However, the planar shape of the electronic device ED is not limited to a rectangular shape, and the electronic device ED can have various planar shapes such as circular shapes, other polygonal shapes, etc.

[0035] In this embodiment, the third direction DR3 may be substantially perpendicular to the plane defined by the first direction DR1 and the second direction DR2. The front (or upper) surface and the rear (or lower) surface of each component of the electronic device ED may be opposite to each other on the third direction DR3, and the normal direction of each of the front and rear surfaces may be substantially parallel to the third direction DR3. The spacing between the front and rear surfaces on the third direction DR3 may correspond to the thickness on the third direction DR3 (e.g., the thickness of the electronic device ED).

[0036] In this disclosure, the phrase "when viewed in a plane" can mean the state observed in a third direction DR3. In this disclosure, the phrase "when viewed in a cross section" can mean the state observed in a first direction DR1 or a second direction DR2. The directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 can be related to each other, and therefore, the directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 can be changed to other directions.

[0037] Electronic devices (EDs) can be rigid or flexible. As used herein, the term "flexible" refers to the property of being able to be bent, and flexible EDs can include all structures from those that are fully bendable to those that are bent at a scale of a few nanometers. For example, in the case of a flexible ED, it can be a bent electronic device, a rollable electronic device, or a foldable electronic device.

[0038] The electronic device ED can display an image IM via a display surface FS that is substantially parallel to a plane defined by a first direction DR1 and a second direction DR2. The image IM can include still images as well as videos. Figure 1 shows a clock widget and an application icon as representative examples of image IMs.

[0039] The display surface FS of the electronic device ED may consist only of a plane, or may further include a curved surface bent from at least one side of the plane. The display surface FS may be the front surface of the electronic device ED, or it may be the front surface of the window WM. In the following, the display surface FS may refer to both the front surface of the electronic device ED and the front surface of the window WM.

[0040] The electronic device ED can sense external input TC applied from outside the electronic device ED. External input TC can include various forms of input such as force, pressure, temperature, light, etc. In this embodiment, touch input generated by the user's hand and applied to the electronic device ED is described as an example of external input TC. However, this is only an example, and external input TC can include input from pen contact or proximity input (such as hover) applied when close to the electronic device ED.

[0041] An electronic device ED can sense user input via a display surface FS defined in the front surface of the electronic device ED, and can respond to the sensed user input. However, the area in which an external input TC is sensed by the electronic device ED is not limited to the front surface of the electronic device ED, and can vary depending on the embodiment. As an example, the electronic device ED can sense user input applied to the side surface or rear surface of the electronic device ED.

[0042] An electronic device ED may include a display device DD, an electronic module ELM, a power module PSM (e.g., a power supply), and a housing HAU. The display device DD may include a window WM, an optical layer RPL, a display module DM (e.g., a display), a cover plate CP, and a cover portion COP. The window WM may be coupled to the housing HAU to form the appearance of the electronic device ED.

[0043] The window WM can be set on the display module DM. The window WM can cover the display module DM and protect the display module DM from external impacts and scratches.

[0044] The window WM may include an optically transparent insulating material. As an example, the window WM may include glass or synthetic resin as a base film (or optically transparent substrate). The window WM may have a single-layer or multi-layer structure. As an example, a multi-layer window WM may include synthetic resin films attached to each other with an adhesive, or may include a glass film and a synthetic resin film attached to the glass film with an adhesive. The window WM may further include functional layers disposed on the optically transparent substrate, such as an anti-fingerprint layer, a phase control layer, a hard coating, etc.

[0045] The front surface FS of the window WM can be the display surface FS of the electronic device ED. The front surface FS of the window WM can include the transmissive area TA and the border area BZA.

[0046] The transmissive region TA can be an optically transparent region. The transmissive region TA can transmit the image IM provided from the display module DM. In this embodiment, the transmissive region TA is shown as having a quadrilateral shape. However, the transmissive region TA can have various shapes depending on the embodiment.

[0047] The border area BZA can be an area with a lower light transmittance than the transmissive area TA. The border area BZA can be an area printed with a material of a selected color. The border area BZA can block light and prevent components of the display module DM that can be positioned to overlap with the border area BZA from being observed from the outside.

[0048] The border region BZA may be adjacent to the transmission region TA, and the shape of the transmission region TA may be defined by the border region BZA. As an example, the border region BZA may be located outside the transmission region TA and may surround the transmission region TA. However, the border region BZA is not limited to this or is not subject to this limitation. The border region BZA may be adjacent only to one side of the transmission region TA, or it may be located on the side surface of the electronic device ED rather than the front surface of the electronic device ED. Furthermore, the border region BZA may be omitted.

[0049] As shown in the figure (e.g., Figure 2), an optical layer RPL can be disposed between the display module DM and the window WM. The optical layer RPL can reduce the reflectivity of the electronic device ED relative to external light. The optical layer RPL may include a retarder and / or a polarizer. The optical layer RPL may include at least a polarizing film. In this case, the optical layer RPL can be attached to the window WM by an adhesive. However, this is only an example. As an example, the optical layer RPL may include a color filter.

[0050] The display module DM can be positioned between the window WM and the housing HAU. The display module DM can display the image IM and sense external input TC. The image IM can be displayed through the front surface IS of the display module DM. The front surface IS of the display module DM can include an active area AA and a peripheral area NAA.

[0051] The effective area AA can be activated in response to an electrical signal. As an example, an image IM can be displayed through the effective area AA, and an external input TC can be sensed within the effective area AA. The effective area AA can overlap with at least a portion of the transmission area TA. Accordingly, a user can observe the image IM through the transmission area TA or provide the external input TC through the transmission area TA. However, this is merely an example, and the areas for displaying the image IM and sensing the external input TC are not specifically limited. For example, within the effective area AA, the areas for displaying the image IM and sensing the external input TC can be separated from each other.

[0052] The peripheral region NAA may be adjacent to the active region AA. For example, the peripheral region NAA may surround the active region AA. The drive circuit or drive line used to drive the active region AA may be arranged in the peripheral region NAA. The peripheral region NAA may overlap with at least a portion of the border region BZA, and the border region BZA may be used to prevent the components that may be arranged in the peripheral region NAA from being observed from the outside.

[0053] The display module DM may include a display panel DP and an input sensing unit ISP (e.g., an input sensor). The display panel DP can display an image IM, and the input sensing unit ISP can sense external input TC. These will be described in detail below.

[0054] The display panel DP can be flexible. As used herein, the term "flexible" refers to the property of being able to be bent, and a flexible display panel DP can include all structures ranging from fully bent to partially bent. For example, the display panel DP can be a curved display panel or a foldable display panel. According to an embodiment, the display panel DP can be rigid, as illustrated.

[0055] The display device DD according to an embodiment of the present disclosure may further include a driver chip DIC, a connection circuit board CF, and a main circuit board MB connected to the display panel DP.

[0056] The connecting circuit board CF connects the display panel DP and the main circuit board MB. The side of the connecting circuit board CF adjacent to the display module DM can be electrically connected to the display panel DP. The other side of the connecting circuit board CF adjacent to the main circuit board MB can be electrically connected to the main circuit board MB.

[0057] In Figure 2, a connecting circuit board CF is shown connecting the display panel DP and the main circuit board MB. However, embodiments of this disclosure are not limited to this or are not limited thereto. Multiple connecting circuit boards CF may be provided, and multiple connecting circuit boards CF may connect the display panel DP and the main circuit board MB.

[0058] According to an embodiment, the connecting circuit board CF may have curvature and may be bent in a direction toward the rear surface of the display panel DP. As an example, the connecting circuit board CF may be bent about a bending axis parallel to the second direction DR2. In this case, the main circuit board MB may be disposed on the rear surface of the display panel DP. For example, the main circuit board MB may be disposed on the rear surface of the cover plate CP.

[0059] The connecting circuit board (CF) can be a flexible printed circuit board. The connecting circuit board (CF) applies electrical signals to the display panel (DP) to drive it. These electrical signals can be generated by either the connecting circuit board (CF) or the main circuit board (MB).

[0060] The driver chip DIC can be mounted on the display panel DP. However, according to an embodiment, the driver chip DIC can be mounted on the connection circuit board CF. The driver chip DIC may include driving elements for driving the pixels of the display panel DP. The driver chip DIC may include driving circuitry, and the driving circuitry may be implemented as an integrated circuit. The driving circuitry may include a drive controller, a data driver, and a voltage generator, etc.

[0061] The main circuit board (MB) may include a main controller. The main circuit board (MB) may further include signal lines for transmitting control signals and image signals from the main controller to the connection circuit board (CF) and the display panel (DP). The main circuit board (MB) may be a rigid printed circuit board or a flexible printed circuit board.

[0062] The electronic device ED may further include an input circuit board electrically connected to an input sensing unit ISP. The input circuit board can connect the input sensing unit ISP and a main circuit board MB. In this embodiment, the input circuit board can be provided as a flexible circuit film and can connect the input sensing unit ISP and the main circuit board MB. The input circuit board can apply electrical signals to the input sensing unit ISP to drive the input sensing unit ISP. The electrical signals can be generated through the input circuit board or the main circuit board MB.

[0063] Each of the connection circuit board CF and the input circuit board can be connected to a main circuit board MB. According to an embodiment, one of the connection circuit board CF and the input circuit board may not be connected to the main circuit board MB, but embodiments of this disclosure are not limited thereto.

[0064] A cover plate (CP) can be disposed beneath the display panel (DP). The cover plate (CP) enhances resistance to compressive forces caused by external pressure. Accordingly, the cover plate (CP) prevents deformation of the display module (DM). The cover plate (CP) can comprise a flexible plastic material such as, for example, polyimide or polyethylene terephthalate. Furthermore, the cover plate (CP) can be a colored film with low light transmittance. The cover plate (CP) can absorb light incident upon it from the outside. As an example, the cover plate (CP) can be a black synthetic resin film.

[0065] A support plate may be further disposed below the cover plate CP. The support plate may include a high-strength metal material. The support plate may include a reinforcing fiber composite material. The support plate may include reinforcing fibers disposed in the matrix portion. The reinforcing fibers may be carbon fiber or glass fiber. The matrix portion may include a polymer resin. The matrix portion may include a thermoplastic resin. As an example, the matrix portion may include a polyamide resin or a polypropylene resin. For example, the reinforcing fiber composite material may be carbon fiber reinforced plastic (CFRP) or glass fiber reinforced plastic (GFRP).

[0066] The COP (Covering Part) can be positioned below the CP (Covering Board). The COP can cover the main circuit board MB in the direction opposite to the third direction DR3, and can cover the driver chip DIC in the direction opposite to the first direction DR1. This will be described in detail below.

[0067] The Electronic Module (ELM) and Power Supply Module (PSM) can be located below the Display Module (DM). The ELM and PSM can be electrically connected to each other via separate circuit boards.

[0068] A power supply module (PSM) can provide power for the operation of an electronic device (ED). As an example, a power supply module (PSM) may include a battery module.

[0069] An electronic module (ELM) may include various functional modules for operating an electronic device (ED). As an example, an ELM may include a control module (e.g., a controller), a wireless communication module (e.g., a wireless communicator or interface), an image input module (e.g., an image input device or interface), an audio input module (e.g., an audio input device or interface), an audio output module (e.g., an audio output device or interface), a memory, an optical module, and / or an external interface module (e.g., an external interface). An ELM may further include an antenna. An ELM may include a main circuit board, and modules within the ELM may be mounted on the main circuit board or electrically connected to the main circuit board via separate circuit boards.

[0070] The control module of the electronic module (ELM) can control the overall operation of the electronic device (ED). For example, the control module can activate or deactivate the display module (DM) in response to user input. The control module may include at least one microprocessor. The optical module of the electronic module (ELM) may be or include a camera module, a proximity sensor, a biometric sensor that identifies parts of the user's body (e.g., fingerprint, iris, or face), and / or a small light source.

[0071] The housing HAU can be connected to the window WM to provide internal space for accommodating the display module DM, electronics module ELM, power module PSM, connection circuit board CF, and main circuit board MB, etc. The housing HAU may comprise materials with relatively high rigidity. For example, the housing HAU may comprise multiple frames and / or plates of glass, plastic, or metal materials, or combinations thereof. The housing HAU protects the components of the electronic device ED housed within it by absorbing externally applied impacts and / or preventing foreign objects or moisture from entering the electronic device ED from the outside.

[0072] Figure 3 is a cross-sectional view of a display module according to an embodiment of the present disclosure.

[0073] Referring to Figure 3, the display module DM may include a display panel DP and an input sensing unit ISP. The input sensing unit ISP may be disposed on the display panel DP. The input sensing unit ISP may be directly disposed on the display panel DP. In this embodiment, the statement "the input sensing unit ISP is directly disposed on the display panel DP" means that the input sensing unit ISP can be formed on the display panel DP through a continuous process, and that the input sensing unit ISP can be connected to the display panel DP without using a separate adhesive layer. That is, the components of the input sensing unit ISP can be formed on the substrate surface provided by the display panel DP.

[0074] Display panel DP can display images in response to electrical signals. According to embodiments, display panel DP can be a light-emitting display panel. However, display panel DP is not limited to this. For example, display panel DP can be an organic light-emitting display panel, an inorganic light-emitting display panel, or a quantum dot light-emitting display panel. The light-emitting layer of an organic light-emitting display panel may include organic light-emitting materials. The light-emitting layer of an inorganic light-emitting display panel may include inorganic light-emitting materials. The light-emitting layer of a quantum dot light-emitting display panel may include quantum dots or quantum rods. Hereinafter, organic light-emitting display panels will be described as examples of display panel DP.

[0075] The display panel DP may include a substrate BS, a circuit element layer DP-CL, a light-emitting element layer DP-OL, and an encapsulation layer ECL that can be sequentially stacked on a third-party DR3.

[0076] The substrate BS can be a rigid substrate or a flexible substrate that can be bent, folded, or rolled. As an example, the substrate BS can be a glass substrate, a metal substrate, or a polymer substrate. The substrate BS can provide a substrate surface on which the circuit element layer DP-CL is disposed.

[0077] The substrate BS may include inorganic layers, organic layers, or composite material layers. The substrate BS may have a single-layer or multi-layer structure. As an example, a multi-layer substrate BS may include synthetic resin layers and inorganic layers having a single-layer or multi-layer structure disposed between the synthetic resin layers. The synthetic resin layers may include acrylic resins, methacrylic resins, polyisoprene resins, vinyl resins, epoxy resins, urethane resins, cellulose resins, siloxane resins, polyamide resins, or perylene resins; however, the materials used for the synthetic resin layers are not limited to or not restricted by these limitations.

[0078] The circuit element layer DP-CL can be disposed on the substrate BS. The circuit element layer DP-CL may include semiconductor patterns, conductive patterns, and at least one insulating layer. The insulating layer, semiconductor patterns, and conductive patterns included in the circuit element layer DP-CL can form driving elements (such as transistors), signal lines, and pads.

[0079] The light-emitting element layer DP-OL can be disposed on the circuit element layer DP-CL. The light-emitting element layer DP-OL can include individual light-emitting elements. For example, each light-emitting element can include an organic light-emitting element, an inorganic light-emitting element, a micron-sized light-emitting diode (LED), or a nano LED. The light-emitting elements of the light-emitting element layer DP-OL can be electrically connected to the driving element of the circuit element layer DP-CL and can emit light in response to an electrical signal provided from the driving element.

[0080] An encapsulation layer (ECL) can be disposed on the light-emitting element layer (DP-OL) and can encapsulate the light-emitting element. The ECL may include at least one thin film to improve the optical efficiency of the DP-OL or to protect it. As an example, the ECL may include at least one of an inorganic layer and an organic layer. The inorganic layer of the ECL can protect the light-emitting element from moisture and oxygen. The organic layer of the ECL can protect the light-emitting element from foreign matter such as dust particles.

[0081] The input sensing unit (ISP) can sense external input and provide an input signal including the coordinate information of the external input to the display panel (DP), allowing the display panel (DP) to display an image corresponding to the external input. The input sensing unit (ISP) can perform sensing in various ways, such as by capacitance, resistance, infrared, acoustic, or pressure methods. However, embodiments of this disclosure are not limited to these methods, and the input sensing unit (ISP) can perform sensing using various other methods that enable it to sense external input. In this embodiment, by way of example, the input sensing unit (ISP) will be described as an input sensing panel that can perform sensing using capacitance.

[0082] The input sensing unit ISP may include a substrate layer IL1, a first sensing conductive layer CL1, a first sensing insulating layer IL2, a second sensing conductive layer CL2, and a second sensing insulating layer IL3. The substrate layer IL1 of the input sensing unit ISP may be in contact with the encapsulation layer ECL. However, embodiments of this disclosure are not limited to this or are not limited thereto, and at least one of the substrate layer IL1 and the second sensing insulating layer IL3 may be omitted.

[0083] Each of the first sensing conductive layer CL1 and the second sensing conductive layer CL2 may have a single-layer or multi-layer structure. A multi-layer conductive layer may include two or more layers, including a transparent conductive layer and a metal layer. A multi-layer conductive layer may include a metal layer containing different metals. The transparent conductive layer may include at least one of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), PEDOT, metal nanowires, and graphene. The metal layer may include at least one of molybdenum, silver, titanium, copper, aluminum, and their alloys. As an example, each of the first sensing conductive layer CL1 and the second sensing conductive layer CL2 may have a two-layer structure of ITO / copper, or a three-layer structure of titanium / aluminum / titanium.

[0084] Each of the first sensing conductive layer CL1 and the second sensing conductive layer CL2 may include a sensing conductive pattern. The sensing conductive patterns of the first sensing conductive layer CL1 and the second sensing conductive layer CL2 may form the sensing electrodes included in the input sensing unit ISP and the sensing lines connected to the sensing electrodes.

[0085] Each of the substrate layer IL1, the first sensing insulating layer IL2, and the second sensing insulating layer IL3 may include at least one of an inorganic layer and an organic layer. As an example, the inorganic layer may include at least one of alumina, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide, and the organic layer may include at least one of acrylic resins, methacrylic resins, polyisoprene resins, vinyl resins, epoxy resins, urethane resins, cellulose resins, siloxane resins, polyamide resins, and perylene resins. However, the materials used for the inorganic and organic layers are not limited to those described above. According to an embodiment, the substrate layer IL1 may include an inorganic layer, and the first sensing insulating layer IL2 and the second sensing insulating layer IL3 may include organic layers. However, embodiments of this disclosure are not limited thereto or are not subject to these limitations.

[0086] Figure 4 is a plan view of a display panel according to an embodiment of the present disclosure.

[0087] Referring to Figure 4, the display panel DP may include a substrate BS, a pixel PX, signal lines electrically connected to the pixel PX (e.g., scan lines SL1 to SLm, data lines DL1 to DLn, transmit lines EL1 to ELm, a first control line CSL1, a second control line CSL2, and a power line PL, where each of m and n is a non-zero natural number), a scan driver SDV, a transmit driver EDV, and display pads D-PD.

[0088] The substrate BS provides the electrical components and wiring of the display panel DP on its substrate surface. The substrate BS may include a display area DA. The display area DA may be the area in which the light-emitting elements of the pixel PX are arranged. Accordingly, the pixel PX can display an image through the display area DA. The display area DA may correspond to the effective area AA (refer to FIG. 2) of the display module DM (refer to FIG. 2) and may overlap with the transmissive area TA (refer to FIG. 2) of the window WM (refer to FIG. 2).

[0089] The area outside the display area DA can be defined as the non-display area NDA. The non-display area NDA can be adjacent to the display area DA, and the image can be displayed without passing through the non-display area NDA. The non-display area NDA can surround the display area DA. Scan drivers SDV, transmit drivers EDV, driver chips DIC, and display pads D-PD electrically connected to signal lines (e.g., scan lines SL1 to SLm, data lines DL1 to DLn, transmit lines EL1 to ELm, first control line CSL1, second control line CSL2, and power line PL) can be arranged in the non-display area NDA to drive pixels PX. Signal lines electrically connected to pixels PX (e.g., scan lines SL1 to SLm, data lines DL1 to DLn, transmit lines EL1 to ELm, first control line CSL1, second control line CSL2, and power line PL) can extend into the non-display area NDA and can be arranged within the non-display area NDA.

[0090] The areas where the display pads D-PD and the sensing pads I-PD (refer to FIG. 5) are arranged can be referred to as the display pad area PD-A and the sensing pad area IPD-A, respectively. As a non-limiting example, FIG. 4 shows a structure in which the display pad area PD-A and the sensing pad area IPD-A are separated from each other in the second direction DR2. As an example, the sensing pad area IPD-A can be formed on opposite sides of the display pad area PD-A to be spaced apart in the second direction DR2, while the display pad area PD-A is positioned in the central area. However, embodiments of this disclosure are not limited to this or not limited thereto, and the arrangement positions of the display pads D-PD and the sensing pads I-PD (refer to FIG. 5) can be changed in various ways.

[0091] The connecting circuit board CF (refer to FIG. 2) can be disposed on the area where the display pad D-PD and the sensing pad I-PD (refer to FIG. 5) are arranged, and can be electrically connected to the display pad D-PD and the sensing pad I-PD (refer to FIG. 5). When the connecting circuit board CF, which is disposed adjacent to the lower end of the non-display area NDA, is bent, a portion of the connecting circuit board CF and the main circuit board MB can be disposed on the rear surface of the display panel DP. Since a portion of the connecting circuit board CF and the main circuit board MB are disposed below the display panel DP when viewed from the front surface of the electronic device ED (refer to FIG. 2), the bezel area of ​​the electronic device ED (refer to FIG. 2) can be reduced.

[0092] Each pixel PX may include a pixel driving circuit comprising multiple transistors (e.g., switching transistors, driving transistors, etc.) and at least one capacitor, as well as a light-emitting element electrically connected to the pixel driving circuit. Each pixel PX may emit light in response to an electrical signal applied to it, and an image may be displayed through the display area DA. According to an embodiment, some pixels PX may include transistors disposed in the non-display area NDA, but embodiments of this disclosure are not limited thereto.

[0093] The scan driver SDV and transmit driver EDV can be disposed in a non-display area NDA adjacent to the side of the display area DA. The driver chip DIC can be disposed in a non-display area NDA adjacent to the lower end of the display area DA. According to an embodiment, the driver chip DIC can be mounted in the non-display area NDA of the display panel DP and can be provided as an integrated circuit chip. However, the embodiments of this disclosure are not limited to this or are not limited thereto, and the driver chip DIC can be mounted on a connection circuit board CF (refer to FIG. 2).

[0094] The signal lines may include multiple scan lines SL1 to SLm, multiple data lines DL1 to DLn, multiple transmit lines EL1 to ELm, a first control line CSL1, a second control line CSL2, and a power line PL. Each of m and n is a non-zero natural number.

[0095] Data lines DL1 to DLn can be insulated from scan lines SL1 to SLm and transmit lines EL1 to ELm while crossing them. As an example, scan lines SL1 to SLm can extend in the second direction DR2 and can be electrically connected to the scan driver SDV. Data lines DL1 to DLn can extend in the first direction DR1 and can be electrically connected to the driver chip DIC. Transmit lines EL1 to ELm can extend in the second direction DR2 and can be electrically connected to the transmit driver EDV.

[0096] The power line PL may include a portion extending in a first direction DR1 and a portion extending in a second direction DR2. The portions of the power line PL extending in the first direction DR1 and the portions extending in the second direction DR2 may be disposed on different layers, or they may be integrally provided and disposed on the same layer. The portion of the power line PL extending in the second direction DR2 may be electrically connected to the pixel PX and the portion of the power line PL extending in the first direction DR1. The portion of the power line PL extending in the first direction DR1 may be disposed in the non-display area NDA and may be electrically connected to the display pad D-PD. The power line PL can apply electrical voltage to the pixel PX.

[0097] The first control line CSL1 can be electrically connected to the scan driver SDV, and the second control line CSL2 can be electrically connected to the transmit driver EDV.

[0098] Display pads D-PD can be located in a non-display area NDA adjacent to the lower end of the display area DA. Display pads D-PD can be positioned closer to the lower end of the substrate BS than the driver chip DIC. Display pads D-PD can be spaced apart from each other in the second direction DR2. Power lines PL, the first control line CSL1, and the second control line CSL2 can be electrically connected to their respective display pads D-PD. Data lines DL1 to DLn can be connected to their respective display pads D-PD via the driver chip DIC.

[0099] Display pads D-PD can be electrically connected to the connection circuit board CF via an adhesive layer (refer to Figure 2), and electrical signals provided from the connection circuit board CF can be applied to the display panel DP via display pads D-PD. However, the connection structure between display pads D-PD and the connection circuit board CF is not limited to this or is not restricted by it.

[0100] The scan driver SDV can generate multiple scan signals in response to a scan control signal. These scan signals can be applied to pixel PX via scan lines SL1 to SLm. The driver chip DIC can generate multiple data voltages corresponding to the image signals in response to a data control signal. These data voltages can be applied to pixel PX via data lines DL1 to DLn. The transmit driver EDV can generate multiple transmit signals in response to a transmit control signal. These transmit signals can be applied to pixel PX via transmit lines EL1 to ELm.

[0101] Pixel PX can receive data voltage in response to a scan signal. Pixel PX can emit light with a brightness corresponding to the data voltage in response to a transmit signal, and thus, an image can be displayed. The emission time of pixel PX can be controlled by the transmit signal.

[0102] Figure 5 is a plan view of an input sensing unit according to an embodiment of the present disclosure. For ease of explanation, Figure 5 schematically shows the components of the input sensing unit ISP disposed on the substrate BS.

[0103] The input sensing unit (ISP) can perform sensing using the mutual capacitance method. Referring to FIG5, the input sensing unit (ISP) may include a first sensing electrode TEX (e.g., first sensing electrodes TEX1 to TEX6), a second sensing electrode TEY (e.g., second sensing electrodes TEY1 to TEY4), a first sensing line TLX1 to TLX6, a second sensing line TLY1 to TLY4, and a sensing pad I-PD. However, embodiments of this disclosure are not limited thereto, and according to embodiments, the input sensing unit (ISP) can perform sensing using the self-capacitance method.

[0104] The first sensing electrode TEX can extend in the second direction DR2 and can be arranged in the first direction DR1. Figure 5 shows six first sensing electrodes TEX1 to TEX6 as an example. However, the number of first sensing electrodes TEX included in the input sensing unit ISP is not limited to this or is not restricted by it. A first sensing electrode TEX may include a first sensing pattern SP1 arranged in the second direction DR2 and a first connection pattern BP1 connecting the first sensing pattern SP1.

[0105] The second sensing electrode TEY can extend along the first direction DR1, and the second sensing electrode TEY can be arranged along the second direction DR2. Figure 5 shows four second sensing electrodes TEY1 to TEY4 as an example. However, the number of second sensing electrodes TEY included in the input sensing unit ISP is not limited to this or is not restricted by it. A second sensing electrode TEY may include a second sensing pattern SP2 arranged along the first direction DR1 and a second connection pattern BP2 connecting the second sensing pattern SP2.

[0106] The first sensing electrode TEX can be electrically insulated from the second sensing electrode TEY. The input sensing unit ISP can sense external input based on the change in capacitance between the first sensing electrode TEX and the second sensing electrode TEY. The first sensing electrode TEX and the second sensing electrode TEY can be disposed in an area corresponding to (e.g., overlapping with) the display area DA of the substrate BS. Accordingly, the electronic device ED (refer to FIG. 1) can display an image through the display area DA, and substantially simultaneously, can sense the external input applied to the display area DA.

[0107] The first sensing lines TLX1 to TLX6 can be arranged in the non-display area NDA and can be electrically connected to the first sensing electrodes TEX1 to TEX6 respectively. Some of the first sensing lines TLX1 to TLX6 can be arranged in the non-display area NDA adjacent to the left side of the display area DA, and the other sensing lines TLX1 to TLX6 can be arranged in the non-display area NDA adjacent to the right side of the display area DA. As an example, the first sensing lines TLX1, TLX3, and TLX5 connected to the first sensing electrodes TEX1, TEX3, and TEX5 arranged in odd-numbered rows can be connected to the left side of the first sensing electrodes TEX1, TEX3, and TEX5 respectively, and the first sensing lines TLX2, TLX4, and TLX6 connected to the first sensing electrodes TEX2, TEX4, and TEX6 arranged in even-numbered rows can be connected to the right side of the first sensing electrodes TEX2, TEX4, and TEX6 respectively. However, the arrangement of the first sensing lines TLX1 to TLX6 is not limited to this or is not restricted by this, and according to the embodiment, all the first sensing lines TLX1 to TLX6 can be arranged in the non-display area NDA adjacent to the left side of the display area DA, or all the first sensing lines TLX1 to TLX6 can be arranged in the non-display area NDA adjacent to the right side of the display area DA.

[0108] The first sensing lines TLX1 to TLX6 can extend along the first direction DR1 and the second direction DR2. The first sensing lines TLX1 to TLX6 can be electrically connected to the sensing pads I-PD, respectively.

[0109] The second sensing lines TLY1 to TLY4 can be arranged in the non-display area NDA and can be electrically connected to the second sensing electrodes TEY1 to TEY4 respectively. Some of the second sensing lines TLY1 to TLY4 can be arranged adjacent to the left side of the display area DA, and the other sensing lines TLY1 to TLY4 can be arranged adjacent to the right side of the display area DA. As an example, the second sensing lines TLY1 and TLY2 of the second sensing electrodes TEY1 and TEY2, which are electrically connected to the second sensing electrodes TEY1 to TEY4 and are arranged on the left side in the second direction DR2, can be arranged adjacent to the left side of the display area DA, and the second sensing lines TLY3 and TLY4 of the second sensing electrodes TEY1 to TEY4, which are arranged on the right side in the second direction DR2, can be arranged adjacent to the right side of the display area DA. However, the arrangement of the second sensing lines TLY1 to TLY4 is not limited to this or is not restricted by this.

[0110] The second sensing lines TLY1 to TLY4 may extend along the first direction DR1 and / or the second direction DR2. The second sensing lines TLY1 to TLY4 may be electrically connected to the sensing pads I-PD, respectively.

[0111] Some of the sensing pad I-PDs can be arranged in an area adjacent to the left side of the display pad area PD-A, and other sensing pad I-PDs can be arranged in an area adjacent to the right side of the display pad area PD-A. As an example, the sensing pad I-PDs can be divided into two groups spaced apart from each other, and the display pad area PD-A can be positioned between these two groups. However, the arrangement of the sensing pad I-PDs is not limited to this or not restricted by it.

[0112] The sensing pad I-PD can be disposed on the same layer as the display pad D-PD (refer to FIG. 4). The sensing pad I-PD can be disposed on a different layer from the first sensing lines TLX1 to TLX6 and the second sensing lines TLY1 to TLY4, and can be connected to the first sensing lines TLX1 to TLX6 and the second sensing lines TLY1 to TLY4 via contact holes. However, embodiments of this disclosure are not limited to this or are not limited thereto, and the sensing pad I-PD can be disposed on a different layer from the display pad D-PD (refer to FIG. 4). As an example, the sensing pad I-PD can be disposed on the same layer as the first sensing lines TLX1 to TLX6 and the second sensing lines TLY1 to TLY4, and can be provided integrally with the first sensing lines TLX1 to TLX6 and the second sensing lines TLY1 to TLY4.

[0113] The first sensing lines TLX1 to TLX6 and the second sensing lines TLY1 to TLY4 can be positioned at a location higher than the components of the display panel DP (refer to FIG. 4) in the area corresponding to the non-display area NDA of the substrate BS. Accordingly, the first sensing lines TLX1 to TLX6 and the second sensing lines TLY1 to TLY4 can overlap with the components of the display panel DP (refer to FIG. 4) in the non-display area NDA.

[0114] Figure 6 is a cross-sectional view of a display module according to an embodiment of the present disclosure. As an example, Figure 6 shows a cross-section of a pixel PX (refer to Figure 4) disposed in the display area DA.

[0115] Referring to Figure 6, the display module DM may include a display panel DP and an input sensing unit ISP disposed on the display panel DP. The above description can also be applied to the same components in Figure 6.

[0116] As described with reference to Figure 3, the display panel DP may include a substrate BS, a circuit element layer DP-CL, a light-emitting element layer DP-OL, and an encapsulation layer ECL.

[0117] The substrate BS can have insulating properties and can provide a substrate surface on which the components of the display module DM are disposed. The substrate BS can have sufficient flexibility to be bent. As an example, the substrate BS can be bent at a selected curvature.

[0118] The circuit element layer DP-CL may include an insulating layer, a transistor TR for a pixel PX (refer to FIG. 4), an upper electrode UE, and connection electrodes (e.g., a first connection electrode CN1 and a second connection electrode CN2) that can be disposed on a substrate BS. The insulating layer may include a first insulating layer 10, a second insulating layer 20, a third insulating layer 30, a fourth insulating layer 40, a fifth insulating layer 50, and a sixth insulating layer 60 sequentially stacked on the substrate BS along the thickness direction (e.g., the third third direction DR3). However, the first to sixth insulating layers 10 to 60 included in the circuit element layer DP-CL are not limited to this or are not limited thereto, and may vary depending on the structure or manufacturing process of the circuit element layer DP-CL.

[0119] A first insulating layer 10 may be disposed on a substrate BS. The first insulating layer 10 may be a barrier layer and / or a buffer layer to prevent foreign matter from entering from the outside. The first insulating layer 10 may increase the adhesion between the substrate BS and the semiconductor pattern SM and / or between the substrate BS and the conductive pattern of the circuit element layer DP-CL. The first insulating layer 10 may include at least one of a silicon oxide layer and a silicon nitride layer. According to an embodiment, the first insulating layer 10 may include a silicon oxide layer and silicon nitride layers alternately stacked with the silicon oxide layer.

[0120] Pixel PX (refer to FIG. 4) can be disposed on the substrate BS. Pixel PX (refer to FIG. 4) can be configured to correspond to the display area DA (e.g., disposed within the display area DA). Pixel PX (refer to FIG. 4) may include transistor TR and light-emitting element OL.

[0121] The transistor TR may include a semiconductor pattern SM and a gate electrode GE. The semiconductor pattern SM may be disposed on the first insulating layer 10. The semiconductor pattern SM may include a channel C, a source S, and a drain D. The semiconductor pattern SM may include a silicon semiconductor, such as a crystalline silicon semiconductor, a polycrystalline silicon semiconductor, or an amorphous silicon semiconductor. However, embodiments of this disclosure are not limited thereto, and the semiconductor pattern SM may include an oxide semiconductor. The semiconductor pattern SM according to embodiments of this disclosure may include various materials, as long as the semiconductor pattern SM has semiconductor properties.

[0122] A semiconductor pattern SM may include multiple regions, each possessing different electrical characteristics depending on whether it is doped or whether the metal oxide is reduced. As an example, the semiconductor pattern SM may include regions with high conductivity obtained through doping or reduction of the metal oxide, and these regions with high conductivity can be used as electrodes for signal lines or transistors TR. The regions with high conductivity may correspond to the source (S) and drain (D) of the transistor TR. The semiconductor pattern SM may also include undoped regions with relatively low conductivity, and these regions may correspond to the channel (C) (or active region) of the transistor TR.

[0123] A second insulating layer 20 may be disposed on the first insulating layer 10 and may cover the semiconductor pattern SM. A gate electrode GE may be disposed on the second insulating layer 20. The second insulating layer 20 may be disposed between the semiconductor pattern SM of the transistor TR and the gate electrode GE. When viewed in a plane (e.g., on a third-direction DR3), the gate electrode GE may overlap with the channel C of the semiconductor pattern SM. In the process of doping the semiconductor pattern SM, the gate electrode GE may be used as a mask. The gate electrode GE may include heat-resistant molybdenum (Mo), alloys including molybdenum (Mo), titanium (Ti), or alloys including titanium (Ti), etc. However, the material of the gate electrode GE is not limited to these.

[0124] The structure of the transistor TR shown in Figure 6 is merely an example, and the source S or drain D of the transistor TR can be formed independently of the semiconductor pattern SM. In this case, the source S and drain D can be in contact with the semiconductor pattern SM or can be connected to the semiconductor pattern SM after penetrating the insulating layer. Furthermore, the gate electrode GE can be disposed under the semiconductor pattern SM. The transistor TR according to embodiments of this disclosure can have various structures and is not specifically limited thereto.

[0125] The second insulating layer 20 and the third to sixth insulating layers 30 to 60 described below may include at least one of inorganic and organic layers. As an example, the inorganic layer may include at least one of alumina, titanium dioxide, silicon dioxide, silicon oxynitride, zirconium oxide, and hafnium oxide. The organic layer may include at least one of acrylic resins, methacrylic resins, polyisoprene resins, vinyl resins, epoxy resins, urethane resins, cellulose resins, siloxane resins, polyamide resins, and perylene resins.

[0126] The third insulating layer 30 may be disposed on the second insulating layer 20 and may cover the gate electrode GE. The upper electrode UE may be disposed on the third insulating layer 30. When viewed in a plane (e.g., on a third-direction DR3), the upper electrode UE may overlap with the gate electrode GE, and the gate electrode GE and the upper electrode UE overlapping the gate electrode GE may define a capacitor.

[0127] A fourth insulating layer 40 may be disposed on the third insulating layer 30 and may cover the upper electrode UE. The connecting electrodes may include a first connecting electrode CN1 and a second connecting electrode CN2. The first connecting electrode CN1 may be disposed on the fourth insulating layer 40. A fifth insulating layer 50 may be disposed on the fourth insulating layer 40 and may cover the first connecting electrode CN1. The second connecting electrode CN2 may be disposed on the fifth insulating layer 50. A sixth insulating layer 60 may be disposed on the fifth insulating layer 50 and may cover the second connecting electrode CN2. According to an embodiment, at least one of the fifth insulating layer 50 and the sixth insulating layer 60 may include an organic layer and may compensate for step differences between components disposed beneath the fifth insulating layer 50 and the sixth insulating layer 60 to provide a flat upper surface.

[0128] The first connecting electrode CN1 can be electrically connected to the semiconductor pattern SM via a contact hole defined through the second insulating layer 20 to the fourth insulating layer 40. The second connecting electrode CN2 can be electrically connected to the first connecting electrode CN1 via a contact hole defined through the fifth insulating layer 50.

[0129] Each of the first connecting electrode CN1 and the second connecting electrode CN2 may include a conductive material. Each of the first connecting electrode CN1 and the second connecting electrode CN2 may include gold, silver, copper, aluminum, platinum, molybdenum, titanium, and alloys thereof. At least one of the first connecting electrode CN1 and the second connecting electrode CN2 may have a multilayer structure with conductive layers. As an example, at least one of the first connecting electrode CN1 and the second connecting electrode CN2 may have a titanium / aluminum / titanium three-layer structure. However, embodiments of this disclosure are not limited thereto or are not restricted thereto.

[0130] Depending on the embodiment of the circuit element layer DP-CL, at least one of the first connection electrode CN1 and the second connection electrode CN2 may be omitted. According to an embodiment, depending on the embodiment of the circuit element layer DP-CL, additional connection electrodes connecting the transistor TR and the light-emitting element OL may be further provided. The method of electrically connecting the light-emitting element OL and the transistor TR can be varied depending on the number of insulating layers disposed between the light-emitting element OL and the transistor TR. However, embodiments of this disclosure are not limited thereto or are not subject to this limitation.

[0131] The light-emitting element layer DP-OL may include a light-emitting element OL and a pixel-defining layer PDL. The light-emitting element OL and the pixel-defining layer PDL may be disposed on the sixth insulating layer 60. The light-emitting element OL may include a first electrode AE, a light-emitting layer EM, and a second electrode CE.

[0132] The first electrode AE ​​can be electrically connected to the second connection electrode CN2 via a contact hole defined through the sixth insulating layer 60. The first electrode AE ​​can be electrically connected to the transistor TR via the first connection electrode CN1 and the second connection electrode CN2.

[0133] The pixel opening (PX-OP) can be defined by a pixel defining layer (PDL) to expose at least a portion of the first electrode (AE). The portion of the first electrode (AE) exposed by the pixel defining layer (PDL) can correspond to a light-emitting region. The pixel defining layer (PDL) can include an inorganic layer, an organic layer, or a composite material layer. According to an embodiment, the pixel defining layer (PDL) can further include a black pigment or a black dye.

[0134] A light-emitting layer EM can be disposed on a first electrode AE. The light-emitting layer EM can emit light of a selected color. The light-emitting layer EM can be configured to correspond to a pixel opening PX-OP defined through a pixel defining layer PDL (e.g., disposed within the pixel opening PX-OP). Each of the light-emitting elements OL and the pixel opening PX-OP can be provided in multiples, and the light-emitting layers EM of the light-emitting elements OL can be arranged to correspond to the pixel opening PX-OP respectively (e.g., respectively disposed within the pixel opening PX-OP), and can be spaced apart from each other. However, embodiments of this disclosure are not limited to or are not limited thereto, and according to embodiments, the light-emitting layers EM of the light-emitting elements OL can be integrally provided as a common layer.

[0135] The second electrode CE can be disposed on the light-emitting layer EM and the pixel limiting layer PDL. The second electrode CE can be provided as a common electrode disposed throughout the pixels PX (refer to Figure 4).

[0136] The light-emitting element OL may further include at least one of a hole control region disposed between the first electrode AE ​​and the light-emitting layer EM, and an electron control region disposed between the light-emitting layer EM and the second electrode CE. The hole control region may include at least one of a hole generation layer, a hole transport layer, and an electron blocking layer, and the electron control region may include at least one of an electron generation layer, an electron transport layer, and a hole blocking layer.

[0137] An encapsulation layer ECL can be disposed on the light-emitting element layer DP-OL. The encapsulation layer ECL can be disposed on the light-emitting element OL and the pixel defining layer PDL to encapsulate the light-emitting element OL. The encapsulation layer ECL can include at least one of inorganic and organic layers. In this embodiment, the encapsulation layer ECL can include a first inorganic layer EN1, a second inorganic layer EN3, and an organic layer EN2 disposed between the first inorganic layer EN1 and the second inorganic layer EN3. However, the encapsulation layer ECL is not limited to this or is not subject to this limitation.

[0138] A first inorganic layer EN1 can be disposed on the second electrode CE, and an organic layer EN2 and a second inorganic layer EN3 can be sequentially stacked on the first inorganic layer EN1 in the thickness direction (e.g., third direction DR3) of the display panel DP. The first inorganic layer EN1 and the second inorganic layer EN3 can protect the light-emitting element OL from external moisture or oxygen. As an example, each of the first inorganic layer EN1 and the second inorganic layer EN3 may include at least one of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and aluminum oxide. However, the materials of the first inorganic layer EN1 and the second inorganic layer EN3 are not limited to or are not subject to this limitation. The organic layer EN2 can prevent foreign matter from entering the light-emitting element OL and can compensate for step differences between components disposed below the organic layer EN2. As an example, the organic layer EN2 may include acrylic organic materials. However, the material of the organic layer EN2 is not limited to or is not subject to this limitation.

[0139] The input sensing unit (ISP) can be disposed on the display panel (DP). The input sensing unit (ISP) may include a substrate layer IL1, a first sensing insulating layer IL2, a first sensing conductive layer CL1, and a second sensing conductive layer CL2. As shown in FIG3, the input sensing unit (ISP) may further include a second sensing insulating layer IL3. The above description can also be applied to the same components in FIG6.

[0140] The substrate layer IL1 may contact the topmost layer of the encapsulation layer ECL. As an example, the substrate layer IL1 may contact the second inorganic layer EN3 of the encapsulation layer ECL. The substrate layer IL1 of the input sensing unit ISP may be formed directly on the second inorganic layer EN3 of the encapsulation layer ECL. However, embodiments of this disclosure are not limited to this or not limited thereto, and according to embodiments, the substrate layer IL1 may be omitted. In this case, the first sensing conductive layer CL1 of the input sensing unit ISP may contact the encapsulation layer ECL.

[0141] A first sensing conductive layer CL1 may be disposed on a substrate layer IL1, and a second sensing conductive layer CL2 may be disposed on a first sensing insulating layer IL2. The first sensing conductive layer CL1 and the second sensing conductive layer CL2 may form a sensing electrode TE. The sensing electrode TE may correspond to (for example,) one of a first sensing electrode TEX (refer to FIG. 5) and a second sensing electrode TEY (refer to FIG. 5). As an example, the first sensing conductive layer CL1 may include a connection pattern BP of the sensing electrode TE, and the second sensing conductive layer CL2 may include a sensing pattern SP of the sensing electrode TE. However, embodiments of this disclosure are not limited thereto or are not limited thereto. The first sensing conductive layer CL1 may include a sensing pattern SP, and the second sensing conductive layer CL2 may include a connection pattern BP.

[0142] The connection pattern BP may correspond to (for example, a first connection pattern BP1 (refer to FIG. 5) or a second connection pattern BP2 (refer to FIG. 5), and the sensing pattern SP may correspond to (for example, a first sensing pattern SP1 (refer to FIG. 5) or a second sensing pattern SP2 (refer to FIG. 5). The connection pattern BP and the sensing pattern SP may be disposed on different layers and may be connected to the sensing pattern SP via a contact hole defined through the first sensing insulating layer IL2. However, embodiments of this disclosure are not limited thereto or are not limited thereto. According to embodiments, the connection pattern BP and the sensing pattern SP may be disposed on the same layer and may be provided integrally with each other.

[0143] The sensing electrode TE can be a pattern with a grid shape and can be configured to correspond to an area where a pixel defining layer (PDL) is disposed. However, embodiments of this disclosure are not limited to this or are not limited thereto. According to an embodiment, the sensing electrode TE can be provided as a pattern with a single shape overlapping the light-emitting element OL, and in this case, the sensing electrode TE can include a transparent conductive material.

[0144] Figures 7A and 7B are cross-sectional views of a display device according to an embodiment of the present disclosure. Specifically, Figure 7A is a cross-sectional view of the display device DD taken along line I-I' of Figure 2, and Figure 7B is a cross-sectional view of the display device DD in which the connecting circuit board CF is bent. Repeated descriptions may be omitted below.

[0145] Referring to Figures 7A and 7B, the connecting circuit board CF can be bent with a selected curvature in a direction toward the rear surface of the display module DM. As an example, the connecting circuit board CF can be bent about a bending axis BX parallel to the second direction DR2. In this case, the main circuit board MB can be disposed on the rear surface of the display module DM. Specifically, the main circuit board MB can be disposed on the rear surface CP-BS of the cover plate CP.

[0146] Window WM may include a first edge E1, and display module DM may include a second edge E2. According to embodiments of this disclosure, the first edge E1 of window WM and the second edge E2 of display module DM may not be aligned with each other (e.g., do not overlap) in the third direction DR3. As an example, the first edge E1 of window WM may protrude outward in a direction opposite to the first direction DR1 than the second edge E2 of display module DM. Accordingly, when viewed in the third direction DR3, a portion of the lower surface WM-BS of window WM may not overlap with display module DM.

[0147] According to embodiments of this disclosure, the cover portion COP can be disposed under the cover plate CP and can cover the connecting circuit board CF and the main circuit board MB. Referring to FIG7B, one side of the cover portion COP can contact the portion of the lower surface WM-BS of the window WM that overlaps with the frame area BZA, and the other side of the cover portion COP (opposite to this side of the cover portion COP) can contact the rear surface (or lower surface) CP-BS of the cover plate CP. The cover portion COP can be attached to the lower surface WM-BS of the window WM and the rear surface CP-BS of the cover plate CP. According to embodiments of this disclosure, separate adhesives can be disposed between the cover portion COP and the lower surface WM-BS of the window WM and between the cover portion COP and the rear surface CP-BS of the cover plate CP. Since the cover portion COP extends to the lower surface WM-BS of the window WM, the cover portion COP can cover the second edge E2 of the display module DM (e.g., overlap with the second edge E2 of the display module DM) and can protect the second edge E2 of the display module DM, and therefore, the durability of the display device DD can be improved.

[0148] The cover portion COP can cover the connection board CF and the main board MB. As an example, when viewed from a third-party DR3, the cover portion COP can completely overlap the connection board CF and the main board MB, and the connection board CF and the main board MB may not be exposed to the outside. As an example, the cover portion COP can contact a portion of the connection board CF and a portion of the main board MB. The cover portion COP can protect the connection board CF and the main board MB from external electrostatic discharge. The cover portion COP can protect the connection board CF and the main board MB from radio waves or electrostatic discharge generated from the electronic module ELM (refer to Figure 2) (such as, for example, an antenna).

[0149] According to embodiments of this disclosure, the covering portion COP can cover the driver chip DIC (e.g., overlap with the driver chip DIC). Specifically, the covering portion COP can cover the driver chip DIC in a direction opposite to the first direction DR1 (e.g., overlap with the driver chip DIC). The covering portion COP can protect the driver chip DIC from external static electricity. The covering portion COP can include a metallic material with high conductivity to absorb or reflect external radio waves. As an example, the covering portion COP can include iron or nickel to absorb external magnetic fields or can include copper or aluminum to reflect external magnetic fields. That is, since the covering portion COP covers the driver chip DIC in a direction opposite to the first direction DR1, it can protect the driver chip DIC from external static electricity. Specifically, the covering portion COP can protect the driver chip DIC from radio waves or static electricity generated from the electronic module ELM (refer to FIG. 2) (such as, for example, an antenna). Furthermore, the covering portion COP can shield the driver chip DIC to prevent magnetic fields generated from the driver chip DIC from being emitted to the outside. In FIG. 7A and FIG. 7B, the covering portion COP has a single-layer structure. However, the covered portion of the COP can have a multi-layered structure.

[0150] Figure 8 is a cross-sectional view of a display device according to an embodiment of the present disclosure.

[0151] Referring to Figure 8, the display device DDa may include a bendable display module DMa. As an example, the display module DMa may include a bendable bent portion BDP. The main circuit board MB may be in direct contact with and electrically connected to the display module DMa. The cover portion COP may contact the bent portion BDP of the display module DMa to cover at least a portion of the bent portion BDP.

[0152] Figures 9A to 9E are process diagrams of a method for manufacturing a display device according to an embodiment of the present disclosure. More specifically, Figures 9A to 9E are process diagrams of a method for manufacturing the display device DD shown in Figure 7B. In the following text, repeated descriptions of the same elements as those described with reference to Figures 7A and 7B may be omitted.

[0153] Referring to Figure 9A, processes for providing (e.g., forming) a display module DM on a cover plate CP, providing (e.g., forming) an optical layer RPL on the display module DM, and providing (e.g., forming) a driver chip DIC on the display module DM can be performed. The provisioning (e.g., forming) of the driver chip DIC can be performed after the provisioning (e.g., forming) of the optical layer RPL. However, embodiments of this disclosure are not limited to or not limited thereto, and the provisioning (e.g., forming) of the optical layer RPL can be performed after the provisioning (e.g., forming) of the driver chip DIC.

[0154] Referring to FIG9B, a process can be performed to provide (e.g., form) a connection circuit board CF on one side of the display module DM and a process can be performed to provide (e.g., form) a main circuit board MB to be electrically connected to the connection circuit board CF. According to some embodiments, providing (e.g., forming) the connection circuit board CF on one side of the display module DM may include connecting the display pads D-PD (refer to FIG4) disposed on the display module DM to the connection circuit board CF.

[0155] Referring to Figure 9C, a process can be performed to bend the connecting circuit board CF. The connecting circuit board CF can be bent about the bending axis BX with a selected curvature. As an example, the connecting circuit board CF can be bent relative to the bending axis BX in a direction toward the rear surface of the display module DM. When the connecting circuit board CF is bent, the main circuit board MB can be disposed on the rear surface of the display module DM. Specifically, the main circuit board MB can be disposed on the rear surface CP-BS of the cover plate CP.

[0156] Referring to Figures 9D and 9E, a process can be performed to provide (e.g., form) a window WM on the optical layer RPL, and a process can be performed to place a cover portion COP to cover the connection circuit board CF and the main circuit board MB. One side of the cover portion COP can contact the lower surface WM-BS of the window WM, and the other side of the cover portion COP (opposite to this side) can contact the rear surface CP-BS of the cover plate CP. A first pressure F1 can be applied to this side of the cover portion COP to attach this side of the cover portion COP to the lower surface WM-BS of the window WM, and a second pressure F2 can be applied to this other side of the cover portion COP to attach this other side of the cover portion COP to the rear surface CP-BS of the cover plate CP.

[0157] According to embodiments of this disclosure, the covering portion COP can cover the driver chip DIC (e.g., overlap with the driver chip DIC). Specifically, the covering portion COP can cover the driver chip DIC in a direction opposite to the first direction DR1 (e.g., overlap with the driver chip DIC). The covering portion COP can protect the driver chip DIC from external static electricity.

[0158] If the cover portion COP is formed before the window WM is formed and is placed between the window WM and the display module DM, it may be difficult to remove the cover portion COP when a defect occurs in the cover portion COP.

[0159] According to embodiments of this disclosure, after forming the window WM on the optical layer RPL, the cover portion COP can be formed. In this case, even if defects are detected in the cover portion COP after inspection for defects, it becomes easier to separate the cover portion COP from the lower surface WM-BS of the window WM and the rear surface CP-BS of the cover plate CP, and it also becomes easier to reattach the cover portion COP to the lower surface WM-BS of the window WM and the rear surface CP-BS of the cover plate CP. As a result, the manufacturing yield of the display device DD (refer to FIG. 2) of this disclosure can be improved.

[0160] While non-limiting exemplary embodiments of this disclosure have been described above, it should be understood that this disclosure is not limited to these exemplary embodiments. Various changes and modifications can be made by those skilled in the art, and such changes and modifications are included within the spirit and scope of the claimed disclosure. Therefore, this disclosure is not limited to any single embodiment described herein.

Claims

1. A display device, comprising: The display extends at least partially in a first direction and in a second direction intersecting the first direction; The window is positioned on the display in a third direction intersecting the first and second directions; A connecting circuit board is connected to the display on a first side of the display; a main circuit board is located on the rear surface of the display in a fourth direction opposite to the third direction and is connected to the connecting circuit board. And a cover portion that overlaps with the connecting circuit board and the main circuit board, wherein a first side of the cover portion contacts the lower surface of the window in the fourth direction.

2. The display device according to claim 1, further comprising: A cover plate, located below the display in the fourth direction.

3. The display device according to claim 2, wherein, The second side of the covering portion, opposite to the first side of the covering portion, contacts the lower surface of the covering plate in the fourth direction.

4. The display device according to claim 1, wherein, The window includes a transmissive area and a border area that at least partially surrounds the transmissive area, and the first side of the covered portion overlaps with the border area.

5. The display device according to claim 1, further comprising: An optical layer is located between the display and the window.

6. The display device according to claim 1, wherein, The display includes: a display area; and a non-display area, at least partially surrounding the display area, and wherein the display device further includes: a driver chip in the non-display area.

7. The display device according to claim 6, wherein, The window includes a first edge, the display includes a second edge, and the first edge protrudes outward from the second edge in a fifth direction opposite to the first direction.

8. The display device according to claim 7, wherein, The covered portion overlaps with the driver chip in the fifth direction, which is opposite to the first direction.

9. The display device according to claim 1, wherein, The covered portion is in contact with the connecting circuit board and the main circuit board.

10. The display device according to claim 1, wherein, The covering portion includes a metallic material.

11. An electronic device comprising: shell; The electronic module is located within the housing. And a display device according to any one of claims 1 to 5, 9 and 10, overlapping with the electronic module.

12. The electronic device according to claim 11, wherein, The electronic module includes an antenna, wherein the display device further includes a driver chip on one side of the display, and wherein the covering portion prevents the connection circuit board, the main circuit board and the driver chip from being exposed to the antenna.

13. A method for manufacturing a display device, comprising: A display and a main circuit board are connected to a connecting circuit board, wherein the display extends at least partially in a first direction and a second direction intersecting the first direction, the main circuit board is on the rear surface of the display, and the connection includes: connecting the connecting circuit board and the display on one side of the display; and bending the connecting circuit board, wherein the bent connecting circuit board connects the display to the main circuit board; placing a window on the display with a third direction intersecting the first and second directions facing upwards; and placing a cover portion such that the cover portion overlaps with the connecting circuit board and the main circuit board.

14. The method according to claim 13, wherein, The placement of the cover portion includes: bringing a first side of the cover portion into contact with the lower surface of the window in a fourth direction opposite to the third direction.

15. The method according to claim 14, wherein, The covered portion is in contact with the connecting circuit board and the main circuit board.

16. The method of claim 14, further comprising: The cover plate is placed under the display in the fourth direction.

17. The method according to claim 16, wherein, The placement of the covering portion further includes: in the fourth direction, making a second side of the covering portion opposite to the first side of the covering portion contact the lower surface of the cover plate.

18. The method of claim 13, further comprising: An optical layer is placed between the display and the window.

19. The method of claim 13, further comprising: A driver chip is placed prior to the placement of the window, wherein the display includes a display area and a non-display area at least partially surrounding the display area, and wherein the driver chip is located in the non-display area.

20. The method according to any one of claims 13 to 19, further comprising: Check the covered area for defects.

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