Silicon carbide gate oxide layer, preparation method thereof and semiconductor device
By employing nitrogen-containing atmosphere oxidation, bias temperature stress treatment, wet etching, and annealing during the fabrication of the silicon carbide gate oxide layer, the threshold voltage instability problem of silicon carbide gate control devices was solved, resulting in higher breakdown field strength and more stable threshold voltage.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BEIJING SMART ENERGY RES INST
- Filing Date
- 2025-12-29
- Publication Date
- 2026-05-01
AI Technical Summary
The threshold voltage of silicon carbide gate-controlled devices is unstable, especially in high temperature and high field environments, which affects the long-term service life and switching performance of the devices. This is mainly due to mobile ions and defects in the gate oxide layer.
A high-quality gate oxide film is formed by performing oxidation treatment in a nitrogen-containing atmosphere, combined with bias temperature stress treatment, wet etching and annealing, which reduces mobile ions and defects and improves threshold voltage stability.
The silicon carbide gate oxide layer prepared by this method significantly reduces the number of mobile ions, improves the stability of breakdown field strength and threshold voltage, and enhances the long-term performance of the device.
Smart Images
Figure CN121968674A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and in particular to silicon carbide gate oxide layers and their preparation methods, and semiconductor devices. Background Technology
[0002] With advancements in semiconductor materials and device manufacturing technologies, silicon-based power electronic devices are approaching the theoretical limits determined by material properties. Compared to traditional silicon-based materials, silicon carbide (SiC) materials offer advantages such as a large bandgap, high thermal conductivity, high saturated electron drift velocity, and high breakdown field strength, making them an excellent choice for high-temperature, high-frequency, and high-power applications. They have wide applications in electric vehicles, aerospace, and power conversion. However, compared to mature silicon-based technologies, the large-scale application of SiC power devices, especially SiC MOSFETs, still faces a key bottleneck: unstable threshold voltage. This problem is particularly pronounced when devices operate under high-temperature and high-field conditions for extended periods, directly limiting the device's long-term lifespan and switching performance.
[0003] Studies show that gate interface charge affects the threshold voltage stability of silicon carbide gate-controlled devices. Currently, the main processes for reducing mobile charge generation are RCA cleaning or adjustments to the RCA cleaning process, such as introducing O3 to clean the silicon carbide wafer surface. However, after the formation of the silicon carbide gate oxide layer, the number of mobile ions and defects on its surface remains relatively high, resulting in unstable threshold voltage in the obtained device. Summary of the Invention
[0004] Therefore, it is necessary to provide a silicon carbide gate oxide layer that can effectively remove mobile ions and gate oxide defects in the gate oxide film, as well as a method for preparing the same and a semiconductor device.
[0005] In a first aspect, this application provides a method for preparing a silicon carbide gate oxide layer.
[0006] A method for preparing a silicon carbide gate oxide layer includes the following steps:
[0007] A silicon carbide epitaxial wafer is oxidized in a nitrogen-containing atmosphere to form a gate oxide film on the surface of the silicon carbide epitaxial wafer, thereby forming a first structure.
[0008] The first structure is subjected to bias temperature stress treatment to prepare the second structure;
[0009] The second structure is wet-etched to prepare the third structure;
[0010] The third structure is then subjected to annealing.
[0011] In some embodiments, the oxidation treatment is performed at a temperature of 1400°C to 1600°C; and / or
[0012] The oxidation treatment time is 5 min to 60 min.
[0013] In some embodiments, the nitrogen-containing atmosphere includes one or more of NO and N2O; or, the nitrogen-containing atmosphere includes N2 and one or more of NO and N2O.
[0014] In some embodiments, the electric field strength of the bias temperature stress treatment is -2.5MV / cm to -9MV / cm.
[0015] In some embodiments, the temperature of the bias temperature stress treatment is 150°C to 250°C;
[0016] And / or, the bias temperature stress treatment time is 5 min to 15 min.
[0017] In some embodiments, the annealing temperature is 1150°C to 1300°C; and / or
[0018] The annealing process takes 60 to 120 minutes.
[0019] In some embodiments, the depth of the wet etching is 5 nm to 20 nm.
[0020] In some embodiments, the silicon carbide epitaxial wafer includes an n-type 4H-SiC epitaxial wafer, wherein the crystal plane of the silicon carbide epitaxial wafer is the (0001)Si plane.
[0021] In a second aspect, this application provides a silicon carbide gate oxide layer. The silicon carbide gate oxide layer is prepared using the preparation method described above.
[0022] A third aspect of this application provides a semiconductor device. The semiconductor device comprises a silicon carbide gate oxide layer as described above.
[0023] The aforementioned method for fabricating a silicon carbide gate oxide layer involves oxidation under a nitrogen-containing atmosphere, resulting in a gate oxide film with few gate oxide defects and good uniformity. Further, combining this with bias temperature stress treatment allows surface impurities to migrate outwards, which are then removed by wet etching, effectively reducing the number of mobile ions in the gate oxide film. Moreover, post-etching oxidation annealing further reduces gate oxide defects and improves the quality of the gate oxide film, ultimately yielding a gate oxide film with low effective charge density and high breakdown field strength. Semiconductor devices fabricated using this silicon carbide gate oxide layer exhibit more stable threshold voltages. Attached Figure Description
[0024] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0025] Figure 1 This is a schematic diagram of the steps in a method for preparing a silicon carbide gate oxide layer according to an embodiment of this application.
[0026] Figure 2 These are characteristic curves showing the leakage current density of the silicon carbide gate oxide layer as a function of electric field strength in Embodiment 1 and Comparative Example 1 of this application. Detailed Implementation
[0027] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, a detailed description of specific embodiments of this application is provided below. Many specific details are set forth in the following description to provide a thorough understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.
[0028] In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. In this application, "at least one" means one or more, such as one, two, or more than two. "Multiple" or "several" means at least two, such as two, three, etc.
[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.
[0030] When a numerical range is disclosed herein, the range is considered continuous and includes the minimum and maximum values of the range, as well as every value between the minimum and maximum values. Furthermore, when the range refers to integers, it includes every integer between the minimum and maximum values of the range. Additionally, when multiple ranges are provided to describe a feature or characteristic, the ranges may be combined. In other words, unless otherwise specified, all ranges disclosed herein should be understood to include any and all subranges to which they are incorporated.
[0031] Unless otherwise specified, all steps in this application may be performed sequentially or randomly. For example, the method includes steps (a) and (b), indicating that the method may include steps (a) and (b) performed sequentially, or it may include steps (b) and (a) performed sequentially. For example, the method may also include step (c), indicating that step (c) may be added to the method in any order. For example, the method may include steps (a), (b), and (c), or it may include steps (a), (c), and (b), or it may include steps (c), (a), and (b), etc.
[0032] In this application, "above" or "below" includes the number itself. For example, "below 1" includes 1.
[0033] Unless otherwise specified, the temperature parameters in this application are permitted to be either constant-temperature treatment or variations within a certain temperature range. It should be understood that the constant-temperature treatment allows temperature fluctuations within the precision range of the instrument control, such as ±5℃, ±4℃, ±3℃, ±2℃, or ±1℃.
[0034] Silicon carbide materials have advantages such as large bandgap, high thermal conductivity, high saturated electron drift velocity and high breakdown field strength, but the threshold voltage of the resulting devices is unstable.
[0035] Studies show that the threshold voltage stability of silicon carbide gate-controlled devices is affected by oxide traps, near-interface traps, interface traps, and mobile ions. The closer these factors are to the interface between the device channel and the gate oxide film, the greater their adverse effects. Oxide traps are formed due to inherent oxidation defects in silicon dioxide (SiO2) and residual carbon monoxide (CO) during growth. These traps can be captured through particle radiation, hot carrier injection, and Fowler-Nordheim (FN) tunneling. Located within the gate oxide layer, oxide traps have large capture and release time constants, primarily affecting the long-term stability of the threshold voltage and the reliability of the gate oxide in silicon carbide gate-controlled devices. Near-interface traps are located in the transition layer region a few nanometers thick between SiC and SiO2. These traps mainly originate from oxygen vacancy defects near the interface. The formation of these oxygen vacancies is caused by an imbalance in the ratio of silicon to oxygen in the transition layer. Compared to oxide traps, near-interface traps have shorter capture and release time constants, making them easier to capture and release. Movable ions are usually caused by metal contamination during the device fabrication process. A common movable ion in gate oxide films is K+. + and Na +Besides external metal contamination, the dry oxidation and post-oxidation annealing processes of SiC substrates can also lead to the generation of mobile ions in devices. During normal operation of silicon carbide gate-controlled devices, interface charges and near-interface trapped charges trap electrons and holes, causing threshold voltage drift. Oxide layer trapped charges trap electrons and holes under high temperature and high electric field, resulting in increased gate oxide leakage current and permanent threshold voltage drift. Mobile ions migrate under high temperature and high electric field, affecting threshold voltage drift.
[0036] Based on this, in a first aspect, this application provides a method for preparing a silicon carbide gate oxide layer that can effectively remove mobile ions and gate oxide defects in the gate oxide film, so as to obtain a semiconductor device with low threshold voltage drift.
[0037] For example, please see Figure 1 , Figure 1 This is a schematic diagram illustrating the steps involved in fabricating a silicon carbide gate oxide layer. (Refer to...) Figure 1 As shown, the method for preparing the silicon carbide gate oxide layer includes steps S1 to S4, specifically including:
[0038] Step S1: Oxidize the silicon carbide epitaxial wafer under a nitrogen-containing atmosphere to prepare a gate oxide film on the surface of the silicon carbide epitaxial wafer, forming the first structure.
[0039] Step S2: Apply bias temperature stress treatment to the first structure to prepare the second structure.
[0040] Step S3: Perform wet etching on the second structure to prepare the third structure. During the dry etching plasma process, a certain current will flow through the gate oxide layer. This charging current will cause new oxide layer traps and interface states. In this embodiment, wet etching can avoid damage to the oxide layer caused by the etching step.
[0041] Step S4: Anneal the third structure.
[0042] The aforementioned method for fabricating a silicon carbide gate oxide layer involves oxidation under a nitrogen-containing atmosphere, resulting in a gate oxide film with few gate oxide defects and good uniformity. Further, combining this with bias temperature stress treatment allows surface impurities to migrate outwards, which are then removed by wet etching, effectively reducing the number of mobile ions in the gate oxide film. Furthermore, post-etching oxidation annealing further reduces gate oxide defects and improves the quality of the gate oxide film, ultimately yielding a gate oxide film with low effective charge density and high breakdown field strength. Semiconductor devices fabricated using this silicon carbide gate oxide layer exhibit more stable threshold voltages.
[0043] In some embodiments, the wet etching solution includes a buffered oxide etchant. Optionally, the mixing ratio of hydrofluoric acid and ammonium fluoride is 1:(5~8).
[0044] In some embodiments, the oxidation temperature in step S1 is 1400°C to 1600°C. Optionally, the oxidation temperature can be, but is not limited to, 1400°C, 1450°C, 1500°C, 1550°C, 1600°C, or other values within the range of 1400°C to 1600°C. Maintaining the aforementioned higher processing temperature helps reduce defects in the oxide layer. Furthermore, when the oxidizing gas is NO, excessively long oxidation times can lead to defects in the oxide layer and exacerbate negative bias temperature instability (NBTI). Increasing the oxidation temperature helps shorten the oxidation time, thereby avoiding adverse effects.
[0045] In some embodiments, the oxidation treatment time in step S1 is 5 min to 60 min. Optionally, the oxidation treatment time can be, but is not limited to, 5 min, 10 min, 15 min, 20 min, 25 min, 30 min, 35 min, 40 min, 45 min, 50 min, 55 min, 60 min, or other values within the range of 5 min to 60 min. Further, the oxidation treatment time is 5 min to 20 min. Studies have shown that selecting a high temperature and a short treatment time helps to reduce gate oxide defects and improve the quality of the gate oxide film.
[0046] In some embodiments, in step S1, the nitrogen-containing atmosphere includes one or more of NO and N2O. Alternatively, the nitrogen-containing atmosphere may include N2 and one or more of NO and N2O. It is understood that the nitrogen-containing atmosphere may include N2 and NO, or N2 and N2O, or N2, NO, and N2O. Oxidation treatment under a nitrogen-containing atmosphere is more conducive to forming a gate oxide film with fewer defects. Further, the nitrogen-containing atmosphere contains NO. Oxidation using NO gas helps to improve the gate oxide quality, reduce defects in the oxide film, and effectively suppress positive bias temperature instability (PBTI).
[0047] In some embodiments, the electric field strength for the bias temperature stress treatment in step S2 is -2.5 MV / cm to -9 MV / cm. Optionally, the electric field strength for the bias temperature stress treatment can be, but is not limited to, values within the range of -2.5 MV / cm, -3 MV / cm, -3.5 MV / cm, -4 MV / cm, -5 MV / cm, -6 MV / cm, -7 MV / cm, -8 MV / cm, -9 MV / cm, or other values within the range of -2.5 MV / cm to -9 MV / cm. Maintaining the above-mentioned electric field strength can effectively facilitate the migration of mobile ions to the surface of the gate oxide film. The electric field strength for the bias temperature stress treatment should not be too large, otherwise it may easily cause breakdown damage to the gate oxide layer.
[0048] In some embodiments, the bias temperature stress treatment temperature in step S2 is 150°C to 250°C. Optionally, the bias temperature stress treatment temperature can be, but is not limited to, 150°C, 175°C, 200°C, 225°C, 250°C, or other values within the range of 150°C to 250°C. If the bias temperature stress treatment temperature is too low, a large number of mobile ions cannot move; if the bias temperature stress treatment temperature is too high, the applied electrical stress at high temperatures accelerates the aging of the gate oxide layer and easily damages the gate oxide layer and interface.
[0049] In some embodiments, the bias temperature stress treatment time in step S2 is 5 min to 15 min. Optionally, the bias temperature stress treatment time can be, but is not limited to, 5 min, 6 min, 7 min, 8 min, 9 min, 10 min, 11 min, 12 min, 13 min, 14 min, 15 min, or other values within the range of 5 min to 15 min. Maintaining the above temperature and time during the bias temperature stress treatment is more conducive to the migration of mobile ions to the surface of the gate oxide film.
[0050] In some embodiments, in step S2, a bias temperature stress is applied using a device equipped with plasma. This allows for the application of electrical stress to the sample without the need for electrode fabrication.
[0051] In some embodiments, the depth of wet etching in step S3 is 5nm to 20nm. Optionally, it can be, but is not limited to, 5nm, 6nm, 7nm, 8nm, 9nm, 10nm, 12nm, 14nm, 16nm, 18nm, 20nm, or other values within the range of 5nm to 20nm. After maintaining the above-mentioned bias temperature stress treatment, wet etching is used to remove the oxide layer on the surface, which can effectively remove mobile ions and help reduce the impact of bias temperature stress treatment on the surface, further reducing gate oxide defects.
[0052] In some embodiments, in step S4, the annealing atmosphere includes one or more of NO and N2O. Alternatively, the annealing atmosphere includes N2 and one or more of NO and N2O. It is understood that the annealing atmosphere may include N2 and NO, or N2 and N2O, or N2, NO, and N2O. Annealing in the above-mentioned nitrogen-containing atmosphere is more conducive to passivating defects and forming a gate oxide film with fewer defects.
[0053] In some embodiments, the annealing temperature in step S4 is 1150°C to 1300°C. Optionally, the annealing temperature can be, but is not limited to, 1150°C, 1200°C, 1250°C, 1300°C, or other values within the range of 1150°C to 1300°C. If the annealing temperature is too low, the passivation time will be too long; if the annealing temperature is too high, a large amount of NO or N2O gas will decompose, reducing the passivation effect and increasing interface defects. Maintaining the above-mentioned annealing temperature can effectively reduce gate oxide defects and improve the quality of the gate oxide film.
[0054] In some embodiments, the annealing time in step S4 is 60 min to 120 min. Optionally, the annealing time can be, but is not limited to, 60 min, 70 min, 80 min, 90 min, 100 min, 110 min, 120 min, or other values within the range of 60 min to 120 min. If the annealing time is too short, the passivation effect will be insufficient, resulting in too many interface defects and low migration rate; if the annealing time is too long, defects in the oxide layer are likely to occur, exacerbating the instability of the negative bias temperature.
[0055] In some embodiments, the silicon carbide epitaxial wafer is a 4H-SiC epitaxial wafer. 4H-SiC epitaxial wafers have a low lattice constant and high electron mobility and saturation electron velocity, making them ideal materials for high-frequency and high-power devices. Further, the silicon carbide epitaxial wafer is an n-type 4H-SiC epitaxial wafer. Since SiC gate devices are N-type, the silicon carbide epitaxial wafer can be an n-type 4H-SiC epitaxial wafer. Further, the crystal plane of the silicon carbide epitaxial wafer is the (0001) Si plane.
[0056] In a second aspect, this application provides a silicon carbide gate oxide layer. The silicon carbide gate oxide layer is prepared using the preparation method described above.
[0057] A third aspect of this application provides a semiconductor device. The semiconductor device comprises a silicon carbide gate oxide layer as described above. In some embodiments, the semiconductor device includes a SiC MOSFET.
[0058] The present application will be further described in detail below with reference to specific embodiments.
[0059] Unless otherwise specified, the raw materials used in the following specific embodiments and comparative examples are all commercially available products; the instruments used are all commercially available products; and the processes used are all conventionally selected by those skilled in the art unless otherwise specified.
[0060] Example 1
[0061] This embodiment provides a silicon carbide gate oxide layer.
[0062] The method for preparing the silicon carbide gate oxide layer is as follows:
[0063] An n-type 4H-SiC silicon carbide epitaxial wafer was obtained. The silicon carbide epitaxial wafer was then subjected to oxidation treatment in an atmosphere of NO, at a temperature of 1450℃, and for 10 minutes to form the first structure.
[0064] The first structure was subjected to bias temperature stress treatment using PECVD. The electric field strength of the bias temperature stress treatment was 3MV / cm, the temperature was 200℃, and the time was 5min, thus forming the second structure.
[0065] The second structure was wet-etched to remove a 10nm surface oxide layer, yielding the third structure.
[0066] The third structure was annealed in an atmosphere of NO at a temperature of 1250°C for 90 minutes to obtain a silicon carbide gate oxide layer.
[0067] Example 2
[0068] This embodiment provides a silicon carbide gate oxide layer.
[0069] The method for preparing the silicon carbide gate oxide layer is as follows:
[0070] An n-type 4H-SiC silicon carbide epitaxial wafer was obtained. The silicon carbide epitaxial wafer was then subjected to oxidation treatment in an atmosphere of NO, at a temperature of 1250℃, and for a time of 390 min to form the first structure.
[0071] The first structure was subjected to bias temperature stress treatment using PECVD. The electric field strength of the bias temperature stress treatment was 3MV / cm, the temperature was 200℃, and the time was 5min, thus forming the second structure.
[0072] The second structure was wet-etched to remove a 10nm surface oxide layer, yielding the third structure.
[0073] The third structure was annealed in an atmosphere of NO at a temperature of 1250°C for 90 minutes to obtain a silicon carbide gate oxide layer.
[0074] Example 3
[0075] This embodiment provides a silicon carbide gate oxide layer.
[0076] The difference between the method for preparing the silicon carbide gate oxide layer and Example 1 is that the first structure is subjected to bias temperature stress treatment by PECVD. The electric field strength of the bias temperature stress treatment is 3MV / cm, the temperature is 50℃, and the time is 5min, thus forming the second structure.
[0077] Comparative Example 1
[0078] This comparative example provides a silicon carbide gate oxide layer.
[0079] The method for preparing the silicon carbide gate oxide layer is as follows:
[0080] An n-type 4H-SiC silicon carbide epitaxial wafer was obtained. The silicon carbide epitaxial wafer was then subjected to oxidation treatment in an O2 atmosphere at a temperature of 1200℃ for 150 min to form the first structure.
[0081] The first structure was annealed in an atmosphere of NO at a temperature of 1250°C for 90 minutes to obtain a silicon carbide gate oxide layer.
[0082] Comparative Example 2
[0083] This comparative example provides a silicon carbide gate oxide layer.
[0084] The method for preparing the silicon carbide gate oxide layer is as follows:
[0085] An n-type 4H-SiC silicon carbide epitaxial wafer was obtained. The silicon carbide epitaxial wafer was then subjected to oxidation treatment in an atmosphere of NO, at a temperature of 1450℃, and for 10 minutes to form the first structure.
[0086] The first structure was subjected to wet etching to remove a 10nm surface oxide layer, resulting in the third structure.
[0087] The third structure was annealed in an atmosphere of NO at a temperature of 1250°C for 90 minutes to obtain a silicon carbide gate oxide layer.
[0088] Comparative Example 3
[0089] This comparative example provides a silicon carbide gate oxide layer.
[0090] The method for preparing the silicon carbide gate oxide layer is as follows:
[0091] An n-type 4H-SiC silicon carbide epitaxial wafer was obtained. The silicon carbide epitaxial wafer was then subjected to oxidation treatment in an atmosphere of NO, at a temperature of 1450℃, and for 10 minutes to form the first structure.
[0092] The first structure was subjected to bias temperature stress treatment using PECVD. The electric field strength of the bias temperature stress treatment was 3MV / cm, the temperature was 200℃, and the time was 5min, thus forming the second structure.
[0093] The second structure was annealed in an atmosphere of NO at a temperature of 1250°C for 90 minutes to obtain a silicon carbide gate oxide layer.
[0094] Comparative Example 4
[0095] This comparative example provides a silicon carbide gate oxide layer.
[0096] The method for preparing the silicon carbide gate oxide layer is as follows:
[0097] An n-type 4H-SiC silicon carbide epitaxial wafer was obtained. The silicon carbide epitaxial wafer was then subjected to oxidation treatment in an atmosphere of NO, at a temperature of 1450℃, and for 10 minutes to form the first structure.
[0098] The first structure was annealed in an atmosphere of NO at a temperature of 1250°C for 90 minutes to obtain a silicon carbide gate oxide layer.
[0099] Test case
[0100] Performance tests were performed on the silicon carbide gate oxide layers of the embodiments and comparative examples. The test results are shown in Table 1 and... Figure 2 , Figure 2 These are characteristic curves showing the leakage current density of the silicon carbide gate oxide layer as a function of electric field strength in Embodiment 1 and Comparative Example 1 of this application.
[0101] The performance testing method is as follows:
[0102] Gate oxide breakdown field strength test method: The Agilent B1505A semiconductor parameter analyzer is used to test the sample. The voltage is applied from 0V until the current of the sample gate oxide layer increases instantaneously to the instrument's test limit current. The sample current-voltage (IV) characteristic curve is obtained. Based on the curve, the sample current density-electric field strength (JE) characteristic curve is obtained to obtain the gate oxide breakdown field strength.
[0103] Gate oxide charge density testing method: The Agilent B1505A semiconductor parameter analyzer was used to perform capacitance-voltage (CV) tests on the sample to obtain CV characteristic curves at quasi-static and high frequency (1MHz) conditions. The gate oxide charge density was calculated based on the curves.
[0104] The threshold voltage drift (bias temperature instability test) shall be performed in accordance with the national standard GB / T 45716-2025.
[0105] Table 1 Performance test results of the examples and comparative examples
[0106]
[0107] As shown in Table 1, the method for preparing the silicon carbide gate oxide layer of this application can effectively reduce the number of mobile ions in the gate oxide film and increase the breakdown field strength. Semiconductor devices prepared using this silicon carbide gate oxide layer can have a more stable threshold voltage.
[0108] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0109] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this invention patent should be determined by the appended claims, and the specification can be used to interpret the content of the claims.
Claims
1. A method for preparing a silicon carbide gate oxide layer, characterized in that, Includes the following steps: A silicon carbide epitaxial wafer is oxidized in a nitrogen-containing atmosphere to form a gate oxide film on the surface of the silicon carbide epitaxial wafer, thereby forming a first structure. The first structure is subjected to bias temperature stress treatment to prepare the second structure; The second structure is wet-etched to prepare the third structure; The third structure is then subjected to annealing.
2. The method for preparing the silicon carbide gate oxide layer according to claim 1, characterized in that, The oxidation treatment temperature is 1400℃~1600℃; and / or The oxidation treatment time is 5 min to 60 min.
3. The method for preparing the silicon carbide gate oxide layer according to claim 1, characterized in that, The nitrogen-containing atmosphere includes one or more of NO and N2O; or, The nitrogen-containing atmosphere includes N2, and one or more of NO and N2O.
4. The method for preparing the silicon carbide gate oxide layer according to claim 1, characterized in that, The electric field strength of the bias temperature stress treatment is -2.5MV / cm to -9MV / cm.
5. The method for preparing the silicon carbide gate oxide layer according to claim 4, characterized in that, The temperature of the bias temperature stress treatment is 150℃~250℃; and / or The bias temperature stress treatment time is 5 min to 15 min.
6. The method for preparing the silicon carbide gate oxide layer according to claim 1, characterized in that, The annealing temperature is 1150℃~1300℃; and / or The annealing process takes 60 to 120 minutes.
7. The method for preparing the silicon carbide gate oxide layer according to any one of claims 1 to 6, characterized in that, The depth of the wet etching is 5nm~20nm.
8. The method for preparing the silicon carbide gate oxide layer according to any one of claims 1 to 6, characterized in that, The silicon carbide epitaxial wafer includes an n-type 4H-SiC epitaxial wafer, and the crystal plane of the silicon carbide epitaxial wafer is the (0001)Si plane.
9. A silicon carbide gate oxide layer, characterized in that, It is prepared by the preparation method according to any one of claims 1 to 8.
10. A semiconductor device, characterized in that, Includes the silicon carbide gate oxide layer as described in claim 9.