RC-IGBT device structure and manufacturing method thereof
By introducing a deep P+ trench design and precise matching of the P+/N+ regions on the back side in the RC-IGBT device, the current path is optimized, solving the performance balance and coupling problem of the RC-IGBT device, and achieving high-efficiency operation with small size, high power density and low loss.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- JINAN QIANRUI XINGUANG NETWORK TECHNOLOGY PARTNERSHIP (GENERAL PARTNERSHIP)
- Filing Date
- 2026-01-28
- Publication Date
- 2026-05-01
AI Technical Summary
Existing RC-IGBT devices face challenges in integrated design regarding functional coupling and performance balance, making it difficult to achieve simultaneous optimization of IGBT and FRD. They also suffer from low cell density, large chip area, long current path, and high losses.
By generating a deep trench P+ region in the P-Body region of the IGBT, the P-Body region is reused as the anode of the FRD. Through the reasonable layout of the P+/N+ regions on the back side, the current path is optimized. Combined with the Trench gate structure, a three-dimensional deep trench depletion layer is formed, which shortens the conduction path, improves the current carrying capacity and reduces losses.
This achieves efficient operation with small size, high power density, and low loss, meeting the needs of high-frequency power conversion in new energy and industrial applications, and improving the stability and reliability of the devices.
Smart Images
Figure CN121968683A_ABST
Abstract
Description
An RC-IGBT device structure and its fabrication method Technical Field
[0001] This invention relates to the field of semiconductor technology, specifically to an RC-IGBT device structure and its fabrication method. Background Technology
[0002] RC-IGBT is a composite power semiconductor device that integrates IGBT and FRD on a single chip. With the structural advantage of "single-chip integration of dual functions", it is widely used in medium and high voltage and high current power conversion scenarios such as inverters for new energy vehicles, industrial frequency converters, energy storage converters and rail transit traction converters. Compared with the traditional combination of IGBT + discrete FRD, RC-IGBT can significantly simplify the circuit topology, reduce the device package size, reduce parasitic inductance and thermal resistance, and improve the system power density and integration.
[0003] With the increasing demand for high integration, high efficiency, and high reliability in power conversion systems in the fields of new energy and industrial automation, RC-IGBTs, as core switching components, directly determine the power density, heat dissipation efficiency, and cost control of the system. Especially in space- and weight-sensitive scenarios such as main inverters for new energy vehicles and energy storage converters, the forward conduction voltage drop, reverse recovery characteristics, switching losses, and maximum withstand junction temperature of RC-IGBTs have become key indicators affecting the overall performance of the system. For example, a lower VCE(sat) can reduce conduction losses, better reverse recovery characteristics can reduce additional losses during the switching process, and a higher Tj can improve the stability of the device under high load conditions.
[0004] However, traditional RC-IGBTs face the core challenge of functional coupling and performance balance in integrated design. On the one hand, IGBTs and FRDs share the same substrate and drift region, and their carrier distributions affect each other. If the doping concentration of the drift region is increased to optimize the on-state voltage drop of the IGBT, the reverse breakdown voltage of the FRD will decrease. Conversely, if the drift region is thinned to improve the reverse breakdown voltage of the FRD, the conduction loss of the IGBT will increase. It is difficult to achieve synchronous optimization of the performance of the two. On the other hand, under high-frequency switching conditions, the reverse recovery process of the integrated FRD is prone to coupling interference with the switching process of the IGBT, causing voltage overshoot and electromagnetic oscillation. Especially under high-current conditions, it may increase the risk of dynamic avalanche breakdown of the device. In addition, the heat concentration effect of a single chip is more significant. If the heat dissipation design is insufficient, it will accelerate device aging and shorten its service life.
[0005] Currently, the industry mainly optimizes RC-IGBT performance through three major technical paths: first, adopting an asymmetric drift region doping design to balance the IGBT on-state voltage drop and FRD reverse breakdown voltage through gradient doping processes; second, introducing carrier lifetime control technology to precisely regulate the carrier recombination rate in the IGBT and FRD regions, simultaneously improving switching speed and reverse recovery characteristics; and third, improving the chip structure to reduce functional coupling interference between the two and enhance dynamic reliability. However, existing solutions still have limitations. For example, lifetime control technology may lead to a decrease in device high-temperature stability, and structural improvements will increase process complexity and cost. Therefore, developing a new RC-IGBT integrated structure with low coupling and high compatibility, which can decouple and optimize the performance of IGBT and FRD while taking into account low cost and high reliability, has become the core direction for adapting to the high-frequency power conversion needs of new energy and industrial applications. Summary of the Invention
[0006] To address the shortcomings of existing technologies, this invention provides an RC-IGBT device structure and its fabrication method, which solves the problems of low cell density, large chip area, long current path, and high loss in existing RC-IGBTs.
[0007] To achieve the above objectives, the present invention is implemented through the following technical solution: an RC-IGBT device structure and its fabrication method, comprising: a wafer, wherein a back metal layer is disposed at the bottom of the wafer, an FRD cathode is disposed at the top of the back metal layer, a collector is disposed on the outside of the FRD cathode, the top of the collector is in contact with a buffer layer, and a cell region is disposed at the top of the wafer;
[0008] The cell region includes:
[0009] The front metal layer is located on the top of the wafer, and there are multiple front metal layers distributed horizontally.
[0010] The P-Body area is located at the bottom of the front metal layer and corresponds one-to-one with the front metal layer.
[0011] The carrier storage layer is located at the bottom of the P-Body region and corresponds one-to-one with the P-Body region.
[0012] Trench gate structure, the Trench gate structure is located outside the carrier storage layer and corresponds one-to-one with the carrier storage layer;
[0013] The outer side of the N-source region is in contact with the Trench gate structure. The N-source region is located near the top of the wafer and inside the P-Body region.
[0014] The P-type deep trench region is located inside the P-Body region, and its lower end penetrates the carrier storage layer and extends downward. There are multiple P-type deep trench regions, which are horizontally equidistantly distributed.
[0015] Preferably, the top of the FRD cathode is in contact with the buffer layer.
[0016] Preferably, the number of FRD cathodes is multiple and they are horizontally equidistant, and the number of collectors is multiple and they are located outside the FRD cathodes respectively.
[0017] Preferably, the number of N-source regions is multiple and they are symmetrically distributed on the left and right ends near the bottom of the front metal layer.
[0018] Preferably, the Trench gate structure consists of a gate oxide layer and a gate polycrystalline layer, wherein the outer side of the gate oxide layer is in contact with the carrier storage layer, and the gate polycrystalline layer is located inside the gate oxide layer.
[0019] A method for fabricating an RC-IGBT device, based on any one of the RC-IGBT device structures described above, includes the following steps:
[0020] S1. First, heavily doped P-type implants are generated on the front side of the N-type epitaxial layer to form a deep P-type trench region, which serves as the anode of the FRD.
[0021] S2. Then, N-type implantation is generated on the front side of the wafer to form the carrier storage layer of the IGBT.
[0022] S3. Then, P-type implantation with intermediate doping is generated on the front side of the wafer to form the P-Body region of the IGBT;
[0023] S4. Deep trench etching is performed on the surface to generate a gate oxide layer and deposit gate polycrystalline material, forming a Trench gate structure.
[0024] S5. Then, a heavily doped N-type implant is generated in the P-Body region to form a heavily doped N-source region, which serves as the emitter of the IGBT.
[0025] S6. Deposit a front metal layer on the front side of the wafer to serve as the emitter of the IGBT and the anode of the FRD;
[0026] S7. After wafer thinning, heavily doped N-type implantation is performed on the back side as a buffer layer for IGBTs.
[0027] S8. Photolithography on the back of the wafer, performing heavily doped N-type implantation and heavily doped P-type implantation respectively to form the IGBT collector and FRD cathode;
[0028] S9. Deposit a back metal layer on the back side of the wafer to serve as the collector of the IGBT and the cathode of the FRD.
[0029] This invention provides an RC-IGBT device structure and its fabrication method. It has the following beneficial effects:
[0030] This RC-IGBT device structure and fabrication method, by generating a deep trench P+ region in the P-Body region of the IGBT and reusing the P-Body region of the IGBT as the anode of the FRD, increases the IGBT conduction path, reduces the chip area, improves the current carrying capacity, and reduces the IGBT VCE(sat). When the IGBT is forward-biased, the P+ deep trench extending into the N drift region and the lightly injected N drift region form a deep trench depletion layer, which can provide a more concentrated and shorter current path for the IGBTs on both sides of the Trench gate, reducing VCE(sat). When the IGBT is forward-biased, the P+ deep trench extending into the N drift region and the lightly injected N drift region form a 3D deep trench depletion layer, which can improve the IGBT's withstand voltage during forward conduction. During the IGBT turn-off process, the P+ deep trench extending into the N drift region can provide a shorter recovery path for the minority carrier holes concentrated under the carrier layer, accelerating the turn-off speed and reducing losses during the process.
[0031] By rationally arranging the P+ and N+ regions on the back side, the widths of the P+ and N+ regions are each half the pitch of the front cell. This allows the P+ region to act as the collector of the IGBT, directly facing the IGBT current path on both sides of the trench gate after the device is fabricated, effectively shortening the current conduction path and reducing VCEsat. The N+ region, acting as the cathode of the FRD, directly faces the FRD anode formed by the deep P+ trench on the front side, effectively shortening the current conduction path and reducing VF.
[0032] By employing a dual innovation of front-side P-Body reuse with deep P+ trench design and rear-side N+ / P+ wide-range precise matching, the problem of low cell density, large chip area, long current path, and high loss of existing RC-IGBTs is fundamentally solved. This fully meets the power system's requirements for "small size, high power density, low loss, and high efficiency," demonstrating significant technological innovation and application value. Attached Figure Description
[0033] Figure 1 is a schematic diagram of the P-type deep groove region of the present invention;
[0034] Figure 2 is a schematic diagram of the carrier storage layer of the present invention;
[0035] Figure 3 is a schematic diagram of the P-Body region of the present invention;
[0036] Figure 4 is a schematic diagram of the Trench gate structure of the present invention;
[0037] Figure 5 is a schematic diagram of the N-source region of the present invention;
[0038] Figure 6 is a schematic diagram of the front metal layer of the present invention;
[0039] Figure 7 is a schematic diagram of the buffer layer of the present invention;
[0040] Figure 8 is a schematic diagram of the collector and FRD cathode of the present invention;
[0041] Figure 9 is a schematic diagram of the back metal layer of the present invention.
[0042] Among them, 1. wafer; 2. P-type deep trench region; 3. carrier storage layer; 4. P-body region; 5. Trench gate structure; 6. N-source region; 7. front metal layer; 8. buffer layer; 9. collector; 10. FRD cathode; 11. back metal layer; 12. cell region; 13. gate oxide layer; 14. gate polycrystalline. Detailed Implementation
[0043] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0044] Example 1
[0045] As shown in Figure 9, this embodiment of the invention provides an RC-IGBT device structure and its fabrication method, including a wafer 1, a back metal layer 11 disposed at the bottom of the wafer 1, an FRD cathode 10 disposed at the top of the back metal layer 11, a collector 9 disposed on the outside of the FRD cathode 10, the top of the collector 9 being in contact with a buffer layer 8, and a cell region 12 disposed at the top of the wafer 1.
[0046] Cell region 12 includes:
[0047] The front metal layer 7 is located on top of wafer 1, and there are multiple front metal layers 7 distributed horizontally.
[0048] P-Body region 4 is located at the bottom of the front metal layer 7 and corresponds one-to-one with the front metal layer 7.
[0049] Carrier storage layer 3 is located at the bottom of P-Body region 4 and corresponds one-to-one with P-Body region 4.
[0050] Trench gate structure 5 is located outside the carrier storage layer 3 and corresponds one-to-one with the carrier storage layer 3.
[0051] N-source region 6, the outer side of which is in contact with Trench gate structure 5, is located near the top of wafer 1 and inside P-Body region 4.
[0052] P-type deep trench region 2 is located inside P-Body region 4, and its lower end penetrates the carrier storage layer 3 and extends downward. There are multiple P-type deep trench regions 2, which are horizontally equidistantly distributed.
[0053] The top of the FRD cathode 10 is in contact with the buffer layer 8. There are multiple FRD cathodes 10 and they are horizontally equidistantly distributed. There are multiple collectors 9 and they are located on the outside of the FRD cathodes 10. There are multiple N-source regions 6 and they are symmetrically distributed on the left and right ends near the bottom of the front metal layer 7. The Trench gate structure 5 is composed of a gate oxide layer 13 and a gate polycrystalline layer 14. The outside of the gate oxide layer 13 is in contact with the carrier storage layer 3, and the gate polycrystalline layer 14 is located inside the gate oxide layer 13.
[0054] During forward conduction, the Trench gate structure 5 forms a channel after the voltage exceeds the threshold, and electrons are injected into the N-source region 6. At the same time, the P-Body region 4 is reused as the FRD anode. Together with the P-type deep trench region 2 that extends into the N drift region, it forms a three-dimensional deep trench depletion layer with the lightly injected N drift region. This provides a more concentrated and shorter current path for the IGBTs on both sides of the Trench gate and improves the forward withstand voltage. At this time, the carrier storage layer 3 stores charge, and the width of the back p+ collector 9 matches half of the front cell pitch, facing the current path on both sides of the trench gate, further shortening the conduction path and significantly reducing vce(sat). At the same time, the chip area is reduced by reusing the P-Body region, which improves the current carrying capacity.
[0055] During reverse conduction, the gate voltage is below the threshold. The front-side P-type deep trench region 2 acts as the FRD anode, precisely corresponding to the n+FRD cathode 10, whose width matches half the pitch of the front-side cell, forming a short-path conductive channel and reducing the reverse conduction voltage vf. During turn-off, the P-type deep trench region 2 provides a shorter recovery path for minority carrier holes under the carrier storage layer 3, accelerating the turn-off speed and reducing losses. Through the synergy of these structures, the device achieves high efficiency with small size, high power density, and low losses.
[0056] Example 2
[0057] Based on Figures 1-8, the manufacturing process of an RC-IGBT device structure is illustrated in the following embodiments:
[0058] S1. First, heavily doped P-type implants are generated on the front side of the N-type epitaxial layer to form a P-type deep trench region 2, which serves as the anode of the FRD.
[0059] S2. Then, N-type implantation is generated on the front side of wafer 1 to form the carrier storage layer 3 of IGBT.
[0060] S3. Then, P-type implantation is generated on the front side of wafer 1 to form the P-Body region 4 of the IGBT.
[0061] S4. A deep trench etching process is performed on the surface to generate a gate oxide layer 13 and deposit a gate polycrystalline layer 14, forming a Trench gate structure 5.
[0062] S5. Then, a heavily doped N-type implant is generated in the P-Body region 4 to form a heavily doped N-source region 6, which serves as the emitter of the IGBT.
[0063] S6. Deposit a front metal layer 7 on the front side of wafer 1 to serve as the emitter of the IGBT and the anode of the FRD.
[0064] S7. After wafer 1 is thinned, heavily doped N-type implantation is performed on the back side as a buffer layer 8 for IGBTs.
[0065] S8, back-side photolithography of wafer 1, performing heavily doped N-type implantation and heavily doped P-type implantation respectively to form IGBT collector 9 and FRD cathode 10.
[0066] S9. A back metal layer 11 is deposited on the back side of wafer 1 to serve as the collector 9 of the IGBT and the cathode 10 of the FRD.
[0067] Working principle: Based on the dual innovative structure of front P-Body reuse + P+ deep groove design and back N+ / P+ wide precise matching, efficient forward and reverse conduction is achieved.
[0068] During forward conduction, the Trench gate structure 5 forms a channel after the voltage exceeds the threshold, and electrons are injected into the N-source region 6. At the same time, the P-Body region 4 is reused as the FRD anode. Together with the P-type deep trench region 2 that extends into the N drift region, it forms a three-dimensional deep trench depletion layer with the lightly injected N drift region. This provides a more concentrated and shorter current path for the IGBTs on both sides of the Trench gate and improves the forward withstand voltage. At this time, the carrier storage layer 3 stores charge, and the width of the back P+ collector 9 matches half of the front cell pitch, facing the current path on both sides of the trench gate, further shortening the conduction path and significantly reducing VCE(sat). At the same time, the chip area is reduced by reusing the P-Body region, which improves the current carrying capacity.
[0069] During reverse conduction, the gate voltage is below the threshold. The front-side P-type deep trench region 2 acts as the FRD anode, precisely corresponding to the N+FRD cathode 10, whose width matches half the front-side cell pitch, forming a short-path conductive channel and reducing the reverse conduction voltage VF. During turn-off, the P-type deep trench region 2 provides a shorter recovery path for minority carrier holes under the carrier storage layer 3, accelerating the turn-off speed and reducing losses. Through the synergy of these structures, the device achieves high efficiency with small size, high power density, and low losses.
[0070] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.
Claims
1. An RC-IGBT device structure, characterized in that, include: A wafer (1) has a back metal layer (11) at its bottom and an FRD cathode (10) at its top. A collector electrode (9) is disposed on the outside of the FRD cathode (10). The top of the collector electrode (9) is in contact with a buffer layer (8). A cell region (12) is disposed on the top of the wafer (1). The widths of the FRD cathode (10) and the collector electrode (9) are respectively the cell pitch of the front cell region (12). Half of the front cell, and corresponding one-to-one with the front cell; the cell region (12) includes: a front metal layer (7), the front metal layer (7) is located at the top of the wafer (1), and there are multiple and they are horizontally distributed; a P-Body region (4), the P-Body region (4) is located at the bottom of the front metal layer (7), and corresponds one-to-one with the front metal layer (7); a carrier storage layer (3), the carrier storage layer (3) is located at the bottom of the P-Body region (4), and corresponds one-to-one with the P-Body region (4); a Trench gate structure (5), the Trench gate structure (5) is located at the bottom of the front metal layer (7), and corresponds one-to-one with the front metal layer (7); a carrier storage layer (3), the carrier storage layer (3) is located at the bottom of the P-Body region (4), and corresponds one-to-one with the P-Body region (4); a ... The outer side of the carrier storage layer (3) and corresponding one-to-one with the carrier storage layer (3); N-source region (6), the outer side of the N-source region (6) is in contact with the Trench gate structure (5), the N-source region (6) is located near the top of the wafer (1) and inside the P-Body region (4); P-type deep trench region (2), the P-type deep trench region (2) is located inside the P-Body region (4), and its lower end penetrates the carrier storage layer (3) and extends downward, the number of the P-type deep trench regions (2) is multiple and horizontally equidistantly distributed.
2. The RC-IGBT device structure according to claim 1, characterized in that: The top of the FRD cathode (10) is in contact with the buffer layer (8).
3. The RC-IGBT device structure according to claim 1, characterized in that: The number of FRD cathodes (10) is multiple and they are horizontally equidistantly distributed, and the number of collectors (9) is multiple and they are located on the outside of the FRD cathodes (10).
4. The RC-IGBT device structure according to claim 1, characterized in that: The number of N-source regions (6) is multiple and they are symmetrically distributed on the left and right ends near the bottom of the front metal layer (7).
5. The RC-IGBT device structure according to claim 1, characterized in that: The Trench gate structure (5) consists of a gate oxide layer (13) and a gate polycrystalline layer (14). The outer side of the gate oxide layer (13) is in contact with the carrier storage layer (3), and the gate polycrystalline layer (14) is located inside the gate oxide layer (13).
6. The method for fabricating an RC-IGBT device according to claim 1, based on the RC-IGBT device structure according to any one of claims 1-5, characterized in that, Includes the following steps: S1. First, heavily doped P-type implants are generated on the front side of the N-type epitaxial layer to form a P-type deep trench region (2), which serves as the anode of the FRD. S2. Then, moderately doped N-type implants are generated on the front side of the wafer (1) to form the carrier storage layer (3) of the IGBT. S3. Then, moderately doped P-type implants are generated on the front side of the wafer (1) to form the P-Body region (4) of the IGBT. S4. The gate oxide layer (13) is generated and the gate polysilicon (14) is deposited on the surface through deep trench etching to form the Trench gate structure (5). S5. Then, heavily doped N-type implants are generated in the P-Body region (4) to form the... S6. A heavily doped N-source region (6) is used as the emitter of the IGBT. S7. A front metal layer (7) is deposited on the front side of the wafer (1) as the emitter of the IGBT and the anode of the FRD. S8. After the wafer (1) is thinned, a heavily doped N-type implantation is performed on the back side as the buffer layer (8) of the IGBT. S9. Photolithography is performed on the back side of the wafer (1) to perform heavily doped N-type implantation and heavily doped P-type implantation to form the collector (9) of the IGBT and the cathode (10) of the FRD. S10. A back metal layer (11) is deposited on the back side of the wafer (1) as the collector (9) of the IGBT and the cathode (10) of the FRD.