Display panel and display device

Abstract

The invention provides a display panel and a display device. In the specific sub-pixel arrangement structure, the three anode via holes corresponding to each repeating unit are arranged in one row in the preset direction, so that the three anode via holes are arranged in three rows and one column, punching paths in the column direction are reduced, and the punching efficiency is improved; or, two anode via holes corresponding to the first pixel row are arranged in a row in the first direction, and anode via holes corresponding to the second pixel row and one anode via hole corresponding to the first pixel row are arranged in a row in the second direction, so that the three anode via holes are arranged in two rows and two columns, and the punching paths in the row direction are reduced; therefore, the punching path of the anode via hole is optimized, and the punching efficiency is improved.

Description

Display panel and display device Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel and display device. Background Technology

[0002] Organic light-emitting diode (OLED) displays are devices that utilize the reversible color-changing phenomenon produced by organic semiconductor materials under the drive of electric current to achieve graphic display. OLED displays offer advantages such as ultra-lightweight, ultra-thin design, high brightness, wide viewing angle, low voltage, low power consumption, fast response, high definition, shock resistance, flexibility, low cost, simple manufacturing process, use of fewer raw materials, high luminous efficiency, and wide temperature range. Therefore, OLED display technology is considered the most promising next-generation display technology.

[0003] In the prior art, the anode via of OLED display devices is generally set at the center of the sub-pixel. This setting of the anode via increases the drilling path, thereby reducing the drilling efficiency. Summary of the Invention

[0004] This application provides a display panel and a display device to solve the problem of low drilling efficiency of anode vias in the prior art display panel.

[0005] To address the aforementioned technical problems, the first technical solution provided in this application is: to provide a display panel, comprising:

[0006] Silicon-based driving substrate;

[0007] The light-emitting carrier is bonded to the silicon-based driving substrate; the light-emitting carrier includes:

[0008] The glass substrate has multiple anode vias;

[0009] Multiple repeating units arranged in an array are disposed on the surface of a glass substrate away from the silicon-based driving substrate; each repeating unit includes three sub-pixels of different colors, and each sub-pixel is configured to correspond one-to-one with an anode via; the three sub-pixels of different colors are defined as a first sub-pixel, a second sub-pixel, and a third sub-pixel; in each repeating unit, the first sub-pixel and the second sub-pixel are arranged along a first direction to form a first pixel row; the third sub-pixel extends along the first direction to form a second pixel row; the first pixel row and the second pixel row are arranged along a second direction; the first direction and the second direction intersect.

[0010] in,

[0011] The three anode vias corresponding to each repeating unit are arranged in a row along a preset direction, which is either the first direction or the second direction.

[0012] or,

[0013] In each repeating unit, the two anode vias corresponding to the first pixel row are arranged in a row along the first direction, and the anode vias corresponding to the second pixel row and the anode vias corresponding to the first pixel row are arranged in a row along the second direction.

[0014] In this configuration, the sub-pixels and their corresponding anode vias are staggered in the direction parallel to the glass substrate; the three anode vias corresponding to each repeating unit are located between the first pixel row and the second pixel row, and are arranged in a row along the first direction; in the first direction, the three anode vias corresponding to the repeating unit are arranged at equal intervals.

[0015] In the second direction, the side of the first sub-pixel away from the second sub-pixel is aligned with the first side of the third sub-pixel; the side of the second sub-pixel away from the first sub-pixel is aligned with the second side of the third sub-pixel, and the first and second sides are positioned opposite each other along the first direction; in the first direction, the anode vias corresponding to the first sub-pixel, the anode vias corresponding to the third sub-pixel, and the anode vias corresponding to the second sub-pixel are located at 1 / 4, 2 / 4, and 3 / 4 of the third sub-pixel, respectively.

[0016] In this configuration, sub-pixels and their corresponding anode vias are staggered in a direction parallel to the glass substrate; the three anode vias corresponding to each repeating unit are arranged in a row along the second direction; the two anode vias corresponding to the first pixel row are located between the first sub-pixel and the second sub-pixel, and the anode vias corresponding to the third sub-pixel are located between the first pixel row and the second pixel row.

[0017] In this configuration, the sub-pixel covers the corresponding anode via; the three anode vias corresponding to each repeating unit are arranged in a row along the second direction; the projection patterns of the first sub-pixel and the second sub-pixel on the glass substrate are both L-shaped, and the first sub-pixel and the second sub-pixel are partially overlapped in the second direction.

[0018] Among them, the sub-pixel covers the corresponding anode via; the two anode vias corresponding to the first pixel row are arranged in a row along the first direction;

[0019] in,

[0020] The anode vias corresponding to the third sub-pixel and the anode vias corresponding to the first sub-pixel are arranged in a row along the second direction;

[0021] or,

[0022] The anode vias corresponding to the third sub-pixel and the anode vias corresponding to the second sub-pixel are arranged in a row along the second direction.

[0023] In the first pixel row, the anode via corresponding to the sub-pixel is located at the geometric center of the light-emitting area of ​​the corresponding sub-pixel.

[0024] In the direction parallel to the glass substrate, the repeating unit, the first pixel row and the second pixel row are both rectangles or both parallelograms; the first sub-pixel and the third sub-pixel are arranged in a centrally symmetrical manner.

[0025] The row direction of the repeating cell is the second direction, and the column direction of the repeating cell is the first direction.

[0026] The first sub-pixel is red, the second sub-pixel is green, and the third sub-pixel is blue.

[0027] To solve the above-mentioned technical problems, the second technical solution provided in this application is: to provide a display device, which includes a motherboard and the above-mentioned display panel.

[0028] The beneficial effects of this application are as follows: Unlike existing technologies, this application provides a display panel and a display device. The display panel includes a silicon-based driving substrate and a light-emitting carrier. The light-emitting carrier includes a glass substrate and a plurality of repeating units arranged in an array. The glass substrate has a plurality of anode vias. The plurality of repeating units arranged in an array are disposed on the surface of the glass substrate away from the silicon-based driving substrate. Each repeating unit includes three sub-pixels of different colors, and each sub-pixel corresponds one-to-one with an anode via. The three sub-pixels of different colors are defined as a first sub-pixel, a second sub-pixel, and a third sub-pixel, respectively. In each repeating unit, the first and second sub-pixels are arranged along a first direction to form a first pixel row. The third sub-pixel extends along the first direction to form a second pixel row. The first pixel row and the second pixel row are arranged along a second direction. The first and second directions intersect. In this application, the three anode vias corresponding to each repeating unit are arranged in a row along a preset direction, which may be either a first direction or a second direction. Alternatively, in each repeating unit, the two anode vias corresponding to the first pixel row are arranged in a row along the first direction, and the anode vias corresponding to the second pixel row and the anode vias corresponding to the first pixel row are arranged in a row along the second direction. In a specific sub-pixel arrangement structure, this application arranges the three anode vias corresponding to each repeating unit in a row along a preset direction to arrange the three anode vias in three rows and one column, reducing the drilling path in the column direction and improving drilling efficiency. Alternatively, the two anode vias corresponding to the first pixel row are arranged in a row along the first direction, and the anode vias corresponding to the second pixel row and the anode vias corresponding to the first pixel row are arranged in a row along the second direction, arranging the three anode vias in two rows and two columns to reduce the drilling path in the row direction, thereby optimizing the drilling path of the anode vias and improving drilling efficiency. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0030] Figure 1 is a schematic diagram of the structure of a display panel in the prior art;

[0031] Figure 2 is a structural schematic diagram of the first embodiment of the display panel provided in this application;

[0032] Figure 3 is a cross-sectional structural diagram of an embodiment at EE in Figure 2;

[0033] Figure 4 is a structural schematic diagram of the second embodiment of the display panel provided in this application;

[0034] Figure 5 is a structural schematic diagram of the third embodiment of the display panel provided in this application;

[0035] Figure 6 is a structural schematic diagram of the fourth embodiment of the display panel provided in this application;

[0036] Figure 7 is a cross-sectional structural diagram of an embodiment at FF in Figure 6;

[0037] Figure 8 is a structural schematic diagram of the fifth embodiment of the display panel provided in this application;

[0038] Figure 9 is a structural schematic diagram of an embodiment of the display device provided in this application.

[0039] Explanation of icon numbers:

[0040] 100, Display panel; 10, Light-emitting substrate; 11, Glass substrate; 111, Anode via; 112, Cathode via; 12, Repeating unit; 120, Sub-pixel; 121, Anode; 122, Light-emitting layer; 123, Cathode; 120A, First sub-pixel; 120B, Second sub-pixel; 120C, Third sub-pixel; TS, First side edge; BS, Second side edge; 124, First extension; 125, Second extension; 12A, First pixel row; 12B, Second pixel row; 15, Encapsulation layer; 16, Anode extension; 17, Isolation structure; 20, Silicon-based driving substrate; 21, Silicon substrate; 22, Driving circuit layer; D1, First direction; D2, Second direction; 200, Main board; 300, Display device. Detailed Implementation

[0041] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0042] In the following description, specific details such as particular system architectures, interfaces, and technologies are presented for illustrative purposes rather than for limiting purposes, in order to provide a thorough understanding of this application.

[0043] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0044] The terms "first," "second," and "third" in this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationships and movements between components in a specific orientation (as shown in the figures). If the specific orientation changes, the directional indications also change accordingly. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0045] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0046] Please refer to Figure 1, which is a schematic diagram of the structure of a display panel in the prior art.

[0047] In the prior art, the anode via 111 is located at the center of the sub-pixel 120. One sub-pixel 120 corresponds to one anode via 111. Three sub-pixels 120 are arranged in a triangular pattern to form a pixel unit (i.e., repeating unit 12). The three anode vias 111 in each pixel unit are arranged in three rows and two columns. The drilling path of the anode via 111 is relatively large, which increases the drilling time and reduces the drilling efficiency.

[0048] Please refer to Figures 2 and 3. Figure 2 is a structural schematic diagram of the first embodiment of the display panel provided in this application, and Figure 3 is a cross-sectional structural schematic diagram of an embodiment at EE in Figure 2.

[0049] To address the aforementioned technical problems, this application provides a display panel 100. The display panel 100 includes a silicon-based driving substrate 20 and a light-emitting carrier 10. The light-emitting carrier 10 is bonded to the silicon-based driving substrate 20. The light-emitting carrier 10 includes a glass substrate 11 and a plurality of arrayed repeating units 12. The glass substrate 11 has a plurality of anode vias 111. The plurality of arrayed repeating units 12 are disposed on the surface of the glass substrate 11 away from the silicon-based driving substrate 20. Each repeating unit 12 includes three sub-pixels 120 of different colors, with each sub-pixel 120 corresponding to one of the anode vias 111. The three sub-pixels 120 of different colors are defined as a first sub-pixel 120A, a second sub-pixel 120B, and a third sub-pixel 120C. In each repeating unit 12, the first sub-pixel 120A and the second sub-pixel 120B are arranged along a first direction D1 to form a first pixel row 12A. The third sub-pixel 120C extends along the first direction D1 to form a second pixel row 12B. The first pixel row 12A and the second pixel row 12B are arranged along the second direction D2. The first direction D1 and the second direction D2 intersect. Each repeating unit 12 has three anode vias 111 arranged in a row along a preset direction, which is either the first direction D1 or the second direction D2; or, in each repeating unit 12, the two anode vias 111 corresponding to the first pixel row 12A are arranged in a row along the first direction D1, and the anode vias 111 corresponding to the second pixel row 12B and the one anode via 111 corresponding to the first pixel row 12A are arranged in a row along the second direction D2.

[0050] In a specific sub-pixel 120 arrangement structure, this application arranges the three anode vias 111 corresponding to each repeating unit 12 in a row along a preset direction to arrange the three anode vias 111 in three rows and one column, reducing the drilling path in the column direction and improving drilling efficiency; or, the two anode vias 111 corresponding to the first pixel row 12A are arranged in a row along the first direction D1, and the anode vias 111 corresponding to the second pixel row 12B and the anode via 111 corresponding to the first pixel row 12A are arranged in a row along the second direction D2, so that the three anode vias 111 are arranged in two rows and two columns to reduce the drilling path in the row direction, thereby optimizing the drilling path of the anode vias 111 and improving drilling efficiency.

[0051] The silicon-based driving substrate 20 includes a silicon substrate 21 and a driving circuit layer 22, with the driving circuit layer 22 disposed on the side of the silicon substrate 21 close to the light-emitting carrier 10.

[0052] Silicon substrate 21 refers to a substrate based on monocrystalline silicon material.

[0053] The driving circuit layer 22 includes an active driving circuit (not shown) integrated on the silicon substrate 21 using CMOS (Complementary Metal-Oxide-Semi conductor) technology.

[0054] The separate fabrication of the silicon-based driving substrate 20 and the light-emitting carrier 10 can improve production efficiency. Secondly, it can avoid the impact of the vapor deposition process on the silicon-based driving substrate 20, reducing losses. In other words, from a process perspective, separate fabrication of the silicon-based driving substrate 20 and the light-emitting carrier 10 can not only improve yield but also reduce costs.

[0055] The glass substrate 11 also has a cathode via 112, which is spaced apart from the anode via 111. The cathode 123 of the sub-pixel 120 is electrically connected to the silicon-based driving substrate 20 through the cathode via 112. Both the anode via 111 and the cathode via 112 penetrate the glass substrate 11.

[0056] The anode via 111 can be a through-hole or a non-through-hole. For example, the cross-section of the anode via 111 in the direction perpendicular to the glass substrate 11 can be rectangular, trapezoidal, parallelogram, or other shapes. Similarly, the cathode via 112 can be a through-hole or a non-through-hole.

[0057] In this embodiment, both the anode via 111 and the cathode via 112 are through holes, which reduces the current path and facilitates the fabrication of the through holes.

[0058] Both the cathode via 112 and the anode via 111 include through holes and conductive material filling the through holes. The conductive material filling the anode via 111 and the cathode via 112 is not limited here and can be selected according to actual needs.

[0059] The through holes in the cathode via 112 and the anode via 111 are both prepared using through-glass via (TGV) technology.

[0060] It should be understood that, compared with through-silicon via (TSV) technology, glass via technology has the advantages of superior high-frequency electrical characteristics, low cost, simple process flow, and strong mechanical stability.

[0061] Compared to the prior art where the sub-pixel 120 is fabricated on the silicon-based driving substrate 20 and electrically connected to the silicon-based driving substrate 20 through silicon vias, this application sets the sub-pixel 120 on the glass substrate 11 and bonds the sub-pixel 120 to the silicon-based driving substrate 20 through glass vias, which can reduce costs and improve high-frequency electrical characteristics.

[0062] The size of the cathode via 112 and the anode via 111 is not restricted here; the selection should be made according to actual needs.

[0063] In some embodiments, the ratio of the size of a single anode via 111 to the size of the corresponding sub-pixel 120 is in the range of 1 / 4 to 1 / 2. This ensures the via yield of the anode via 111 and the conductivity between the anode 121 of the sub-pixel 120 and the anode via 111 without affecting the pixel opening of the sub-pixel 120.

[0064] In other embodiments, the ratio of the size of a single anode via 111 to the size of the corresponding sub-pixel 120 can be other values, without much restriction, and can be selected according to actual needs.

[0065] In some embodiments, the cross-section of the anode via 111 in the direction parallel to the glass substrate 11 can be a regular or irregular shape such as a circle, triangle, rhombus, rectangle, or hexagon. There are no restrictions here, and the selection can be made according to actual needs.

[0066] In this embodiment, the cross-section of the anode via 111 is circular in the direction parallel to the glass substrate 11, which is beneficial to the uniform distribution of contact current.

[0067] Sub-pixel 120 is an OLED. Sub-pixel 120 includes an anode 121, a light-emitting layer 122, and a cathode 123 stacked sequentially. The anode 121 is disposed on the side surface of the glass substrate 11 away from the silicon-based driving substrate 20.

[0068] In some embodiments, the size of subpixel 120 is 6 micrometers to 15 micrometers. It should be understood that the size of subpixel 120 can also be other values.

[0069] In some embodiments, the first sub-pixel 120A is a red sub-pixel 120, the second sub-pixel 120B is a green sub-pixel 120, and the third sub-pixel 120C is a blue sub-pixel 120.

[0070] In other embodiments, subpixel 120 can also be other colors, selected according to actual needs.

[0071] In some embodiments, in a direction parallel to the glass substrate 11, the repeating unit 12, the first pixel row 12A, and the second pixel row 12B are all rectangles or parallelograms, and the first sub-pixel 120A and the third sub-pixel 120C are centrally symmetrically arranged. The row direction of the repeating unit 12 is the second direction D2, and the column direction of the repeating unit 12 is the first direction D1.

[0072] It should be understood that in other embodiments, the first sub-pixel 120A and the second sub-pixel 120B do not need to be centrally symmetrically arranged, as long as the first pixel row 12A and the second pixel row 12B can form a rectangle or a parallelogram.

[0073] The row direction of the repeating unit 12 is the second direction D2, and the column direction of the repeating unit 12 is also the second direction D2. This ensures that the multiple anode vias 111 corresponding to each column of repeating unit 12 are arranged in a column along the first direction D1, and the multiple anode vias 111 corresponding to each row of repeating unit 12 are arranged in three rows along the first direction D1. This reduces the drilling path of the anode vias 111 in the column direction, thereby improving drilling efficiency. In the first direction D1, the three anode vias 111 corresponding to the repeating unit 12 are arranged at equal intervals, and the anode vias 111 are evenly distributed to improve drilling efficiency.

[0074] In this embodiment, the repeating unit 12, the first pixel row 12A, and the second pixel row 12B are all rectangular in the direction parallel to the glass substrate 11. The first direction D1 is perpendicular to the second direction D2.

[0075] In some embodiments, sub-pixels 120 and their corresponding anode vias 111 are staggered in a direction parallel to the glass substrate 11. The three anode vias 111 corresponding to each repeating unit 12 are located between the first pixel row 12A and the second pixel row 12B, and are arranged in a row along the first direction D1. In the first direction D1, the three anode vias 111 corresponding to the repeating unit 12 are arranged at equal intervals to facilitate the fabrication of the anode vias 111.

[0076] Specifically, the anode via 111 is located on the side of the corresponding sub-pixel 120. The anode via 111 corresponding to the first sub-pixel 120A is located on the side of the first sub-pixel 120A close to the third sub-pixel 120C, the anode via 111 corresponding to the second sub-pixel 120B is located on the side of the second sub-pixel 120B close to the third sub-pixel 120C, and the anode via 111 corresponding to the third sub-pixel 120C is located on the side of the third sub-pixel 120C close to the first pixel row 12A.

[0077] In some embodiments, in the second direction D2, the side of the first sub-pixel 120A away from the second sub-pixel 120B is aligned with the first side TS of the third sub-pixel 120C. The side of the second sub-pixel 120B away from the first sub-pixel 120A is aligned with the second side BS of the third sub-pixel 120C, and the first side TS and the second side BS are opposite to each other along the first direction D1. In the first direction D1, the anode via 111 corresponding to the first sub-pixel 120A, the anode via 111 corresponding to the third sub-pixel 120C, and the anode via 111 corresponding to the second sub-pixel 120B are located sequentially at 1 / 4, 2 / 4, and 3 / 4 of the third sub-pixel 120C, respectively, to reduce the spacing between the anode via 111 and the corresponding sub-pixel 120, reduce the cross-line length of the electrical connection between the anode 121 of the sub-pixel 120 and the anode via 111, and improve the drilling efficiency.

[0078] In this embodiment, the first sub-pixel 120A and the second sub-pixel 120B are arranged symmetrically at the center. In the direction parallel to the glass substrate 11, both the first sub-pixel 120A and the second sub-pixel 120B are trapezoidal, and the third sub-pixel 120C is rectangular.

[0079] Please refer to Figures 2 to 4. Figure 4 is a structural schematic diagram of the second embodiment of the display panel provided in this application.

[0080] In other embodiments, as shown in FIG4, in a direction parallel to the glass substrate 11, both the first sub-pixel 120A and the second sub-pixel 120B are trapezoidal, and the repeating unit 12, the first pixel row 12A and the second pixel row 12B are parallelograms. The first direction D1 and the second direction D2 are not perpendicular. One side of the parallelogram extends along the first direction D1, and the other side of the parallelogram extends along the second direction D2.

[0081] The display panel 100 also includes an anode extension 16, which is correspondingly disposed with anode vias 111. The anode extension 16 and the anode 121 are patterned together using the same conductive layer, simplifying the manufacturing process. The anode 121 is electrically connected to the anode via 111 via the anode extension 16. It should be understood that, compared to a design where the sub-pixel 120 covers the corresponding anode via 111, a design that misaligns the anode via 111 with the corresponding sub-pixel 120 better avoids the influence of the anode via 111 on the uniformity of the light-emitting layer 122 of the sub-pixel 120, and thus better improves the light-emitting effect of the sub-pixel 120.

[0082] Please refer to Figures 2 to 5. Figure 5 is a structural schematic diagram of the third embodiment of the display panel provided in this application.

[0083] The third embodiment of the display panel 100 provided in this application is similar to the first embodiment provided in this application in terms of structural substrate, except that the three anode vias 111 corresponding to each repeating unit 12 are arranged in a row along the second direction D2.

[0084] In some embodiments, sub-pixels 120 and their corresponding anode vias 111 are staggered in a direction parallel to the glass substrate 11. The three anode vias 111 corresponding to each repeating unit 12 are arranged in a row along the second direction D2. The two anode vias 111 corresponding to the first pixel row 12A are located between the first sub-pixel 120A and the second sub-pixel 120B, and the anode via 111 corresponding to the third sub-pixel 120C is located between the first pixel row 12A and the second pixel row 12B.

[0085] In this embodiment, the multiple anode vias 111 corresponding to each row of repeating unit 12 are arranged in a row along the second direction D2, and the multiple anode vias 111 corresponding to each column of repeating unit 12 are arranged in three columns along the first direction D1, so as to reduce the drilling path of the anode vias 111 in the row direction and thereby improve the drilling efficiency.

[0086] Please refer to Figures 2 to 7. Figure 6 is a structural schematic diagram of the fourth embodiment of the display panel provided in this application, and Figure 7 is a cross-sectional structural schematic diagram of an embodiment at FF in Figure 6.

[0087] The fourth embodiment of the display panel 100 provided in this application is similar to the third embodiment in terms of structural substrate, except that the sub-pixels 120 cover the corresponding anode vias 111. The projected patterns of the first sub-pixel 120A and the second sub-pixel 120B are both L-shaped, and the first sub-pixel 120A and the second sub-pixel 120B are partially overlapped in the second direction D2.

[0088] In some embodiments, sub-pixels 120 cover the corresponding anode vias 111. The three anode vias 111 corresponding to each repeating unit 12 are arranged in a row along the second direction D2. The projection patterns of the first sub-pixel 120A and the second sub-pixel 120B on the glass substrate 11 are both L-shaped, and the first sub-pixel 120A and the second sub-pixel 120B are partially overlapped in the second direction D2.

[0089] Sub-pixel 120 covers the corresponding anode via 111, which can be understood as the orthographic projection of the anode via 111 onto sub-pixel 120 being entirely within sub-pixel 120.

[0090] It should be understood that when the sub-pixel 120 covers the corresponding anode via 111, there is no need to set the anode extension 16. The anode 121 of the sub-pixel 120 can directly contact the anode via 111, thereby simplifying the manufacturing process.

[0091] Each sub-pixel 120 in the first pixel row 12A includes a first extension 124 and a second extension 125. The first extension 124 extends along a first direction D1, and the second extension 125 extends along a second direction D2. One end of the first extension 124 is connected to one end of the second extension 125 to form an L-shaped structure. The first extension 124 covers the corresponding anode via 111.

[0092] In the second direction D2, the first extension 124 of the first sub-pixel 120A and the first extension 124 of the second sub-pixel 120B are partially overlapped, so that the two anode vias 111 corresponding to the first pixel row 12A can be arranged in a row along the second direction D2.

[0093] In this embodiment, the multiple anode vias 111 corresponding to each row of repeating unit 12 are arranged in a row along the second direction D2, and the multiple anode vias 111 corresponding to each column of repeating unit 12 are arranged in three columns along the first direction D1, so as to reduce the drilling path of the anode vias 111 in the row direction and thereby improve the drilling efficiency.

[0094] Please refer to Figures 2 to 8. Figure 8 is a structural schematic diagram of the fifth embodiment of the display panel provided in this application.

[0095] The fifth embodiment of the display panel 100 provided in this application has a similar structural substrate to the first embodiment provided in this application, except that: the two anode vias 111 corresponding to the first pixel row 12A are arranged in a row along the first direction D1. The anode via 111 corresponding to the third sub-pixel 120C and the anode via 111 corresponding to one sub-pixel 120 in the first pixel row 12A are arranged in a row along the second direction D2.

[0096] In some embodiments, sub-pixel 120 covers the corresponding anode via 111. The two anode vias 111 corresponding to the first pixel row 12A are arranged in a row along the first direction D1. The anode via 111 corresponding to the third sub-pixel 120C is arranged in a row with the anode via 111 corresponding to the first sub-pixel 120A along the second direction D2; or, the anode via 111 corresponding to the third sub-pixel 120C is arranged in a row with the anode via 111 corresponding to the second sub-pixel 120B along the second direction D2.

[0097] In this embodiment, the example is taken as the anode via 111 corresponding to the third sub-pixel 120C and the anode via 111 corresponding to the first sub-pixel 120A being arranged in a row along the second direction D2.

[0098] In some embodiments, in the first pixel row 12A, the anode via 111 corresponding to the sub-pixel 120 is located at the geometric center of the light-emitting area of ​​the corresponding sub-pixel 120. The light-emitting area of ​​the sub-pixel 120 is the projection area of ​​the sub-pixel 120 on the glass substrate 11. This design helps to achieve a uniform distribution of contact current on the anode 121.

[0099] It should be understood that in other embodiments, in the first pixel row 12A, the anode via 111 corresponding to the sub-pixel 120 can be located in other places in the corresponding light-emitting area. There are no excessive restrictions here, and the selection can be made according to actual needs.

[0100] In this embodiment, the multiple anode vias 111 corresponding to each row of repeating unit 12 are arranged in two rows along the second direction D2, and the multiple anode vias 111 corresponding to each column of repeating unit 12 are arranged in two columns along the first direction D1, so as to reduce the drilling path of the anode vias 111 in the row direction and thereby improve the drilling efficiency.

[0101] The light-emitting carrier 10 also includes an encapsulation layer 15, which is located on the side of the sub-pixel 120 away from the glass substrate 11. The material of the encapsulation layer 15 is not limited here and can be selected according to actual needs.

[0102] The light-emitting substrate 10 also includes an isolation structure 17, which is disposed on the side of the sub-pixel 120 to isolate the light-emitting layer 122 of the sub-pixel 120 and avoid pixel crosstalk problems. The isolation structure 17 can isolate the cathode 123 of the sub-pixel 120, or it can electrically connect the cathodes 123 of adjacent sub-pixels 120. The material of the isolation structure 17 is not limited here and can be selected according to actual needs. In this application, the isolation structure 17 also isolates the cathode 123 of the sub-pixel 120. The cathode 123 of the sub-pixel 120 is a single-layer structure. The cathode 123 is located on the side of the isolation structure 17 away from the glass substrate 11.

[0103] Please refer to Figure 9, which is a structural schematic diagram of an embodiment of the display device provided in this application.

[0104] This application provides a display device 300. The display device 300 includes a motherboard 200 and the aforementioned display panel 100. The display device 300 in this embodiment is an AMOLED.

[0105] The motherboard 200 is electrically connected to the display panel 100. The motherboard 200 is used to transmit various required signals to the display panel 100 to control the display screen of the display panel 100. For example, clock signals (CK), low potential signals (Vss), power supply voltage signals (VDD), and data signals (Data) required by the driving circuit layer.

[0106] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0107] The above are merely embodiments of this application and do not limit the scope of patent protection of this application. Any equivalent structural or procedural changes made using the content of this application’s specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of this application.

Claims

1. A display panel, characterized in that, include: Silicon-based driving substrate; The light-emitting carrier is bonded to the silicon-based driving substrate; The light-emitting substrate includes: a glass substrate having multiple anode vias; multiple repeating units arranged in an array, disposed on the side surface of the glass substrate away from the silicon-based driving substrate; each repeating unit includes three sub-pixels of different colors, each sub-pixel corresponding to one of the anode vias; the three sub-pixels of different colors are defined as a first sub-pixel, a second sub-pixel, and a third sub-pixel; in each repeating unit, the first sub-pixel and the second sub-pixel are arranged along a first direction to form a first pixel row; the third sub-pixel extends along the first direction to form a second pixel row; the first pixel row and the second pixel row are arranged along a second direction; the first direction and the second direction intersect; wherein, the three anode vias corresponding to each repeating unit are arranged in a row along a preset direction, the preset direction being either the first direction or the second direction; or, in each repeating unit, the two anode vias corresponding to the first pixel row are arranged in a row along the first direction, and the anode vias corresponding to the second pixel row and the anode vias corresponding to the first pixel row are arranged in a row along the second direction.

2. The display panel according to claim 1, characterized in that, In a direction parallel to the glass substrate, the sub-pixels are staggered with the corresponding anode vias; the three anode vias corresponding to each repeating unit are located between the first pixel row and the second pixel row, and are arranged in a row along the first direction; in the first direction, the three anode vias corresponding to the repeating unit are arranged at equal intervals.

3. The display panel according to claim 2, characterized in that, In the second direction, the side of the first sub-pixel away from the second sub-pixel is aligned with the first side of the third sub-pixel; the side of the second sub-pixel away from the first sub-pixel is aligned with the second side of the third sub-pixel, and the first side and the second side are positioned opposite each other along the first direction; in the first direction, the anode vias corresponding to the first sub-pixel, the anode vias corresponding to the third sub-pixel, and the anode vias corresponding to the second sub-pixel are located at 1 / 4, 2 / 4, and 3 / 4 of the third sub-pixel, respectively.

4. The display panel according to claim 1, characterized in that, In a direction parallel to the glass substrate, the sub-pixel and the corresponding anode via are staggered; the three anode vias corresponding to each repeating unit are arranged in a row along the second direction; the two anode vias corresponding to the first pixel row are located between the first sub-pixel and the second sub-pixel, and the anode via corresponding to the third sub-pixel is located between the first pixel row and the second pixel row.

5. The display panel according to claim 1, characterized in that, The sub-pixel covers the corresponding anode via; the three anode vias corresponding to each repeating unit are arranged in a row along the second direction; the projection patterns of the first sub-pixel and the second sub-pixel on the glass substrate are both L-shaped, and the first sub-pixel and the second sub-pixel are partially overlapped in the second direction.

6. The display panel according to claim 1, characterized in that, The sub-pixel covers the corresponding anode via; the two anode vias corresponding to the first pixel row are arranged in a row along the first direction; wherein, the anode via corresponding to the third sub-pixel is arranged in a row along the second direction with the anode via corresponding to the first sub-pixel; or, the anode via corresponding to the third sub-pixel is arranged in a row with the anode via corresponding to the second sub-pixel along the second direction.

7. The display panel according to claim 6, characterized in that, In the first pixel row, the anode via corresponding to the sub-pixel is located at the geometric center of the light-emitting area corresponding to the sub-pixel.

8. The display panel according to claim 1, characterized in that, In a direction parallel to the glass substrate, the repeating unit, the first pixel row, and the second pixel row are all rectangular or parallelograms; the first sub-pixel and the third sub-pixel are centrally symmetrically arranged; the row direction of the repeating unit is the second direction, and the column direction of the repeating unit is the first direction.

9. The display panel according to claim 1, characterized in that, The first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a blue sub-pixel.

10. A display device, characterized in that, Includes a motherboard and a display panel according to any one of claims 1 to 9.

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