DRAM (Dynamic Random Access Memory) state management method and system and terminal equipment

Abstract

The invention relates to the technical field of memory management, and discloses a DRAM state management method and system and terminal device.The method comprises the steps that physical interface signals connected with a DRAM are continuously collected based on a preset time window, and time sequence correlation parameters of the DRAM at the corresponding moment are obtained; inputting the preprocessed time sequence correlation parameters into a prediction model for prediction to obtain time sequence correlation parameters of a plurality of future moments, and further determining predicted safety thresholds of the plurality of future moments and a minimum hour sequence margin in the plurality of future moments; when the minimum time sequence margin is lower than the predicted safety threshold value of the corresponding moment, generating a coding early warning signal based on the time sequence correlation parameter of the future moment; and based on the risk level code, the risk type code and the load state code, matching a target state self-healing strategy in a preset strategy library, and executing the strategy. By adopting the method, the overall reliability and availability of the system can be improved on the premise of ensuring the safety margin.

Description

Technical Field

[0001] This application relates to the field of memory management technology, and in particular to a DRAM state management method, system, and terminal device. Background Technology

[0002] With the rapid development of cloud computing, artificial intelligence, and edge computing, the requirements for bandwidth, capacity, and reliability in data access have reached a certain level. DRAM (Dynamic Random Access Memory), as the system's main memory, is the core foundation for the reliability of the entire computing system, and its stable operation is essential.

[0003] Current DRAM technology development faces challenges such as significantly increased sensitivity to charge interference, substantial compression of timing parameter tolerance space, and dynamic reduction of the actual usable timing margin in DRAM. However, traditional methods for ensuring DRAM reliability cannot achieve dynamic perception of DRAM timing status, prediction of potential risks, and proactive adaptive adjustment. Therefore, there is an urgent need for an intelligent memory management method that shifts from "passive error correction" to "proactive error prevention." Summary of the Invention

[0004] In view of this, embodiments of this application provide a DRAM state management method, system, and terminal device, which can effectively solve the technical problem that traditional methods for ensuring DRAM reliability cannot achieve dynamic perception, potential risk prediction, and adaptive adjustment of DRAM timing status.

[0005] In a first aspect, embodiments of this application provide a DRAM state management method, the method comprising: Based on a preset time window, the physical interface signal connected to the DRAM memory is continuously acquired to obtain the timing correlation parameters of the DRAM memory at the corresponding time and the timing correlation parameters are preprocessed. The preprocessed time-series correlation parameters are input into the prediction model for prediction to obtain time-series correlation parameters for multiple future times, and then the prediction safety threshold and a minimum time-series margin within the multiple future times are determined. When the minimum time margin is lower than the predicted safety threshold at the corresponding future time, an coded warning signal is generated based on the time-series correlation parameters of the multiple future times, wherein the coded warning signal includes risk level coding, risk type coding and load status coding. Based on the risk level code, the risk type code, and the load state code, a target state self-healing strategy is matched in the preset strategy library and the target state self-healing strategy is executed.

[0006] Secondly, embodiments of this application provide a DRAM status management device, the device comprising: The data acquisition module is used to continuously acquire the physical interface signal connected to the DRAM memory based on a preset time window, obtain the timing correlation parameters of the DRAM memory at the corresponding time, and preprocess the timing correlation parameters. The prediction and early warning module is used to input the preprocessed time series correlation parameters into the prediction model for prediction, obtain the time series correlation parameters of multiple future times, and then determine the prediction safety threshold of the multiple future times and a minimum time series margin within the multiple future times. The prediction and early warning module is also used to generate an coded early warning signal based on the time-series correlation parameters of the multiple future times when the minimum time-series margin is lower than the predicted safety threshold at the corresponding future time. The coded early warning signal includes a risk level code, a risk type code, and a load status code. The strategy execution module is used to match a target state self-healing strategy in a preset strategy library based on the risk level code, the risk type code, and the load state code, and execute the target state self-healing strategy.

[0007] Thirdly, this application also provides a DRAM state management system, including: The system-on-a-chip includes a main controller, a memory controller, and a command scheduler. The system-on-a-chip also connects to DRAM memory via a physical layer interface. The main controller is used to perform the following steps: Based on a preset time window, the physical interface signal connected to the DRAM memory is continuously acquired to obtain the timing correlation parameters of the DRAM memory at the corresponding time and the timing correlation parameters are preprocessed. The preprocessed time-series correlation parameters are input into the prediction model for prediction to obtain time-series correlation parameters for multiple future times, and then the prediction safety threshold and a minimum time-series margin within the multiple future times are determined. When the minimum time margin is lower than the predicted safety threshold at the corresponding future time, an coded warning signal is generated based on the time-series correlation parameters of the multiple future times, wherein the coded warning signal includes risk level coding, risk type coding and load status coding. Based on the risk level code, the risk type code, and the load state code, a target state self-healing strategy is matched in the preset strategy library; Specifically, when executing the target state self-healing strategy, the memory controller and / or the command scheduler are triggered to configure the electrical parameters of the physical layer interface through the DFI interface.

[0008] The embodiments of this application have the following beneficial effects: The DRAM state management method proposed in this application evolves from passive error correction to proactive early warning and self-healing. It upgrades timing margin from static threshold monitoring to dynamic trend prediction, providing early warning and intervention before timing violations occur, significantly improving mean time between failures (MTBF). Furthermore, it shifts from conservative design to on-demand optimization, using real-time operating conditions (timing-related parameters) to drive a layered self-healing strategy. This releases performance redundancy while ensuring safety margins, thereby improving energy efficiency. Attached Figure Description

[0009] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 This paper shows a framework diagram of a DRAM state management system according to an embodiment of the present application; Figure 2 A flowchart of a DRAM state management method according to an embodiment of this application is shown; Figure 3 This diagram illustrates the hierarchical self-healing strategy selection logic of the DRAM state management method according to an embodiment of this application. Figure 4 A schematic diagram of a DRAM state management device according to an embodiment of this application is shown. Detailed Implementation

[0011] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0012] The components of the embodiments of this application described and illustrated in the accompanying drawings can be arranged and designed in a variety of different configurations. Therefore, the following detailed description of the embodiments of this application provided in the drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0013] In the following text, the terms "comprising," "having," and their cognates, which may be used in various embodiments of this application, are intended only to indicate a particular feature, number, step, operation, element, component, or combination thereof, and should not be construed as primarily excluding the presence of one or more other features, numbers, steps, operations, elements, components, or combinations thereof, or adding the possibility of one or more combinations thereof. Furthermore, the terms "first," "second," "third," etc., are used only for distinguishing descriptions and should not be construed as indicating or implying relative importance.

[0014] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the various embodiments of this application pertain. Terms (such as those defined in a generally used dictionary) shall be interpreted as having the same meaning as in the context of the relevant technical field and shall not be interpreted as having an idealized or overly formal meaning, unless clearly defined in the various embodiments of this application.

[0015] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0016] DRAM typically serves as the main memory in a system, and its stable operation is the core foundation for the reliability of the entire computing system. Currently, mainstream technologies and related existing technologies for ensuring DRAM reliability all have significant limitations and cannot fundamentally solve reliability problems caused by timing violations. Specifically: 1. Reactive error handling technologies: such as parity checking, error correction codes (ECC), and on-die ECC, can only detect and correct data errors after they occur, but cannot prevent the root cause of errors, namely timing violations. These technologies are "post-incident remedies," unable to avoid the impact on business operations when errors occur, and cannot reduce the probability of errors. 2. Static guard band technology: During the system design phase, fixed timing parameters are set based on worst-case process, voltage, and temperature conditions. This method is too conservative, wasting a lot of performance under most actual operating conditions, and may still result in insufficient protection under extreme conditions or in the later stages of chip aging, leading to timing violations. 3. Passive protocol monitoring technologies, such as DFI (DDR PHY Interface) or JEDECDRAM protocol checkers, can only detect command / timing protocol violations at the hardware level and usually trigger system-level fatal errors (such as Uncorrectable Error), causing program crashes, operating system downtime or server resets, which seriously affect service availability. Some existing technologies also suffer from limited functionality and lack of a closed-loop system. For example, patent US11211139B2 can only calibrate timing drifts that have already occurred in real time, without predictive capabilities or a layered self-healing strategy, and cannot cope with long-term timing degradation caused by chip aging. Another example is the solution described in patent CN118939586A, which only optimizes multi-bank mapping to reduce conflicts, without addressing timing margin management and early warning, and cannot solve the risk of timing violations. Yet another example is patent application CN118489140A, which describes adjusting the clock cycle only during the interface training phase and cannot dynamically adapt to changes in operating conditions (such as sudden load increases or temperature fluctuations) during runtime.

[0017] To overcome the shortcomings of existing technologies, embodiments of this application utilize a system-on-a-chip (SoC) to manage the state of DRAM memory. Specifically, this enables the prediction of DRAM timing errors, proactive warnings, and self-healing adjustments, thereby ensuring the reliability of DRAM.

[0018] The following describes the DRAM state management method, system, and terminal device using specific embodiments.

[0019] Figure 1 A framework diagram of a DRAM state management system according to an embodiment of this application is shown. Exemplarily, the DRAM state management system includes a system-on-chip (SoC) comprising an integrated host controller, memory controller, command scheduler, and physical layer interface (PHY), etc. Furthermore, the SoC is connected to the DRAM memory via the physical layer interface.

[0020] In this application, the main controller refers to the core decision-making unit of the DRAM state management device. The memory controller is a dedicated controller on-chip used to control the DRAM; in this application, it receives parameter configuration instructions from the main controller to implement optimized scheduling strategies. The command scheduler is a submodule within the memory controller used for command scheduling; in this application, the command scheduler is dynamically intervened by the main controller through register write operations to implement lightweight timing mitigation actions such as inserting idle cycles and cross-bank priority scheduling. It can be understood that in this application, when executing the target state self-healing strategy, the memory controller and / or command scheduler can configure the electrical parameters of the physical layer interface through the DFI interface.

[0021] DRAM memory, or Dynamic Random Access Memory, is the managed object. In one example, the memory controller in the system-on-a-chip can send addresses / commands to the DRAM memory via the DFI interface to enable the DRAM memory to perform corresponding read and write operations.

[0022] Combination Figure 1It can be understood that the SoC platform executes the functions of each module in the DRAM state management device of this application embodiment through the main controller for DRAM state management. Specifically, the DRAM state management device includes a data acquisition module, a prediction and early warning module, and a strategy execution module. Specifically, the main controller continuously acquires data through the data acquisition module and forms corresponding data frames, which are sent to the prediction and early warning module for processing. Then, the prediction and early warning module performs timing parameter prediction and state early warning, and when the corresponding early warning conditions are met, it outputs an coded early warning signal containing information such as risk level to the strategy execution module. Furthermore, the strategy execution module performs strategy matching and strategy execution, thereby achieving self-healing adjustment. It can be understood that the functions of each module in the DRAM state management device correspond to the DRAM state management method of this application embodiment.

[0023] The following section will provide a detailed explanation using DRAM state management methods.

[0024] Figure 2 A flowchart of a DRAM state management method according to an embodiment of this application is shown. Exemplarily, a master controller in an on-chip system is used to execute the DRAM state management method according to an embodiment of this application. The DRAM state management method includes the following steps: Step S202: Based on a preset time window, continuously acquire the physical interface signal connected to the DRAM memory, obtain the timing correlation parameters of the DRAM memory at the corresponding time, and preprocess the timing correlation parameters.

[0025] In this context, the preset time window refers to a fixed duration period used in the DRAM status management method for continuously and periodically acquiring physical interface signals.

[0026] Timing-related parameters refer to a set of quantitative indicators obtained from physical interface signals after preprocessing, which directly characterize the current timing stability of DRAM. They are divided into two categories: 1. Environmental / Aging Parameters: including operating temperature, cumulative operating time, etc.

[0027] 2. Dynamic / load parameters: including specified timing parameters, operating frequency, memory load rate, etc.

[0028] As an example, to monitor and acquire physical interface signals of the DRAM memory, dedicated analog probes are deployed on the physical layer interface and critical paths of the DRAM command / address (C / A) bus. To ensure acquisition accuracy, a time-to-digital converter is used to measure the actual time interval between critical commands, achieving a measurement accuracy of ±10 ps. In some implementations, the monitored parameters include, but are not limited to, tRCD (row address to column address delay), tRP (row precharge time), tRC (row cycle time), tFAW (fourth activation window time), and tRRD (row to row delay). Simultaneously, the parameter monitoring module integrates a temperature sensor and voltage monitoring circuitry to synchronously acquire operating parameters of the DRAM memory, such as operating voltage and junction temperature.

[0029] Furthermore, the collected timing-related parameter data will undergo data preprocessing before being used for subsequent state management. For example, the cumulative DRAM runtime and CE / UE error count are statistically analyzed using the memory controller as raw data for aging factor calculation, with a statistical period of, for example, 1 minute. The monitored parameters and the statistically analyzed raw data are used together as timing-related parameters and converted into digital timestamps via TDC. Using a preset time window (e.g., 1 μs) as the unit, the minimum value, average temperature, and average voltage of all timing parameters measured within this window are packaged into a data frame and sent to the prediction model or other modules via a lightweight bus.

[0030] In one implementation, the step of continuously acquiring physical interface signals connected to the DRAM memory based on a preset time window to obtain timing correlation parameters of the DRAM memory at corresponding times includes: Obtain the preset smoothing coefficient and the original timing correlation parameters of the DRAM memory at each acquisition time point within the preset time window; For each acquisition time point within the preset time window, determine the previous original time series correlation parameter corresponding to the previous acquisition time point of the target acquisition time point; Based on the previous original time series correlation parameters, the original time series correlation parameters corresponding to the target acquisition time point, and the preset smoothing coefficient, the time series correlation parameters for the target acquisition time point are determined.

[0031] Exemplary, the above preprocessing may include smoothing, for example, using an exponentially weighted moving average (EWMA) filter to smooth the input time-series measurements, filtering out high-frequency noise and extracting stable trends. This smoothing formula can be expressed as: St =α×Xt + (1-α) ×S{t-1}; Where Xt is the time-series correlation parameter collected at time t; S{t-1} is the smoothed output value at time t-1; St is the final smoothed output value at time t; α is the smoothing coefficient, for example, α is 0.2-0.3, and the final smoothed value St is used for subsequent time-series margin calculation, trend prediction and strategy effect evaluation.

[0032] Step S204: Input the preprocessed time series correlation parameters into the prediction model for prediction to obtain time series correlation parameters for multiple future times, and then determine the prediction safety threshold for multiple future times and a minimum time series margin within multiple future times.

[0033] Exemplarily, time-series correlation parameters collected at each time point can be used to form a sequence feature, which may include, but is not limited to, specified time-series parameters, operating frequency, and load parameters. This sequence feature is then input into a prediction model, and the output is the time-series correlation parameters for each time point within a preset future time period. Furthermore, based on the time-series correlation parameters for each future time point, a prediction safety threshold is determined for each future time point. Next, based on the time-series correlation parameters and the prediction safety threshold for each future time point, a prediction time-series margin is determined for each future time point. Finally, a minimum time-series margin is determined from multiple prediction time-series margins for subsequent status warnings.

[0034] In one implementation, the prediction model can be a time-series regression model built on a long short-term memory network (LSTM). Its input is preprocessed time-series correlation parameters (including temperature, frequency, load, operating voltage, time-series parameters, etc.) organized in time series, and its output is the time-series correlation parameters for each future time step within N time steps (e.g., N=5, corresponding to 25 ms).

[0035] Specifically, the time-series correlation parameters at each time point include: the smoothed value of each specified time-series parameter, average junction temperature, average voltage, current operating frequency, and memory load rate (provided by the memory controller, with a value of 0-100%). The preprocessed time-series correlation parameters are then input into the prediction model, which employs a lightweight long short-term memory network (LSTM). Its input layer receives standardized feature data from multiple recent time points (e.g., 16 1μs cycles), and its output layer predicts the smoothed values ​​of each time-series parameter for multiple future time points (e.g., 10 1μs cycles).

[0036] The safety threshold refers to a dynamic critical value set by the system for a specific DRAM timing parameter under real-time operating conditions to determine whether it is in a safe operating state. It is worth noting that in this embodiment, the safety threshold changes dynamically at different times, rather than being a fixed value, and is related to specific operating conditions and the state of the DRAM.

[0037] In one embodiment, the safety threshold at any given time can be calculated as follows: obtain the difference between the operating temperature and the nominal temperature at the corresponding time, and the aging factor calculated based on the operating time and error count at the corresponding time; calculate the safety threshold at the corresponding time based on the nominal timing margin, temperature compensation coefficient and the difference, aging compensation coefficient and aging factor.

[0038] The nominal temperature refers to the reference operating temperature specified for DRAM devices under standard testing and calibration conditions.

[0039] The aging factor is a dimensionless quantitative parameter that characterizes the degree of chip aging, calculated based on the cumulative DRAM operating time and the correctable error (CE) / uncorrectable error (UE) count.

[0040] Nominal timing margin refers to the target safety margin benchmark value set for a certain timing parameter (such as tRCD) according to the specification under nominal operating conditions (i.e., nominal temperature, rated voltage, zero aging, typical load).

[0041] The temperature compensation coefficient is used to quantify the linear scaling factor of the negative impact of junction temperature rise on the timing margin safety boundary.

[0042] The aging compensation coefficient is used to quantify the linear scaling factor of the negative impact of chip aging on timing margin safety boundaries.

[0043] If described by an expression, the calculation formula for the above security threshold is as follows: Threshold dynamic = Threshold base × (1 - Ktemp × ΔT - K aging × Age factor); In the formula, Threshold base is the nominal timing margin; Ktemp is the temperature compensation coefficient, with a value of 0.004 / ℃ (positive number, as the temperature increases, the dynamic safety threshold decreases); ΔT is the difference between the current temperature and the nominal temperature; Kaging is the aging compensation coefficient, with a value of 0.1 (positive number, as the degree of aging increases, the dynamic safety threshold decreases); Age factor is the aging factor based on runtime and error count.

[0044] Understandably, the above method for calculating the safety threshold is also applicable to predicting the safety threshold. The only difference is that the two methods correspond to different times and the values ​​of the time-series correlation parameters used to calculate the corresponding time are different.

[0045] For the timing margin at any given time, the dynamic timing margin is, by way of example, calculated based on the timing correlation parameters after smoothing filtering. In one implementation, the calculation formula is as follows: Margin t=Threshold dynamic-St; In the formula, St is the filtered timing correlation parameter, representing the stable operating value of the key timing parameters of DRAM. Using St can ensure the stability of the timing margin calculation results and avoid frequent margin jumps and false alarms caused by noise in the original measurement value. Threshold dynamic is the safety threshold at the corresponding time, and Margin t is the timing margin at the same time as the safety threshold.

[0046] Furthermore, based on the predicted time series margin for each future time moment, a minimum time series margin is determined among multiple predicted time series margins. It can be understood that the predicted time series margin for future time moments can also be obtained using the dynamic time series margin calculation formula described above. Specifically, the predicted time series margin for the corresponding future time moment is determined based on the difference between the predicted safety threshold and the smoothed value of the time series parameters. Finally, the minimum predicted time series margin is selected from the predicted time series margins for each future time moment.

[0047] The minimum timing margin refers to the minimum available time margin remaining in all critical timing paths of the DRAM memory within a preset future prediction time window (e.g., the next 100 ms). Exemplarily, based on the current margin calculation logic combined with a predicted safety threshold, the minimum margin value within the next 1-10 μs is selected as the minimum timing margin for the predicted future time. It can be understood that by selecting a minimum timing margin to determine whether a warning signal needs to be generated in the future, frequent margin jumps can be avoided.

[0048] Optionally, the prediction model is trained offline on the server side using massive simulation and test data, and then the weight parameters are fixed into read-only memory (ROM) or configurable registers and implemented in hardware as a dedicated inference engine.

[0049] Step S206: When the minimum time margin is lower than the predicted safety threshold for the corresponding future time, an coded warning signal is generated based on the time-series correlation parameters of multiple future time. The coded warning signal includes risk level coding, risk type coding, and load status coding.

[0050] Among them, the coding warning signal refers to the multi-bit digital coding signal used to characterize the future timing risk status of DRAM.

[0051] Risk level coding refers to the discrete level identifier field in the coded early warning signal used to quantify the urgency of time-series margin, safety margin, and safety margin.

[0052] Risk type coding refers to the field in the coded warning signal used to identify specific failure-sensitive timing parameters.

[0053] Load status coding refers to the field in the coded warning signal that reflects the current operating condition of the system, including both memory load rate and performance mode information.

[0054] As an example, the predicted minimum future time-series margin is compared in real time with a margin warning threshold set according to a preset ratio based on the future dynamic safety threshold. If the predicted margin is lower than the threshold, a warning signal is generated. The warning signal is a multi-bit code and includes at least the following: risk level (e.g., 3 levels: low, medium, and high, divided according to different safety threshold ratios).

[0055] Optional warnings include: High-risk warning: Future minimum timing margin < 10% of dynamic safety threshold, timing buffer is extremely insufficient, and failure may be triggered at any time; Medium-risk warning: Dynamic safety threshold × 10% ≤ Future minimum timing margin < 20% of dynamic safety threshold, timing buffer is tight, and risk is gradually increasing; Low-risk warning: Dynamic safety threshold × 20% ≤ Future minimum timing margin < 30% of dynamic safety threshold, timing buffer is tight, requiring mild intervention), risk type (related to specific timing parameters, such as tRCD risk), and load status.

[0056] Step S208: Based on the risk level code, risk type code, and load status code, match the target state self-healing strategy in the preset strategy library and execute the target state self-healing strategy.

[0057] Among them, the target state self-healing strategy refers to a specific hardware operation combination that is pre-installed in the hardware / firmware strategy library and is executed in real time based on all encoded fields (risk level + risk type + load status) in the encoded early warning signal; in essence, it is a set of atomically executable register configuration instruction sequences.

[0058] In one embodiment, all state self-healing strategies in the preset strategy library are divided into three levels according to the degree of hardware adjustment. The three levels include an optimization scheduling strategy with increasing levels, a parameter fine-tuning strategy, and a tag isolation strategy.

[0059] Among them, the optimized scheduling strategy (denoted as Level 1) refers to a low-overhead strategy that improves timing buffer performance by fine-tuning the internal scheduling logic of the memory controller without changing the electrical parameters of the DRAM.

[0060] In one embodiment, the optimized scheduling strategy includes: writing to the idle insertion field of the memory controller configuration register via an arbitrator within the memory controller, and / or prioritizing the scheduling of commands accessing different banks. The idle insertion field refers to a hardware-writable bit field in the arbitration control register within the memory controller (MC) specifically used to configure the idle cycle insertion ratio.

[0061] For example, optimized scheduling strategies include: temporarily inserting a very small percentage of idle cycles (e.g., 0.5%) through the arbitrator inside the memory controller and writing the idle insertion field of the memory controller configuration register ARB_CTRL; prioritizing the scheduling of commands accessing different banks to alleviate timing pressure; and optimizing refresh scheduling / light command throttling.

[0062] The parameter fine-tuning strategy (referred to as Level 2) refers to a medium-overhead strategy that dynamically configures the electrical parameters of the PHY physical layer through the DFI interface to improve signal integrity and widen the data eye diagram.

[0063] Electrical parameters refer to key configurable analog / digital parameters in the DRAM physical layer interface (PHY) that directly affect signal integrity and setup / hold time. For example, parameter fine-tuning strategies include configuring PHY electrical parameters via the DFI interface to adjust drive strength, on-chip termination resistors, sampling clock phase, and minor voltage / frequency (V / F) adjustments. The marker isolation strategy (denoted as Level 3) is a high-overhead fault-tolerant strategy for high-risk scenarios involving data plane intervention, requiring coordinated hardware and software implementation.

[0064] In one embodiment, the marking and isolation strategy includes: marking high-risk access commands with warning signals; if an ECC error is returned, retrieving the high-risk access command from the retry queue and retransmitting it; and / or migrating frequently warning physical memory pages to a spare storage area, triggering the CE / UE (Correctable / Uncorrectable Error) processing flow. Here, a high-risk access command refers to a specific DRAM access command marked by the warning module as highly likely to cause data errors due to timing violations. The retry queue is a dedicated hardware FIFO buffer queue inside the memory controller, used to temporarily store access commands marked as high-risk that have not yet completed data verification. A physical memory page refers to a basic addressable data unit organized in rows within a DRAM storage array.

[0065] Based on the above three strategies, the step of matching the target state self-healing strategy in the preset strategy library includes the following sub-steps in some embodiments: If the current risk level corresponding to the risk level code is high, then the marked isolation strategy will be matched in the preset strategy library as the target state self-healing strategy.

[0066] If the current risk level corresponding to the risk level code is low, then it is further determined whether there is an aging trend. If not, then based on the load rate corresponding to the load status code, it is determined whether to match the optimized scheduling strategy as the target state self-healing strategy.

[0067] If the current risk level corresponding to the risk level code is medium, then it is further determined whether the operating temperature is greater than a preset temperature threshold. If it is, then a parameter fine-tuning strategy and / or optimized scheduling strategy are matched from the preset strategy library as the target state self-healing strategy. Furthermore, if the performance mode is high-performance mode, then a parameter fine-tuning strategy is matched from the preset strategy library as the target state self-healing strategy; if the performance mode is not high-performance mode, then a parameter fine-tuning strategy and optimized scheduling strategy are matched from the preset strategy library as the target state self-healing strategy.

[0068] To facilitate understanding of the above strategy matching rules, please refer to... Figure 3 Assuming that the multi-bit coded early warning signal is taken as the root node, the risk level is extracted as the core judgment criterion, and then combined with the ambient temperature (threshold 85°C), system load mode (high performance / low power consumption / load > 70% / load ≤ 70%) and aging trend as branch conditions, the optimal strategy is output based on the matching rules. For example, in low-risk + aging trend scenarios, only optimized scheduling strategies (such as optimized refresh scheduling) are executed; in low-risk + system load > 70%, only optimized scheduling strategies (mild command throttling) are executed; in low-risk + system load ≤ 70%, no active strategy is implemented, and continuous monitoring is performed; in medium-risk + temperature > 85°C, optimized scheduling strategies (such as idle cycle insertion) + parameter fine-tuning strategies (such as ODT, on-chip system termination resistor adjustment) are executed; in medium-risk + high-performance mode, only parameter fine-tuning strategies (such as PHY parameter fine-tuning) are executed; in medium-risk + temperature ≤ 85°C + low-power mode, optimized scheduling strategies (optimized scheduling) + parameter fine-tuning strategies (mild drive strength fine-tuning) are executed; in high-risk + any scenario, a marking and isolation strategy (high-risk command retry, partial data migration) is executed.

[0069] In one embodiment, the method further includes: after the strategy is executed, continuing to acquire the physical interface signal of the DRAM memory to obtain the updated timing correlation parameters, calculating the updated minimum timing margin based on the updated timing correlation parameters, and feeding back the calculated change in timing margin before and after the strategy execution to the prediction model to evaluate the effectiveness of the target state self-healing strategy.

[0070] It is understandable that after the self-healing strategy is executed, the system re-collects time series data and calculates new smoothing values ​​through filters. By comparing the smoothing values ​​before and after the strategy execution and the corresponding changes in margin, the effectiveness of the strategy is evaluated: if the smoothing value decreases and the margin increases, the strategy is deemed effective; if there is no significant improvement, a higher priority self-healing strategy is immediately switched.

[0071] Optionally, the method further includes: using a circular buffer to store log entries, each log entry containing: a timestamp, an alert event, an execution policy, and changes in timing margin before and after policy execution. It supports dynamic updating of policy library parameters or alert thresholds at runtime via a software interface to achieve system optimization. Furthermore, the smoothed continuous timing-related parameter data is permanently retained as core health data, used by operations and maintenance personnel to trace DRAM aging trends, locate intermittent faults, and conduct predictive maintenance.

[0072] Figure 4 A schematic diagram of a DRAM state management device according to an embodiment of this application is shown. Exemplarily, the DRAM state management device 400 includes: The data acquisition module 402 is used to continuously acquire the physical interface signal connected to the DRAM memory based on a preset time window, obtain the timing correlation parameters of the DRAM memory at the corresponding time, and preprocess the timing correlation parameters. The prediction and early warning module 404 is used to input the preprocessed time series correlation parameters into the prediction model for prediction, obtain the time series correlation parameters of multiple future times, and then determine the prediction safety threshold of multiple future times and a minimum time series margin within multiple future times. The prediction and early warning module 404 is also used to generate a coded early warning signal based on time-series correlation parameters of multiple future times when the minimum time-series margin is lower than the predicted safety threshold of the corresponding future time. The coded early warning signal includes risk level coding, risk type coding and load status coding. The strategy execution module 406 is used to match the target state self-healing strategy in the preset strategy library based on the risk level code, risk type code, and load state code, and then execute the target state self-healing strategy.

[0073] Optionally, the DRAM status management device 400 further includes a health status reporting module, which receives and records the aforementioned encoded warning signals, target status self-healing strategies, and execution results, and generates a report log to feed back to the memory controller.

[0074] It is understood that the device in this embodiment corresponds to the DRAM state management method in the above embodiment, and the options in the above embodiment are also applicable to this embodiment, so they will not be described again here.

[0075] This application also provides a terminal device, exemplary of which includes a processor and a memory, wherein the memory stores a computer program, and the processor executes the computer program to enable the terminal device to perform the functions of the various modules in the above-described DRAM state management method or the above-described DRAM state management device.

[0076] The processor can be an integrated circuit chip with signal processing capabilities. The processor can be a general-purpose processor, including at least one of a Central Processing Unit (CPU), Graphics Processing Unit (GPU), Network Processor (NP), Digital Signal Processor (DSP), Application-Specific Integrated Circuit (ASIC), Field-Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The general-purpose processor can be a microprocessor or any conventional processor, capable of implementing or executing the methods, steps, and logic block diagrams disclosed in the embodiments of this application.

[0077] Memory can be, but is not limited to, Random Access Memory (RAM), Read Only Memory (ROM), Programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM), and Electrically Erasable Programmable Read-Only Memory (EEPROM). Memory is used to store computer programs, and the processor can execute these programs upon receiving execution instructions.

[0078] This application also provides a computer-readable storage medium for storing computer programs used in the aforementioned terminal devices. For example, the computer-readable storage medium may include, but is not limited to, various media capable of storing program code, such as a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0079] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings show the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code, which contains one or more executable instructions for implementing a specified logical function. It should also be noted that, as an alternative implementation, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and combinations of blocks in the block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0080] In addition, the functional modules or units in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0081] If a function is implemented as a software module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a smartphone, personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application.

[0082] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A DRAM state management method, characterized in that, include: Based on a preset time window, the physical interface signal connected to the DRAM memory is continuously acquired to obtain the timing correlation parameters of the DRAM memory at the corresponding time and the timing correlation parameters are preprocessed. The preprocessed time-series correlation parameters are input into the prediction model for prediction to obtain time-series correlation parameters for multiple future times, and then the prediction safety threshold and a minimum time-series margin within the multiple future times are determined. When the minimum time margin is lower than the predicted safety threshold at the corresponding future time, an coded warning signal is generated based on the time-series correlation parameters of the multiple future times, wherein the coded warning signal includes risk level coding, risk type coding and load status coding. Based on the risk level code, the risk type code, and the load state code, a target state self-healing strategy is matched in the preset strategy library and the target state self-healing strategy is executed.

2. The method according to claim 1, characterized in that, The method further includes: After the strategy is executed, the physical interface signal of the DRAM memory is collected to obtain the updated timing correlation parameters. The updated minimum timing margin is calculated based on the updated timing correlation parameters. The calculated change in timing margin before and after the strategy execution is fed back to the prediction model to evaluate the effectiveness of the target state self-healing strategy.

3. The method according to claim 1, characterized in that, The timing correlation parameters include specified timing parameters, operating frequency, and load parameters for each acquisition time point of the DRAM memory; the step of inputting the preprocessed timing correlation parameters into the prediction model for prediction to obtain the timing correlation parameters for future times, and then determining the prediction safety threshold for future times and a minimum timing margin within the future times, includes: The specified time series parameters, the operating frequency, and the load parameters collected at each time point are collected in time sequence to form a sequence feature, which is then input into the prediction model to output the time series correlation parameters for each moment within a future preset time period. Based on the temporal correlation parameters at each future time, the predicted safety threshold for each future time is determined; Based on the time-series correlation parameters and the prediction safety threshold for each future time, the prediction time-series margin for each future time is determined, and the minimum time-series margin is determined among the multiple prediction time-series margins. The prediction model is constructed based on a long short-term memory network.

4. The method according to claim 3, characterized in that, The timing correlation parameters also include the DRAM memory's operating temperature, runtime, and error count data. Determining the predicted safety threshold for each future time based on the timing correlation parameters for each future time includes: Obtain the difference between the operating temperature and the nominal temperature at the corresponding future time, and the aging factor calculated based on the running time and the error count at the corresponding future time; Based on the nominal timing margin, temperature compensation coefficient and the difference, aging compensation coefficient and the aging factor, the predicted safety threshold for the corresponding future time is calculated.

5. The method according to claim 3, characterized in that, All state self-healing strategies in the preset strategy library are divided into three levels according to the degree of hardware adjustment in a timely manner. The three levels include an optimization scheduling strategy with increasing level, a parameter fine-tuning strategy, and a marking isolation strategy. The step of matching a target state self-healing strategy in a preset strategy library based on the risk level code, the risk type code, and the load state code includes: If the current risk level corresponding to the risk level code is high, then the marked isolation strategy is matched in the preset strategy library as the target state self-healing strategy. If the current risk level corresponding to the risk level code is low, then it is further determined whether there is an aging trend. If not, then it is determined whether to match the optimized scheduling strategy as the target state self-healing strategy based on the load rate corresponding to the load state code. If the current risk level corresponding to the risk level code is medium, then it is further determined whether the working temperature is greater than the preset temperature threshold. If it is greater, then the parameter fine-tuning strategy and / or the optimized scheduling strategy are matched in the preset strategy library as the target state self-healing strategy.

6. The method according to claim 5, characterized in that, Also includes: If the current risk level corresponding to the risk level code is medium, then it is further determined whether the operating temperature is greater than the preset temperature threshold. If the operating temperature is less than or equal to the preset temperature threshold, it is determined whether the performance mode of the DRAM memory is high performance mode. If it is in high-performance mode, the parameter fine-tuning strategy is matched in the preset strategy library as the target state self-healing strategy. If it is a non-high-performance mode, the parameter fine-tuning strategy and / or the optimized scheduling strategy are matched in the preset strategy library as the target state self-healing strategy.

7. The method according to claim 5 or 6, characterized in that, The optimized scheduling strategy includes: writing to the free insertion field of the memory controller configuration register through the arbitrator inside the memory controller, and / or prioritizing the scheduling of commands that access different banks; The parameter fine-tuning strategy includes: configuring the electrical parameters of the physical layer interface of the system-on-chip via the DFI interface; The marking and isolation strategy includes: marking high-risk access commands of the warning signal; if an ECC error is returned, retrieving the high-risk access command from the command retry queue and resending it; and / or migrating the physical memory pages with frequent warnings to a spare storage area.

8. The method according to claim 1, characterized in that, The process of continuously acquiring physical interface signals connected to the DRAM memory based on a preset time window, obtaining timing correlation parameters of the DRAM memory at corresponding times, and preprocessing the timing correlation parameters includes: Based on a preset time window, the physical interface signal connected to the DRAM memory is continuously acquired to obtain the original timing correlation parameters of the DRAM memory at each acquisition time point within the preset time window; For each acquisition time point within the preset time window, determine the previous original time sequence correlation parameter corresponding to the previous acquisition time point of the target acquisition time point. Based on the previous original time series correlation parameters, the original time series correlation parameters corresponding to the target acquisition time point, and the preset smoothing coefficient, the time series correlation parameters for the target acquisition time point are determined.

9. A DRAM status management device, characterized in that, include: The data acquisition module is used to continuously acquire the physical interface signal connected to the DRAM memory based on a preset time window, obtain the timing correlation parameters of the DRAM memory at the corresponding time, and preprocess the timing correlation parameters. The prediction and early warning module is used to input the preprocessed time series correlation parameters into the prediction model for prediction, obtain the time series correlation parameters of multiple future times, and then determine the prediction safety threshold of the multiple future times and a minimum time series margin within the multiple future times. And when the minimum time margin is lower than the predicted safety threshold at the corresponding future time, an coded warning signal is generated based on the time-series correlation parameters of the multiple future times, wherein the coded warning signal includes risk level coding, risk type coding and load status coding; The strategy execution module is used to match a target state self-healing strategy in a preset strategy library based on the risk level code, the risk type code, and the load state code, and execute the target state self-healing strategy.

10. A DRAM state management system, characterized in that, include: The system-on-a-chip includes a main controller, a memory controller, and a command scheduler. The system-on-a-chip is also connected to a DRAM memory via a physical layer interface. The controller is used to execute the DRAM state management method according to any one of claims 1 to 8, wherein, when executing the target state self-healing strategy, the memory controller and / or the command scheduler are triggered to configure the electrical parameters of the physical layer interface through the DFI interface.

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