Preparation method of support plate structure, support plate structure and semiconductor packaging structure

Abstract

The embodiment of the invention provides a preparation method of a support plate structure, the support plate structure and a semiconductor packaging structure, and the preparation method of the support plate structure comprises the steps: preparing a conductive column at one side of a first layer-adding assembly along the thickness direction, the first layer-adding assembly comprises a first conductive part, and the first conductive part is electrically connected with the conductive column; preparing a bonding part on one side of the first layer-adding assembly along the thickness direction of the first layer-adding assembly, wherein the bonding part and the conductive column are located on the same side of the first layer-adding assembly; a through hole is formed in the preparation substrate in a penetrating mode, so that a substrate is formed; sleeving the conductive column with the substrate and pressing the substrate on the bonding part; and curing the bonding part. According to the embodiment of the invention, the processing performance of the support plate structure can be improved.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a method for preparing a substrate structure, the substrate structure, and a semiconductor packaging structure. Background Technology

[0002] The substrate structure for integrated circuits (ICs), also known as the IC packaging substrate, is used directly to mount the IC. It not only provides support and protection for the IC but also enables the connection between the IC and the printed circuit board (PCB). In short, the substrate structure is the core element for supporting the IC and enabling high-speed communication and effective heat dissipation between the IC and the outside world. The IC transmits electrical signals through conductive parts of the add-on components on the upper surface of the substrate to conductive pillars located in the through-holes of the substrate. These conductive pillars then transmit the electrical signals to conductive parts of the add-on components on the other side of the substrate, which in turn transmit the electrical signals to the printed circuit board, thus achieving the electrical interconnection between the IC and the printed circuit board.

[0003] However, current integrated circuit packaging technology still faces several technical challenges. Existing technologies typically involve first creating vias in the substrate, then directly electroplating conductive pillars within these vias, followed by fabricating add-on components on both sides of the substrate. These processes all rely on the substrate as a support, making them susceptible to reliability issues such as substrate cracking. This compromises the process performance of the substrate structure and consequently affects the electrical interconnection between the integrated circuit and the printed circuit board. Therefore, it is necessary to select appropriate processing methods to reduce the risk of cracking. Summary of the Invention

[0004] This application provides a method for preparing a carrier structure, a carrier structure, and a semiconductor packaging structure, aiming to improve the process performance of the carrier structure.

[0005] An embodiment of the first aspect of this application provides a method for preparing a carrier plate structure, the method comprising: A conductive post is prepared on one side of the first add-layer assembly along its thickness direction. The first add-layer assembly includes a first conductive portion, which is electrically connected to the conductive post. An adhesive portion is prepared on one side of the first add-layer component along its thickness direction, and the adhesive portion and the conductive post are located on the same side of the first add-layer component. Through-holes are formed on a pre-substrate to form a substrate; The substrate is fitted onto the conductive post and pressed onto the adhesive portion; The bonded portion is then cured.

[0006] According to the embodiment described in the first aspect of this application, in the step of sleeved the substrate on the conductive post and pressed it onto the adhesive portion, a first gap is formed between the side surface of the conductive post surrounding its axial direction and the wall of the through hole. Before curing the adhesive portion, the method further includes: filling the first gap with a first buffer portion, the first buffer portion being connected to the adhesive portion, and at least a portion of the surface of the conductive post being exposed from the first buffer portion; In the step of curing the adhesive portion: The adhesive portion and the first buffer portion are cured.

[0007] According to any of the foregoing embodiments of the first aspect of this application, in the step of filling the first gap with the first buffer portion: A buffer material is applied to the surface of the substrate opposite to the first layering component, and the buffer material is allowed to penetrate into the first gap. After the buffer material located within the first gap cures, it forms the first buffer portion; after the buffer material located outside the first gap cures, it forms the second pre-buffered portion. Following the step of curing the adhesive portion and the first buffer portion, the method further includes: Remove the second pre-buffered portion to expose the conductive post; Alternatively, after the step of curing the adhesive portion and the first buffer portion, the method further includes: The second pre-buffered portion is patterned to form a first clearance hole and a second buffer portion surrounding the first clearance hole, with at least a portion of the surface of the conductive post exposed through the first clearance hole.

[0008] According to any of the foregoing embodiments of the first aspect of this application, in the step of fabricating a conductive pillar on one side of the first layered assembly along its thickness direction: A seed layer is formed on the first layering component, the seed layer including a first seed portion and a second seed portion connected together; The conductive pillar is formed on the seed layer, and the orthographic projection of the conductive pillar along the thickness direction covers the orthographic projection of the first seed portion along the thickness direction. Remove the second seed portion, and the conductive post is electrically connected to the first conductive portion through the first seed portion.

[0009] According to any of the foregoing embodiments of the first aspect of this application, in the step of forming the conductive pillar on the seed layer: Photoresist is applied to the side of the seed layer opposite to the first build-up assembly; The photoresist is patterned to form photoresist openings and photoresist residues surrounding the photoresist openings, the photoresist openings exposing at least a portion of the seed layer; Conductive material is electroplated on the exposed seed layer through the photoresist opening to form the conductive pillar; Remove the photoresist residue.

[0010] According to any of the foregoing embodiments of the first aspect of this application, in the step of fabricating a conductive pillar on one side of the first layered assembly along its thickness direction: Photoresist is applied to the first layered component; The photoresist is patterned to form photoresist openings and photoresist residues surrounding the photoresist openings, the photoresist openings exposing at least a portion of the first conductive portion; Conductive material is electroplated on the exposed first conductive portion through the photoresist opening to form the conductive pillar; Remove the photoresist residue.

[0011] According to any of the foregoing embodiments of the first aspect of this application, at least a portion of the adhesive portion is in contact with the sidewall of the conductive post surrounding its axial direction, and the end face of the conductive post away from the first layering assembly is recessed within the through hole. In the step of filling the first buffer portion into the first gap: A buffer material is applied to the surface of the substrate opposite to the first layering component, and the buffer material is allowed to penetrate the through-hole, with the buffer material covering the end face of the conductive post away from the first layering component. In the step of curing the adhesive portion and the first buffer portion: The buffer material located within the first gap is cured to form the first buffer portion; the buffer material located on the side of the conductive post opposite to the first layering assembly and within the through hole is cured to form a first pre-material portion; and the buffer material located outside the through hole is cured to form a second pre-material portion. After the step of curing the adhesive portion and the first buffer portion, the method further includes: The second preparatory material portion and the first preparatory material portion are patterned to form a second buffer portion. The second buffer portion has a through-hole first clearance hole, and at least a portion of the surface of the conductive post is exposed through the first clearance hole. Alternatively, after the step of curing the adhesive portion and the first buffer portion, the method further includes: Remove the second preparatory material section; The first preparatory material is patterned to form a second buffer portion, the second buffer portion having a through-hole first clearance hole, at least a portion of the surface of the conductive post being exposed through the first clearance hole.

[0012] According to any of the foregoing embodiments of the first aspect of this application, prior to the step of fabricating a conductive pillar on one side of the first layered assembly along its thickness direction, the method further includes: The first layered assembly is prepared on a first temporary stage. The first layered assembly includes a first insulating portion and a conductive portion including a first conductive sub-part and an electrical connection portion connected together. The first conductive sub-part is embedded in the first insulating portion, and the surface of the first conductive sub-part facing away from the electrical connection portion is flush with the first insulating portion. The electrical connection portion protrudes from the side of the first insulating portion facing away from the first temporary stage. Debond the first conductive part and the first insulating part to the first temporary stage; The electrical connection portion is temporarily bonded to the first temporary stage to expose at least a portion of the surface of the first conductive electronic portion.

[0013] A second aspect of this application provides a carrier plate structure obtained by a method for preparing a carrier plate structure as described in any embodiment of the first aspect of this application, the carrier plate structure comprising: The first layering component includes a first conductive portion; A conductive post, which is electrically connected to the first conductive part; A substrate having a through hole extending through its thickness, wherein the conductive post is located in the through hole; An adhesive portion is located between the first layering component and the substrate, and is used to fix the substrate to the first layering component; The conductive post forms a first gap with the wall of the through hole by its axially surrounding side surface. The carrier plate structure further includes a first buffer portion, at least a portion of which is located in the first gap, and the adhesive portion is connected to the first buffer portion.

[0014] According to any of the foregoing embodiments of the second aspect of this application, it further includes: The first seed section is connected to the first conductive section and the conductive post, respectively; The adhesive portion is disposed between adjacent first seed portions, and the dimension of the adhesive portion along the thickness direction is equal to the dimension of the first seed portion along the thickness direction; The projection of the adhesive portion along the thickness direction at least partially overlaps with the projection of the through hole along the thickness direction; the adhesive portion is in contact with the first seed portion; and the first buffer portion is located within the first gap. Alternatively, the projection of the adhesive portion along the thickness direction is spaced apart from the projection of the through hole along the thickness direction, and the first buffer portion extends from the first gap to the space between the substrate and the first layering component, and is connected to the adhesive portion.

[0015] According to any of the foregoing embodiments of the second aspect of this application, it further includes: A second buffer section has a first clearance hole, through which at least a portion of the surface of the conductive post is exposed. The second buffer portion is located on the surface of the substrate opposite to the first layering component and surrounds at least a portion of the hole wall of the through hole.

[0016] The third aspect of this application also provides a semiconductor packaging structure, including a carrier structure prepared by the method for preparing a carrier structure according to any embodiment of the first aspect of this application, or including a carrier structure according to any embodiment of the second aspect of this application.

[0017] In this embodiment, conductive pillars are fabricated on one side of the first add-layer assembly along its thickness direction. The first add-layer assembly includes a first conductive portion, which is electrically connected to the conductive pillar. That is, the conductive pillar can be formed on the first add-layer assembly using it as a support. Compared to the prior art method of directly fabricating conductive pillars within the through-holes of the substrate, this embodiment reduces the difficulty of filling the holes and eliminates the need to fabricate the first add-layer assembly on the surface of the substrate, reducing the risk of substrate cracking during fabrication. An adhesive portion is fabricated on one side of the first add-layer assembly along its thickness direction. The adhesive portion and the conductive pillar are located on the same side of the first add-layer assembly. The adhesive portion is used to bond and fix the substrate to the first add-layer assembly during fabrication. A through-hole is fabricated on the pre-fabricated substrate to form the substrate. This step provides the necessary conditions for the subsequent mounting of the substrate onto the conductive pillar. After forming the adhesive portion and the through-hole on the substrate, the substrate is fitted onto the conductive post and pressed onto the adhesive portion. The conductive post is located in the through-hole, thus achieving a fixed connection between the substrate, the conductive post and the first add-on component. Finally, the adhesive portion is cured. The cured adhesive portion can provide buffer protection for the substrate, which can buffer the stress between the substrate and the first add-on component, thereby reducing the risk of substrate cracking during use, improving the process performance of the carrier board structure, and thus ensuring the electrical interconnection effect between the integrated circuit and the printed circuit board. Attached Figure Description

[0018] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings, wherein the same or similar reference numerals denote the same or similar features.

[0019] Figure 1 This is a flowchart illustrating a method for preparing a carrier plate structure according to an embodiment of this application; Figure 2 This is one of the illustrations showing the fabrication process of a carrier plate structure provided in the embodiments of this application; Figure 3 This is the second illustration of the fabrication process of a carrier plate structure provided in this application embodiment; Figure 4 This is the third illustration of the fabrication process of a carrier plate structure provided in this application embodiment; Figure 5 This is the fourth illustration of the fabrication process of a carrier plate structure provided in this application embodiment; Figure 6 This is a flowchart illustrating a method for preparing a carrier plate structure according to another embodiment of this application; Figure 7 This is the fifth illustration of the fabrication process of a carrier plate structure provided in this application embodiment; Figure 8 This is the sixth illustration of the fabrication process of a carrier plate structure provided in this application embodiment; Figure 9 This is a flowchart of a method for preparing a carrier plate structure according to another embodiment of this application; Figure 10 This is the seventh illustration of the fabrication process of a carrier plate structure provided in this application embodiment; Figure 11 This is the eighth illustration of the fabrication process of a carrier plate structure provided in this application embodiment; Figure 12 This is a flowchart of a method for preparing a carrier plate structure according to another embodiment of this application; Figure 13 This is the ninth illustration of the fabrication process of a carrier plate structure provided in the embodiments of this application; Figure 14 This application also provides a flowchart of a method for preparing a carrier plate structure according to another embodiment; Figure 15 This application also provides a flowchart of a method for preparing a carrier plate structure according to another embodiment; Figure 16 This is the tenth illustration of the fabrication process of a carrier plate structure provided in the embodiments of this application; Figure 17 This is Figure eleven illustrating the fabrication process of a carrier plate structure provided in this application embodiment; Figure 18 This application also provides a flowchart of a method for preparing a carrier plate structure according to another embodiment; Figure 19 This is one of the illustrations showing the fabrication process of a carrier plate structure provided in another embodiment of this application; Figure 20 This is the second illustration of the fabrication process of a carrier plate structure provided in another embodiment of this application; Figure 21 This is the third illustration of the fabrication process of a carrier plate structure provided in another embodiment of this application; Figure 22 This is the fourth illustration of the fabrication process of a carrier plate structure provided in another embodiment of this application; Figure 23 This is the fifth illustration of the fabrication process of a carrier plate structure provided in another embodiment of this application; Figure 24 This is the sixth illustration of the fabrication process of a carrier plate structure provided in another embodiment of this application; Figure 25 This application also provides a flowchart of a method for preparing a carrier plate structure according to another embodiment; Figure 26 This is the seventh illustration of the fabrication process of a carrier plate structure provided in another embodiment of this application; Figure 27 This application also provides a flowchart of a method for preparing a carrier plate structure according to another embodiment; Figure 28 This is the eighth illustration of the fabrication process of a carrier plate structure provided in another embodiment of this application; Figure 29 This application also provides a flowchart of a method for preparing a carrier plate structure according to another embodiment; Figure 30 This is the ninth illustration of the fabrication process of a carrier plate structure provided in another embodiment of this application; Figure 31 This is the tenth illustration of the fabrication process of a carrier plate structure provided in another embodiment of this application; Figure 32 This is a partial cross-sectional view of a carrier plate structure provided in the second aspect embodiment of this application; Figure 33 This is a partial cross-sectional view of a carrier plate structure provided in another embodiment of the second aspect of this application; Figure 34 This is a partial cross-sectional view of a carrier plate structure provided in another embodiment of the second aspect of this application; Figure 35 This is a partial cross-sectional view of a carrier plate structure provided in another embodiment of the second aspect of this application.

[0020] Explanation of reference numerals in the attached figures: 1. First layering component; 11. First conductive part; 111. First conductive part; 112. Electrical connection part; 12. First insulating part; 2. Conductive pillar; 3. Adhesive part; 31. Connecting hole; 4. Substrate; 41. Through hole; 42. First gap; 5. First buffer section; 6. Second buffer section; 61. First clearance hole; 7. Seed layer; 71. First seed part; 72. Second seed part; 8. Photoresist; 81. Photoresist opening; 82. Photoresist residue; 10 First preparatory material section; 20 Second preparatory material section; 30 First temporary stage; 301 Bonding adhesive; 40 Second add-on assembly; 401 Second conductive part; 50. Solder resist layer; 501. First opening; 60. Solder section; 70. Surface treatment material; Z, thickness direction. Detailed Implementation

[0021] The features and exemplary embodiments of various aspects of this application will now be described in detail. Numerous specific details are set forth in the following detailed description to provide a comprehensive understanding of this application. However, it will be apparent to those skilled in the art that this application can be implemented without requiring some of these specific details. The following description of embodiments is merely intended to provide a better understanding of this application by illustrating examples. In the accompanying drawings and the following description, at least some well-known structures and techniques are not shown to avoid unnecessarily obscuring the application; and, for clarity, the dimensions of some structures may be exaggerated. Furthermore, the features, structures, or characteristics described below can be combined in any suitable manner in one or more embodiments.

[0022] In the description of this application, it should be noted that, unless otherwise stated, "a plurality of" means two or more; the terms "upper," "lower," "left," "right," "inner," "outer," etc., indicating orientation or positional relationships are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0023] The directional terms appearing in the following description refer to the directions shown in the figures and are not intended to limit the specific structure of the embodiments of this application. It should also be noted in the description of this application that, unless otherwise explicitly specified and limited, the terms "installation" and "connection" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0024] The substrate structure for integrated circuits (ICs), also known as the IC packaging substrate, is used directly to mount the IC. It not only provides support and protection for the IC but also enables the connection between the IC and the printed circuit board (PCB). In short, the substrate structure is the core element for supporting the IC and enabling high-speed communication and effective heat dissipation between the IC and the outside world. The IC transmits electrical signals through conductive parts of the add-on components on the upper surface of the substrate to conductive pillars located in the through-holes of the substrate. These conductive pillars then transmit the electrical signals to conductive parts of the add-on components on the other side of the substrate, which in turn transmit the electrical signals to the printed circuit board, thus achieving the electrical interconnection between the IC and the printed circuit board.

[0025] However, current integrated circuit packaging technology still faces several technical challenges. Existing technologies typically involve first creating vias in the substrate, then directly electroplating conductive pillars within these vias, followed by fabricating add-on components on both sides of the substrate. These processes all rely on the substrate as a support, making them susceptible to reliability issues such as substrate cracking. This compromises the process performance of the substrate structure and consequently affects the electrical interconnection between the integrated circuit and the printed circuit board. Therefore, it is necessary to select appropriate processing methods to reduce the risk of cracking.

[0026] The following provides a detailed description of the preparation method of the carrier structure, the carrier structure, and the semiconductor packaging structure according to the embodiments of this application.

[0027] like Figure 1 As shown in the embodiment of this application, a method for preparing a carrier plate structure is provided, the method comprising: Step S01: A conductive post 2 is fabricated on one side of the first add-layer assembly 1 along its thickness direction Z. The first add-layer assembly 1 includes a first conductive portion 11, which is electrically connected to the conductive post 2. (See reference...) Figure 2 .

[0028] Step S02: An adhesive portion 3 is prepared on one side of the first layering component 1 along its thickness direction Z. The adhesive portion 3 and the conductive post 2 are located on the same side of the first layering component 1. (See reference...) Figure 3 .

[0029] Step S03: A through-hole 41 is formed on the pre-substrate 4 to form the substrate 4. (See reference...) Figure 4 .

[0030] Step S04: Place the substrate 4 onto the conductive post 2 and press it onto the adhesive portion 3. (See reference...) Figure 5 .

[0031] Step S05: Curing the bonded portion 3.

[0032] In this embodiment, in step S01, a conductive post 2 is prepared on one side of the first add-layer component 1 along its thickness direction Z. The first add-layer component 1 includes a first conductive part 11, which is electrically connected to the conductive post 2. That is, the conductive post 2 can be formed on the first add-layer component 1 as a support. Compared with the prior art method of directly preparing the conductive post 2 in the through hole 41 of the substrate 4, this embodiment can reduce the difficulty of filling the hole and eliminate the need to prepare the first add-layer component 1 on the surface of the substrate 4, thus reducing the risk of cracking of the substrate 4 during the preparation process. In step S02, an adhesive part 3 is prepared on one side of the first add-layer component 1 along its thickness direction Z. The adhesive part 3 and the conductive post 2 are located on the same side of the first add-layer component 1. The adhesive part 3 is used to bond and fix the substrate 4 to the first add-layer component 1 during the preparation process. In step S03, a through hole 41 is prepared on the prepared substrate 4 to form the substrate 4. This step is used to provide the necessary conditions for the subsequent mounting of the substrate 4 onto the conductive post 2. After forming the adhesive portion 3 and the through hole 41 on the substrate 4, the substrate 4 is fitted onto the conductive post 2 and pressed onto the adhesive portion 3 in step S04. The conductive post 2 is located in the through hole 41, realizing the fixed connection between the substrate 4, the conductive post 2 and the first layer addition component 1. Finally, the adhesive portion 3 is cured in step S05. The cured adhesive portion 3 can provide buffer protection for the substrate 4, which can buffer the stress between the substrate 4 and the first layer addition component 1, thereby reducing the risk of cracking of the substrate 4 during use, improving the process performance of the carrier board structure, and thus ensuring the electrical interconnection effect between the integrated circuit and the printed circuit board.

[0033] In this embodiment, steps S01 and S02 are performed sequentially, and steps S04 and S05 are performed sequentially. Optionally, step S03 can be performed simultaneously with step S01 or step S02, or before step S01, or after step S02. That is, while preparing the conductive pillar 2 or the adhesive portion 3, through holes 41 can be formed on the pre-substrate 4 on the temporary worktable, or through holes 41 can be formed on the pre-substrate 4 before preparing the conductive pillar 2, in order to improve preparation efficiency. Alternatively, through holes 41 can be formed on the pre-substrate 4 after preparing the adhesive portion 3; this embodiment does not specifically limit this.

[0034] Optionally, the preparation process is carried out in the order of steps S03, S01, S02, S04 and S05.

[0035] Optionally, the substrate 4 in this embodiment is made of glass. Substrate 4 not only possesses advantages in material properties such as high modulus, high flatness, low coefficient of thermal expansion, and good chemical and high-temperature resistance, but also exhibits superior material properties. During packaging, substrate 4 can withstand higher temperatures better than organic substrates, and its coefficient of thermal expansion is similar to that of silicon, thereby reducing stress warping problems caused by thermal mismatch. The high flatness and low roughness of the glass surface allow for denser wiring. Furthermore, the glass substrate 4 has a lower dielectric constant and dielectric loss, which can improve signal transmission speed and signal integrity, while also exhibiting excellent chemical stability, effectively resisting environmental corrosion such as moisture and acids / alkalis.

[0036] Optionally, the substrate 4 is at least one of borosilicate glass, aluminoborosilicate glass, quartz glass, alkali-free glass, and alkaline glass.

[0037] In some embodiments, the first layering assembly 1 further includes a first insulating portion 12. At least a portion of the first conductive portion 11 is embedded in the first insulating portion 12, wherein both the substrate 4 and the first insulating portion 12 are made of glass.

[0038] The first conductive portion 11 is embedded in the first insulating portion 12 to provide physical protection for the first conductive portion 11, reducing the risk of short circuits and moisture intrusion. The substrate 4 and the first insulating portion 12 are made of the same material, glass, which allows for a smaller difference in their coefficients of thermal expansion, mitigating displacement, warping, glass breakage, or localized stress concentration caused by mismatched coefficients of thermal expansion. Compared to using organic materials such as epoxy resin or polyimide for the first insulating portion 12, the carrier structure of this embodiment has a lower dielectric constant, lower dielectric loss, and greater mechanical strength, improving the processability of the carrier structure.

[0039] In some embodiments, the material of the first insulating part 12 may also be at least one of borosilicate glass, aluminoborosilicate glass, quartz glass, alkali-free glass, and alkaline glass.

[0040] Optionally, the first insulating part 12 is formed by curing a liquid glass coating.

[0041] In other embodiments, the material of the first insulating portion 12 may also be an organic material, such as polyimide, photosensitive polyimide, or resin material.

[0042] When substrate 4 is a glass substrate 4, via 41 is a through glass via (TGV). A through glass via is a structure that enables electrical interconnection through holes in substrate 4, similar to through silicon via (TSV), and has better three-dimensional interconnection capabilities.

[0043] Optionally, the cross-sectional shape of the through hole 41 in the direction parallel to the through hole 41 may include rectangular, circular, trapezoidal or X-shaped, etc., and the embodiments of this application are not limited thereto.

[0044] Optionally, the conductive post 2 may be made of a metallic material, such as, but not limited to, at least one of copper (Cu), aluminum (Al), nickel (Ni), gold (Au), tin (Sn), silver (Ag).

[0045] Optionally, the first conductive part 11 includes a metallic material, such as, but not limited to, at least one of copper (Cu), aluminum (Al), nickel (Ni), gold (Au), tin (Sn), silver (Ag).

[0046] Optionally, the material of the first conductive part 11 is the same as the material of the conductive post 2, in order to simplify the manufacturing process and reduce the resistivity between the first conductive part 11 and the conductive post 2.

[0047] Optionally, in step S02, the material of the adhesive portion 3 includes at least one of epoxy resin, polyimide, or Ajinomoto build-up film (ABF), possessing good adhesion to ensure that the substrate 4 can be securely fixed to the first build-up component 1. In step S05, after curing, the adhesive portion 3 exhibits good buffering properties, providing buffer protection for the substrate 4. It can buffer the stress between the substrate 4 and the first build-up component 1, thereby reducing the risk of cracking of the substrate 4 during use, improving the process performance of the carrier structure, and thus ensuring the electrical interconnection effect between the integrated circuit and the printed circuit board.

[0048] In some embodiments, before step S01, such as Figure 6 As shown, the method further includes step S10: Step S11: Fabricate a first layering assembly 1 on the first temporary stage 30. The first layering assembly 1 includes a first insulating portion 12 and a conductive portion including a connected first conductive sub-portion 111 and an electrical connection portion 112. The first conductive sub-portion 111 is embedded in the first insulating portion 12, and the surface of the first conductive sub-portion 111 facing away from the electrical connection portion 112 is flush with the first insulating portion 12. The electrical connection portion 112 protrudes from the side of the first insulating portion 12 facing away from the first temporary stage 30. (See reference...) Figure 7 .

[0049] Step S12: Debond the first conductive part 111 and the first insulating part 12 to the first temporary stage 30.

[0050] Step S13: Temporarily bond the electrical connection portion 112 to the first temporary stage 30 to expose at least a portion of the surface of the first conductive electronic portion 111. (See reference...) Figure 8 .

[0051] In these embodiments, before performing step S01, the first add-layer assembly 1 is first fabricated on the first temporary stage 30 via step S11. During fabrication, bonding adhesive 301 is first applied to the first temporary stage 30, and a first conductive portion 111 and a first insulating portion 12 are formed on the surface of the bonding adhesive 301. The first conductive portion 111 is embedded within the first insulating portion 12, and then an electrical connection portion 112 connected to the first conductive portion 111 is formed. The electrical connection portion 112 is located on the side of the first insulating portion 12 facing away from the first temporary stage 30. The electrical connection portion 112 is exposed outside the first insulating portion 12 and is used for soldering to a solder portion 60, which enables interconnection with an integrated circuit or printed circuit board.

[0052] After step S11, in step S12, the first conductive part 111 and the first insulating part 12 are debonded to the first temporary stage 30. Then, the first add-layer assembly 1 is flipped over. In step S13, the electrical connection part 112 is temporarily bonded to the first temporary stage 30 using bonding adhesive 301, exposing at least a portion of the surface of the first conductive part 111. This facilitates subsequent processes in connecting the conductive post 2 to the first conductive part 111. The surface of the first conductive part 111 facing away from the electrical connection part 112 is flush with the first insulating part 12, facilitating subsequent processes in aligning and connecting the substrate 4 to the first add-layer assembly 1, ensuring the flatness of the substrate 4.

[0053] Optionally, the manufacturing processes of the first conductive electronic portion 111, the first insulating portion 12, and the electrical connection portion 112 can refer to the prior art and will not be described in detail here.

[0054] In some embodiments, such as Figure 9 As shown, in step S03: Step S031: Perform laser modification treatment on the target area on the pre-substrate 4. Modifying the target area ensures easier material removal in subsequent processes. In step S031, a laser beam scans the target area to modify its material. The laser scans the target area, penetrating along the thickness direction Z of the substrate 4. The laser energy interacts with the substrate 4 material, causing changes in the physical or chemical properties of the target area, thus modifying the material. Due to the high focus and adjustability of the laser, it ensures that only the target area is affected, without damaging non-target areas, thereby precisely modifying the target area on the substrate 4.

[0055] Step S032: Wet etching is performed on the modified material in the target area to form through holes 41.

[0056] Alternatively, in some other embodiments, in step S03: The pre-substrate 4 is patterned using laser melting, focused discharge machining, plasma etching, or electrochemical discharge machining to form through-holes 41. Users can choose the opening method of the pre-substrate 4 according to their specific needs.

[0057] In some embodiments, in step S04, a first gap 42 is formed between the side surface of the conductive post 2 surrounding its axial direction and the wall of the through hole 41. The method further includes step S040 before step S05: A first buffer portion 5 is filled into the first gap 42. The first buffer portion 5 is connected to the adhesive portion 3, and at least a portion of the surface of the conductive post 2 is exposed from the first buffer portion 5. (See reference...) Figure 10 .

[0058] In this embodiment, the diameter of the through-hole 41 is larger than the diameter of the conductive post 2, so that the conductive post 2 can be formed on the first layer assembly 1 first, and then the substrate 4 is fitted onto the conductive post 2, so that a first gap 42 is formed between the side surface of the conductive post 2 around its axial direction and the hole wall of the through-hole 41. In step S040, a first buffer portion 5 is filled into the first gap 42, and the first buffer portion 5 realizes the fixed connection between the conductive post 2 and the hole wall of the through-hole 41, reducing the risk of misalignment between the substrate 4 and the conductive post 2, and reducing the stress caused by the inconsistency of the coefficients of thermal expansion between the substrate 4 and the conductive post 2, thereby reducing the risk of cracking of the substrate 4. The first buffer portion 5 is connected to the adhesive portion 3, and after curing, it forms an integral buffer structure, which provides better buffer protection for the substrate 4, the conductive post 2 and the first layer assembly 1, and improves the process performance of the carrier structure.

[0059] Optionally, the buffer coefficient of the first buffer portion 5 is less than the buffer coefficient of the conductive post 2. By setting the buffer coefficient of the first buffer portion 5 to be less than the buffer coefficient of the conductive post 2, the first buffer portion 5 is ensured to have good buffering performance, guaranteeing the ability of the first buffer portion 5 to absorb the thermal stress of the conductive post 2, thereby reducing the stress on the substrate 4 at the through hole 41 and reducing the risk of cracking of the substrate 4 at the through hole 41.

[0060] Optionally, the material of the first buffer portion 5 includes the material of the adhesive portion 3, which includes at least one of epoxy resin, polyimide, or Ajinomoto thickening film.

[0061] Optionally, the material of the first buffer portion 5 and the material of the adhesive portion 3 may be the same or different.

[0062] In step S05: The adhesive portion 3 and the first buffer portion 5 are cured.

[0063] Optionally, the adhesive part 3 and the first buffer part 5 can be made of the same material. For example, both materials can include resin-based organic adhesives so that they can be cured simultaneously using the same process, thereby improving the preparation efficiency.

[0064] The adhesive portion 3 and the first buffer portion 5 are cured to ensure the adhesive material between them is fully cured, forming a stable connection structure. The specific method of curing can be selected according to the type of adhesive used. For example, when thermosetting adhesives are used for the adhesive portion 3 and the first buffer portion 5, they can be placed in an oven at a preset temperature (e.g., 60℃ to 120℃) for a certain time (e.g., 30 minutes to 2 hours), or rapid curing can be achieved through infrared heating. If photocurable adhesives are used for the adhesive portion 3 and the first buffer portion 5, they can be cured by irradiation with ultraviolet light of the appropriate wavelength. During the curing process, it is necessary to ensure that the adhesive portion 3 and the first buffer portion 5 are stable under pressure or have their positions fixed to avoid displacement that could affect the bonding quality. After curing, the first buffer portion 5 and the adhesive portion 3 are tightly bonded, effectively providing a buffering effect and thus extending the service life of the carrier plate structure.

[0065] Optionally, the materials of the adhesive portion 3 and the first buffer portion 5 may be different. For example, the material of the adhesive portion 3 may include a resin-based organic adhesive, while the material of the first buffer portion 5 may include polyimide. When the materials of the adhesive portion 3 and the first buffer portion 5 are different, they can be cured separately to ensure the curing effect.

[0066] In some embodiments, in step S040: A buffer material is applied to the surface of the substrate 4 facing away from the first layering component 1, and the buffer material is allowed to penetrate into the first gap 42.

[0067] After step S040, the buffer material located in the first gap 42 solidifies to form the first buffer part 5, and the buffer material located outside the first gap 42 solidifies to form the second pre-buffered part.

[0068] Following step S05, the method further includes step S06: The second pre-buffered portion is removed to expose the conductive post 2. That is, only the cured buffer material within the first gap 42 is retained to form the first buffer portion 5, and the second pre-buffered portion on the side of the substrate 4 facing away from the first add-on assembly 1 is not retained. This allows the second add-on assembly 40 to be directly fabricated on the surface of the substrate 4 facing away from the first add-on assembly 1, thereby facilitating a reduction in the overall thickness of the carrier plate structure. Optionally, the second pre-buffered portion can be removed by grinding, exposing at least a portion of the surface of the conductive post 2, facilitating contact and connection with the second conductive portion 401 of the subsequent second add-on assembly 40.

[0069] Alternatively, after step S05, the method may further include step S060: The second pre-buffered portion is patterned to form a first clearance hole 61 and a second buffer portion 6 surrounding the first clearance hole 61, with at least a portion of the surface of the conductive post 2 exposed through the first clearance hole 61.

[0070] For reference Figure 11 That is, the first buffer portion 5 within the first gap 42 and the second buffer portion 6 on the surface of the substrate 4 facing away from the first layering component 1 are retained. The adhesive portion 3, the first buffer portion 5 and the second buffer portion 6 together buffer and protect the substrate 4, further reducing the risk of the substrate 4 cracking.

[0071] After forming the second pre-buffered portion, the second pre-buffered portion is patterned to form the second buffered portion 6. The second buffered portion 6 includes a first clearance hole 61 through which the conductive post 2 is exposed, facilitating contact and connection with the second conductive portion 401 of the subsequent second layering assembly 40.

[0072] In some embodiments, such as Figure 12 As shown, in step S01: Step S011: A seed layer 7 is formed on the first layering component 1. The seed layer 7 includes a first seed portion 71 and a second seed portion 72 connected together. (See reference...) Figure 13 .

[0073] Step S012: A conductive post 2 is formed on the seed layer 7, and the orthographic projection of the conductive post 2 along the thickness direction Z covers the orthographic projection of the first seed part 71 along the thickness direction Z.

[0074] Step S013: Remove the second seed portion 72. The conductive post 2 is electrically connected to the first conductive portion 11 through the first seed portion 71. (See reference...) Figure 2 .

[0075] In this embodiment, a seed layer 7 is first formed on the first add-layer component 1 in step S011. The seed layer 7 provides an electrical path for the fabrication of the conductive pillar 2. Then, the conductive pillar 2 is formed on the seed layer 7 in step S012. Next, the second seed portion 72 is removed in step S013. The conductive pillar 2 is connected to the first conductive portion 11 through the first seed portion 71 to ensure the stability of the electrical connection between the conductive pillar 2 and the first conductive portion 11.

[0076] Optionally, the first seed portion 71 includes a metallic material, such as, but not limited to, at least one of copper (Cu), aluminum (Al), nickel (Ni), gold (Au), tin (Sn), silver (Ag).

[0077] In some embodiments, such as Figure 14 As shown, in step S02: Step S021: Clean the first layer addition component 1 and the conductive post 2.

[0078] Step S022: Dry the cleaned first layering component 1 and conductive post 2.

[0079] Step S023: Apply the adhesive portion 3 to the surface of the first layering assembly 1 on the side where the conductive post 2 is located. The dimension of the adhesive portion 3 along the thickness direction Z is equal to the dimension of the first seed portion 71 along the thickness direction Z. (See reference...) Figure 3 .

[0080] In this embodiment, step S021 is first performed to clean the first layering component 1 and the conductive post 2 to remove any oil, oxides, or other impurities that may be attached to their surfaces, ensuring a clean bonding interface. This cleaning can be achieved using methods such as plasma cleaning, ultrasonic cleaning with organic solvents, or acid / alkaline solution cleaning. After cleaning, step S022 is performed to dry the cleaned first layering component 1 and the conductive post 2, for example, by blowing them dry in a nitrogen gas stream or by low-temperature drying in an oven, to completely remove any cleaning solution residue and avoid adverse effects on bonding performance. Then, step S023 is performed to coat the bonding portion 3 onto the first layering component 1. On the surface of the layering component 1 with the conductive post 2, the coating process needs to be precisely controlled during the coating process to ensure that the dimension of the adhesive part 3 along the thickness direction Z is equal to the dimension of the first seed part 71 along the thickness direction Z. This can be achieved by screen printing, scraping, or spraying, combined with high-precision online monitoring of the coating thickness, to ensure that the surface of the adhesive part 3 and the surface of the first seed part 71 remain coplanar in the final structure. This provides a flat reference surface for subsequent processes, ensuring that the substrate 4 can be flatly connected to the first layering component 1, ensuring uniform stress on the substrate 4, improving the phenomenon of warping and peeling of the substrate 4 from the first layering component 1, and reducing the risk of cracking of the substrate 4.

[0081] In some embodiments, such as Figure 15 As shown, in step S012: Step S0121: Cover the seed layer 7 with photoresist 8 on the side opposite to the first layering component 1.

[0082] Step S0122: Pattern the photoresist 8 to form a photoresist opening 81 and a photoresist residue 82 surrounding the photoresist opening 81, wherein the photoresist opening 81 exposes at least a portion of the seed layer 7. (See reference...) Figure 16 .

[0083] Step S0123: Electroplating a conductive material onto the exposed seed layer 7 through the photoresist opening 81 to form the conductive pillar 2. (See reference...) Figure 17 .

[0084] Step S0124: Remove photoresist residue 82.

[0085] In this embodiment, step S0121 is performed first, where photoresist 8 is covered on the side of the seed layer 7 away from the first layer-adding component 1. The photoresist 8 can be uniformly coated by spin coating, spraying or lamination, and then pre-baked to form a photoresist 8 with a uniform thickness.

[0086] After coating is completed, proceed to step S0122 to pattern the photoresist 8, for example, by standard photolithography processes such as ultraviolet light exposure and development, to form a photoresist opening 81 and a photoresist residue 82 surrounding the photoresist opening 81. The photoresist opening 81 precisely exposes at least part of the seed layer 7 as a growth window for subsequent electroplating, while the surrounding photoresist residue 82 serves as a barrier layer to define the lateral growth area of ​​the conductive pillar 2.

[0087] Then, in step S0123, conductive material is electroplated on the exposed seed layer 7 through the photoresist opening 81. By controlling parameters such as electroplating time, current density, and electroplating solution composition, the conductive material is directionally grown on the seed layer 7 until it fills the photoresist opening 81 or reaches a preset thickness, thereby forming a conductive pillar 2 with a predetermined height and diameter.

[0088] Finally, step S0124 is executed to remove the photoresist residue 82. For example, by immersion in chemical stripping solution, plasma ashing, or high-temperature decomposition, the photoresist 8 surrounding the conductive pillar 2 is completely removed, exposing the electroplated conductive pillar 2 structure. This completes the selective fabrication of the conductive pillar 2 on the seed layer 7, providing a basis for electrical interconnection with the first layer-addition component 1.

[0089] In other embodiments, such as Figure 18 As shown, in step S01: Step S100: Cover the first layering component 1 with photoresist 8.

[0090] Step S101: Pattern the photoresist 8 to form a photoresist opening 81 and a photoresist residue 82 surrounding the photoresist opening 81, wherein the photoresist opening 81 exposes at least a portion of the first conductive portion 11. (See reference...) Figure 19 .

[0091] Step S102: Conductive material is electroplated onto the exposed first conductive portion 11 through the photoresist opening 81 to form the conductive pillar 2. (See reference...) Figure 20 .

[0092] Step S103: Remove photoresist residue 82. (See reference...) Figure 21 .

[0093] In this embodiment, step S100 is performed first, where photoresist 8 is covered on the first layering component 1. The photoresist 8 can be uniformly coated on the surface of the first layering component 1 by spin coating, spraying or dry film lamination, and then pre-baking is performed to form a photoresist 8 with uniform thickness and good adhesion.

[0094] After coating is completed, step S101 is performed to pattern the photoresist 8, for example by standard photolithography processes such as ultraviolet light exposure and development, to form a photoresist opening 81 and a photoresist residue 82 surrounding the photoresist opening 81. The photoresist opening 81 precisely exposes at least a portion of the first conductive portion 11 as a growth window for subsequent electroplating, while the surrounding photoresist residue 82 serves as a barrier layer to define the lateral growth area of ​​the conductive pillar 2.

[0095] Then, in step S102, conductive material is electroplated on the exposed first conductive part 11 through the photoresist opening 81. By controlling parameters such as electroplating time, current density and electroplating solution composition, the conductive material is directionally grown on the first conductive part 11 until it fills the photoresist opening 81 or reaches a preset thickness, thereby forming a conductive pillar 2 with a predetermined height and diameter.

[0096] Finally, step S103 is executed to remove the photoresist residue 82, for example by immersion in chemical stripping solution, plasma ashing, or high-temperature decomposition, to completely remove the photoresist 8 surrounding the conductive pillar 2, exposing the conductive pillar 2. This completes the electrical connection and physical shaping between the conductive pillar 2 and the first conductive part 11, providing a vertical interconnection path for subsequent layer addition processes.

[0097] Compared to the method of forming the first seed portion 71 on the first layering component 1, this embodiment directly uses the already prepared first conductive portion 11 as the seed material when electroplating conductive material, so as to simplify the process.

[0098] In some embodiments, such as Figure 22 As shown, at least a portion of the adhesive portion 3 is in contact with the sidewall of the conductive post 2 surrounding its axial direction, and the end face of the conductive post 2 away from the first layering component 1 is recessed within the through hole 41. In step S040: A buffer material is applied to the surface of the substrate 4 away from the first layering component 1, and the buffer material is allowed to penetrate the through hole 41. The buffer material covers the end face of the conductive post 2 away from the first layering component 1.

[0099] In step S05: The buffer material located within the first gap 42 is cured to form the first buffer section 5. The buffer material located on the side of the conductive post 2 opposite to the first layering assembly 1 and within the through hole 41 is cured to form the first pre-material section 10. The buffer material located outside the through hole 41 is cured to form the second pre-material section 20. (See reference...) Figure 23 .

[0100] Following step S05, the method further includes step S051: The second preparatory material section 20 and the first preparatory material section 10 are patterned to form a second buffer section 6. The second buffer section 6 has a first clearance hole 61 that is provided through it, and at least a portion of the surface of the conductive post 2 is exposed through the first clearance hole 61.

[0101] For reference Figure 24 The first clearance hole 61 exposes at least a portion of the surface of the conductive post 2, so that the conductive post 2 can contact and connect with the second conductive part 401 of the subsequent second layer assembly 40. The adhesive part 3, the first buffer part 5 and the second buffer part 6 together provide buffer protection for the substrate 4, further reducing the risk of cracking of the substrate 4. The second buffer part 6 is at least partially located at the opening of the through hole 41, which helps to reduce the amount of metal at the opening, thereby reducing the thermal stress of the conductive post 2 at the opening. In addition, the second buffer part 6 can absorb the thermal stress generated by the conductive post 2 during operation, playing a buffering role for the substrate 4, thereby reducing the risk of cracking of the substrate 4 at the opening.

[0102] Alternatively, after step S05, such as Figure 25 As shown, the method further includes step S052: Step S0521: Remove the second preparatory material section 20.

[0103] Step S0522: The first preparatory material portion 10 is patterned to form a second buffer portion 6. The second buffer portion 6 has a through-hole 61 through which at least a portion of the surface of the conductive post 2 is exposed. (For reference...) Figure 26 .

[0104] In this embodiment, the adhesive part 3, the first buffer part 5, and the second buffer part 6 jointly buffer and protect the substrate 4, further reducing the risk of cracking of the substrate 4. The second buffer part 6 is at least partially located at the opening of the through hole 41, which helps to reduce the amount of metal at the opening, thereby reducing the thermal stress of the conductive post 2 at the opening. The second buffer part 6 can absorb the thermal stress generated by the conductive post 2 during operation, playing a buffering role on the substrate 4, thereby reducing the risk of cracking of the substrate 4 at the opening, and helping to achieve a reduction in the thickness of the carrier plate structure.

[0105] Optionally, the carrier structure of this application embodiment may only provide the first layer addition component 1, or the second layer addition component 40 may be provided on the other side of the substrate 4 along the thickness direction Z.

[0106] In some embodiments, after step S05, the method further includes step S07: A second layering component 40 is prepared on the side of the substrate 4 away from the first layering component 1. The second layering component 40 includes a second conductive part 401, which is in contact with the conductive post 2.

[0107] One or more insulating dielectric layers can be formed directly on the side of the substrate 4 away from the first add-on component 1 by lamination, coating or deposition. The required openings or trenches are formed in the dielectric layer by laser drilling, photolithography or plasma etching. On this basis, conductive materials are deposited in the openings or trenches and on the surface of the dielectric layer by sputtering, chemical plating or electroplating to construct the second conductive part 401 included in the second add-on component 40. During the preparation process, the process alignment accuracy needs to be precisely controlled to ensure that the second conductive part 401 can extend into the interior of the substrate 4 or pass through the dielectric layer, so as to achieve reliable physical contact and electrical connection with the exposed part of the pre-formed conductive post 2. This realizes the vertical interconnection of the first conductive part 11 and the second conductive part 401 on both sides of the substrate 4 through the conductive post 2, providing a basis for three-dimensional packaging or double-sided wiring structure.

[0108] Alternatively, in other embodiments, after step S05, such as Figure 27 As shown, the method further includes step S07: Step S071: Prepare the second layering component 40 on the second temporary stage.

[0109] Step S072: Remove the second temporary stage and bond the second add-on assembly 40 to the surface of the substrate 4 opposite to the first add-on assembly 1. The second add-on assembly 40 includes a second conductive portion 401, which is in contact with the conductive post 2. (See reference...) Figure 28 .

[0110] After the fabrication of the second add-on component 40 is completed, the second temporary stage is removed, for example, by mechanical peeling, laser ablation or chemical dissolution, to separate the second temporary stage from the second add-on component 40, exposing the bottom surface of the second add-on component 40. Subsequently, the second add-on component 40 after removing the stage is bonded to the surface of the substrate 4 away from the first add-on component 1. During the bonding process, the alignment accuracy needs to be precisely controlled to ensure that the second conductive part 401 in the second add-on component 40 and the exposed part of the pre-formed conductive post 2 are precisely aligned and reliably physically contacted and electrically connected. The bonding can be achieved by means of insulating film, liquid adhesive or direct lamination, so as to realize the integration of the second add-on component 40 on the substrate 4.

[0111] In this embodiment, the second add-on component 40 is not directly formed on the substrate 4, which helps to reduce the risk of substrate 4 cracking and improve the preparation yield.

[0112] After completing the second layering component 40, the first layering component 1 is debonded to the first temporary stage 30.

[0113] In some embodiments, such as Figure 29 As shown, after step S07, the method further includes: Step S08: A solder resist layer 50 is prepared on the electrical connection portion 112. The solder resist layer 50 has a first opening 501 to expose at least a portion of the surface of the electrical connection portion 112. (See reference...) Figure 30 The solder resist layer 50 can be made of inorganic materials, such as silicon dioxide, silicon nitride, or polycrystalline silicon, or it can be polyimide or solder resist ink. The solder resist layer 50 isolates water and oxygen from the external environment, preventing them from entering the build-up assembly. At least a portion of the surface of the electrical connection portion 112 facing away from the substrate 4 is exposed through the first opening 501. This step ensures that at least a portion of the electrical connection portion 112 can be electrically connected to the integrated circuit or printed circuit board, ensuring electrical interconnection between the integrated circuit and the printed circuit board.

[0114] Step S09: Solder part 60 is soldered to the surface of electrical connection part 112 exposed from the first opening 501. At least a portion of solder part 60 protrudes from the solder mask layer 50, so that solder part 60 can be better aligned and interconnected with integrated circuit or printed circuit board. (See reference...) Figure 31 .

[0115] Optionally, after the solder section 60 on one side of the substrate 4 is prepared, the solder section 60 on the other side of the substrate 4 is then prepared. After all solder sections 60 are prepared, an integrated circuit is soldered to the solder section 60 on one side of the substrate 4, and a printed circuit board (not shown in the figure) is soldered to the solder section 60 on the other side of the substrate 4.

[0116] Optionally, after soldering the integrated circuit, insulating material can be filled into the gap between the integrated circuit and the solder resist layer 50 on one side of the substrate 4 to form a first filling portion (not shown in the figure), and insulating material can be filled into the gap between the printed circuit board and the solder resist layer 50 on the other side of the substrate 4 to form a second filling portion (not shown in the figure), thereby providing encapsulation protection for the carrier board structure.

[0117] like Figure 31 As shown, a second aspect embodiment of this application also provides a carrier plate structure, which is obtained based on any of the embodiments of the first aspect of this application. The carrier plate structure includes: a first layering component 1, including a first conductive portion 11; a conductive post 2, the conductive post 2 and the first conductive portion 11 being electrically connected; a substrate 4, having a through hole 41 disposed through it in the thickness direction Z, the conductive post 2 being located in the through hole 41; an adhesive portion 3, located between the first layering component 1 and the substrate 4, for fixing the substrate 4 to the first layering component 1; a first gap 42 is formed between the side surface of the conductive post 2 surrounding its axial direction and the hole wall of the through hole 41; the carrier plate structure includes a first buffer portion 5, at least a portion of the first buffer portion 5 being located in the first gap 42, the adhesive portion 3 and the first buffer portion 5 being connected.

[0118] In the second aspect embodiment of this application, the adhesive portion 3 provides buffer protection for the substrate 4, buffering the stress between the substrate 4 and the first add-on component 1, thereby reducing the risk of cracking of the substrate 4 during use, improving the process performance of the carrier board structure, and ensuring the electrical interconnection effect between the integrated circuit and the printed circuit board. The first gap 42 is filled with the first buffer portion 5, which realizes the fixed connection between the conductive post 2 and the hole wall of the through hole 41, reducing the risk of misalignment between the substrate 4 and the conductive post 2, and reducing the stress caused by the inconsistency of the coefficients of thermal expansion between the substrate 4 and the conductive post 2, thereby reducing the risk of cracking of the substrate 4. The first buffer portion 5 is connected to the adhesive portion 3, and after curing, forms an integral buffer structure, which provides better buffer protection for the substrate 4, the conductive post 2 and the first add-on component 1, and improves the process performance of the carrier board structure.

[0119] Since the carrier plate structure of the second aspect embodiment of this application includes the carrier plate structure prepared by the preparation method of the carrier plate structure of any of the first aspects embodiment of this application, the carrier plate structure of the second aspect embodiment of this application has the beneficial effects of the carrier plate structure prepared by the preparation method of the carrier plate structure of any of the first aspects embodiment, which will not be repeated here.

[0120] In some embodiments, such as Figure 31As shown, the carrier board structure further includes: a first seed portion 71, which connects the first conductive portion 11 and the conductive post 2 respectively. An adhesive portion 3 is disposed between adjacent first seed portions 71, and the dimension of the adhesive portion 3 along the thickness direction Z is equal to the dimension of the first seed portion 71 along the thickness direction Z. The first seed portion 71 is used to ensure an effective electrical connection between the first conductive portion 11 and the conductive post 2. The surface of the adhesive portion 3 facing away from the first add-layer assembly 1 is coplanar with the surface of the first seed portion 71 facing away from the first add-layer assembly 1, thereby providing a flat reference surface for subsequent processes. This ensures that the substrate 4 can be flatly connected to the first add-layer assembly 1, ensures uniform stress on the substrate 4, improves the phenomenon of warping and peeling from the first add-layer assembly 1, and reduces the risk of cracking of the substrate 4.

[0121] The projection of the adhesive portion 3 along the thickness direction Z overlaps at least partially with the projection of the through hole 41 along the thickness direction Z. The adhesive portion 3 is in contact with the first seed portion 71. The first buffer portion 5 is located in the first gap 42 to form a continuous buffer structure between the first seed portion 71, the conductive post 2 and the substrate 4, providing a continuous buffer path for the first seed portion 71, the conductive post 2 and the substrate 4.

[0122] Or, such as Figure 32 As shown, the projection of the adhesive portion 3 along the thickness direction Z and the projection of the through hole 41 along the thickness direction Z are spaced apart. The first buffer portion 5 extends from the first gap 42 to the space between the substrate 4 and the first layering component 1 and is connected to the adhesive portion 3 to ensure that there is sufficient connection area between the first buffer portion 5 and the adhesive portion 3, reducing the risk of peeling or breakage between the first buffer portion 5 and the adhesive portion 3, and further ensuring that a continuous buffer structure is formed between the first seed portion 71, the conductive post 2 and the substrate 4, providing a continuous buffer path for the first seed portion 71, the conductive post 2 and the substrate 4.

[0123] In some embodiments, such as Figure 33 As shown, the adhesive part 3 has a through-hole 31, a part of the conductive post 2 is located in the through hole 41, and another part is located in the connecting hole 31 and is in contact with the first conductive part 11. The surface of the conductive post 2 on the side away from the first layering component 1 is recessed in the through hole 41.

[0124] In this embodiment, at least a portion of the conductive post 2 is located in the connection hole 31, that is, the adhesive portion 3 surrounds the end of the conductive post 2 facing the first layering component 1, which is beneficial to provide buffer protection for the conductive post 2 through the adhesive portion 3 and reduce the thermal stress of the conductive post 2 at the end.

[0125] In some embodiments, the carrier plate structure further includes a second buffer portion 6 having a first clearance hole 61, through which at least a portion of the surface of the conductive post 2 is exposed.

[0126] like Figure 11 As shown, with the first seed portion provided, the surface of the conductive post 2 facing away from the first add-layer assembly 1 is flush with the surface of the substrate 4 facing away from the first add-layer assembly 1. The first clearance hole 61 exposes at least a portion of the surface of the conductive post 2 to ensure electrical connection between the conductive post 2 and the second conductive portion 401 of the second add-layer assembly 40. The second buffer portion 6 is located on the side of the substrate 4 facing away from the first add-layer assembly. The adhesive portion 3, the first buffer portion 5, and the second buffer portion 6 together buffer and protect the substrate 4, further reducing the risk of cracking of the substrate 4.

[0127] In other embodiments, without providing a first seed section, such as Figure 33 As shown, the second buffer part 6 is located inside the through hole 41 and contacts the end face of the conductive post 2 away from the first layering component 1, so as to reduce the overall thickness of the carrier plate structure and reduce the stress at the opening of the through hole 41.

[0128] In this embodiment, the first clearance hole 61 exposes at least a portion of the surface of the conductive post 2, so that the conductive post 2 can contact and connect with the second conductive portion 401 of the subsequent second layering assembly 40. The adhesive portion 3, the first buffer portion 5, and the second buffer portion 6 jointly provide buffer protection for the substrate 4, further reducing the risk of cracking of the substrate 4.

[0129] In other embodiments, such as Figure 34 As shown, the second buffer portion 6 is located on the surface of the substrate 4 away from the first layering component 1, so as to buffer the stress between the second layering component 40 and the substrate 4.

[0130] Alternatively, in other embodiments, such as Figure 35 As shown, the second buffer portion 6 is located on the surface of the substrate 4 away from the first layering component 1 and surrounds at least part of the hole wall of the through hole 41. This helps to reduce the amount of metal at the hole opening, thereby reducing the thermal stress of the conductive post 2 at the hole opening. The second buffer portion 6 can absorb the thermal stress generated by the conductive post 2 during operation and play a buffering role on the substrate 4, thereby reducing the risk of cracks in the substrate 4 at the hole opening.

[0131] A third aspect of this application also provides a semiconductor packaging structure, including a carrier structure prepared by the method described in any of the embodiments of the first aspect, or including a carrier structure described in any of the embodiments of the second aspect.

[0132] A third aspect of this application also provides a semiconductor packaging structure, including a carrier structure prepared by the method described in any of the embodiments of the first aspect, or including a carrier structure described in any of the embodiments of the second aspect.

[0133] Since the semiconductor packaging structure of the third aspect of this application includes the carrier structure prepared by the carrier structure preparation method of any of the first aspects of this application, or includes the carrier structure of any of the second aspects of this application, the semiconductor packaging structure of the third aspect of this application has the beneficial effects of the carrier structure prepared by the carrier structure preparation method of any of the first aspects of this application, or has the beneficial effects of the carrier structure of any of the second aspects of this application, which will not be elaborated here.

[0134] Although this application has been described with reference to preferred embodiments, various modifications can be made thereto and components can be replaced with equivalents without departing from the scope of this application. In particular, the technical features mentioned in the various embodiments can be combined in any manner, provided there is no structural conflict. This application is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. A method for preparing a carrier plate structure, characterized in that, The method includes: A conductive post is prepared on one side of the first add-layer assembly along its thickness direction. The first add-layer assembly includes a first conductive portion, which is electrically connected to the conductive post. An adhesive portion is prepared on one side of the first add-layer component along its thickness direction, and the adhesive portion and the conductive post are located on the same side of the first add-layer component. Through-holes are formed on a pre-substrate to form a substrate; The substrate is fitted onto the conductive post and pressed onto the adhesive portion; The adhesive portion is then cured.

2. The method for preparing the carrier plate structure according to claim 1, characterized in that, In the step of fitting the substrate onto the conductive post and pressing it onto the adhesive portion, a first gap is formed between the side surface of the conductive post surrounding its axial direction and the wall of the through hole. Before curing the adhesive portion, the method further includes: filling the first gap with a first buffer portion, the first buffer portion being connected to the adhesive portion, and at least a portion of the surface of the conductive post being exposed from the first buffer portion; In the step of curing the adhesive portion: The adhesive portion and the first buffer portion are cured.

3. The method for preparing the carrier plate structure according to claim 2, characterized in that, In the step of filling the first buffer portion into the first gap: A buffer material is applied to the surface of the substrate opposite to the first layering component, and the buffer material is allowed to penetrate into the first gap. After the buffer material located within the first gap cures, it forms the first buffer portion; after the buffer material located outside the first gap cures, it forms the second pre-buffered portion. Following the step of curing the adhesive portion and the first buffer portion, the method further includes: Remove the second pre-buffered portion to expose the conductive post; Alternatively, after the step of curing the adhesive portion and the first buffer portion, the method further includes: The second pre-buffered portion is patterned to form a first clearance hole and a second buffer portion surrounding the first clearance hole, with at least a portion of the surface of the conductive post exposed through the first clearance hole.

4. The method for preparing the carrier plate structure according to claim 1, characterized in that, In the step of preparing a conductive pillar on one side of the first layered assembly along its thickness direction: A seed layer is formed on the first layering component, the seed layer including a first seed portion and a second seed portion connected together; The conductive pillar is formed on the seed layer, and the orthographic projection of the conductive pillar along the thickness direction covers the orthographic projection of the first seed portion along the thickness direction. Remove the second seed portion, and the conductive post is electrically connected to the first conductive portion through the first seed portion.

5. The method for preparing the carrier plate structure according to claim 4, characterized in that, In the step of forming the conductive pillars on the seed layer: Photoresist is applied to the side of the seed layer opposite to the first build-up assembly; The photoresist is patterned to form photoresist openings and photoresist residues surrounding the photoresist openings, the photoresist openings exposing at least a portion of the seed layer; Conductive material is electroplated on the exposed seed layer through the photoresist opening to form the conductive pillar; Remove the photoresist residue.

6. The method for preparing the carrier plate structure according to claim 2, characterized in that, In the step of preparing a conductive pillar on one side of the first layered assembly along its thickness direction: Photoresist is applied to the first layered component; The photoresist is patterned to form photoresist openings and photoresist residues surrounding the photoresist openings, the photoresist openings exposing at least a portion of the first conductive portion; Conductive material is electroplated on the exposed first conductive portion through the photoresist opening to form the conductive pillar; Remove the photoresist residue.

7. The method for preparing the carrier plate structure according to claim 6, characterized in that, At least a portion of the adhesive portion is in contact with the sidewall of the conductive post surrounding its axial direction, and the end face of the conductive post away from the first add-layer assembly is recessed within the through hole. In the step of filling the first buffer portion into the first gap: A buffer material is applied to the surface of the substrate opposite to the first layering component, and the buffer material is allowed to penetrate the through-hole, with the buffer material covering the end face of the conductive post away from the first layering component. In the step of curing the adhesive portion and the first buffer portion: The buffer material located within the first gap is cured to form the first buffer portion; the buffer material located on the side of the conductive post opposite to the first layering assembly and within the through hole is cured to form a first pre-material portion; and the buffer material located outside the through hole is cured to form a second pre-material portion. After the step of curing the adhesive portion and the first buffer portion, the method further includes: The second preparatory material portion and the first preparatory material portion are patterned to form a second buffer portion. The second buffer portion has a through-hole first clearance hole, and at least a portion of the surface of the conductive post is exposed through the first clearance hole. Alternatively, after the step of curing the adhesive portion and the first buffer portion, the method further includes: Remove the second preparatory material section; The first preparatory material is patterned to form a second buffer portion, the second buffer portion having a through-hole first clearance hole, at least a portion of the surface of the conductive post being exposed through the first clearance hole.

8. The method for preparing the carrier plate structure according to claim 1, characterized in that, Prior to the step of fabricating a conductive pillar on one side of the first layered assembly along its thickness direction, the method further includes: The first layered assembly is prepared on a first temporary stage. The first layered assembly includes a first insulating portion and a conductive portion including a first conductive sub-part and an electrical connection portion connected together. The first conductive sub-part is embedded in the first insulating portion, and the surface of the first conductive sub-part facing away from the electrical connection portion is flush with the first insulating portion. The electrical connection portion protrudes from the side of the first insulating portion facing away from the first temporary stage. Debond the first conductive part and the first insulating part to the first temporary stage; The electrical connection portion is temporarily bonded to the first temporary stage to expose at least a portion of the surface of the first conductive electronic portion.

9. A carrier plate structure obtained by the method for preparing the carrier plate structure according to any one of claims 1-8, characterized in that, The carrier plate structure includes: The first layering component includes a first conductive portion; A conductive post, which is electrically connected to the first conductive part; A substrate having a through hole extending through its thickness, wherein the conductive post is located in the through hole; An adhesive portion is located between the first layering component and the substrate, and is used to fix the substrate to the first layering component; The conductive post forms a first gap with the wall of the through hole by its axially surrounding side surface. The carrier plate structure includes a first buffer portion, at least a portion of which is located in the first gap, and the adhesive portion is connected to the first buffer portion.

10. The carrier plate structure according to claim 9, characterized in that, Also includes: The first seed section is connected to the first conductive section and the conductive post, respectively; The adhesive portion is disposed between adjacent first seed portions, and the dimension of the adhesive portion along the thickness direction is equal to the dimension of the first seed portion along the thickness direction; The projection of the adhesive portion along the thickness direction at least partially overlaps with the projection of the through hole along the thickness direction; the adhesive portion is in contact with the first seed portion; and the first buffer portion is located within the first gap. Alternatively, the projection of the adhesive portion along the thickness direction is spaced apart from the projection of the through hole along the thickness direction, and the first buffer portion extends from the first gap to the space between the substrate and the first layering component, and is connected to the adhesive portion.

11. The carrier plate structure according to claim 9, characterized in that, Also includes: A second buffer section has a first clearance hole, through which at least a portion of the surface of the conductive post is exposed. The second buffer portion is located on the surface of the substrate opposite to the first layering component and surrounds at least a portion of the hole wall of the through hole.

12. A semiconductor packaging structure, characterized in that, The carrier plate structure includes the carrier plate structure prepared by the method of any one of claims 1-8, or the carrier plate structure as described in any one of claims 9-11.

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