Semiconductor device

Abstract

Some embodiments of the present disclosure provide a semiconductor device including a contact electrically connected to a Group III-V semiconductor body layer. The metal layer stack of the contact comprises a plurality of metal layers and a metal nitride cap layer located at the topmost layer of the metal layer stack, the plurality of metal layers comprise a metal bottom layer located at the bottommost layer and having a metal element, and the metal nitride cap layer has a nitride of the metal element. And the thickness of the metal bottom layer is greater than that of the metal nitride cover layer, so that the contact element can relieve the stress of the main body layer and reduce the risk of material fracture in the semiconductor device.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices, and more particularly to III-V semiconductor devices. Background Technology

[0002] Gallium nitride (GaN) and its III-V group semiconductor materials possess characteristics such as wide bandgap, high breakdown voltage, high electron saturation velocity, and good thermal stability. Therefore, III-V semiconductor materials can be selected for semiconductor devices to meet the requirements of high power conversion, high-speed transmission, and low energy consumption. However, III-V semiconductor materials may cause high stress in semiconductor devices, making components in the device prone to defects such as material cracking. Summary of the Invention

[0003] According to some embodiments of this disclosure, a semiconductor device includes a contact electrically connected to a III-V semiconductor body layer. The metal layer stack of the contact includes a plurality of metal layers and a metal nitride capping layer at the top layer of the metal layer stack. The plurality of metal layers include a bottom metal substrate having a metal element, and the metal nitride capping layer has a nitride of the metal element. The thickness of the bottom metal substrate is greater than the thickness of the metal nitride capping layer.

[0004] In some implementations, the ratio between the thickness of the metal substrate and the thickness of the metal nitride capping layer is between 1:1 and 20:1.

[0005] In some embodiments, the semiconductor device further includes a first metal layer located between a metal substrate and a metal nitride capping layer, and a second metal layer located between the first metal layer and the metal nitride capping layer, wherein any adjacent metal substrate, first metal layer and second metal layer have different metal materials.

[0006] In some implementations, the metal substrate is a titanium layer, the first metal layer is an aluminum layer, and the second metal layer is a titanium layer.

[0007] In some embodiments, the second metal layer includes a plurality of second metal sublayers and at least one interlayer metal nitride layer, wherein the interlayer metal nitride layer separates the second metal sublayers.

[0008] In some embodiments, the total thickness of the second metal sublayer is between 5 nanometers and 100 nanometers, and the total thickness of the interlayer metal nitride layer is between 5 nanometers and 200 nanometers.

[0009] In some embodiments, the metal element of the interlayer metal nitride layer is selected from titanium, tantalum, tungsten, zinc, zirconium, strontium, tin, nickel, scandium, vanadium, chromium, manganese, molybdenum, niobium, rhenium, aluminum, gallium, indium, lithium, magnesium, tellurium, yttrium, hafnium, ruthenium, rhodium, osmium, iridium, and uranium. A group consisting of furnaces and cerium.

[0010] According to some embodiments of this disclosure, a semiconductor device includes a body layer, a gate structure located on the body layer, and a contact located on the body layer and adjacent to the gate structure. The body layer includes at least one layer of a III-V semiconductor material and has compressive stress. The contact has tensile stress and includes a plurality of stacked metal layers and a metal nitride capping layer above the plurality of metal layers, wherein the thickness of the bottommost metal layer is greater than the thickness of the metal nitride capping layer.

[0011] In some embodiments, the main body layer includes a gallium nitride layer and an aluminum gallium nitride layer, wherein the aluminum gallium nitride layer is located on the gallium nitride layer and directly contacts the gallium nitride layer, and the bottom layer of the contact directly contacts the aluminum gallium nitride layer.

[0012] In some implementations, the contacts are ohmic contacts of a semiconductor device.

[0013] According to the above embodiments, the semiconductor device of this disclosure includes a contact electrically connected to the body layer of a III-V semiconductor, wherein the contact includes a bottom metal substrate and a top metal nitride capping layer, and the thickness of the bottom metal substrate is greater than the thickness of the metal nitride capping layer. Therefore, the tensile stress of the contact can reduce the compressive stress of the body layer, thereby reducing the risk of material fracture in the semiconductor device. Attached Figure Description

[0014] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial methods, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0015] Figure 1 A cross-sectional view of a semiconductor device is shown according to one embodiment of the present disclosure.

[0016] Figures 2 to 4 A cross-sectional schematic diagram of the contact element is shown according to some embodiments of this disclosure. Detailed Implementation

[0017] To achieve the different features of the mentioned subject matter, the following disclosure provides many different implementations or examples. Specific examples of components, configurations, etc., are described below to simplify this disclosure. Of course, these are merely examples and not limiting. For example, in the following description, forming a first feature on or above a second feature can include implementations where the first and second features are formed in direct contact, and can also include implementations where an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. Additionally, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself imply a relationship between the various implementations and / or configurations discussed.

[0018] Furthermore, this document may use spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” etc., to facilitate the description of the relationship between one element or feature and another element or feature as shown in the figure. In addition to the orientations shown in the figure, spatial relative terms are intended to include different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other directions), and the spatial relative descriptive symbols used herein may be interpreted accordingly.

[0019] Embodiments of this disclosure provide a semiconductor device including contacts electrically connected to a III-V semiconductor body layer, wherein the layer stack of the contacts includes a bottom metal substrate and a top metal nitride capping layer, and the thickness of the metal substrate is greater than the thickness of the metal nitride capping layer. Therefore, the contacts can reduce the overall stress in the semiconductor device, thereby reducing the risk of material cracking and improving the manufacturing yield of the semiconductor device.

[0020] According to one embodiment of this disclosure Figure 1 A cross-sectional view of a semiconductor device 100 is shown. The semiconductor device 100 includes a substrate 110, a body layer 120 on the substrate 110, a gate structure 130 on the body layer 120, and a contact 200 on the body layer 120 and adjacent to the gate structure 130. Specifically, the substrate 110 may include elemental semiconductors, compound semiconductors, or substrate materials suitable for use as the semiconductor device 100, such as silicon, silicon carbide, silicon germanium, or the like. The substrate 110 may be formed of undoped or doped semiconductor materials, such as those doped with nitrogen, phosphorus, arsenic, or other n-type dopants, or doped with boron, gallium, or other p-type dopants.

[0021] The host layer 120 includes at least one layer of group III-V semiconductor material as a channel layer of the semiconductor device 100. The group III-V semiconductor material of the host layer 120 can be a compound semiconductor formed from at least one group III element and at least one group V element, such as, but not limited to, gallium nitride (GaN), gallium arsenide (GaAs), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), or the like. For example, the host layer 120 may include a gallium nitride layer 122 and an aluminum gallium nitride layer 124 located on the gallium nitride layer 122, wherein a two-dimensional electron gas (2DEG) can be formed at the interface where the gallium nitride layer 122 and the aluminum gallium nitride layer 124 directly contact each other, generating a high concentration of charge carriers, thus giving the semiconductor device 100 high electron mobility. Such a semiconductor device 100 can also be called a high electron mobility transistor (HEMT).

[0022] Gate structure 130 may include a doped group III-V semiconductor material to control current in the host layer 120 as an enhanced-mode gate. For example, gate structure 130 may include a p-type gallium nitride (p-GaN) layer 132 and a capping layer 134 on the p-type GaN layer 132, wherein the capping layer 134 may be formed of titanium nitride (TiN). In some embodiments, gate structure 130 may also include a gate dielectric layer (not specifically shown) between the p-type GaN layer 132 and the host layer 120, such as a silicon oxide layer, a metal oxide layer, or the like. In some embodiments, semiconductor device 100 may also include a protective layer 140 on the host layer 120 and gate structure 130, wherein the protective layer 140 covers the top surface of the host layer 120, the top surface of the gate structure 130, and the sidewalls to reduce the risk of wear and tear and corrosion from moisture or contaminants on the host layer 120 and gate structure 130.

[0023] Contact 200 is located on one side of gate structure 130 and electrically connected to body layer 120. When semiconductor device 100 includes protective layer 140, contact 200 can extend through protective layer 140 to contact top surface of body layer 120, for example... Figure 1 The aluminum gallium nitride layer 124 is present. The contact 200 can be a source / drain contact of the semiconductor device 100, but embodiments of this disclosure are not limited thereto. The contact 200 includes a suitable stack of metal layers such that the contact resistance between the contact 200 and the body layer 120 is sufficiently small, thus the contact 200 can serve as an ohmic contact of the semiconductor device 100.

[0024] To further illustrate the details of contact 200, Figure 2 A cross-sectional schematic diagram of the contact member 200a is shown according to one embodiment of the present disclosure. Figure 2 The material stack of contact 200a in the middle can be used for Figure 1 Contact element 200, in other words, Figure 2 The material stack shown can be a partial cross-sectional view of contact 200.

[0025] Contact 200a includes a bottom metal substrate 210, a first metal layer 220 on the metal substrate 210, a second metal layer 230 on the first metal layer 220, and a metal nitride capping layer 240 on the second metal layer 230. Materials from the metal substrate 210 to the metal nitride capping layer 240 can be sequentially deposited using techniques such as physical vapor deposition (PVD), chemical vapor deposition (CVD), sputtering, or other suitable techniques to form the metal layer stack of contact 200a.

[0026] Any two adjacent metal layers 210, 220, and 230 can be formed of different metal materials to reduce the contact resistance between the contact 200a and the III-V semiconductor material. For example, the metal layer 210 can be a titanium (Ti) layer, the first metal layer 220 can be an aluminum (Al) layer, and the second metal layer 230 can be a titanium layer. Figure 2 The contact 200a is illustrated as including two additional metal layers (a first metal layer 220 and a second metal layer 230) between the metal underlayer 210 and the metal nitride capping layer 240. However, in some other embodiments, fewer or more additional metal layers may be included between the metal underlayer 210 and the metal nitride capping layer 240, and these additional metal layers may include other metal-containing materials. For example, the first metal layer 220 may be a layer of aluminum doped with a non-metallic element, or the second metal layer 230 may be a layer of nickel (Ni).

[0027] The metal nitride capping layer 240, located at the top layer of the contact 200a, protects the remaining material layers of the contact 200a. The metal nitride capping layer 240 may include nitrides of metals such as titanium (Ti), zirconium (Zr), niobium (Nb), tantalum (Ta), molybdenum (Mo), and tungsten (W), or combinations thereof. For example, the metal nitride capping layer 240 may be a titanium nitride (TiN) layer. In such an embodiment, the metal bottom layer 210 and the metal nitride capping layer 240 may have the same metal element; that is, the metal bottom layer 210 is formed of the metal element, while the metal nitride capping layer 240 is formed of nitrides of the aforementioned metal element.

[0028] It is worth noting that, Figure 2 The thickness T1 of the metal substrate 210 in the Z direction is greater than the thickness T2 of the metal nitride capping layer 240 in the Z direction. In other words, when depositing the material of the contact 200a, the thickness T1 of the deposited metal substrate 210 is greater than the thickness T2 of the deposited metal nitride capping layer 240. The thickness difference between the metal substrate 210 and the metal nitride capping layer 240 can adjust the stress of the contact 200a, thereby reducing the risk of defect generation in the semiconductor device and improving the stability of the semiconductor device.

[0029] More specifically, this includes the host layer of group III-V semiconductor materials (e.g. Figure 1 The host layer 120 in the semiconductor device typically exhibits compressive stress. When the metal underlayer 210 of the contact 200a is thicker than the metal nitride capping layer 240, the contact 200a tends to exhibit tensile stress, which can alleviate the compressive stress of the host layer. In other words, the contact 200a can reduce the overall stress in the semiconductor device, thereby reducing the risk of material fracture of components in the semiconductor device and improving the manufacturing yield of the semiconductor device. In addition, a thicker metal underlayer 210 can also increase the adhesion between the contact 200a and the host layer, thus improving the structural stability of the semiconductor device. In some embodiments, the ratio (thickness T1:thickness T2) between the thickness T1 of the metal underlayer 210 and the thickness T2 of the metal nitride capping layer 240 can be between 1:1 and 20:1 to alleviate the overall stress in the semiconductor device. If the ratio of thickness T1 to thickness T2 is less than 1:1, the tensile stress of the contact 200a may be large and difficult to balance. If the ratio of thickness T1 to thickness T2 is greater than 20:1, there may be insufficient relief of stress in the semiconductor device, leading to cracking.

[0030] According to another embodiment of this disclosure, Figure 3 A cross-sectional schematic diagram of contact 200b is shown. Contact 200b is similar to... Figure 2The contact 200a is a metal layer, but the second metal layer 230 of the contact 200b includes a plurality of second metal sublayers and an interlayer metal nitride layer. Specifically, the contact 200b includes a metal underlayer 210 with a thickness T1, a metal nitride capping layer 240 with a thickness T2, and a first metal layer 220 and a second metal layer 230 located between the metal underlayer 210 and the metal nitride capping layer 240, wherein the thickness T1 is greater than the thickness T2. The second metal layer 230 includes a second metal sublayer 230a, a second metal sublayer 230b, and an interlayer metal nitride layer 250 located between the second metal sublayers 230a and 230b. In other words, the interlayer metal nitride layer 250 intervenes between the second metal sublayers 230a and 230b to separate the two second metal sublayers.

[0031] According to another embodiment of this disclosure, Figure 4 A cross-sectional schematic diagram of contact 200c is shown. Contact 200c is similar to contact 200b, but contact 200c has multiple second metal sublayers and multiple interlayer metal nitride layers. Specifically, contact 200c includes a metal underlayer 210 with thickness T1, a metal nitride capping layer 240 with thickness T2, and a first metal layer 220 and a second metal layer 230 located between the metal underlayer 210 and the metal nitride capping layer 240, wherein thickness T1 is greater than thickness T2. The second metal layer 230 includes a second metal sublayer 230a, a second metal sublayer 230b, a second metal sublayer 230c, an interlayer metal nitride layer 250a located between the second metal sublayers 230a and 230b, and an interlayer metal nitride layer 250b located between the second metal sublayers 230b and 230c. In other words, the interlayer metal nitride layer 250a and the interlayer metal nitride layer 250b are respectively inserted between the second metal sublayer 230a and the second metal sublayer 230b and the second metal sublayer 230c to separate the three second metal sublayers.

[0032] exist Figure 3 and Figure 4 In this configuration, the second metal layer 230 has multiple second metal sublayers and at least one interlayer metal nitride layer, wherein the second metal sublayers and the interlayer metal nitride layer are alternately stacked to form a composite layer, thereby allowing the contacts 200b and 200c to be further adjusted to the desired stress. In some embodiments, the second metal sublayers of the second metal layer 230 may have the same material, for example... Figure 3The second metal sublayer 230a and the second metal sublayer 230b can both be titanium layers. The interlayer metal nitride layer 250 of the second metal layer 230 can be a metal nitride layer with a single metal element or an alloy nitride layer with multiple metal elements, wherein the one or more metal elements can be selected from titanium (Ti), tantalum (Ta), tungsten (W), zinc (Zn), zirconium (Zr), strontium (Sr), tin (Sn), nickel (Ni), scandium (Sc), vanadium (V), chromium (Cr), manganese (Mn), molybdenum (Mo), niobium (Nb), rhenium (Re), aluminum (Al), gallium (Ga), indium (In), lithium (Li), magnesium (Mg), tellurium (Te), yttrium (Y), hafnium (Hf), ruthenium (Ru), rhodium (Rh), osmium (Os), iridium (Ir), and tris(II)monium (Tc). (Db) (Sg) The group consisting of (Bh), furnace (Rf), and cerium (Ce).

[0033] In some embodiments, the total thickness of the second metal sublayer of the second metal layer 230 can be between 5 nanometers and 100 nanometers, and the total thickness of the interlayer metal nitride layer can be between 5 nanometers and 200 nanometers, so that the second metal layer 230 and the adjacent first metal layer 220 can adjust the brittleness and mechanical strength of the contact element in accordance with the material layer other than the contact element.

[0034] like Figure 3 As shown, the second metal sublayer 230a has a thickness T3 in the Z direction, the interlayer metal nitride layer 250 has a thickness T4 in the Z direction, and the second metal sublayer 230b has a thickness T5 in the Z direction. When the sum of thickness T3 and thickness T5 is between 5 nm and 100 nm, and thickness T4 is between 5 nm and 200 nm, the brittleness and mechanical strength of the second metal layer 230 can be improved. Similarly, as Figure 4 As shown, the second metal sublayer 230a, the interlayer metal nitride layer 250a, the second metal sublayer 230b, the interlayer metal nitride layer 250b, and the second metal sublayer 230c have thicknesses T6, T7, T8, T9, and T10 respectively in the Z direction, wherein the sum of thicknesses T6, T8, and T10 is between 5 nanometers and 100 nanometers, and the sum of thicknesses T7 and T9 is between 5 nanometers and 200 nanometers.

[0035] According to the above embodiments, the semiconductor device of this disclosure includes a contact electrically connected to a III-V semiconductor body layer, wherein the contact comprises a stack of multiple metal layers serving as an ohmic contact of the semiconductor device. The metal layer stack of the contact includes a bottom metal sublayer and a top metal nitride capping layer, and the thickness of the metal sublayer is greater than the thickness of the metal nitride capping layer. Therefore, the tensile stress of the contact can reduce the compressive stress of the body layer, thereby reducing the risk of material fracture and increasing the adhesion between components. The metal layer stack may also include a composite layer formed by metal sublayers and interlayer metal nitride layers, thereby further adjusting the stress, brittleness, and mechanical strength of the contact according to other material layers.

[0036] The foregoing outlines some features of the embodiments to enable those skilled in the art to better understand the ideas presented in this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

[0037] [Symbol Explanation]

[0038] 100: Semiconductor devices

[0039] 110:Substrate

[0040] 120: Main Layer

[0041] 122: Gallium nitride layer

[0042] 124: AlGaN layer

[0043] 130: Gate structure

[0044] 132: p-type gallium nitride layer

[0045] 134: Cap layer

[0046] 140: Protective layer

[0047] 200, 200a, 200b, 200c: Contact elements

[0048] 210: Metal base layer

[0049] 220: First metal layer

[0050] 230: Second metal layer

[0051] 230a, 230b, 230c: Second metal sublayer

[0052] 240: Metal nitride capping layer

[0053] 250, 250a, 250b: Interlayer metal nitride layers

[0054] T1, T2, T3, T4, T5, T6, T7, T8, T9, T10: Thickness

[0055] X, Y, Z: Direction.

Claims

1. A semiconductor device, characterized in that, The contact includes a contact electrically connected to the body layer of a III-V semiconductor, wherein the metal layer stack of the contact includes: Multiple metal layers, including a bottom metal substrate, wherein the bottom metal substrate has a metallic element; and A metal nitride capping layer is located on the top layer of the metal layer stack, wherein the metal nitride capping layer has a nitride of the metal element, and the thickness of the metal bottom layer is greater than the thickness of the metal nitride capping layer.

2. The semiconductor device of claim 1, wherein the ratio between the thickness of the metal substrate and the thickness of the metal nitride capping layer is between 1:1 and 20:

1.

3. The semiconductor device according to claim 1, wherein, Further includes: A first metal layer is located between the metal underlayer and the metal nitride capping layer; and The second metal layer is located between the first metal layer and the metal nitride capping layer. The metal substrate, the first metal layer, and the second metal layer are any two adjacent metal materials.

4. The semiconductor device according to claim 3, wherein the metal substrate is a titanium layer, the first metal layer is an aluminum layer, and the second metal layer is a titanium layer.

5. The semiconductor device of claim 3, wherein the second metal layer comprises a plurality of second metal sublayers and at least one interlayer metal nitride layer, and the at least one interlayer metal nitride layer separates the plurality of second metal sublayers.

6. The semiconductor device of claim 5, wherein the total thickness of the plurality of second metal sublayers is between 5 nanometers and 100 nanometers, and the total thickness of the at least one interlayer metal nitride layer is between 5 nanometers and 200 nanometers.

7. The semiconductor device of claim 5, wherein the metal element of the at least one interlayer metal nitride layer is selected from titanium, tantalum, tungsten, zinc, zirconium, strontium, tin, nickel, scandium, vanadium, chromium, manganese, molybdenum, niobium, rhenium, aluminum, gallium, indium, lithium, magnesium, tellurium, yttrium, hafnium, ruthenium, rhodium, osmium, iridium, uranium, and uranium. A group consisting of furnaces and cerium.

8. A semiconductor device, characterized in that, include: The host layer includes at least one layer of group III-V semiconductor material, wherein the host layer is under compressive stress; A gate structure is located on the main body layer; and A contact element, located on the body layer and adjacent to the gate structure, wherein the contact element has tensile stress, the contact element comprising a plurality of stacked metal layers and a metal nitride capping layer above the plurality of metal layers, wherein the thickness of the bottommost of the plurality of metal layers is greater than the thickness of the metal nitride capping layer.

9. The semiconductor device of claim 8, wherein the body layer comprises: Gallium nitride layer; and An aluminum gallium nitride layer is located on the gallium nitride layer and in direct contact with the gallium nitride layer, wherein the bottommost layer of the plurality of metal layers is in direct contact with the aluminum gallium nitride layer.

10. The semiconductor device of claim 8, wherein the contact is an ohmic contact of the semiconductor device.

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