Chip verification test point intelligent decomposition method and electronic equipment

Abstract

This invention discloses an intelligent decomposition method and electronic device for chip verification test points. The method includes: obtaining a chip requirement document provided by a user; using natural language processing technology to perform word segmentation and entity recognition on the chip requirement document to construct input vector features; obtaining a trained large model; inputting training data containing historical test point decomposition results into the large model; and optimizing and adjusting the parameters of the large model; and inputting the input vector features into the parameter-optimized large model to generate a test point list. Compared with existing technologies, this invention can decompose test points that conform to verification specifications from a user-provided chip requirement document based on a large model, and the test point decomposition efficiency is high, which can shorten the chip verification cycle.

Description

Technical Field

[0001] This invention relates to the field of chip verification technology, and in particular to a method and device for intelligent decomposition of chip verification test points. Background Technology

[0002] With the rapid development of the integrated circuit field, the integration and scale of chips are constantly increasing, posing new challenges to design and chip verification. In the traditional chip verification field, there is currently no mature, fully automated solution for test point decomposition. Industry practice still relies heavily on manual decomposition, which depends heavily on the experience and professional level of verification engineers. On the one hand, this makes test point decomposition prone to omissions, requiring multiple rounds of review and process standardization to ensure completeness. On the other hand, complex SoC projects have a large number of test points, and purely manual decomposition is time-consuming and inefficient, leading to a prolonged chip verification cycle.

[0003] Therefore, there is an urgent need for an AI agent based on large model fine-tuning training that can solve the above problems, and an intelligent decomposition method for chip verification test points using this AI agent. Summary of the Invention

[0004] The purpose of this invention is to provide a method and electronic device for intelligent decomposition of chip verification test points. It can decompose test points that conform to verification specifications from the chip requirement document provided by the user based on a large model. Moreover, the test point decomposition efficiency is high and the chip verification cycle can be shortened.

[0005] To achieve the above objectives, the present invention provides an intelligent decomposition method for chip verification test points, comprising: obtaining a chip requirement document provided by a user; using natural language processing technology to perform word segmentation and entity recognition on the chip requirement document to construct input vector features; obtaining a trained large model; inputting training data containing historical test point decomposition results into the large model; optimizing and adjusting the parameters of the large model; and inputting the input vector features into the parameter-optimized large model to generate a test point list.

[0006] Preferably, the training data also includes chip architecture documentation and industry standards.

[0007] Preferably, after generating the test point list, the process further includes: validating the generated test point list using a prior knowledge base; if the validation fails, filling in the missing information and performing a coverage validation; if the validation succeeds, directly performing a coverage validation. The coverage validation includes: using a rule engine to detect whether the generated test point list covers all functional modules of the chip requirement document; if so, converting the test point list into a validation tool of the corresponding format for output; otherwise, returning to step: inputting the input vector features into the parameter-optimized large model to generate the test point list.

[0008] Specifically, the prior knowledge base includes industry test case templates.

[0009] Specifically, converting the test point list into the corresponding format of the verification tool output includes: organizing the test points according to priority and module, and then converting the test points marked with priority information into the corresponding format of the verification tool output according to module. In this embodiment, the output is in a format that the verification tool can directly use, such as CSV or JSON.

[0010] Preferably, the large model is a Transformer model to ensure the semantic understanding capability of the AI ​​agent. Of course, the Transformer model can also be replaced by a CNN model or an RNN model.

[0011] Preferably, the test point list is categorized into functional tests, performance tests, boundary tests, and error tests, covering various functional states and possible scenarios of chip operation.

[0012] Specifically, the functional test test point list is a list of verification test points for each functional module of the chip, the performance test test point list is a list of standard performance test points for the chip, the boundary test test point list is a list of test points for the chip's operating state under extreme environments, and the error test test point list is a list of test points for the chip's error handling capability.

[0013] Preferably, the process of using natural language processing (NLP) technology to perform word segmentation and entity recognition on the chip requirement document includes: converting the chip requirement document into structured data, performing word segmentation and entity recognition on the structured data of the chip requirement document using NLP technology to extract key information including functional modules, interface definitions, ecosystem compatibility, reliability, and performance indicators, and constructing input vector features based on the key information.

[0014] This invention also provides an electronic device with an AI agent, including a memory, a processor, and one or more operation instructions. The one or more operation instructions are stored in the memory, and the processor executes the one or more operation instructions to implement the intelligent decomposition method for chip verification test points as described above. The electronic device of this invention incorporates an automated verification platform to complete the entire process from test point decomposition to verification. This automated verification platform is a platform such as Verdi or VCS.

[0015] The present invention also provides a readable storage device storing one or more operation instructions, which can be executed by a processor to implement the chip verification test point intelligent decomposition method as described above.

[0016] Compared to existing technologies, this invention, on the one hand, directly obtains test points from the chip requirement document provided by the user, making the final test points closer to the user's needs, and eliminating the need for manual conversion of user requirements into corresponding specification documents. On the other hand, this invention inputs training data containing historical test point decomposition results into a pre-trained large model, optimizes the parameters in the large model, fine-tunes the final test point template, and specifically adjusts the semantic understanding capability of the large model, enabling it to better understand the semantics of the chip requirement document and generate test points that conform to the verification specifications. Thus, by automatically understanding the chip requirement document and automatically decomposing test points through a large model, this significantly improves test point decomposition efficiency, reduces labor costs, and compresses test point generation time from several hours to minutes, shortening the chip verification cycle. Attached Figure Description

[0017] Figure 1 This is a flowchart of the intelligent decomposition method for chip verification test points in this invention.

[0018] Figure 2 This is a flowchart of step S4 of the present invention for generating test points that conform to the verification specifications.

[0019] Figure 3 This is a structural diagram of the electronic device with an AI agent according to the present invention. Detailed Implementation

[0020] To illustrate the technical content, structural features, objectives, and effects of the present invention in detail, the following description is provided in conjunction with the embodiments and accompanying drawings.

[0021] refer to Figure 1 The present invention provides a chip verification test point intelligent decomposition method 100, including steps S1 to S4.

[0022] S1, obtain the chip requirement document provided by the user.

[0023] S2, Natural Language Processing (NLP) is used to segment and identify entities in the chip requirement document to construct input vector features, thereby completing the preprocessing of the chip requirement document.

[0024] In step S2, natural language processing technology is used to perform word segmentation and entity recognition on the structured data of the chip requirement document. Specifically, the chip requirement document is first converted into structured data, and natural language processing technology is used to perform word segmentation and entity recognition on the structured data of the chip requirement document to extract key information including functional modules, interface definitions, ecosystem compatibility, reliability and performance indicators. Input vector features are then constructed based on the key information.

[0025] S3. Obtain the trained large model, input the training data containing the decomposition results of historical test points into the large model, optimize and adjust the parameters of the large model so that the large model understands the semantics of the chip requirement document.

[0026] The training data also includes chip architecture documents and industry standards.

[0027] The large model mentioned is a Transformer model to ensure the semantic understanding capability of the AI ​​agent. Of course, this Transformer model can also use CNN, RNN, BERT, or GPT models for test point decomposition; a lightweight model, such as MobileNet, can also be used to optimize inference speed, but a trade-off between accuracy and efficiency is required.

[0028] In step S3, the present invention, based on the pre-trained large model (the trained large model), performs fine-tuning training on the large model to form an AI agent focused on chip verification test point decomposition. Specifically, training data containing historical test point decomposition results is used to perform customized training on the large model through fine-tuning, thereby optimizing the parameters of the large model for test point decomposition and improving the model's adaptability to the test point decomposition task.

[0029] S4. Input the input vector features constructed from the chip requirements document into the large model after parameter optimization to generate a list of test points.

[0030] The test point list is categorized into functional testing, performance testing, boundary testing, and error testing, covering various functional states and possible scenarios of chip operation. Specifically, the functional testing test point list is a list of verification test points for each functional module of the chip; the performance testing test point list is a list of standard performance test points for the chip; the boundary testing test point list is a list of test points for the chip's operating state under extreme environments; and the error testing test point list is a list of test points for the chip's error handling capabilities.

[0031] refer to Figure 2 Specifically, step S4 is followed by steps S5 to S7.

[0032] S5 uses a prior knowledge base to validate the generated test point list to obtain the validation results. If validation passes, proceed to the next step; if validation fails, handle the exception (fill in the missing information) and proceed to the next step. For example, if there is abnormal input, fill in the missing scenario and proceed to the next step. Filling in the missing information at abnormal points can be done manually by completing the test points.

[0033] In this embodiment, the prior knowledge base includes industry test case templates. Specifically, the prior knowledge base is a structured knowledge set containing historical chip verification data, test case templates, and industry standards.

[0034] S6: The rule engine checks whether the generated test point list covers all functional modules of the chip requirements document. If yes, proceed to step S7; otherwise, return to step S4.

[0035] S7. Convert the test point list into the corresponding format of the verification tool output.

[0036] Step S7, converting the test point list into a verification tool output in the corresponding format, includes: organizing the test points according to priority and module, and then converting the test points marked with priority information into a verification tool output in the corresponding format according to module. The verification tool can be exported to a directly usable format such as CSV or JSON.

[0037] refer to Figure 3 The present invention also discloses an electronic device 200 with an AI agent, including a memory 21, a processor 22 and one or more operation instructions 23, wherein the one or more operation instructions 23 are stored in the memory 21, and the processor 22 executes the one or more operation instructions 23 to implement the chip verification test point intelligent decomposition method 100 as described above.

[0038] The present invention also discloses a readable storage device storing one or more operation instructions, which can be executed by a processor to implement the chip verification test point intelligent decomposition method 100 as described above.

[0039] In this invention, after obtaining the test point list, the test point list (or verification tool) is input into the corresponding chip testing software, so that the chip testing software performs chip testing based on the test point list, that is, according to the priority in the test point list, the content of each test point is specifically tested.

[0040] Compared with existing technologies, after chip design is completed, this invention forms a new AI agent based on the intelligent decomposition method 100 for chip verification test points. This AI agent is loaded onto the electronic device 200 and serves as the core module of the chip verification toolchain. It can intelligently extract test points directly from the chip requirement document provided by the user, making the final test points closer to the user's requirements, without the need for manual conversion of the user's requirements into corresponding specification documents. On the other hand, this invention inputs training data containing historical test point decomposition results into a trained large model, optimizes the parameters in the large model, fine-tunes the final test point template, and specifically adjusts the semantic understanding ability of the large model. This allows the large model to better understand the semantics of the chip requirement document and generate test points that conform to the verification specifications. Thus, by automatically understanding the chip requirement document and automatically decomposing test points through a large model, the efficiency of test point decomposition is greatly improved, labor costs are reduced, and the test point generation time is reduced from several hours to minutes, shortening the chip verification cycle.

[0041] The above-disclosed embodiments are merely preferred embodiments of the present invention and should not be construed as limiting the scope of the present invention. Therefore, any equivalent variations made in accordance with the scope of the present invention are still within the scope of the present invention.

Claims

1. A method for intelligent decomposition of chip verification test points, characterized in that, include: Obtain the chip requirement document provided by the user, and use natural language processing technology to perform word segmentation and entity recognition on the chip requirement document in order to construct input vector features; Once a well-trained large model is obtained, training data containing the decomposition results of historical test points is input into the large model, and the parameters of the large model are optimized and adjusted. The input vector features are input into the large model after parameter optimization to generate a list of test points.

2. The intelligent decomposition method for chip verification test points as described in claim 1, characterized in that, The training data also includes chip architecture documents and industry standards.

3. The intelligent decomposition method for chip verification test points as described in claim 1, characterized in that, After generating the test point list, it also includes: The generated test point list is validated using a prior knowledge base. If the validation fails, the missing points are filled in and then a coverage validation is performed. If the validation succeeds, a coverage validation is performed directly. The coverage verification includes: using a rule engine to detect whether the generated test point list covers all functional modules of the chip requirement document; if so, converting the test point list into a verification tool output in the corresponding format; otherwise, returning to step: inputting the input vector features into the parameter-optimized large model to generate the test point list.

4. The intelligent decomposition method for chip verification test points as described in claim 3, characterized in that, The prior knowledge base includes industry test case templates.

5. The intelligent decomposition method for chip verification test points as described in claim 3, characterized in that, Converting the test point list into the corresponding format of the verification tool output includes: organizing the test points according to priority and module, and then converting the test points marked with priority information into the corresponding format of the verification tool output according to module.

6. The intelligent decomposition method for chip verification test points as described in claim 1, characterized in that, The large model is the Transformer model.

7. The intelligent decomposition method for chip verification test points using AI agents as described in claim 1, characterized in that, The test point list is categorized into functional tests, performance tests, boundary tests, and error tests.

8. The intelligent decomposition method for chip verification test points as described in claim 7, characterized in that, The functional test test point list is a list of verification test points for each functional module of the chip; the performance test test point list is a list of standard performance test points for the chip; the boundary test test point list is a list of test points for the chip's operating state under extreme environments; and the error test test point list is a list of test points for the chip's error handling capability.

9. The intelligent decomposition method for chip verification test points as described in claim 1, characterized in that, Using natural language processing technology to perform word segmentation and entity recognition on the chip requirement document includes: converting the chip requirement document into structured data, using natural language processing technology to perform word segmentation and entity recognition on the structured data of the chip requirement document to extract key information including functional modules, interface definitions, ecosystem compatibility, reliability and performance indicators, and constructing input vector features based on the key information.

10. An electronic device, characterized in that: The method includes a memory, a processor, and one or more operation instructions, wherein the one or more operation instructions are stored in the memory, and the processor executes the one or more operation instructions to implement the intelligent decomposition method for chip verification test points as described in any one of claims 1-9.

Images