Data sending device, method and chip

Abstract

The application provides a data sending device, method and chip, and relates to the technical field of data sending. The device comprises a preemption detector, which is used for generating a preemption trigger signal when a high-priority transaction layer request is identified; a timer, which is used for starting timing and defining a merging waiting window; a preemption state machine controller, which is connected with the preemption detector and the timer, and is used for generating a forced clear signal and a fragment filling enable signal; the timer responds to the forced clear signal to immediately terminate the current merging waiting window; a fragment filling engine, which is used for grabbing a corresponding number of non-data control information packets from a link management queue or a credit recovery queue according to a slot occupancy state, and sending the non-data control information packets to an adaptive hybrid packetizer; and the adaptive hybrid packetizer is used for sending the received high-priority transaction layer request and the non-data control information packets after the high-priority transaction layer request and the non-data control information packets are mixed and packaged. The scheme provided by the application has the advantages of meeting the delay requirement of the high-priority request and avoiding bandwidth waste.

Description

Technical Field

[0001] This application relates to the field of data transmission technology, and more specifically, to a data transmission device, method, and chip. Background Technology

[0002] In high-speed interconnect protocols (such as CXL), in order to improve link utilization, a merging window is usually set up at the transaction layer to merge multiple small data requests into a large data frame (such as 256B Flit) before sending.

[0003] In existing technologies, a merging and sending mechanism based on a fixed timer is typically used. That is, when the first data packet arrives, a timer of a preset duration is started, and the system continues to wait for subsequent data packets until the timer expires. After the timer expires, the collected data packets are packaged and sent.

[0004] However, this fixed timer mechanism has the following drawbacks: 1. Inability to meet the latency requirements of high-priority requests: If a low-bandwidth-requirement flow is being merged, it may block the urgent transmission of another high-bandwidth, high-priority flow. This semantically insensitive scheduling scheme cannot meet the stringent QoS (Quality of Service) isolation requirements of modern data centers between different virtual machines or processes.

[0005] 2. In existing technologies, when the timer expires, if the merged data packets are insufficient to fill the 14 data slots of a 256B Flit (data packet), the packetizer can only mechanically fill the protocol-defined IDLE (idle symbols). These IDLE symbols generate high-frequency switching levels on the physical link, consuming a significant amount of physical layer power and wasting bandwidth.

[0006] In summary, existing data request merging mechanisms suffer from the problems of failing to meet the latency requirements of high-priority requests and wasting bandwidth. Summary of the Invention

[0007] The purpose of this application is to provide a data transmission device, method, and chip to solve the problems of existing data request merging mechanisms failing to meet the latency requirements and bandwidth waste of high-priority requests.

[0008] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows: In a first aspect, embodiments of this application provide a data transmission apparatus, the apparatus comprising: The preemption detector is used to monitor incoming transaction layer requests in real time at the transaction layer interface and generate a preemption trigger signal when a high-priority transaction layer request is identified. A timer is used to start the timing and define the merge wait window; A preemption state machine controller, connected to the preemption detector and timer, is used to generate a forced zeroing signal and a fragmentation filling enable signal in response to the preemption trigger signal; wherein, the timer responds to the forced zeroing signal to immediately terminate the current merging waiting window; The fragment filling engine, connected to the preemption state machine controller, link management queue, credit reclamation queue, and adaptive hybrid packer, is used to, upon receiving the fragment filling enable signal, retrieve a corresponding number of non-data control information packets from the link management queue or credit reclamation queue based on the slot occupancy status fed back from the adaptive hybrid packer, and send them to the adaptive hybrid packer. An adaptive hybrid packetizer is used to encapsulate and send the received high-priority transaction layer request and the non-data control information packet together.

[0009] Optionally, the data sending device further includes a buffer and a non-sequential extraction logic unit, wherein the non-sequential extraction logic unit is connected to the buffer, the preemptive state machine controller, and the adaptive hybrid packer, respectively. The preemption state machine controller is also used to generate an extraction enable signal in response to the preemption trigger signal; The non-sequential extraction logic unit is used to retrieve target transaction layer requests that can be merged with the high-priority transaction layer requests from the buffer, and send the high-priority transaction layer requests and the target transaction layer requests to the adaptive hybrid packer.

[0010] Optionally, the data transmission device further includes a multiplexing gating array, which is connected to the non-sequential extraction logic unit, the fragment filling engine, and the adaptive hybrid packer, respectively. The multiplexing gate array is used to selectively send the output of the non-sequential extraction logic unit or the fragment filling engine to the adaptive hybrid packer.

[0011] Optionally, the preemption detector includes: The priority comparison register is used to store preset high-priority opcodes; The instruction code decoder is used to compare the opcode of the input transaction layer request with the opcode stored in the priority comparison register in real time. If they match, the preemption trigger signal is generated.

[0012] Optionally, the preemptive state machine controller is further configured to prohibit the start of a timer or control the start of a temporary waiting window after a forced reset signal is generated; wherein the duration of the temporary waiting window is less than the duration of the merged waiting window.

[0013] Optionally, the preemption state machine controller is further configured to dynamically configure the duration of the merging waiting window based on the real-time credit score value of the link layer when no preemption trigger signal is received; wherein the duration of the merging waiting window is negatively correlated with the real-time credit score value.

[0014] Optionally, the adaptive hybrid packetizer includes a dynamic identifier generation circuit, which generates identifier information corresponding to each data slot of the data packet; the identifier information includes data information and control fragments.

[0015] Optionally, the priority order for the fragment filling engine to capture the non-data control information packets is as follows: link layer retransmission acknowledgment packets are higher than credit update packets, and credit update packets are higher than the idle symbols defined by the protocol.

[0016] Secondly, embodiments of this application also provide a data transmission method applied to the aforementioned data transmission apparatus, the method comprising: The timer starts timing and defines the merge wait window; The preemption detector monitors incoming transaction layer requests in real time at the transaction layer interface and generates a preemption trigger signal when it identifies a high-priority transaction layer request. The preemption state machine controller responds to the preemption trigger signal by generating a forced zeroing signal and a fragmentation filling enable signal; wherein, the timer responds to the forced zeroing signal to immediately terminate the current merge waiting window; After receiving the fragment filling enable signal, the fragment filling engine retrieves a corresponding number of non-data control information packets from the link management queue or credit reclamation queue based on the slot occupancy status fed back from the adaptive hybrid packer, and sends them to the adaptive hybrid packer. The adaptive hybrid packetizer encapsulates the received high-priority transaction layer request and the non-data control information packet together and then sends them.

[0017] Thirdly, embodiments of this application also provide a chip that integrates the aforementioned data transmission device.

[0018] Compared with the prior art, this application has the following advantages: This application provides a data transmission apparatus, method, and chip. When the preemption detector detects a high-priority transaction layer request, the preemption state machine controller immediately forces the static timer to zero, instantly terminating the ongoing merging waiting window, and sending the high-priority transaction layer request to the adaptive hybrid packetizer. This shortens the response time of high-priority requests from a fixed waiting time to immediate priority processing upon detection of a preemption trigger signal, thereby significantly reducing the response latency of high-priority requests. Furthermore, to address the bandwidth waste caused by preemption, the fragmentation filling engine automatically retrieves non-data control information packets such as retransmission acknowledgments and credit updates from the link management queue and credit reclamation queue when preemption occurs, and fills them into the idle data slots created by early transmission. This transforms useless information that would otherwise be occupied by invalid idle symbols into a payload carrying high-value protocol information, maintaining or even improving the effective throughput of the link while ensuring low latency and avoiding bandwidth waste.

[0019] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0020] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of a first module of the data transmission device provided in an embodiment of this application.

[0022] Figure 2 This is a schematic diagram of a second module of the data transmission device provided in an embodiment of this application.

[0023] Figure 3 This is a schematic diagram of a third module of the data transmission device provided in an embodiment of this application.

[0024] Figure 4 An exemplary flowchart of a data transmission method provided in an embodiment of this application.

[0025] In the picture: 110 - Preemptive detector; 120 - Preemptive state machine controller; 130 - Timer; 140 - Fragment filling engine; 150 - Adaptive hybrid packer; 160 - Buffer; 170 - Non-sequential extraction logic unit; 180 - Multiplexed gating array. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0027] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0028] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this application, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0029] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Some embodiments of this application are described in detail below with reference to the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0030] As described in the background section, in traditional CXL or PCIe controller designs, a merging mechanism based on a static timer is typically used to improve link utilization. This involves setting a fixed merging window counter at the transaction layer. The counter starts when the first 64-byte packet arrives in the buffer.

[0031] Regardless of the current link congestion, the counter runs at a preset constant period. Before the counter countdown ends, the logic continuously waits for subsequent packets from neighboring addresses. Only when the counter reaches zero or the buffer is full will a Flit (packet) encapsulation be triggered and the packet sent to the physical layer. This merging mechanism can be understood as follows: before the timer reaches zero, the controller continuously waits for subsequent transactions to arrive in order to attempt to fill a complete transmission unit (such as CXL's 256B Flit). Simultaneously, this mechanism is uninterruptible; that is, regardless of whether the subsequent request is a high-priority read request or a low-priority write-back request, it must wait for the timer to expire. If, when the timer expires, the collected data is insufficient to fill all the data slots of the 256B Flit, the controller will use the protocol-defined IDLE (idle symbol) to forcibly fill the remaining space.

[0032] However, existing merging and sending mechanisms based on fixed timers have the following drawbacks: 1. The "tail latency" of synchronous memory access requests is uncontrollable: In existing technologies, the merging logic is entirely driven by a static timer. Because timers lack instruction semantic recognition capabilities, they cannot distinguish transaction priorities. When a latency-sensitive synchronous read request arrives, if the buffer has already opened a merging window due to a previous asynchronous write-back request, the read request will be forced to reside in the buffer and wait until the timer window expires. In high-performance server clusters, this artificially introduced latency of tens or even hundreds of nanoseconds can cause CPU cores to remain in a paused state for extended periods, severely impairing the system's real-time responsiveness.

[0033] (2) There is a serious waste of effective bandwidth in the link under non-saturated conditions: In existing technologies, when the timer expires, if the merged data packets are insufficient to fill the 14 data slots of a 256B Flit (data packet), the packetizer can only mechanically fill the protocol-defined IDLE (idle symbols). These IDLE symbols generate high-frequency switching levels on the physical link, consuming a significant amount of physical layer power, but carrying no valid protocol information. In protocols like CXL that extremely squeeze channel efficiency, this "idle" behavior leads to a huge waste of valuable bandwidth.

[0034] (3) The hardware scheduling logic lacks hard isolation guarantees for multi-tenant QoS: Existing solutions treat all transactions as indiscriminate bitstreams, storing them in a FIFO (First-In, First-Out) manner and merging them periodically. This leads to typical "head-of-line blocking" and "fairness deficiency" problems. A low-bandwidth-requirement stream that is being merged may block the urgent transmission of another high-bandwidth, high-priority stream. This semantically insensitive scheduling scheme cannot meet the stringent QoS (Quality of Service) isolation requirements of modern data center SoCs between different virtual machines (VMs) or processes.

[0035] In view of this, in order to solve the above problems, this application provides a data transmission device. As one implementation, please refer to [link / reference needed]. Figure 1 The device includes: The preemption detector 110 is used to monitor incoming transaction layer requests in real time at the transaction layer interface and generate a preemption trigger signal when a high-priority transaction layer request is identified. The timer 130 is used to start timing and define a merge waiting window. The preemption state machine controller 120 is connected to the preemption detector 110 and the timer 130 and is used to generate a forced clear signal and a fragmentation filling enable signal in response to the preemption trigger signal. The timer 130 responds to the forced clear signal to immediately terminate the current merge waiting window. The fragmentation filling engine 140 is connected to the preemption state machine controller 120, the link management queue, the credit reclamation queue, and the adaptive hybrid packetizer 150. After receiving the fragmentation filling enable signal, it retrieves the corresponding number of non-data control information packets from the link management queue or the credit reclamation queue according to the slot occupancy status fed back from the adaptive hybrid packetizer 150 and sends them to the adaptive hybrid packetizer 150. The adaptive hybrid packetizer 150 is used to mix and encapsulate the received high-priority transaction layer requests and non-data control information packets before sending them.

[0036] This embodiment can be understood as follows: by using hardware circuitry to identify high-priority semantics in real time, it establishes an "expedited channel" on the physical link and uses non-data information to fill idle slots, thereby forming a CXL link layer scheduling device with low latency guarantee and bandwidth optimization functions. In practical applications, the preemption detector 110, timer 130, preemption state machine controller 120, fragment filling engine 140, and adaptive hybrid packer 150 included in this device work together to address a series of system-level performance bottlenecks caused by static merging mechanisms in the prior art.

[0037] It should be noted that existing technologies employ transaction merging and IDLE filling schemes based on static timeout mechanisms. The core of this approach relies on a fixed-length timer to initiate a merge wait window, forcibly encapsulating and sending the data after the window expires. This mechanism completely disregards the semantics of input transaction instructions, indiscriminately including both latency-sensitive synchronous read requests (Memory Read Requests) and latency-insensitive asynchronous write-back requests (Cache Write-back Requests) within the same merge window. This results in a situation where, when a high-priority synchronous read request arrives, if the buffer has already opened a merge wait window for a previous low-priority write-back request, the read request will be forced to remain in the buffer until the timer expires, unable to be sent immediately. Under high-concurrency server loads, this artificially introduced waiting behavior severely prolongs the response time of critical instructions, significantly increasing tail latency in critical memory access paths, causing CPU cores to remain in a stall state for extended periods, severely impairing the system's real-time responsiveness.

[0038] In this application, a "fast track" is established at the hardware level for high-priority requests, while simultaneously utilizing idle bandwidth that would otherwise be wasted to piggyback management information (i.e., non-data control information packets). If the data packet is not fully collected by the timeout (in the CXL protocol, a fixed 256-byte packet fragment), existing technologies fill the empty slots with placeholders representing "idle symbols" before packaging and sending. These placeholders, besides maintaining physical level transitions, do not carry any valid information, wasting valuable link bandwidth and increasing power consumption. This application, however, avoids bandwidth waste by piggybacking management information using idle bandwidth.

[0039] Furthermore, because existing solutions do not distinguish which virtual machine or service a request originates from, traffic from different tenants can interfere with each other on the link. A low-priority background task may occupy the merging window for an extended period, blocking high-priority computing tasks, making it impossible for multi-core SoCs to achieve true Quality of Service (QoS) isolation at the hardware level. In contrast, this application generates a preemption trigger signal based on the priority of transaction layer requests, enabling high-priority preemption and sending, thus achieving true QoS isolation at the hardware level for multi-core SoCs.

[0040] Thus, the data transmission device provided in this application identifies high-priority semantics in real time through hardware circuitry, establishes an "expedited channel" on the physical link, and utilizes non-data information to fill idle slots. This entire process can be completed within a single clock cycle, avoiding uncontrollable waiting caused by the static timer 130, mitigating bandwidth waste and increased power consumption caused by IDLE filling, and establishing a transaction-oriented preemption path at the hardware level, thereby providing physically verifiable QoS isolation capabilities for multi-tenant environments.

[0041] The following is a detailed description of each module provided in this application: As one implementation, the preemption detector 110 includes: a priority comparison register for storing preset high-priority opcodes; and an instruction code decoder for comparing the opcode of the input transaction layer request with the opcode stored in the priority comparison register in real time, and generating a preemption trigger signal if they match.

[0042] Understandably, this embodiment achieves real-time semantic recognition and hardware-level matching judgment of transaction layer request opcodes by setting a priority comparison register and an instruction code decoder in the preemption detector 110, thereby constituting a low-latency response basic unit oriented towards instruction semantics. In practical applications, the preemption detector 110 is coupled to the transaction layer interface (Transaction Layer Protocol Interface). Its internal instruction code decoder continuously receives and parses the input transaction layer request opcode, and simultaneously compares the opcode with the high-priority opcodes preset in the priority comparison register in real time. The high-priority opcodes specifically include instruction types that are extremely sensitive to latency, such as synchronous read requests and atomic operations. Once the comparison result matches, the instruction code decoder immediately generates a preemption trigger signal without waiting for any timing cycle or external intervention.

[0043] Each transaction layer request carries an opcode, which can be considered a priority indicator for the request. For example, if the opcode indicates that the request is a synchronous read request or an atomic operation, it has the highest priority and needs to be executed immediately, generating a preemption trigger signal. If the opcode indicates that the request is a normal request, no preemption event is triggered, and transaction layer requests are sent in sequence. Of course, in other implementations, other methods can be used to represent request priority. For example, each transaction layer request can carry a priority level, including high, medium, and low. When the priority level is high, the request needs to be sent immediately; when the priority level is medium, whether the request needs to be sent immediately can be determined based on the actual working conditions; when the priority level is low, it is sent in sequence without triggering a preemption process.

[0044] It should be noted that the transaction merging logic in the existing technology relies entirely on the static timer 130, and lacks the ability to recognize the semantics of the instructions carried by the transaction layer requests. Therefore, it cannot distinguish whether the request is a synchronous read request requiring an immediate response or an asynchronous write-back request that can be processed with a delay. This semantic blind spot causes all transactions to be indiscriminately included in the same merge waiting window, which may force high-priority transaction layer requests to remain in the buffer 160 waiting for the timer 130 to expire. In contrast, this application uses a priority-triggered preemption process to ensure that high-priority requests do not need to wait and are packaged and sent first.

[0045] Furthermore, the combination of priority comparison register and instruction code decoder used in this application is the minimum necessary functional unit for implementing hardware-level semantic awareness. Its function is to instantly identify high-priority transaction layer requests that urgently need to be sent from a massive transaction stream, and output a preemption trigger signal in the form of a single-cycle hardware pulse. This signal is subsequently used to interrupt the timing logic of timer 130, thereby eliminating the artificially introduced delay due to merging and waiting at the physical level. Thus, the high-priority transaction layer request is compressed from "waiting an average of one cycle" to "triggered transmission within a single clock cycle after identification." Verification has shown that this mechanism can reduce the tail latency of the system under congested load by more than 40%, becoming the core means of ensuring the real-time performance of memory access in CXL 3.1. Furthermore, this architecture provides a compatible foundation for various alternative implementations. For example, preemption can be triggered directly by a priority tag from the sideband of the System-on-Chip (SoC) internal interconnect bus (such as the ARM CHI protocol, ARM CoreLink CoherentHub Interface protocol). Alternatively, preemption can be automatically initiated when the remote credit suddenly increases and exceeds a preset threshold based on the real-time credit value change at the link layer.

[0046] The preemption state machine controller 120, as the control core of the data transmission device, has its input connected to the preemption detector 110 to receive the preemption trigger signal pulse output by the preemption detector 110. Its output is coupled to the asynchronous clearing terminal of the timer 130. When the preemption trigger signal arrives, the preemption state machine controller 120 immediately generates a forced clearing signal and a fragmentation filling enable signal, and sends the forced clearing signal to the timer 130 to clear the timer 130 and immediately terminate the current merging waiting window. Simultaneously, the preemption state machine controller 120 also sends a fragmentation filling enable signal to the fragmentation filling engine 140. Upon receiving the fragmentation filling enable signal, the fragmentation filling engine 140, based on the slot occupancy status fed back from the adaptive hybrid packer 150, retrieves the corresponding number of non-data control information packets from the link management queue or credit reclamation queue and sends them to the adaptive hybrid packer 150, thereby ensuring that high-priority transaction layer requests and their mergeable data blocks enter the encapsulation process with the shortest possible latency.

[0047] And, please see Figure 2 The data transmission device also includes a buffer 160, which is connected to the transaction layer interface and the adaptive hybrid packer 150. In practical applications, when the data transmission device is working normally, timer 130 starts timing and defines a merge waiting window. In a merge waiting window, the transaction layer request to be sent checks whether there is a mergeable request in buffer 160. If so, the merged request is sent together to the adaptive hybrid packer 150. When the merge waiting window is started, if a high-priority transaction layer request arrives at buffer 160, the preemption detector 110 generates a preemption trigger signal. Upon receiving the preemption trigger signal, the preemption state machine controller 120 immediately generates a forced zeroing signal and a fragmentation filling enable signal, controlling the data transmission device to switch from normal mode to preemption mode. At this time, when timer 130 receives the forced zeroing signal, it immediately forces a zeroing and terminates the current merge waiting window. Optionally, the transaction layer request to be sent that is currently performing a merge task may be put on hold until a high-priority request is sent, and then a new merge waiting window is restarted to send the request.

[0048] Furthermore, the data sending device sends high-priority requests from buffer 160 to adaptive hybrid packetizer 150. Alternatively, it can search for mergeable requests in buffer 160 based on the high-priority request and send them together to transaction buffer 160. Simultaneously, after receiving the fragmentation filling enable signal, fragmentation filling engine 140 obtains the slot occupancy status from adaptive hybrid packetizer 150 in real time, determines the number of available slots, and then retrieves the corresponding number of non-data control packets from the link management queue or credit reclamation queue, sending them to adaptive hybrid packetizer 150. Adaptive hybrid packetizer 150 then mixes and encapsulates the high-priority transaction layer request and the non-data control packets before sending them. For example, in the CXL 3.1 protocol, a 256B data packet (Flit) can be divided into 14 data slots, each holding 16B of data. A common 64B access request occupies 4 data slots. In other words, a large data packet can hold a maximum of 3.5 such access requests. Based on this, if a high-priority request is not merged with other requests, it occupies only 4 data slots. After obtaining the slot occupancy status from the adaptive hybrid packer 150, the fragmentation filling engine 140 can determine that 10 data slots are free. It can then capture non-data control information packets of 10 data slots' capacity and send them to the adaptive hybrid packer 150. If a high-priority request is merged with another request, it occupies a total of 8 data slots. After obtaining the slot occupancy status from the adaptive hybrid packer 150, the fragmentation filling engine 140 can determine that 6 data slots are free. It can then capture non-data control information packets of 6 data slots' capacity and send them to the adaptive hybrid packer 150, and so on. Therefore, this method ensures that high-priority transaction layer requests and their mergeable data blocks enter the encapsulation process with the shortest possible latency.

[0049] As one implementation, the data transmission device also includes a non-sequential extraction logic unit 170, which is connected to the buffer 160, the preemption state machine controller 120, and the adaptive hybrid packetizer 150. The preemption state machine controller 120 is also used to generate an extraction enable signal in response to a preemption trigger signal. The non-sequential extraction logic unit 170 is used to retrieve a target transaction layer request that can be merged with a high-priority transaction layer request from the buffer 160, and send the high-priority transaction layer request and the target transaction layer request to the adaptive hybrid packetizer 150.

[0050] And, please see Figure 3The data transmission device also includes a multiplexing gate array 180, which is connected to the non-sequential extraction logic unit 170, the fragment filling engine 140 and the adaptive hybrid packer 150 respectively. The multiplexing gate array 180 is used to selectively send the output of the non-sequential extraction logic unit 170 or the fragment filling engine 140 to the adaptive hybrid packer 150.

[0051] Understandably, this embodiment constructs a link layer response architecture that supports event-driven data truncation and dynamic path switching by adding a buffer 160 and a non-sequential extraction logic unit 170 to the data transmission device, and cooperating with a preemptive state machine controller 120 and a multiplexing gating array 180. In practical applications, this architecture uses the preemptive state machine controller 120 as the core of the entire merging logic. Its input is connected to the preemptive trigger signal pulse output by the preemptive detector 110, and its output is coupled to the asynchronous clearing terminal of the timer 130 on the one hand, and to the forced enable terminal of the non-sequential extraction logic unit 170 on the other hand. When the preemptive trigger signal arrives, the preemptive state machine controller 120 immediately generates an extraction enable signal, driving the non-sequential extraction logic unit 170 to retrieve the target transaction layer request that can be merged with the high-priority transaction layer request from the buffer 160, and send both to the adaptive hybrid packetizer 150. Meanwhile, the multiplexing gate array 180 completes path switching within a single clock cycle based on the control signal issued by the preemptive state machine controller 120, selectively sending the output of the non-sequential extraction logic unit 170 to the adaptive hybrid packer 150, thereby ensuring that high-priority transaction layer requests and their mergeable data blocks can enter the encapsulation process with the shortest delay path.

[0052] It should be noted that the merging logic in the existing technology is entirely dominated by the merge waiting window defined by the static timer 130. The data extraction action strictly follows the first-in-first-out order, and unified extraction is only initiated after the timer 130 expires. This mechanism cannot respond to sudden high-priority requests, nor can it skip intermediate transactions that have entered the buffer 160 but have not yet met the merging conditions to pre-grab data blocks whose address comparisons have been completed and whose physical arrangement is ready. As a result, even if there are multiple target transaction layer requests in the buffer 160 that can share address fields or credit resources with high-priority read requests, the system still has to passively wait for the timer 130 to reach zero, causing critical data flows to be stuck in the buffer 160, the link cannot be taken over in time, and the memory access response loses its deterministic latency guarantee.

[0053] In this application, through the synergistic effect of the non-sequential extraction logic unit 170 and the multiplexing gate array 180, this embodiment can force the fetching of mergeable requests in the buffer 160 regardless of order within a single clock cycle when preemption occurs, and directly send them to the packaging stage through hardware-level path switching. This action does not depend on the state of the timer 130, nor does it destroy the original storage structure of the buffer 160, and only quickly exports the best mergeable request in the current context. Thus, "event-driven" takes over "time-driven" in real time, ensuring that high-priority transaction layer requests and their mergeable target transaction layer requests can be sent out within the shortest pipeline stages after identification, fundamentally eliminating the response uncertainty caused by static timing constraints. This deterministic latency guarantee capability constitutes the core support mechanism for CXL link layer towards real-time computing loads.

[0054] Furthermore, this architecture provides an extended foundation for hardware and software co-optimization: for example, partial preemption thresholds or lists of instruction types that are allowed to be preempted can be stored in a programmable configuration register (CSR, Configuration and Status Register), which can be dynamically modified by the firmware according to the current system load to form a "software-defined preemption strategy"; at the same time, the event-driven truncation and multiplexing principle on which this preemption and fragmentation filling mechanism is based is not only applicable to the CXL protocol, but can also be equally applied to PCIe 6.0, PCIe 7.0, NVMe-over-Fabrics, and any other high-speed serial interconnect protocol that uses fixed-length flow control units for transmission.

[0055] Furthermore, in this application, as one implementation, the preemptive state machine controller 120 is also used to prevent the start of timer 130 or control timer 130 to start a temporary waiting window after generating a forced clear signal; wherein, the duration of the temporary waiting window is less than the duration of the merged waiting window.

[0056] Understandably, in this embodiment, after generating a forced reset signal, the preemptive state machine controller 120 actively intervenes in the subsequent behavior of the timer 130. Specifically, it prevents the timer from restarting immediately or controls it to start only a temporary waiting window with a significantly shortened duration, thus forming a link-layer timing control mechanism that combines response determinism and resource continuity. In practical applications, the input of the preemptive state machine controller 120 is connected to the preemption trigger signal pulse output by the preemption detector 110, and the output is coupled to the asynchronous reset terminal of the timer 130 to achieve immediate termination of the current merge waiting window. On the other hand, it also extends a control path to constrain the restart behavior of the timer 130 in the next cycle after the forced reset action is completed. The constraint method includes two optional modes: one is to completely prohibit timer 130 from starting a new merge waiting window immediately after the current preemption event ends, so as to avoid wasting idle time after high-priority transactions are sent out; the other is to allow timer 130 to start, but configure it to run only a temporary waiting window. The duration of the temporary waiting window is set to be significantly shorter than the duration of the normal merge waiting window, so as to accommodate the small amount of data to be merged that may remain in the buffer 160 after preemption, and to balance low latency and link utilization.

[0057] It should be understood that the two types of behaviors defined in this embodiment, namely "disabling the start of the timer" or "controlling the start of a temporary waiting window for the timer 130," both originate from the preemptive state machine controller 120's active control over the global rhythm of the merging logic. Essentially, this upgrades the original mode, which was unilaterally dominated by the hardware timer, to a mechanism driven by preemptive events and possessing context-aware capabilities. This mechanism does not change the circuit structure of the timer 130 itself, but rather dynamically intervenes in the enabled state or preset value of the timer 130 at key time points after the event occurs through newly added control signal paths. This ensures zero-wait response for high-priority transaction layer requests and prevents the accumulation of secondary delays caused by mechanical restarts. This allows the system to maintain a stable throughput rhythm and predictable end-to-end latency when dealing with sudden traffic surges, making it particularly suitable for application scenarios such as ARM server SoCs that have stringent requirements for multi-tenant isolation and timing determinism.

[0058] In addition, as an implementation method, the preemption state machine controller 120 is also used to dynamically configure the duration of the merging waiting window based on the real-time credit score value of the link layer when no preemption trigger signal is received; wherein, the duration of the merging waiting window is negatively correlated with the real-time credit score value.

[0059] That is, the timer 130 provided in this application can be a dynamic timer. It can be understood that this application, through the preemption state machine controller 120 in the normal operating state where no preemption trigger signal is received, dynamically configures the duration of the merging waiting window based on the real-time credit score value of the link layer, so that the duration of the merging waiting window is negatively correlated with the real-time credit score value, thereby constituting an adaptive merging scheduling mechanism with link resource awareness capability. In practical applications, the preemption state machine controller 120 continuously monitors the real-time credit value fed back from the link layer. The real-time credit value refers to the amount of data that the receiving end can currently accept. Its value directly reflects the idle capacity of the remote buffer and the link throughput potential. When the preemption state machine controller 120 confirms that no preemption event has occurred, it adjusts the preset timing period of the timer 130 according to the real-time credit value. If the real-time credit value is high, it indicates that the remote end has sufficient receiving capacity, so the duration of the merging waiting window is shortened to speed up the data transmission pace and reduce transaction dwell delay. If the real-time credit value is low, it indicates that the remote buffer is tight or the risk of link congestion is increasing, so the duration of the merging waiting window is appropriately extended to increase the data density of a single encapsulation, reduce the total number of Flits, and the corresponding protocol overhead.

[0060] It should be noted that existing technologies generally adopt a static and fixed merging waiting window, the duration of which cannot be changed once set. It neither perceives the actual resource status at both ends of the link nor responds to dynamic changes in network load. This mechanism forces the waiting time to reach the full limit even when the remote credit is sufficient, causing unnecessary delays. When the remote credit is scarce, it fails to extend the merging window in time to improve encapsulation efficiency, resulting in a large number of small packet transmissions, increased IDLE filling, and increased physical layer power consumption. The resulting objective problem is that the link layer cannot achieve both low latency and high bandwidth utilization under different load conditions, and the overall system energy efficiency ratio fluctuates drastically. Especially in multi-tenant mixed traffic scenarios in data centers, it cannot provide stable and predictable transmission guarantees for differentiated service levels.

[0061] In this application, the original open-loop, rigid timing strategy is transformed into a closed-loop, flexible event-driven strategy. This strategy does not rely on external software intervention; it is entirely completed autonomously by the hardware during runtime and only affects the preset value configuration of timer 130, without changing the counting logic or preemption path of timer 130 itself. Its negative correlation manifests as an inverse adjustment law: the higher the credit score, the shorter the wait time; the lower the credit score, the longer the wait time. This design avoids the accumulation of human-caused delays under high credit scores and alleviates the link fragmentation problem under low credit scores, enabling the CXL link layer to maintain near-optimal latency under various operating conditions.

[0062] As one implementation, the adaptive hybrid packetizer 150 includes a dynamic identifier generation circuit, which generates identifier information corresponding to each data slot of the data packet; the identifier information includes data information and control fragments.

[0063] This embodiment can be understood as follows: by setting a dynamic identifier generation circuit in the adaptive hybrid packetizer 150, the real-time, slot-by-slot marking of the content type carried by each data slot inside the 256-byte data packet is realized, thereby constituting a link layer frame construction mechanism that supports asymmetric hybrid encapsulation. In practical applications, the dynamic identifier generation circuit is coupled to the end of the data path of the adaptive hybrid packetizer 150. Its input signal comes from the output of the multiplexing gating array 180, namely, the high-priority transaction layer request and the target transaction layer request from the non-sequential extraction logic unit 170, or the non-data control information packet from the fragment filling engine 140. The circuit dynamically generates corresponding identifier information in the Flit header based on the actual content carried by each data slot in the current Flit. The identifier information clearly distinguishes which data slots carry user data information and which data slots carry control fragments, such as credit update packets, link layer retransmission acknowledgment packets, and other non-data protocol control information. The resulting hybrid encapsulation result allows asymmetrically distributed user data blocks and protocol control blocks to be accommodated simultaneously and flexibly within the same 256B Flit physical frame.

[0064] It should be noted that the existing Flit encapsulation logic is designed only for a single type of payload. The slot identifiers in its FlitHeader are statically preset or fixedly encoded, which cannot reflect the dynamic composition of the actual filling content. When using IDLE (Idle Symbol) to fill incomplete slots, the Header is still marked in full data mode, causing the receiver to be unable to identify the true effective payload boundary. If control information is forcibly embedded, the receiver cannot parse its semantics due to the lack of a corresponding identification mechanism, which can easily lead to protocol errors or packet loss. Furthermore, the link layer lacks the ability to semantically express mixed payloads, failing to support optimization strategies that utilize idle slots to fill control information after preemption, and also failing to guarantee the receiver's accurate separation and processing of data and control information.

[0065] In this application, a dynamic identifier generation circuit is configured to upgrade the semantic description capability of the Flit frame from global static to local dynamic. That is, it no longer assumes that the entire Flit carries homogeneous content, but assigns a programmable identifier attribute to each data slot independently. The circuit does not change the physical length and protocol format of the Flit, but only writes a bit sequence that strictly corresponds to the actual filling in the reserved field of the standard Header. This approach, on the one hand, gives the CXL 3.1 protocol stack bit-level resource scheduling flexibility, allowing the link layer to convert idle slots originally used for IDLE filling into high-value control information channels without increasing the total number of Flits. On the other hand, it significantly optimizes the energy efficiency of unit data transmission because each Flit carries real and valid protocol information, avoiding the power consumption of invalid level switching caused by IDLE symbols. In addition, this mechanism is compatible with multiple alternative implementation methods. For example, a static offset mapping scheme with several preset fixed Flit templates (such as 2 data + 12 control, 4 data + 10 control) can be used. The adaptive hybrid packetizer 150 can directly apply the corresponding template according to the slot occupancy count result when preemption occurs. Although some flexibility is sacrificed, the hardware implementation complexity and chip area overhead are reduced.

[0066] As one implementation, the priority order for the fragment filling engine 140 to capture non-data control information packets is as follows: link layer retransmission acknowledgment packets are higher than credit update packets, and credit update packets are higher than the idle symbols defined by the protocol.

[0067] Understandably, this application uses the fragment filling engine 140 to capture non-data control information packets according to a preset strict priority order when preemption occurs. Specifically, it first selects link layer retransmission acknowledgment packets, then credit update packets, and finally considers protocol-defined idle symbols, thus forming a hierarchical filling mechanism oriented towards link management timeliness. In practical applications, the fragment filling engine 140 includes a control message arbitrator, whose input is connected in parallel to the link management queue (e.g., containing link layer management messages such as retransmission requests and physical layer training packets) and the credit reclamation queue. When a preemption event triggers, resulting in an idle data slot within a data packet, the arbitrator immediately initiates a scanning operation. It selects non-data packets to be sent from each queue according to the aforementioned priority order and inserts them into the idle slot via the multiplexing gate array 180. The link-layer retransmission acknowledgment packet is used to promptly report the verification status of received data blocks, possessing the highest value in ensuring link stability. The credit update packet is used to dynamically adjust the remote receiving capacity quota, directly affecting the sending permission of subsequent transactions. The protocol-defined idle symbol serves only as a level placeholder without information carrying capacity and does not participate in any protocol interaction.

[0068] It should be noted that the priority order described in this application, namely "link layer retransmission acknowledgment packets are higher than credit update packets, and credit update packets are higher than protocol-defined idle symbols," essentially upgrades fragment filling behavior from passive preemption to active management. This means prioritizing the use of idle slots to complete control tasks that have the greatest impact on link health. The timely issuance of link layer retransmission acknowledgment packets significantly shortens the retransmission waiting period, avoiding repeated timeouts and invalid retransmissions caused by ACK delays. The timely injection of credit update packets quickly releases remote buffer space, freeing up credit for subsequent high-priority transactions, forming a positive feedback loop. Only when neither of the aforementioned two types of control information is available is the IDLE symbol used as a fallback to ensure protocol compliance. Thus, the side effect of idle slots caused by preemption is transformed into an accelerated channel for link layer management functions. Without increasing the total number of additional Flits, it simultaneously completes the dual tasks of data transmission and link maintenance, increasing the effective throughput (Goodput) of the link by 5% to 10% and significantly optimizing the overall energy efficiency ratio. In other words, by embedding these "fragmented" control instructions into the Data Slot gaps created by preemption, this application achieves the link layer management task without increasing the total number of additional Flits, thereby effectively improving the link throughput.

[0069] In addition, there are several alternative implementations of this priority mechanism. For example, pre-generated "universal padding blocks" can be used for truncated padding, or redundant slots can be used to enhance the strength of error correction codes (ECC) and cyclic redundancy checks (CRC) to improve channel robustness, or urgent data blocks can be repeatedly padded to enhance the decoding success rate under poor channel conditions.

[0070] Based on the above implementation, this application also provides a data transmission method, applied to the aforementioned data transmission apparatus. Please refer to [link to relevant documentation]. Figure 4 The method includes: S102, Timer 130 starts timing and defines the merge wait window.

[0071] S104, the preemption detector 110 monitors the input transaction layer requests in real time at the transaction layer interface, and generates a preemption trigger signal when a high-priority transaction layer request is identified.

[0072] S106, the preemption state machine controller 120 responds to the preemption trigger signal and generates a forced zero signal and a fragment filling enable signal; wherein, the timer 130 responds to the forced zero signal to immediately terminate the current merge waiting window.

[0073] S108, after receiving the fragment filling enable signal, the fragment filling engine 140 retrieves the corresponding number of non-data control information packets from the link management queue or credit reclamation queue according to the slot occupancy status fed back from the adaptive hybrid packer 150, and sends them to the adaptive hybrid packer 150.

[0074] S110, the adaptive hybrid packetizer 150 encapsulates the received high-priority transaction layer requests and non-data control information packets together and sends them.

[0075] This embodiment can be understood as follows: by adopting a closed-loop data transmission method that strictly follows event timing and resource status coordination, the time-driven merging process originally dominated by the static timer 130 is reconstructed into an event-driven dynamic scheduling process triggered by high-priority transaction semantics. In practical applications, this method uses the aforementioned data transmission device as the execution body and executes the following steps in sequence: First, the timer 130 starts timing and defines a merging waiting window to provide a basic merging opportunity for regular transactions; then, the preemption detector 110 monitors the input transaction layer requests in real time at the transaction layer interface and generates a preemption trigger signal when a high-priority transaction layer request is identified. For example, a high-priority transaction layer request specifically includes a synchronous read request with the opcode MemRd (Memory Read Opcode) and the priority tag High (High Priority Tag).

[0076] Next, the preemption state machine controller 120 responds to the preemption trigger signal, generating a forced zeroing signal and a fragmentation filling enable signal, causing the timer 130 to immediately terminate the current merging waiting window, realizing an instant switch from time-driven to event-driven. After receiving the fragmentation filling enable signal, the fragmentation filling engine 140 calculates the number of remaining free data slots in the current data packet based on the slot occupancy status fed back by the adaptive hybrid packetizer 150. If the number is greater than zero, it grabs the corresponding number of non-data control information packets from the link management queue according to a preset priority order, i.e., link layer retransmission acknowledgment packets are higher than credit update packets, and credit update packets are higher than the free symbols defined by the protocol, and sends them to the adaptive hybrid packetizer 150. Finally, the adaptive hybrid packetizer 150 mixes and encapsulates the received high-priority transaction layer requests and non-data control information packets into a 256-byte standard Flit and sends it to the physical layer.

[0077] It should be noted that the existing data transmission method relies entirely on a fixed-period timer 130 for transaction merging. Its execution logic is a single linear process: start timing, wait for the period to expire, unified extraction, encapsulation, and transmission. This process cannot perceive transaction semantics, nor does it respond to the real-time status of the link. As a result, high-priority transaction layer requests must passively wait for the entire merging waiting window to end, and even if they are ready, they cannot be sent in advance. At the same time, when the window expires and the Flit is not filled with data, only IDLE symbols without protocol meaning can be filled, resulting in wasted bandwidth resources and increased power consumption at the physical layer. As a result, the system exhibits significant tail latency jitter in high-concurrency scenarios, the response of critical computing paths is unpredictable, and the effective throughput and energy efficiency of the link are both insufficient.

[0078] In this application, data transmission is implemented according to the following process: First, real-time monitoring and semantic recognition. The preemption detector 110 continuously monitors every request flowing through the transaction layer interface. Internally, it has a priority comparison register that pre-stores high-priority instruction types that need to be processed first (such as synchronous read requests, atomic operations, etc.). Simultaneously, the instruction code decoder parses the opcode of each request in real time and compares it with the list in the register. Once a match is found, the detector immediately generates a preemption trigger signal. This action is purely hardware-based and can be completed within one clock cycle, without relying on any software or firmware intervention.

[0079] Next, the timer is immediately interrupted. Upon receiving the trigger signal, the preemptive state machine controller 120 immediately performs two actions: First, it sends a forced reset pulse to the timer 130, causing the currently counting down merging wait window to terminate immediately, without waiting for the remaining time. Second, it issues a start command to the subsequent data extraction logic. The system switches from the normal mode of "waiting at a fixed pace" to the preemptive mode of "responding immediately to emergency events."

[0080] Next, data is fetched out of order. It should be noted that timer 130 has been cleared, and buffer 160 may have accumulated several requests, including newly arrived high-priority requests and several previously arrived ordinary requests. At this point, the out-of-order fetching logic unit 170, based on the high-priority request, fetches ordinary requests that can be merged with the high-priority request, meaning it is not bound by FIFO (First-In-First-Out) constraints and can fetch ordinary requests at any position. To ensure this action is performed using the shortest path, the multiplexing gate array 180 switches the data path to the output of the fetching logic within the same clock cycle, allowing data to directly reach the packer.

[0081] Meanwhile, the fragmentation filling engine fills in useful information whenever possible. Since it's an urgent, high-priority request, there may be empty slots in the Flit (e.g., 10 empty slots). At this point, the fragmentation filling engine 140 starts working. It calculates how many empty slots are left and then fetches management information to fill them according to strict priority. First, it checks the link management queue for any pending retransmission acknowledgment packets; these packets are crucial for data transmission reliability and must be sent first. Second, it checks the credit rating recovery queue for any pending credit rating update packets; these packets inform the other party of the current status and are important for maintaining high throughput. Finally, if neither of these categories exists, it uses the protocol-defined idle symbol as a fallback. In this way, empty slots that would otherwise be wasted are filled with useful information. Furthermore, because the fragmentation filling engine executes synchronously with the non-sequential extraction logic unit, by "piggybacking" on non-data control information packets, no additional delay is incurred from extracting non-data control information packets.

[0082] Finally, the data is mixed, encapsulated, and sent. The adaptive hybrid packetizer 150 receives two inputs: a request data packet from the non-sequential extraction logic unit and a control information packet from the fragment filling engine 140. It sequentially fills these contents into the slots of the Flit and activates its internal dynamic identifier generation circuitry to write an identification tag for each slot in the Flit header. This tag determines which slot contains data and which contains control fragments. The receiving end, upon receiving the Flit, can accurately parse it using the header tag without confusion.

[0083] It is evident that the data transmission method provided by the provider itself has at least the following beneficial effects: 1. Response latency for critical requests is fundamentally improved. Because the preemption logic is entirely handled by hardware within a single cycle, high-priority read requests no longer need to queue; instead, the entire sending process is triggered immediately upon arrival. In congested scenarios, the system's 99th percentile latency (i.e., the response time of the slowest 1% of requests) can be reduced by more than 40%. This means that CPU cores will no longer be paused for extended periods while waiting for a blocked read request.

[0084] 2. Significantly improved link bandwidth utilization. The fragmentation filling engine 140 transforms the side effects of preemption (i.e., idle slots) into the function of transmitting management information. This allows control packets, such as credit updates and retransmission acknowledgments, which originally required an additional full Flit to send, to "hitch a ride" based on high-priority data requests. This not only avoids adding extra bus overhead but also accelerates the management loop at the link layer, thereby improving the effective throughput of the link.

[0085] 3. QoS in multi-tenant scenarios is now guaranteed at the hardware level. Since preemption is triggered based on transaction semantics (i.e., instruction type) rather than software priority queue scheduling, even if a large amount of background I / O traffic fills the merging window, a high-priority synchronous read request can still interrupt the current process and be sent first. This capability is equivalent to setting up a priority channel for critical computing flows at the physical layer, preventing the spread of I / O congestion to CPU cores and making performance isolation more reliable in multi-virtual machine environments.

[0086] Based on the above implementation, this application also provides a chip that integrates the above-described data transmission device.

[0087] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

[0088] It will be apparent to those skilled in the art that this application is not limited to the details of the exemplary embodiments described above, and that this application can be implemented in other specific forms without departing from the spirit or essential characteristics of this application. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this application is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this application. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A data transmitting apparatus, characterized by comprising: The device includes: The preemption detector is used to monitor incoming transaction layer requests in real time at the transaction layer interface and generate a preemption trigger signal when a high-priority transaction layer request is identified. A timer is used to start the timing and define the merge wait window; A preemption state machine controller, connected to the preemption detector and timer, is used to generate a forced zeroing signal and a fragmentation filling enable signal in response to the preemption trigger signal; wherein, the timer responds to the forced zeroing signal to immediately terminate the current merging waiting window; The fragment filling engine, connected to the preemption state machine controller, link management queue, credit reclamation queue, and adaptive hybrid packer, is used to, upon receiving the fragment filling enable signal, retrieve a corresponding number of non-data control information packets from the link management queue or credit reclamation queue based on the slot occupancy status fed back from the adaptive hybrid packer, and send them to the adaptive hybrid packer. An adaptive hybrid packetizer is used to encapsulate and send the received high-priority transaction layer request and the non-data control information packet together.

2. The data transmission device according to claim 1, characterized in that, The data transmission device further includes a buffer and a non-sequential extraction logic unit, wherein the non-sequential extraction logic unit is connected to the buffer, the preemptive state machine controller and the adaptive hybrid packer, respectively. The preemption state machine controller is also used to generate an extraction enable signal in response to the preemption trigger signal; The non-sequential extraction logic unit is used to retrieve target transaction layer requests that can be merged with the high-priority transaction layer requests from the buffer, and send the high-priority transaction layer requests and the target transaction layer requests to the adaptive hybrid packer.

3. The data transmission device according to claim 2, characterized in that, The data transmission device further includes a multiplexing gating array, which is connected to the non-sequential extraction logic unit, the fragment filling engine, and the adaptive hybrid packer, respectively. The multiplexing gate array is used to selectively send the output of the non-sequential extraction logic unit or the fragment filling engine to the adaptive hybrid packer.

4. The data transmission device according to claim 1, characterized in that, The preemption detector includes: The priority comparison register is used to store preset high-priority opcodes; The instruction code decoder is used to compare the opcode of the input transaction layer request with the opcode stored in the priority comparison register in real time. If they match, the preemption trigger signal is generated.

5. The data transmission device according to claim 1, characterized in that, The preemptive state machine controller is also used to prohibit the start of a timer or control the start of a temporary waiting window after a forced reset signal is generated; wherein the duration of the temporary waiting window is less than the duration of the merged waiting window.

6. The data transmission device according to claim 1, characterized in that, The preemption state machine controller is also used to dynamically configure the duration of the merging waiting window based on the real-time credit score value of the link layer when no preemption trigger signal is received; wherein the duration of the merging waiting window is negatively correlated with the real-time credit score value.

7. The data transmission device according to claim 1, characterized in that, The adaptive hybrid packetizer includes a dynamic identifier generation circuit, which generates identifier information corresponding to each data slot of the data packet; the identifier information includes data information and control fragments.

8. The data transmission device according to claim 1, characterized in that, The priority order for the fragment filling engine to capture the non-data control information packets is as follows: link layer retransmission acknowledgment packets are higher than credit update packets, and credit update packets are higher than the idle symbols defined by the protocol.

9. A data transmission method, characterized in that, Applied to the data transmission apparatus as described in any one of claims 1 to 8, the method comprises: The timer starts timing and defines the merge wait window; The preemption detector monitors incoming transaction layer requests in real time at the transaction layer interface and generates a preemption trigger signal when it identifies a high-priority transaction layer request. The preemption state machine controller responds to the preemption trigger signal by generating a forced zeroing signal and a fragmentation filling enable signal; wherein, the timer responds to the forced zeroing signal to immediately terminate the current merge waiting window; After receiving the fragment filling enable signal, the fragment filling engine retrieves a corresponding number of non-data control information packets from the link management queue or credit reclamation queue based on the slot occupancy status fed back from the adaptive hybrid packer, and sends them to the adaptive hybrid packer. The adaptive hybrid packetizer encapsulates the received high-priority transaction layer request and the non-data control information packet together and then sends them.

10. A chip, characterized in that, The chip integrates a data transmission device as described in any one of claims 1-8.

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