A MCU critical voltage lock fault cause diagnosis method and system

Abstract

This application relates to the field of MCU fault diagnosis technology, and provides a method and system for diagnosing the causes of MCU lock-up faults under critical voltage, to improve the accuracy of diagnosing lock-up fault causes. The method includes: acquiring the time difference between the MCU under test (MCU) power-on and reaching the critical voltage; randomly generating a power-off sequence based on the time difference; starting the Flash software encryption mode; cutting off the power supply circuit of the MCU under test based on the power-off sequence; executing a first power-off cycle and a second power-off cycle; switching the Flash software encryption mode to the programmer hardware encryption mode; re-executing the second power-off cycle a second preset number of times in the programmer hardware encryption mode; calculating the probability of a first fault occurrence in the Flash software encryption mode and the probability of a second fault occurrence in the programmer hardware encryption mode; and determining the cause of the MCU lock-up fault based on the comparison between the first and second fault occurrence probabilities.

Description

Technical Field

[0001] This application belongs to the field of MCU fault diagnosis technology, and in particular relates to a method and system for diagnosing the causes of MCU lock-up faults under critical voltage. Background Technology

[0002] A microcontroller unit (MCU) is a chip-level computer that reduces the frequency and specifications of a central processing unit and integrates peripheral interfaces such as memory and counters onto a single chip. It is widely used in industrial control, smart terminals, and the Internet of Things.

[0003] In actual MCU operation scenarios, voltage fluctuations can easily cause a momentary drop in the supply voltage during power-up. When the MCU's core supply voltage drops to the critical voltage range, the MCU's chip core operating state becomes extremely unstable. If Flash read / write and software encryption access protection operations are performed simultaneously at this time, it will cause abnormal erasure and writing of data in the Flash memory unit, leading to MCU lock-up faults such as communication loss, program loss, or memory corruption.

[0004] Currently, a common method is to cyclically test power-off processes at fixed time intervals, and perform Flash read / write stress tests during these cycles to diagnose the causes of lock-up faults by reproducing them. However, when conducting power-off tests at fixed time intervals, the voltage drop conditions are limited and cannot accurately simulate the transient power supply fluctuations that are common in real-world fault scenarios. This results in an insufficient reproducibility rate for intermittent, latent lock-up faults, making it difficult to accurately pinpoint the root cause of the fault and consequently affecting the accuracy of lock-up fault diagnosis. Summary of the Invention

[0005] This application provides a method and system for diagnosing the causes of MCU lock-up faults under critical voltage, which can improve the accuracy of diagnosing the causes of lock-up faults.

[0006] The first aspect of this application provides a method for diagnosing the causes of MCU lock-up faults under critical voltage, including: When the MCU under test performs a power-on operation, the time difference from the MCU under test starting up to reaching the critical voltage is obtained, the time difference is determined as the reference power-off duration, and the power-off duration interval is set according to the reference power-off duration to randomly generate a power-off sequence based on the power-off duration interval. The Flash software encryption mode is activated, and the power supply circuit of the MCU under test is cut off based on the power-off timing sequence. After waiting for a preset time, the power supply is restored to complete a single first power-off cycle. After completing the first preset number of first power-off cycles, a power-on operation without cutting off is performed, and the MCU under test is checked for a lock-up fault to complete a single second power-off cycle. After completing the second power-off cycle for the second preset number of times, the Flash software encryption mode is switched to the programmer hardware encryption mode, and the second power-off cycle for the second preset number of times is re-executed in the programmer hardware encryption mode. The first probability of failure is obtained by calculating the ratio of the number of times a lock-up failure occurs in the Flash software encryption mode to the second preset number; and the second probability of failure is obtained by calculating the ratio of the number of times a lock-up failure occurs in the programmer hardware encryption mode to the second preset number. The cause of the lock-up fault of the MCU under test is determined by comparing the probability of the first fault occurrence with the probability of the second fault occurrence.

[0007] Optionally, determining the cause of the lockup fault of the MCU under test based on the comparison between the first fault occurrence probability and the second fault occurrence probability includes: Compare the probability of the first fault occurrence with the probability of the second fault occurrence; When the probability of the first fault occurrence is greater than the probability of the second fault occurrence, the cause of the lock-up fault of the MCU under test is determined to be the simultaneous execution of Flash software encryption operation while the voltage fluctuates. When the probability of the first fault occurrence is less than or equal to the probability of the second fault occurrence, the cause of the lock-up fault of the MCU under test is determined to be voltage fluctuation.

[0008] Optionally, the step of setting a power outage duration interval based on the reference power outage duration, and randomly generating a power outage sequence based on the power outage duration interval, includes: The sum of the baseline power outage duration and the preset fluctuation value is determined as the upper limit duration, and the difference between the baseline power outage duration and the preset fluctuation value is determined as the lower limit duration. A power outage duration interval is generated with the upper limit duration and the lower limit duration as the boundary. Several different power outage duration values ​​are randomly obtained within the power outage duration interval, and a power outage sequence is generated based on the several different power outage duration values.

[0009] Optionally, the step of cutting off the power supply circuit of the MCU under test based on the power-off timing includes: Send a cut-off command based on the power-off sequence to the DO control unit to instruct the DO control unit to cut off the power supply circuit of the MCU under test according to the power-off sequence.

[0010] Optionally, obtaining the time difference between the MCU under test powering on and reaching the critical voltage includes: The voltage waveform signal of the MCU under test during power-on operation was acquired using an oscilloscope. Based on the voltage waveform signal, obtain the first current time of the MCU under test when it is powered on and the second current time when the power supply voltage of the MCU under test changes to the critical voltage. Calculate the difference between the second current time and the first current time to obtain the time difference from power-on startup of the MCU under test to reaching the critical voltage.

[0011] Optionally, before determining the cause of the lockup fault of the MCU under test based on the comparison between the first fault occurrence probability and the second fault occurrence probability, the method further includes: Determine whether the probability of the first fault occurring or the probability of the second fault occurring is greater than a preset probability; If so, the step of cutting off the power supply circuit of the MCU under test based on the power-off timing is executed synchronously during the bus operation of the EtherCAT master station, wherein the EtherCAT master station is communicatively connected to the MCU under test. The second power-off loop in the Flash software encryption mode is re-executed. After completing the second preset number of times, the ratio of the number of times a lock-up fault occurs to the second preset number of times is recalculated to obtain a third fault occurrence probability. The second power-off loop in the programmer hardware encryption mode is re-executed. After completing the second preset number of times, the ratio of the number of times a lock-up fault occurs to the second preset number of times is recalculated to obtain a fourth fault occurrence probability. The step of determining the cause of the lock-up fault of the MCU under test based on the comparison between the probability of the first fault occurrence and the probability of the second fault occurrence includes: The first target failure probability is obtained by weighted summing the first failure probability and the third failure probability; and the second target failure probability is obtained by weighted summing the second failure probability and the fourth failure probability. The cause of the lock-up fault of the MCU under test is determined based on the comparison between the first target fault probability and the second target fault probability.

[0012] The second aspect of this application provides a system for diagnosing the causes of MCU lock-up faults under critical voltage, including: The acquisition unit is used to acquire the time difference from the start-up of the MCU under test to the reaching of the critical voltage when the MCU under test performs a power-on operation, and to determine the power-off sequence based on the time difference; The first cycle test unit is used to start the Flash software encryption mode, cut off the power supply circuit of the MCU under test based on the power-off timing, and restore the power supply after waiting for a preset time to complete a single first power-off cycle; after completing the first preset number of first power-off cycles, a non-disconnect power-on operation is performed, and the MCU under test is checked for a lock-up fault to complete a single second power-off cycle. The second cycle test unit is used to switch the Flash software encryption mode to the programmer hardware encryption mode after completing the second power-off cycle for the second preset number of times, and to re-execute the second power-off cycle for the second preset number of times in the programmer hardware encryption mode. The calculation unit is used to calculate the ratio of the number of times a lock-up failure occurs in the Flash software encryption mode to the second preset number of times to obtain a first failure probability; and to calculate the ratio of the number of times a lock-up failure occurs in the programmer hardware encryption mode to the second preset number of times to obtain a second failure probability. The determining unit is used to determine the cause of the lock-up fault of the MCU under test based on the comparison result of the first fault occurrence probability and the second fault occurrence probability.

[0013] Optionally, the determining unit is specifically used for: Compare the probability of the first fault occurrence with the probability of the second fault occurrence; When the probability of the first fault occurrence is greater than the probability of the second fault occurrence, the cause of the lock-up fault of the MCU under test is determined to be the simultaneous execution of Flash software encryption operation while the voltage fluctuates. When the probability of the first fault occurrence is less than or equal to the probability of the second fault occurrence, the cause of the lock-up fault of the MCU under test is determined to be voltage fluctuation.

[0014] A third aspect of this application provides an electronic device, comprising: Processor, memory, input / output units, and bus; The processor is connected to the memory, the input / output unit, and the bus; The memory stores a program, which the processor calls to execute a method for diagnosing the cause of a lock-up fault under the critical voltage of an MCU, as described in the first aspect and any optional method in the first aspect.

[0015] A fourth aspect of this application provides a computer-readable storage medium comprising: instructions that, when executed on a computer, cause the computer to perform a method for diagnosing lock-up fault causes under a critical voltage of an MCU, as described in the first aspect and any optional method in the first aspect.

[0016] As can be seen from the above technical solutions, this application has the following effects: By using the time difference between MCU power-on and critical voltage as the baseline for power-off duration, the high-incidence power-off duration range near the critical voltage is accurately calibrated. Power-off sequences are then randomly generated based on this range to simulate fault scenarios caused by transient power supply disturbances under different operating conditions. Simultaneously, a complete, non-disconnected power-on verification process is interspersed after completing the first preset number of power-off cycles to effectively capture intermittent lock-up faults under critical voltage. Furthermore, a dual-dimensional comparative test system is constructed, using Flash software encryption mode and programmer hardware encryption mode. Two sets of power-off cycles are compared under the same power-off sequence and the same number of test cycles. By calculating the probability of the first fault occurrence corresponding to the Flash software encryption mode and the probability of the second fault occurrence corresponding to the programmer hardware encryption mode, the impact of software and hardware encryption operations on lock-up faults is quantified. This allows for precise localization of lock-up fault causes based on the comparison of the two sets of first and second fault occurrence probabilities, thereby improving the diagnostic accuracy of lock-up fault causes. Attached Figure Description

[0017] Figure 1 This is a flowchart illustrating a method for diagnosing the causes of MCU lock-up faults under critical voltage, as described in this application. Figure 2 This is a schematic diagram of the structure of a MCU lock-up fault cause diagnosis system under critical voltage according to this application; Figure 3 This is a schematic diagram of the structure of an electronic device according to this application. Detailed Implementation

[0018] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0019] It should be understood that, when used in this application specification, the term "comprising" indicates the presence of the described feature, integral, step, operation, element, and / or component, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or collections thereof.

[0020] It should also be understood that the term “and / or” as used in this application specification means any combination of one or more of the associated listed items, as well as all possible combinations, and includes such combinations.

[0021] As used in this application specification, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if [the described condition or event] is detected" may be interpreted, depending on the context, as "once determined," "in response to determination," "once [the described condition or event] is detected," or "in response to detection of [the described condition or event]."

[0022] Furthermore, in the description of this application, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0023] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0024] In actual MCU operation scenarios, power-on is prone to momentary power supply drops due to voltage fluctuations. When the MCU's core power supply voltage drops to the critical voltage range, the MCU's chip core operating state becomes unstable. If Flash read / write and software encryption access protection operations are performed simultaneously at this time, it will cause abnormal erasure and writing of data in the Flash memory unit, resulting in MCU lock-up faults such as communication loss, program loss, or memory damage.

[0025] Currently, a fixed time interval is typically used to cyclically test the power-off process, and Flash read / write stress tests are performed during these cyclic power-off tests to diagnose the causes of lock-up faults by reproducing them. However, when power-off tests are conducted at fixed time intervals, the voltage drop conditions are limited and cannot accurately simulate the transient power supply fluctuations that are common in real-world fault scenarios. This results in a failure to meet testing requirements for the reproducibility of latent lock-up faults, making it difficult to accurately pinpoint the root cause of the fault, and consequently affecting the accuracy of lock-up fault diagnosis.

[0026] To address the aforementioned issues, this application provides a method and system for diagnosing the causes of MCU lock-up faults under critical voltage, thereby improving the accuracy of diagnosing lock-up fault causes.

[0027] Please see Figure 1 A method for diagnosing the cause of MCU lockup faults under critical voltage in an embodiment of this application includes: 101. When the MCU under test performs a power-on operation, obtain the time difference from the MCU under test from power-on to reaching the critical voltage, determine the time difference as the reference power-off duration, and set the power-off duration range according to the reference power-off duration to randomly generate the power-off sequence based on the power-off duration range.

[0028] The MCU under test is electrically connected to the power supply, which supplies power to the MCU. The power supply can be a 24V DC power supply.

[0029] The critical voltage refers to the key threshold voltage during the power-on startup process of the MCU under test (MCU), serving as a state transition node for program loading and hardware register initialization. If the voltage falls below this critical voltage, the MCU under test may fail to start normally. When the supply voltage of the MCU under test fluctuates around this critical voltage, it can easily lead to a lock-up fault.

[0030] Specifically, when the MCU under test needs to be powered on, a 24V DC power supply is activated to turn on the power supply circuit of the MCU under test. At this time, the power supply voltage of the MCU under test gradually increases from 0V until it reaches the rated operating voltage. In this embodiment, the rated operating voltage of the MCU under test can be set to 3.3V, and the critical voltage can be set to 2.6V.

[0031] During the power-on startup of the MCU under test (MCU), the time taken for the MCU's supply voltage to rise from the instant of power-on (0V) to the critical voltage (2.6V) is recorded. This time is the time difference from power-on to reaching the critical voltage. This time difference is determined as the reference power-off duration, which indicates the reference timing for cutting off the MCU's power supply circuit when the critical voltage is reached. It is understandable that, to reduce the randomness of a single test, the MCU under test can be powered on multiple times. During each power-on startup, the time difference from power-on to reaching the critical voltage is recorded, and the average of all time differences is calculated. This average value is then used as the reference power-off duration.

[0032] Specifically, the baseline power outage duration is used as the center value, and a power outage duration interval is set within a certain fluctuation range. Within the power outage duration interval, a power outage sequence consisting of multiple power outage durations is generated by random sampling.

[0033] In some embodiments, obtaining the time difference from power-on startup of the MCU under test to reaching a critical voltage includes: The voltage waveform signal of the MCU under test during the power-on operation is acquired using an oscilloscope; Based on the voltage waveform signal, obtain the first current time when the MCU under test is powered on and the second current time when the power supply voltage of the MCU under test changes to the critical voltage. Calculate the difference between the second current time and the first current time to obtain the time difference from power-on startup of the MCU under test to reaching the critical voltage.

[0034] The oscilloscope probe is connected in parallel to the core power supply pin of the MCU under test, so as to continuously acquire the complete voltage waveform signal of the MCU under test as the voltage rises from 0V to the rated operating voltage during the power-on process.

[0035] In this embodiment, the oscilloscope can be a general-purpose digital storage oscilloscope, a mixed-signal oscilloscope, or a digital phosphor oscilloscope; no specific limitation is made here. The core power supply of the MCU under test refers to the core low-voltage power supply inside the chip, which is used to power internal core components such as registers, buses, and logic units, as well as peripheral components such as serial ports, timers, and peripheral models. Its rated output voltage can be set to 3.3V.

[0036] Specifically, the voltage waveform signal acquired by the oscilloscope is read, and the starting point of the voltage abruptly rising from 0V is located. The corresponding system time is recorded as the first current time. The point at which the voltage waveform stabilizes and reaches the critical voltage (2.6V) is located, and the corresponding system time is recorded as the second current time. The difference between the second current time and the first current time is calculated, and this difference is determined as the time difference from power-on startup of the MCU under test to reaching the critical voltage. By acquiring the voltage waveform signal using an oscilloscope, microsecond-level voltage changes can be accurately captured, eliminating sampling errors and improving the calculation accuracy of the time difference from power-on startup of the MCU under test to reaching the critical voltage.

[0037] In some embodiments, a power outage duration interval is set according to a reference power outage duration, and a power outage sequence is randomly generated based on the power outage duration interval, including: The upper limit duration is determined by the sum of the baseline power outage duration and the preset fluctuation value, and the lower limit duration is determined by the difference between the baseline power outage duration and the preset fluctuation value. A power outage duration range is generated with the upper limit duration and the lower limit duration as the boundaries. Several different power outage duration values ​​are randomly obtained within the power outage duration range, and a power outage sequence is generated based on these different power outage duration values.

[0038] The preset fluctuation value can be determined based on the voltage fluctuation amplitude of the MCU under test in actual working conditions. For example, the preset fluctuation value can be set to 10% of the reference power-off time. The specific value is not limited here.

[0039] Specifically, the sum of the baseline power outage duration and the preset fluctuation value is used as the upper limit duration, and the difference between the baseline power outage duration and the preset fluctuation value is used as the lower limit duration. A power outage duration range is established using the baseline power outage duration as the median, the upper limit duration as the maximum value, and the lower limit duration as the minimum value. For example, if the baseline power outage duration is 10ms, the preset fluctuation value is 1ms, the upper limit duration is 10+1=11ms, and the lower limit duration is 10-1=9ms, then the power outage duration range is [9ms, 11ms].

[0040] Specifically, first, the number of random samples is set, and then the power outage duration values ​​of the set number of samples are randomly selected within the power outage duration range. For example, if the maximum number of samples is set to 5, the RAND random number command is executed to randomly select 5 power outage duration values ​​of 9.1ms, 9.5ms, 10.1ms, 10.2ms, and 10.6ms within the power outage duration range [9ms, 11ms]. Finally, all the power outage duration values ​​are randomly sorted and combined to generate the power outage sequence.

[0041] 102. Start the Flash software encryption mode, cut off the power supply circuit of the MCU under test based on the power-off sequence, and restore the power supply after waiting for a preset time to complete the first power-off cycle. After completing the first preset number of first power-off cycles, perform a power-on operation without cutting off and check whether the MCU under test has a lock-up fault to complete the second power-off cycle.

[0042] The Flash software encryption mode is a working mode in which the MCU under test (MCU) core performs encryption and verification of the Flash-stored program through a built-in program algorithm. In Flash software encryption mode, the Flash program encryption operation runs synchronously during the MCU's power-on startup process. At this time, the MCU core operates under high load, and hardware resource margins are reduced. If a random power-off disturbance occurs within the critical voltage range at this time, it can easily lead to lock-up faults such as program freezes, abnormal register refreshes, and bus communication interruptions. Therefore, performing power-off cycle tests in Flash software encryption mode can improve the reproducibility of lock-up faults and provide a basis for diagnosing the causes of subsequent lock-up faults.

[0043] Specifically, the power-off sequence contains multiple randomly ordered power-off duration values, which are the time difference from the moment the MCU under test is powered on to the moment the power supply circuit of the MCU under test is cut off.

[0044] Specifically, the first power-off cycle is as follows: First, select the first power-off duration value in sequence from the power-off timing sequence; then, start timing from the moment the MCU under test powers on and starts up. After the first power-off duration value has elapsed, cut off the power supply circuit of the MCU under test; after cutting off the power supply circuit of the MCU under test, wait for a preset time, and then restore the power supply to the MCU under test; next, select the second power-off duration value in sequence from the power-off timing sequence, start timing from the moment the MCU under test restores power, and after the second power-off duration value has elapsed, cut off the power supply circuit of the MCU under test, and so on, repeating this cycle.

[0045] Specifically, the second power-down cycle works as follows: After completing the first preset number of power-down cycles, the power supply circuit of the MCU under test is restored. This restoration is a normal power-on process, meaning that no power-off operation is performed while the MCU's power supply voltage rises to its rated operating voltage. When the MCU reaches its rated operating voltage, it is checked whether a lock-up fault has occurred. After the check is completed, the first power-down cycle is executed again, and this cycle is repeated. When the MCU reaches its rated operating voltage, whether a lock-up fault has occurred can be determined by checking whether the MCU's bus communication function is normal and whether the Flash memory data is complete.

[0046] In some embodiments, the power supply circuit of the MCU under test is cut off based on the power-off timing sequence, including: Send a cut-off command based on the power-off sequence to the DO control unit to instruct the DO control unit to cut off the power supply circuit of the MCU under test according to the power-off sequence.

[0047] The DO (Digital Output) control unit is a high-precision digital execution output interface used to convert the 0 / 1 signals of the controller's internal logic into on / off levels usable by external devices.

[0048] Specifically, the disconnect command can include a delay command generated based on the power-off duration value in the power-off sequence and a disconnect command generated from the disconnect logic state, instructing the DO control unit to disconnect the power supply circuit of the MCU under test after a delay of the specified power-off duration. It can be understood that after completing the power supply to the MCU under test, a recovery command based on a preset duration can be sent to the DO control unit, instructing the DO control unit to turn on the power supply circuit of the MCU under test after a preset delay. The DO control unit has microsecond-level power on / off response capability, which has a faster response speed than traditional mechanical relays, thereby improving the success rate of critical voltage power-off capture and further improving the reproducibility rate of lockup faults under critical voltage.

[0049] 103. After completing the second power-off cycle for the second preset number of times, switch the Flash software encryption mode to the programmer hardware encryption mode, and re-execute the second power-off cycle for the second preset number of times in the programmer hardware encryption mode.

[0050] The programmer hardware encryption mode is a working mode in which the Flash encryption verification is independently completed by a dedicated external programmer hardware chip. The entire encryption operation is carried out by the external hardware, without occupying the core computing resources of the MCU under test. During the power-on startup process of the MCU under test, only the basic startup program is executed, without any additional software load. The programmer hardware encryption mode is equivalent to the reference group of the Flash software encryption mode. In the programmer hardware encryption mode, the MCU under test has no Flash software encryption operation load, and the test process only retains the single variable of "critical voltage fluctuation". By replicating the same power-off test process as the Flash software encryption mode, a single-variable comparative test system is constructed to provide comparative data for distinguishing the causes, so as to determine whether Flash software encryption is an influencing factor of the lock-up fault under the critical voltage.

[0051] Specifically, in Flash software encryption mode, a second power-off cycle needs to be completed a second preset number of times. For example, if the first preset number is 50 cycles and the second preset number is 100 cycles, after completing 50 first power-off cycles, a normal power-on process without interruption is executed to check for a lock-up fault, and the detection result is used as the lock-up fault detection result for this round of the second power-off cycle. After completing 100 second power-off cycles, the Flash software encryption mode is switched to the programmer hardware encryption mode. In programmer hardware encryption mode, the second power-off cycle is also executed 100 times. It should be noted that the second power-off cycle and the first power-off cycle in Flash software encryption mode are the same as those in programmer hardware encryption mode in terms of the cycle process and cycle timing.

[0052] In another possible implementation, the programmer hardware encryption mode can be executed first. After the second power-off cycle in the programmer hardware encryption mode completes the second preset number of cycles, the program can then switch to the Flash software encryption mode. This embodiment does not limit the specific execution order of the Flash software encryption mode and the programmer hardware encryption mode.

[0053] 104. Calculate the ratio of the number of times a lockout failure occurs in Flash software encryption mode to the second preset number of times to obtain the probability of the first failure; and calculate the ratio of the number of times a lockout failure occurs in programmer hardware encryption mode to the second preset number of times to obtain the probability of the second failure.

[0054] Specifically, since a lockout fault detection is performed in the second power-off cycle of each round, the probability of fault occurrence under different encryption modes can be determined by calculating the ratio of the number of lockout fault occurrences to the second preset number. This transforms the qualitative lockout fault phenomenon into quantitative probability data, intuitively quantifying the triggering capability of fault causes under different operating conditions. The higher the fault occurrence probability value, the greater the impact of the corresponding cause on the lockout fault of the MCU under test.

[0055] 105. Determine the cause of the MCU lock-up fault based on the comparison between the probability of the first fault and the probability of the second fault.

[0056] Specifically, the first probability of occurrence is used to represent the influence of the dual variables of voltage fluctuation and Flash software encryption operation on the MCU under test's lock-up failure; the second probability of occurrence is used to represent the influence of the single variable of voltage fluctuation on the MCU under test's lock-up failure. Therefore, by comparing the first and second probabilities of occurrence, the specific cause of the MCU under test's lock-up failure can be determined.

[0057] In some embodiments, determining the cause of the lock-up fault of the MCU under test based on a comparison between the probability of a first fault occurrence and the probability of a second fault occurrence includes: Compare the probability of the first failure to the probability of the second failure. When the probability of the first fault is greater than the probability of the second fault, the cause of the lock-up fault of the MCU under test is determined to be the simultaneous execution of Flash software encryption operation while the voltage fluctuates. When the probability of the first fault is less than or equal to the probability of the second fault, the cause of the lock-up fault of the MCU under test is determined to be voltage fluctuation.

[0058] Specifically, the Flash software encryption mode includes a dual trigger of "voltage fluctuation + Flash software encryption operation," while the programmer hardware encryption mode only includes a single trigger of "voltage fluctuation." If the probability of the first fault occurring is greater than the probability of the second fault occurring, it indicates that the Flash software encryption operation has a greater impact on the lock-up fault. In this case, the combined effect of voltage fluctuation and Flash software encryption operation can be determined as the trigger for the lock-up fault of the MCU under test. Conversely, if the probability of the first fault occurring is less than or equal to the probability of the second fault occurring, it indicates that the Flash software encryption operation has a smaller impact on the lock-up fault, and voltage fluctuation alone can independently trigger the lock-up fault. In this case, voltage fluctuation can be determined as the trigger for the lock-up fault of the MCU under test. Based on this, precise source tracing can be achieved through quantitative comparison of fault occurrence probabilities, thus solving the problem that traditional lock-up fault diagnosis cannot distinguish between a single voltage fluctuation trigger and a combined trigger of voltage fluctuation and Flash software encryption operation.

[0059] In some embodiments, before determining the cause of the MCU lockup fault based on the comparison between the first fault occurrence probability and the second fault occurrence probability, the MCU lockup fault cause diagnosis method under the critical voltage in this application embodiment further includes: Determine whether the probability of the first fault or the probability of the second fault occurring is greater than a preset probability; If so, the step of cutting off the power supply circuit of the MCU under test based on the power-off timing is executed synchronously during the bus operation of the EtherCAT master station, wherein the EtherCAT master station and the MCU under test are in communication connection. The second power-off loop in Flash software encryption mode is re-executed. After completing the second preset number of times, the ratio of the number of times the lock-up fault occurred to the second preset number of times is recalculated to obtain the third fault occurrence probability. The second power-off loop in programmer hardware encryption mode is re-executed. After completing the second preset number of times, the ratio of the number of times the lock-up fault occurred to the second preset number of times is recalculated to obtain the fourth fault occurrence probability. Based on the comparison between the probability of the first fault occurrence and the probability of the second fault occurrence, the causes of the MCU under test locking up are determined to include: The first target failure probability is obtained by weighted summing the first failure probability and the third failure probability; and the second target failure probability is obtained by weighted summing the second failure probability and the fourth failure probability. The cause of the lock-up fault in the MCU under test is determined by comparing the first target fault probability with the second target fault probability.

[0060] EtherCAT (Ethernet for Control Automation Technology) is an open architecture fieldbus system based on Ethernet.

[0061] In the EtherCAT industrial real-time Ethernet bus system, the EtherCAT master station is the core control node that initiates communication, manages the entire bus cycle, issues output commands, and collects feedback data from slave stations. It serves as the scheduling and data processing center for the entire EtherCAT network. EtherCAT adopts a master-slave architecture. When the master station sends a complete data frame, the message serially passes through all slave stations. Each slave station reads and writes its corresponding data segment locally at the hardware level, without buffering the complete message, and directly forwards it to the next device. After the message has passed through all slave stations, it returns to the master station along the same path.

[0062] Specifically, in this embodiment, the EtherCAT master station establishes a communication connection with the MCU under test to simulate the load-bearing conditions of industrial fieldbus data interaction and device linkage. Steps 101 to 104 described above constitute the power-off test process under no-load conditions. During bus operation, steps 101 to 104 are re-executed to calculate the probability of the third and fourth faults corresponding to the Flash software encryption mode and the programmer hardware encryption mode under load conditions. Different weighting coefficients are assigned to the first and second fault probabilities under no-load conditions, and the third and fourth fault probabilities under load conditions. These weighting coefficients can be set based on historical experience.

[0063] The probabilities of the first and third faults are multiplied by their respective weighting coefficients, and then the products are summed to obtain the first target fault probability under the Flash software encryption mode, which integrates no-load and load conditions. Similarly, the probabilities of the second and fourth faults are multiplied by their respective weighting coefficients, and then the products are summed to obtain the second target fault probability under the programmer hardware encryption mode, which integrates no-load and load conditions. Finally, the first and second target fault probabilities are compared to determine the cause of the MCU lockup fault under test. Based on this, by fusing the load condition and no-load condition of simulated industrial fieldbus data interaction and device linkage, the deviation between no-load testing and actual industrial load conditions can be eliminated, comprehensively improving the reliability of the lockup fault cause diagnosis results.

[0064] Please see Figure 2 As shown, the MCU lockup fault cause diagnosis system under the critical voltage in this embodiment includes: The acquisition unit 201 is used to acquire the time difference from the start-up of the MCU under test to the reaching of the critical voltage when the MCU under test performs a power-on operation, and determine the power-off sequence based on the time difference; The first cycle test unit 202 is used to start the Flash software encryption mode, cut off the power supply circuit of the MCU under test based on the power-off timing sequence, and restore the power supply after waiting for a preset time to complete a single first power-off cycle; after completing the first preset number of first power-off cycles, it performs a power-on operation without cutting off and detects whether the MCU under test has a lock-up fault to complete a single second power-off cycle. The second cycle test unit 203 is used to switch the Flash software encryption mode to the programmer hardware encryption mode after completing the second power-off cycle for the second preset number of times, and re-execute the second power-off cycle for the second preset number of times in the programmer hardware encryption mode. The calculation unit 204 is used to calculate the ratio of the number of times a lock-up failure occurs in Flash software encryption mode to a second preset number of times to obtain the first failure probability; and to calculate the ratio of the number of times a lock-up failure occurs in programmer hardware encryption mode to a second preset number of times to obtain the second failure probability. The determination unit 205 is used to determine the cause of the lock-up fault of the MCU under test based on the comparison result of the first fault occurrence probability and the second fault occurrence probability.

[0065] In this embodiment, when the MCU under test performs a power-on operation, the acquisition unit 201 acquires the time difference between the MCU under test starting from power-on and reaching the critical voltage, and determines the power-off sequence based on the time difference; the first cycle test unit 202 starts the Flash software encryption mode, cuts off the power supply circuit of the MCU under test based on the power-off sequence, and restores power supply after waiting for a preset time to complete a single first power-off cycle; after completing a first preset number of first power-off cycles, a non-disconnect power-on operation is performed, and it is detected whether the MCU under test has a lock-up fault to complete a single second power-off cycle; after completing a second preset number of second power-off cycles, the first... The two-cycle test unit 203 switches the Flash software encryption mode to the programmer hardware encryption mode, and re-executes the second power-off cycle a second preset number of times in the programmer hardware encryption mode; the calculation unit 204 calculates the ratio of the number of times the lock-up fault occurs in the Flash software encryption mode to the second preset number of times to obtain the first fault occurrence probability; and calculates the ratio of the number of times the lock-up fault occurs in the programmer hardware encryption mode to the second preset number of times to obtain the second fault occurrence probability; the determination unit 205 determines the lock-up fault cause of the MCU under test based on the comparison result of the first fault occurrence probability and the second fault occurrence probability.

[0066] Based on this, the power-off duration can be precisely calibrated near the critical voltage by using the time difference between MCU power-on and critical voltage as the benchmark power-off duration. Power-off timing sequences can then be randomly generated based on these sequences to simulate fault scenarios caused by transient power supply disturbances under different operating conditions. Simultaneously, by interspersing a complete, non-disconnected power-on verification process after completing the first preset number of power-off cycles, occasional lock-up faults under critical voltage can be effectively captured. Furthermore, a dual-dimensional comparative test system is constructed, using Flash software encryption mode and programmer hardware encryption mode. Two sets of power-off cycles are compared under the same power-off timing sequence and the same number of test cycles. By calculating the probability of the first fault occurrence corresponding to the Flash software encryption mode and the probability of the second fault occurrence corresponding to the programmer hardware encryption mode, the impact of software and hardware encryption operations on lock-up faults can be quantified. This allows for precise localization of the lock-up fault cause based on the comparison of the two sets of first and second fault occurrence probabilities, thereby improving the diagnostic accuracy of lock-up fault causes.

[0067] Please see Figure 3 As shown, the electronic device in this application embodiment includes: Processor 301, memory 302, input / output unit 303, and bus 304; The processor 301 is connected to the memory 302, the input / output unit 303, and the bus 304; The memory 302 stores a program, and the processor 301 calls the program to execute the MCU lock-up fault cause diagnosis method under the critical voltage in any of the aforementioned optional embodiments.

[0068] This application also provides a computer-readable storage medium, including: instructions that, when executed on a computer, cause the computer to perform the MCU lock-up fault cause diagnosis method under any of the foregoing optional embodiments.

[0069] In the description of this specification, the references to terms such as "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0070] Furthermore, the above are merely preferred embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A method for diagnosing the causes of MCU lockup faults under critical voltage, characterized in that, include: When the MCU under test performs a power-on operation, the time difference from the MCU under test starting up to reaching the critical voltage is obtained, the time difference is determined as the reference power-off duration, and the power-off duration interval is set according to the reference power-off duration to randomly generate a power-off sequence based on the power-off duration interval. The Flash software encryption mode is activated, and the power supply circuit of the MCU under test is cut off based on the power failure timing. After waiting for a preset time, the power supply is restored to complete the first power failure cycle. After completing the first preset number of power-off cycles, a non-disconnection power-on operation is performed, and the MCU under test is checked for a lock-up fault to complete a single second power-off cycle. After completing the second power-off cycle for the second preset number of times, the Flash software encryption mode is switched to the programmer hardware encryption mode, and the second power-off cycle for the second preset number of times is re-executed in the programmer hardware encryption mode. The probability of the first failure is obtained by calculating the ratio of the number of times a lockout failure occurs in the Flash software encryption mode to the second preset number of times. And calculate the ratio of the number of times a lockout failure occurs in the programmer hardware encryption mode to the second preset number of times to obtain the probability of the second failure occurring; The cause of the lock-up fault of the MCU under test is determined by comparing the probability of the first fault occurrence with the probability of the second fault occurrence.

2. The method for diagnosing the causes of MCU lockup faults under critical voltage according to claim 1, characterized in that, The step of determining the cause of the lockup fault of the MCU under test based on the comparison between the first fault occurrence probability and the second fault occurrence probability includes: Compare the probability of the first fault occurrence with the probability of the second fault occurrence; When the probability of the first fault occurrence is greater than the probability of the second fault occurrence, the cause of the lock-up fault of the MCU under test is determined to be the simultaneous execution of Flash software encryption operation while the voltage fluctuates. When the probability of the first fault occurrence is less than or equal to the probability of the second fault occurrence, the cause of the lock-up fault of the MCU under test is determined to be voltage fluctuation.

3. The method for diagnosing the causes of MCU lockup faults under critical voltage according to claim 1, characterized in that, The step of setting a power outage duration interval based on the reference power outage duration, and randomly generating a power outage sequence based on the power outage duration interval, includes: The sum of the baseline power outage duration and the preset fluctuation value is determined as the upper limit duration, and the difference between the baseline power outage duration and the preset fluctuation value is determined as the lower limit duration. A power outage duration interval is generated with the upper limit duration and the lower limit duration as the boundary. Several different power outage duration values ​​are randomly obtained within the power outage duration interval, and a power outage sequence is generated based on the several different power outage duration values.

4. The method for diagnosing the causes of MCU lockup faults under critical voltage according to claim 1, characterized in that, The step of cutting off the power supply circuit of the MCU under test based on the power-off timing includes: Send a cut-off command based on the power-off sequence to the DO control unit to instruct the DO control unit to cut off the power supply circuit of the MCU under test according to the power-off sequence.

5. The method for diagnosing the causes of MCU lockup faults under critical voltage according to claim 1, characterized in that, The step of obtaining the time difference from power-on startup of the MCU under test to reaching the critical voltage includes: The voltage waveform signal of the MCU under test during power-on operation was acquired using an oscilloscope. Based on the voltage waveform signal, obtain the first current time of the MCU under test when it is powered on and the second current time when the power supply voltage of the MCU under test changes to the critical voltage. Calculate the difference between the second current time and the first current time to obtain the time difference from power-on startup of the MCU under test to reaching the critical voltage.

6. The method for diagnosing the causes of MCU lockup faults under critical voltage according to claim 1, characterized in that, Before determining the cause of the lockup fault of the MCU under test based on the comparison between the first fault occurrence probability and the second fault occurrence probability, the method further includes: Determine whether the probability of the first fault occurring or the probability of the second fault occurring is greater than a preset probability; If so, the step of cutting off the power supply circuit of the MCU under test based on the power-off timing is executed synchronously during the bus operation of the EtherCAT master station, wherein the EtherCAT master station is communicatively connected to the MCU under test. The second power-off loop in the Flash software encryption mode is re-executed. After completing the second preset number of times, the ratio of the number of times a lock-up fault occurs to the second preset number of times is recalculated to obtain a third fault occurrence probability. The second power-off loop in the programmer hardware encryption mode is re-executed. After completing the second preset number of times, the ratio of the number of times a lock-up fault occurs to the second preset number of times is recalculated to obtain a fourth fault occurrence probability. The step of determining the cause of the lock-up fault of the MCU under test based on the comparison between the probability of the first fault occurrence and the probability of the second fault occurrence includes: The first target failure probability is obtained by weighted summing the first failure probability and the third failure probability; and the second target failure probability is obtained by weighted summing the second failure probability and the fourth failure probability. The cause of the lock-up fault of the MCU under test is determined based on the comparison between the first target fault probability and the second target fault probability.

7. A system for diagnosing the causes of MCU lockup faults under critical voltage, characterized in that, include: The acquisition unit is used to acquire the time difference from the start-up of the MCU under test to the reaching of the critical voltage when the MCU under test performs a power-on operation, and to determine the power-off sequence based on the time difference; The first cycle test unit is used to start the Flash software encryption mode, cut off the power supply circuit of the MCU under test based on the power failure sequence, and restore power supply after waiting for a preset time to complete a single first power failure cycle. After completing the first preset number of power-off cycles, a non-disconnection power-on operation is performed, and the MCU under test is checked for a lock-up fault to complete a single second power-off cycle. The second cycle test unit is used to switch the Flash software encryption mode to the programmer hardware encryption mode after completing the second power-off cycle for the second preset number of times, and to re-execute the second power-off cycle for the second preset number of times in the programmer hardware encryption mode. The calculation unit is used to calculate the ratio of the number of times a lockout failure occurs in the Flash software encryption mode to the second preset number of times, so as to obtain the probability of the first failure occurring. And calculate the ratio of the number of times a lockout failure occurs in the programmer hardware encryption mode to the second preset number of times to obtain the probability of the second failure occurring; The determining unit is used to determine the cause of the lock-up fault of the MCU under test based on the comparison result of the first fault occurrence probability and the second fault occurrence probability.

8. The MCU lockup fault cause diagnosis system under critical voltage according to claim 7, characterized in that, The determining unit is specifically used for: Compare the probability of the first fault occurrence with the probability of the second fault occurrence; When the probability of the first fault occurrence is greater than the probability of the second fault occurrence, the cause of the lock-up fault of the MCU under test is determined to be the simultaneous execution of Flash software encryption operation while the voltage fluctuates. When the probability of the first fault occurrence is less than or equal to the probability of the second fault occurrence, the cause of the lock-up fault of the MCU under test is determined to be voltage fluctuation.

9. An electronic device, characterized in that, include: Processor, memory, input / output units, and bus; The processor is connected to the memory, the input / output unit, and the bus; The memory stores a program, which the processor calls to execute the MCU lock-up fault cause diagnosis method under any one of claims 1 to 6.

10. A computer-readable storage medium, characterized in that, include: Instructions, when executed on a computer, cause the computer to perform the MCU lock-up fault cause diagnosis method under any one of claims 1 to 6.

Images