Packaging substrate and method for processing the same

Abstract

The application provides a packaging substrate and a processing method thereof. The packaging substrate comprises a ceramic substrate, a first build-up structure and a second build-up structure. The ceramic substrate comprises a ceramic plate member having a conductive hole penetrating through the ceramic plate member along the thickness direction of the ceramic plate member, a conductive column is arranged in the conductive hole, one side of the ceramic plate member in the thickness direction is provided with a first conductive layer, and the first conductive layer is electrically connected with one end of the conductive column. The first build-up structure is arranged on the side of the first conductive layer away from the ceramic plate member, the first build-up structure is electrically connected with the first conductive layer, the first build-up structure is formed by an RDL process, and the first build-up structure is used for electrical connection with a chip. The second build-up structure is arranged on the other side of the ceramic plate member in the thickness direction, the second build-up structure is electrically connected with the conductive column, the second build-up structure is formed by an MSAP process, and the second build-up structure is used for electrical connection with a PCB. The packaging substrate of the embodiment of the application has high flatness and can meet the demand of interconnection with a chip with a smaller spacing on the basis of being connected with the PCB.

Description

Technical Field

[0001] This invention relates to the field of circuit board technology, and in particular to a packaging substrate and its processing method. Background Technology

[0002] With the rapid iteration and upgrading of artificial chips, the size of packaged devices continues to increase. Currently, the core layer of mainstream packaging substrates generally uses BT resin or FR4 material. These organic substrates have relatively weak rigidity, making them prone to warping and deformation under large-size packaging substrates. This results in poor overall flatness of the packaging substrate, leading to reliability issues such as poor soldering and contact during flip-chip bonding. Furthermore, existing packaging substrates mostly use MSAP technology to fabricate the circuit layers. This process, limited by manufacturing process constraints, makes it difficult to meet the requirements of smaller-pitch interconnection pads between the packaging substrate and the chip.

[0003] Therefore, the packaging substrates in related technologies cannot meet the requirements for interconnecting with chips with smaller pitches while being connected to the PCB. Summary of the Invention

[0004] This invention provides a packaging substrate to solve the problem in related technologies that packaging substrates are difficult to interconnect with chips with smaller pitches while being connected to a PCB, thereby achieving the effect that the packaging substrate can meet the interconnection requirements with chips with smaller pitches while being connected to a PCB.

[0005] The packaging substrate of this invention includes: A ceramic substrate, the ceramic substrate including a ceramic plate having a conductive hole penetrating through it along its thickness direction, a conductive post being disposed in the conductive hole, and a first conductive layer being disposed on one side of the ceramic plate in the thickness direction, the first conductive layer being electrically connected to one end of the conductive post. A first add-in structure is disposed on the side of the first conductive layer away from the ceramic plate. The first add-in structure is electrically connected to the first conductive layer. The first add-in structure is formed by RDL process and is used for electrical connection with the chip. The second add-in structure is located on the other side of the ceramic plate in the thickness direction. The second add-in structure is electrically connected to the conductive pillar. The second add-in structure is formed by MSAP process and is used for electrical connection with PCB.

[0006] It is understood that the packaging substrate of the present invention uses a ceramic substrate as the core layer. The ceramic plate of the ceramic substrate has excellent rigidity and is not prone to warping when processing large-size structures. This ensures that the packaging substrate of the present invention has good flatness, thereby avoiding problems such as poor soldering and poor contact when the packaging substrate of the present invention is soldered to the chip, and greatly improving the quality of the packaged devices processed subsequently.

[0007] A first add-on structure is processed on one side of the ceramic substrate in the thickness direction, and a second add-on structure is processed on the other side of the ceramic substrate in the thickness direction. The first add-on structure is used for electrical connection with the chip, and the second add-on structure is used for electrical connection with the PCB. Thus, after the chip is electrically connected to the first add-on structure and processed to form a packaged device, the chip can be electrically connected to the PCB through the second add-on structure, thereby achieving the effect of electrical connection between the chip and the PCB.

[0008] Meanwhile, the first add-on structure is formed using the RDL process, which has better process precision and can produce patterned circuit layers with smaller line widths and spacings. Therefore, it can adapt to the interconnection requirements of smaller pitch pads in chips, solving the problem of limited line width and spacing in the traditional MSAP process. The second add-on structure, which is used to connect to the PCB, is processed using the MSAP process. The PCB has a larger pad pitch, and the MSAP process can meet the processing requirements. At the same time, it has a lower processing cost than the RDL process, which can balance the processing precision and processing cost of the packaging substrate.

[0009] Therefore, the packaging substrate of the present invention has high flatness and can meet the requirements for interconnection with smaller pitch chips while being connected to a PCB.

[0010] In some embodiments, the first add-in structure includes a plurality of first sub-add-in structures, and the plurality of first sub-add-in structures are stacked sequentially along a direction away from the ceramic plate. The first sub-addition structure includes a first insulating layer and a first patterned circuit layer arranged sequentially along the direction away from the ceramic plate. The first patterned circuit layer is electrically connected to the first conductive layer, and the first patterned circuit layers of adjacent first sub-addition structures are electrically connected. Along the direction away from the ceramic plate, the pitch of the first patterned circuit layer of the first sub-addition structure gradually decreases.

[0011] In some embodiments, the second layer structure includes a second conductive layer and a second sub-layer structure, wherein the second conductive layer and the second layer structure are sequentially disposed along a direction away from the ceramic plate, and the second conductive layer is electrically connected to the conductive pillar. The second sub-addition structure is multiple, and the multiple second sub-addition structures are stacked sequentially along the direction away from the ceramic plate; The second sub-addition structure includes a second insulating layer and a second patterned circuit layer arranged sequentially along the direction away from the ceramic plate. The second patterned circuit layer is electrically connected to the second conductive layer, and the second patterned circuit layers of adjacent second sub-addition structures are electrically connected. Along the direction away from the ceramic plate, the pitch of the second patterned circuit layer of the second sub-addition structure gradually increases.

[0012] In some embodiments, the ceramic plate is made of one of aluminum nitride, silicon nitride, boron nitride, aluminum oxide, beryllium oxide, and silicon carbide.

[0013] The present invention also provides a method for processing a packaging substrate.

[0014] The processing method of the packaging substrate according to an embodiment of the present invention includes the following operations: S100: Obtain a ceramic substrate, the ceramic substrate including a ceramic plate, the ceramic plate having a conductive hole penetrating through it along its thickness direction, a conductive post being provided in the conductive hole, a first conductive layer being provided on one side of the ceramic plate in the thickness direction, and the first conductive layer being electrically connected to one end of the conductive post. S200: A first augmentation structure is formed on the side of the first conductive layer away from the ceramic plate using the RDL process. The first augmentation structure is electrically connected to the first conductive layer and is used for electrical connection with the chip. S300: A second augmentation structure is formed on the side of the ceramic plate away from the first conductive layer using the MSAP process. The second augmentation structure is electrically connected to the conductive pillar and is used for electrical connection with the PCB.

[0015] It is understood that the packaging substrate processing method of the present invention uses a ceramic substrate as the core layer. Since the ceramic plate of the ceramic substrate has excellent rigidity, it is not easy to warp when processing large-size structures. This ensures that the packaging substrate processed by the packaging substrate processing method of the present invention has good flatness. In turn, it can avoid problems such as poor soldering and poor contact when the packaging substrate processed by the packaging substrate processing method of the present invention is soldered to the chip, which can greatly improve the quality of the packaged devices processed subsequently.

[0016] A first add-on structure is processed on one side of the ceramic substrate in the thickness direction, and a second add-on structure is processed on the other side of the ceramic substrate in the thickness direction. The first add-on structure is used for electrical connection with the chip, and the second add-on structure is used for electrical connection with the PCB. Thus, after the chip is electrically connected to the first add-on structure and processed to form a packaged device, the chip can be electrically connected to the PCB through the second add-on structure, thereby achieving the effect of electrical connection between the chip and the PCB.

[0017] Meanwhile, the first add-on structure is formed using the RDL process, which has better process precision and can produce patterned circuit layers with smaller line widths and spacings. Therefore, it can adapt to the interconnection requirements of smaller pitch pads in chips, solving the problem of limited line width and spacing in the traditional MSAP process. The second add-on structure, which is used to connect to the PCB, is processed using the MSAP process. The PCB has a larger pad pitch, and the MSAP process can meet the processing requirements. At the same time, it has a lower processing cost than the RDL process, which can balance the processing precision and processing cost of the packaging substrate.

[0018] Therefore, the packaging substrate processed by the packaging substrate processing method of the present invention has high flatness and can meet the requirements of interconnection with smaller pitch chips while being connected to the PCB.

[0019] In some embodiments, obtaining the ceramic substrate in S100 includes the following steps: S110: Obtain ceramic plates; S120: A conductive hole is machined on the ceramic plate, penetrating the ceramic plate along the thickness direction; S130: Forming a first conductive seed layer on the surface of a ceramic plate; S140: A first conductive electroplating protective film is provided on both sides in the thickness direction of the ceramic plate, and exposure and development are performed to expose the area of ​​the first conductive seed layer that needs to be electroplated and thickened. S150: Electroplating thickening, forming a first conductive electroplating thickening layer on both sides in the thickness direction of the ceramic plate, forming a conductive post in the conductive hole and electrically connecting it with the first conductive electroplating thickening layer, removing the first conductive electroplating protective film, and removing excess first conductive seed layer; S160: Grind the other side of the ceramic plate in the thickness direction to remove the first conductive electroplated thickening layer on the other side of the ceramic plate in the thickness direction, and form a first conductive layer on one side of the ceramic plate in the thickness direction. S170: Obtain the ceramic substrate.

[0020] In some embodiments, forming the first added-layer structure in S200 includes the following steps: S210: A first insulating layer is provided on the side of the first conductive layer away from the ceramic plate; S220: A first interconnect hole extending to the first conductive layer is formed on the first insulating layer; S230: A first seed layer is formed on the side of the first insulating layer away from the first conductive layer and on the inner wall of the first interconnect hole; S240: A first electroplating protective film is formed on the side of the first insulating layer away from the first conductive layer, and exposed and developed to expose the area of ​​the first seed layer that needs to be electroplated and thickened. S250: The first seed layer is thickened by electroplating, the first electroplating protective film is removed, and the excess first seed layer is removed to form a first patterned circuit layer on the side of the first insulating layer away from the first conductive layer, and a first interconnect is formed in the first interconnect hole to connect the first conductive layer and the first patterned circuit layer. Repeat steps S210 to S250 until the target number of layers for the first layered structure is reached.

[0021] In some embodiments, after the last first patterned circuit layer is formed, electroplating is performed on the surface of the last first patterned circuit layer.

[0022] In some embodiments, in S300, forming the second layered structure includes the following steps: S310: A second conductive layer is formed on the side of the ceramic substrate away from the first conductive layer; S320: A second insulating layer is provided on the side of the second conductive layer away from the ceramic plate; S330: A second interconnect hole extending to the second conductive layer is processed on the second insulating layer; S340: A second seed layer is formed on the side of the second insulating layer away from the second conductive layer and on the inner wall of the second interconnect hole; S350: A second electroplating protective film is formed on the side of the second insulating layer away from the second conductive layer, and exposed and developed to expose the area of ​​the second seed layer that needs to be electroplated and thickened. S360: The second seed layer is thickened by electroplating, the second electroplating protective film is removed, and the excess second seed layer is removed to form a second patterned circuit layer on the side of the second insulating layer away from the second conductive layer, and a second interconnect is formed in the second interconnect hole to connect the second conductive layer and the second patterned circuit layer. Repeat steps S320 to S360 until the target number of layers for the second layered structure is reached.

[0023] In some embodiments, forming the second conductive layer in S310 includes the following steps: S311: A second conductive seed layer is formed on the side of the ceramic plate away from the first conductive layer; S312, a second conductive electroplating protective film is formed on the surface of the second seed layer, and exposed and developed to expose the area of ​​the second conductive seed layer that needs to be electroplated and thickened. S313: The second conductive seed layer is thickened by electroplating, the second conductive electroplating protective film is removed, and the excess second conductive seed layer is removed to form a second conductive layer, and the second conductive layer is electrically connected to the conductive pillar. Attached Figure Description To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of the packaging substrate according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of the ceramic substrate of the packaging substrate according to an embodiment of the present invention; Figure 3 This is one of the flowcharts of the processing method for packaging substrate according to an embodiment of the present invention; Figure 4 This is the second flowchart of the processing method for packaging substrate according to an embodiment of the present invention; Figure 5 This is the third flowchart of the processing method for packaging substrate according to an embodiment of the present invention; Figure 6 This is the fourth flowchart of the processing method for packaging substrate according to an embodiment of the present invention; Figure 7 This is the fifth flowchart of the processing method for packaging substrate according to an embodiment of the present invention; Figure 8 This is the sixth flowchart of the processing method for packaging substrate according to an embodiment of the present invention; Figure 9 This is the seventh flowchart of the processing method for packaging substrate according to an embodiment of the present invention; Figure 10 This is the eighth flowchart of the processing method for packaging substrate according to an embodiment of the present invention; Figure 11 This is the ninth flowchart of the processing method for packaging substrate according to an embodiment of the present invention; Figure 12 This is the tenth flowchart of the processing method for packaging substrate according to an embodiment of the present invention; Figure 13 This is 11 of the flowcharts illustrating the processing method of the packaging substrate according to an embodiment of the present invention; Figure 14 This is the twelfth flowchart of the processing method for packaging substrate according to an embodiment of the present invention; Figure 15 This is the thirteenth flowchart of the processing method for packaging substrate according to an embodiment of the present invention; Figure 16 This is the fourteenth flowchart of the processing method for packaging substrate according to an embodiment of the present invention; Figure 17 This is the fifteenth flowchart of the processing method for packaging substrate according to an embodiment of the present invention; Figure 18 This is the sixteenth flowchart of the processing method for packaging substrate according to an embodiment of the present invention; Figure 19 This is the seventeenth flowchart of the processing method for packaging substrate according to an embodiment of the present invention.

[0025] In the picture: 100. Packaging substrate; 1. Ceramic substrate; 101. Conductive via; 102. Conductive post; 103. Ceramic plate; 2. First add-on structure; 201. First sub-add-on structure; 2011. First insulating layer; 2022. First patterned circuit layer; 2023. First interconnect via; 2024. First seed layer; 2025. First interconnect; 2026. First electroplated protective film; 3. Second add-on structure; 301. Second sub-add-on structure; 3011. Second insulating layer; 3022. Second patterned circuit layer; 3023. Second interconnect hole; 3024. Second seed layer; 3025. Second interconnect; 3026. Second electroplating protective film; 4. First conductive layer; 401. First conductive seed layer; 402. First conductive electroplating protective film; 403. First conductive electroplating thickening layer; 5. Second conductive layer; 501. Second conductive seed layer; 502. Second conductive electroplating protective film. Detailed Implementation

[0026] To make the technical problems solved, the technical solutions, and the beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0027] In the description of this invention, it should be understood that the terms "longitudinal," "radial," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientation or positional relationships, are based on the orientation or positional relationships shown in the accompanying drawings and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0028] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal encapsulation of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0029] To address the problem that the packaging substrate 100 in related technologies is difficult to meet the requirements for interconnection with chips with smaller pitch while being connected to a PCB, the present invention provides a packaging substrate 100.

[0030] like Figure 1 As shown, the packaging substrate 100 of this embodiment of the invention includes a ceramic substrate 1, a first layered structure 2, and a second layered structure 3.

[0031] Among them, such as Figure 2 As shown, the ceramic substrate 1 includes a ceramic plate 103, the ceramic plate 103 has a conductive hole 101 extending through it along its thickness direction, a conductive post 102 is provided in the conductive hole 101, a first conductive layer 4 is provided on one side of the ceramic plate 103 in the thickness direction, and the first conductive layer 4 is electrically connected to one end of the conductive post 102. The first add-in structure 2 is disposed on the side of the first conductive layer 4 away from the ceramic plate 103. The first add-in structure 2 is electrically connected to the first conductive layer 4. The first add-in structure 2 is formed by RDL process. The first add-in structure 2 is used for electrical connection with the chip. The second layer structure 3 is located on the other side of the ceramic plate 103 in the thickness direction. The second layer structure 3 is electrically connected to the conductive post 102. The second layer structure 3 is formed by MSAP process and is used for electrical connection with PCB.

[0032] It is understood that the packaging substrate 100 of the present invention uses a ceramic substrate 1 as the core layer. The ceramic plate 103 of the ceramic substrate 1 has excellent rigidity and is not prone to warping when processing large-size structures. This ensures that the packaging substrate 100 of the present invention has good flatness, thereby avoiding problems such as poor soldering and poor contact when the packaging substrate 100 of the present invention is soldered to the chip, and greatly improving the quality of the packaged devices processed subsequently.

[0033] A first add-on structure 2 is processed on one side of the ceramic substrate 1 in the thickness direction, and a second add-on structure 3 is processed on the other side of the ceramic substrate 1 in the thickness direction. The first add-on structure 2 is used for electrical connection with the chip, and the second add-on structure 3 is used for electrical connection with the PCB. Thus, after the chip is electrically connected to the first add-on structure 2 and processed to form a packaged device, it can be electrically connected to the PCB through the second add-on structure 3, thereby achieving the effect of electrical connection between the chip and the PCB.

[0034] Meanwhile, the first add-on structure 2 is formed using the RDL process. The RDL process has better process precision and can process patterned circuit layers with smaller line widths and spacings. Therefore, it can adapt to the interconnection requirements of smaller pitch pads of chips and solve the problem of limited line width and spacing in the traditional MSAP process. The second add-on structure 3, which is used to connect with the PCB, is processed using the MSAP process. The PCB has a larger pad pitch, and the MSAP process can meet the processing requirements. At the same time, the processing cost is lower than that of the RDL process, which can balance the processing precision and processing cost of the packaging substrate 100.

[0035] Therefore, the packaging substrate 100 of the present invention has high flatness and can meet the requirements for interconnection with smaller pitch chips while being connected to a PCB.

[0036] In some embodiments, the first layer structure 2 includes a plurality of first sub-layer structures 201, which are stacked sequentially along a direction away from the ceramic plate 103. The first sub-addition structure 201 includes a first insulating layer 2011 and a first patterned circuit layer 2022 arranged sequentially along the direction away from the ceramic plate 103. The first patterned circuit layer 2022 is electrically connected to the first conductive layer 4, and the first patterned circuit layer 2022 of the adjacent first sub-addition structure 201 is electrically connected. Along the direction away from the ceramic plate 103, the pitch of the first patterned circuit layer 2022 of the first sub-addition structure 201 gradually decreases.

[0037] It is understandable that the outermost first patterned circuit layer 2022 of the first add-on structure 2 is directly electrically connected to the chip's pads. Since the line pitch is smaller closer to the chip, it can just match the small-pitch arrangement requirements of the chip's pads. At the same time, the first add-on structure 2 is configured to include multiple first sub-add-on structures 201 stacked sequentially along the direction away from the ceramic plate 103, which can form a line structure with a layer-by-layer transition, and thus better adapt to the line impedance design requirements and improve signal transmission stability.

[0038] In some embodiments, the second layer structure 3 includes a second conductive layer 5 and a second sub-layer structure 301. The second conductive layer 5 and the second layer structure 3 are arranged sequentially along a direction away from the ceramic plate 103. The second conductive layer 5 is electrically connected to the conductive post 102. There are multiple second sub-addition structures 301, and the multiple second sub-addition structures 301 are stacked sequentially along the direction away from the ceramic plate 103. The second sub-addition structure 301 includes a second insulating layer 3011 and a second patterned circuit layer 3022 arranged sequentially along the direction away from the ceramic plate 103. The second patterned circuit layer 3022 is electrically connected to the second conductive layer 5, and the second patterned circuit layer 3022 of the adjacent second sub-addition structure 301 is electrically connected. Along the direction away from the ceramic plate 103, the pitch of the second patterned circuit layer 3022 of the second sub-addition structure 301 gradually increases.

[0039] It is understandable that the outermost second graphic circuit layer 3022 of the second add-on structure 3 needs to be electrically connected to the interface of the external circuit. The circuit pitch of the external interface is usually larger. The design of the circuit pitch being larger the further away from the ceramic plate 103 is just right to match the large spacing arrangement requirements of the external interface. At the same time, multiple second sub-add-on structures 301 arranged in sequence along the direction away from the ceramic plate 103 can also form a circuit structure with a layer-by-layer transition, adapting to different circuit impedance design requirements and ensuring the stability of the overall signal transmission.

[0040] In some embodiments, the ceramic plate 103 is made of one of aluminum nitride, silicon nitride, boron nitride, aluminum oxide, beryllium oxide, and silicon carbide.

[0041] It is understood that the above-mentioned materials all have good insulation properties, thermal conductivity and structural stability, which can meet the basic performance requirements of the core layer of the packaging substrate 100 in this embodiment of the invention. At the same time, they can withstand the high temperature processing conditions during the packaging process, and can also dissipate the heat generated by the device in a timely manner, reduce the impact of heat accumulation on the overall circuit transmission performance, and improve the long-term reliability of the packaging substrate 100 in this embodiment of the invention.

[0042] The present invention also provides a method for processing a ceramic substrate 1.

[0043] The processing method of the packaging substrate 100 in this embodiment of the invention includes the following operations: S100: Obtain a ceramic substrate 1. The ceramic substrate 1 includes a ceramic plate 103. The ceramic plate 103 has a conductive hole 101 that penetrates through it along its thickness direction. A conductive post 102 is provided in the conductive hole 101. A first conductive layer 4 is provided on one side of the ceramic plate 103 in the thickness direction. The first conductive layer 4 is electrically connected to one end of the conductive post 102. S200: A first augmentation structure 2 is formed on the side of the first conductive layer 4 away from the ceramic plate 103 using the RDL process. The first augmentation structure 2 is electrically connected to the first conductive layer 4 and is used for electrical connection with the chip. S300: A second augmentation structure 3 is formed on the side of the ceramic plate 103 away from the first conductive layer 4 using the MSAP process. The second augmentation structure 3 is electrically connected to the conductive pillar 102 and is used for electrical connection with the PCB.

[0044] It is understood that the processing method of the packaging substrate 100 in this embodiment of the invention uses a ceramic substrate 1 as the core layer. Since the ceramic plate 103 of the ceramic substrate 1 has excellent rigidity, it is not easy to warp when processing large-size structures. This ensures that the packaging substrate 100 processed by the processing method of the packaging substrate 100 in this embodiment of the invention has good flatness. In this way, it can avoid problems such as poor soldering and poor contact when the packaging substrate 100 processed by the processing method of the packaging substrate 100 in this embodiment of the invention is soldered with the chip, which can greatly improve the quality of the packaged devices processed subsequently.

[0045] A first add-on structure 2 is processed on one side of the ceramic substrate 1 in the thickness direction, and a second add-on structure 3 is processed on the other side of the ceramic substrate 1 in the thickness direction. The first add-on structure 2 is used for electrical connection with the chip, and the second add-on structure 3 is used for electrical connection with the PCB. Thus, after the chip is electrically connected to the first add-on structure 2 and processed to form a packaged device, it can be electrically connected to the PCB through the second add-on structure 3, thereby achieving the effect of electrical connection between the chip and the PCB.

[0046] Meanwhile, the first add-on structure 2 is formed using the RDL process. The RDL process has better process precision and can process patterned circuit layers with smaller line widths and spacings. Therefore, it can adapt to the interconnection requirements of smaller pitch pads of chips and solve the problem of limited line width and spacing in the traditional MSAP process. The second add-on structure 3, which is used to connect with the PCB, is processed using the MSAP process. The PCB has a larger pad pitch, and the MSAP process can meet the processing requirements. At the same time, the processing cost is lower than that of the RDL process, which can balance the processing precision and processing cost of the packaging substrate 100.

[0047] Therefore, the packaging substrate 100 processed by the processing method of the packaging substrate 100 in the embodiment of the present invention has high flatness and can meet the requirements of interconnection with chips with smaller pitch while being connected to the PCB.

[0048] In some embodiments, obtaining the ceramic substrate 1 in S100 includes the following steps: S110: Obtain ceramic plate 103, such as Figure 3 As shown; The ceramic plate 103 obtained in S110 is made of one of aluminum nitride, silicon nitride, boron nitride, aluminum oxide, beryllium oxide, and silicon carbide.

[0049] The aforementioned materials all possess excellent insulation, thermal conductivity, and structural stability, which can meet the basic performance requirements of the core layer of the packaging substrate 100 in this embodiment of the invention. They can also withstand the high-temperature processing conditions during the packaging process, and can dissipate the heat generated by the device operation in a timely manner, reducing the impact of heat accumulation on the overall circuit transmission performance and improving the long-term reliability of the packaging substrate 100 in this embodiment of the invention.

[0050] S120: A conductive hole 101 is machined on the ceramic plate 103, extending through the ceramic plate 103 along its thickness direction, such as... Figure 4 As shown; The conductive holes 101 on the ceramic plate 103 can be processed by mechanical methods, such as by using mechanical drilling equipment; they can also be processed by optical methods, such as by using laser equipment.

[0051] S130: A first conductive seed layer 401 is formed on the surface of the ceramic plate 103, such as... Figure 5 As shown; The first conductive seed layer 401 is preferably processed by sputtering, but it can also be processed by vapor deposition, chemical copper plating, and slurry coating.

[0052] S140: As Figure 6 As shown, a first conductive electroplating protective film 402 is provided on both sides of the ceramic plate 103 in the thickness direction, and exposure and development are performed to expose the area of ​​the first conductive seed layer 401 that needs to be electroplated and thickened. The first conductive electroplating protective film 402 used in S140 can be a dry film or a photoresist.

[0053] S150: As Figure 7 As shown, electroplating thickens the ceramic plate 103 by forming a first conductive electroplating thickened layer 403 on both sides in the thickness direction. Conductive pillars 102 are formed in the conductive holes 101 and electrically connected to the first conductive electroplating thickened layer 403. The first conductive electroplating protective film 402 is removed, and excess first conductive seed layer 401 is removed. The first conductive seed layer 401 can be removed by flash etching.

[0054] S160: As Figure 8 As shown, the other side of the ceramic plate 103 in the thickness direction is ground to remove the first conductive electroplated thickening layer 403 on the other side of the ceramic plate 103 in the thickness direction, and a first conductive layer 4 is formed on one side of the ceramic plate 103 in the thickness direction. S170: As Figure 8 As shown, ceramic substrate 1 is obtained.

[0055] In some embodiments, forming the first added-layer structure 2 in S200 includes the following steps: S210: As Figure 9 As shown, a first insulating layer 2011 is provided on the side of the first conductive layer 4 away from the ceramic plate 103; The first insulating layer 2011 can be set by spin coating, spray coating or adsorption process, and the material of the first insulating layer 2011 can be a photosensitive material or a non-photosensitive material.

[0056] S220: As Figure 10 As shown, a first interconnect hole 2023 extending to the first conductive layer 4 is processed on the first insulating layer 2011; The first interconnect hole 2023 can be processed by mechanical methods, such as using mechanical drilling equipment; it can also be processed by optical methods, such as using laser equipment.

[0057] S230: such as Figure 10 As shown, a first seed layer 2024 is formed on the side of the first insulating layer 2011 away from the first conductive layer 4 and on the inner wall of the first interconnect hole 2023; The first seed layer 2024 is preferably formed by sputtering, but it can also be formed by vapor deposition, chemical copper plating, or paste coating.

[0058] S240: As Figure 11 As shown, a first electroplating protective film 2026 is formed on the side of the first insulating layer 2011 away from the first conductive layer 4, and exposed and developed to expose the area of ​​the first seed layer 2024 that needs to be electroplated and thickened. The first electroplating protective film 2026 can be a dry film or a photoresist.

[0059] S250: The first seed layer 2024 is thickened by electroplating, the first electroplating protective film 2026 is removed, and the excess first seed layer 2024 is removed, so as to form a first patterned circuit layer 2022 on the side of the first insulating layer 2011 away from the first conductive layer 4, and a first interconnect 2025 is formed in the first interconnect hole 2023 to connect the first conductive layer 4 and the first patterned circuit layer 2022. Repeat steps S210 to S250 until the target number of layers for the first layered structure 2 is reached.

[0060] When repeating S210~S250, in S210, the first insulating layer 2011 will be formed again on the side of the first patterned circuit layer 2022 away from the first insulating layer 2011, and so on.

[0061] By using the RDL process to form the first add-on structure 2, the RDL process has better process accuracy and can process patterned circuit layers with smaller line widths and spacings. Therefore, it can adapt to the chip's smaller pitch pad interconnection requirements and solve the problem of limited line widths and spacings in the traditional MSAP process.

[0062] In some embodiments, after the last first patterned circuit layer 2022 is formed, an electroplating process is performed on the surface of the last first patterned circuit layer.

[0063] In some embodiments, forming the second add-on structure 3 in S300 includes the following steps: S310: As Figures 13-15 As shown, a second conductive layer 5 is formed on the side of the ceramic plate 103 away from the first conductive layer 4. S320: such as Figure 16 As shown, a second insulating layer 3011 is provided on the side of the second conductive layer 5 away from the ceramic plate 103; S330: such as Figure 17 As shown, a second interconnect hole 3023 extending to the second conductive layer 5 is processed on the second insulating layer 3011; The second interconnecting hole 3023 can be processed by mechanical methods, such as using mechanical drilling equipment; it can also be processed by optical methods, such as using laser equipment.

[0064] S340: such as Figure 17 As shown, a second seed layer 3024 is formed on the side of the second insulating layer 3011 away from the second conductive layer 5 and on the inner wall of the second interconnect hole 3023. The second seed layer 3024 is preferably formed by sputtering, but it can also be formed by vapor deposition, chemical copper plating, or paste coating.

[0065] S350: such as Figure 18 As shown, a second electroplating protective film 3026 is formed on the side of the second insulating layer 3011 away from the second conductive layer 5, and exposed and developed to expose the area of ​​the second seed layer 3024 that needs to be electroplated and thickened. The second electroplated protective film 3026 can be a dry film or a photoresist.

[0066] S360: such as Figure 19 As shown, the second seed layer 3024 is thickened by electroplating, the second electroplated protective film 3026 is removed, and the excess second seed layer 3024 is removed so that a second patterned circuit layer 3022 is formed on the side of the second insulating layer 3011 away from the second conductive layer 5, and a second interconnect 3025 is formed in the second interconnect hole 3023 to connect the second conductive layer 5 and the second patterned circuit layer 3022. Repeat steps S320 to S360 until the target number of layers for the second layered structure 3 is reached.

[0067] When repeating S210~S250, in S210, the second insulating layer 3011 will be formed again on the side of the second patterned circuit layer 3022 away from the second insulating layer 3011, and so on.

[0068] It is understandable that the second add-on structure 3 used for connection with the PCB is processed using the MSAP process. The PCB has a larger pad pitch, and the MSAP process can meet the processing requirements. At the same time, the processing cost is lower than that of the RDL process, which can balance the processing accuracy and processing cost of the packaging substrate 100.

[0069] In some embodiments, forming the second conductive layer 5 in S310 includes the following steps: S311: As Figure 13 As shown, a second conductive seed layer 501 is formed on the side of the ceramic plate 103 away from the first conductive layer 4; The second conductive seed layer 501 is preferably formed by sputtering, but it can also be formed by vapor deposition, chemical copper plating, or paste coating.

[0070] S312, such as Figure 14 As shown, a second conductive electroplating protective film 502 is formed on the surface of the second seed layer 3024, and exposed and developed to expose the area of ​​the second conductive seed layer 501 that needs to be electroplated and thickened. The second conductive electroplating protective film 502 can be a dry film or a photoresist.

[0071] S313: As Figure 15 As shown, the second conductive seed layer 501 is thickened by electroplating, the second conductive electroplating protective film 502 is removed, and the excess second conductive seed layer 501 is removed to form the second conductive layer 5, and the second conductive layer 5 is electrically connected to the conductive pillar 102.

[0072] By electrically connecting the second conductive layer 5 to the conductive post 102, the second conductive layer 5 can be electrically connected to the first conductive layer 4 and the first augmentation structure 2, thereby enabling the first augmentation structure 2 and the second augmentation structure 3 to be electrically connected.

[0073] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A packaging substrate, characterized in that, include: A ceramic substrate, the ceramic substrate including a ceramic plate having a conductive hole penetrating through it along its thickness direction, a conductive post being disposed in the conductive hole, and a first conductive layer being disposed on one side of the ceramic plate in the thickness direction, the first conductive layer being electrically connected to one end of the conductive post. A first add-in structure is disposed on the side of the first conductive layer away from the ceramic plate. The first add-in structure is electrically connected to the first conductive layer. The first add-in structure is formed by RDL process and is used for electrical connection with the chip. The second add-in structure is located on the other side of the ceramic plate in the thickness direction. The second add-in structure is electrically connected to the conductive pillar. The second add-in structure is formed by MSAP process and is used for electrical connection with PCB.

2. The packaging substrate according to claim 1, characterized in that, The first add-layer structure includes a plurality of first sub-add-layer structures, which are stacked sequentially along a direction away from the ceramic plate. The first sub-addition structure includes a first insulating layer and a first patterned circuit layer arranged sequentially along the direction away from the ceramic plate. The first patterned circuit layer is electrically connected to the first conductive layer, and the first patterned circuit layers of adjacent first sub-addition structures are electrically connected. Along the direction away from the ceramic plate, the pitch of the first patterned circuit layer of the first sub-addition structure gradually decreases.

3. The packaging substrate according to claim 1, characterized in that, The second layer structure includes a second conductive layer and a second sub-layer structure. The second conductive layer and the second layer structure are arranged sequentially along the direction away from the ceramic plate. The second conductive layer is electrically connected to the conductive pillar. The second sub-addition structure is multiple, and the multiple second sub-addition structures are stacked sequentially along the direction away from the ceramic plate; The second sub-addition structure includes a second insulating layer and a second patterned circuit layer arranged sequentially along the direction away from the ceramic plate. The second patterned circuit layer is electrically connected to the second conductive layer, and the second patterned circuit layers of adjacent second sub-addition structures are electrically connected. Along the direction away from the ceramic plate, the pitch of the second patterned circuit layer of the second sub-addition structure gradually increases.

4. The packaging substrate according to claim 1, characterized in that, The ceramic plate is made of one of the following materials: aluminum nitride, silicon nitride, boron nitride, aluminum oxide, beryllium oxide, and silicon carbide.

5. A method for processing a packaging substrate, characterized in that, This includes the following operations: S100: Obtain a ceramic substrate, the ceramic substrate including a ceramic plate, the ceramic plate having a conductive hole penetrating through it along its thickness direction, a conductive post being provided in the conductive hole, a first conductive layer being provided on one side of the ceramic plate in the thickness direction, and the first conductive layer being electrically connected to one end of the conductive post. S200: A first augmentation structure is formed on the side of the first conductive layer away from the ceramic plate using the RDL process. The first augmentation structure is electrically connected to the first conductive layer and is used for electrical connection with the chip. S300: A second augmentation structure is formed on the side of the ceramic plate away from the first conductive layer using the MSAP process. The second augmentation structure is electrically connected to the conductive pillar and is used for electrical connection with the PCB.

6. The processing method according to claim 5, characterized in that, In S100, obtaining the ceramic substrate includes the following steps: S110: Obtain ceramic plates; S120: A conductive hole is machined on the ceramic plate, penetrating the ceramic plate along the thickness direction; S130: Forming a first conductive seed layer on the surface of a ceramic plate; S140: A first conductive electroplating protective film is provided on both sides in the thickness direction of the ceramic plate, and exposure and development are performed to expose the area of ​​the first conductive seed layer that needs to be electroplated and thickened. S150: Electroplating thickening, forming a first conductive electroplating thickening layer on both sides in the thickness direction of the ceramic plate, forming a conductive post in the conductive hole and electrically connecting it with the first conductive electroplating thickening layer, removing the first conductive electroplating protective film, and removing excess first conductive seed layer; S160: Grind the other side of the ceramic plate in the thickness direction to remove the first conductive electroplated thickening layer on the other side of the ceramic plate in the thickness direction, and form a first conductive layer on one side of the ceramic plate in the thickness direction. S170: Obtain the ceramic substrate.

7. The processing method according to claim 5, characterized in that, In S200, forming the first added-layer structure includes the following steps: S210: A first insulating layer is provided on the side of the first conductive layer away from the ceramic plate; S220: A first interconnect hole extending to the first conductive layer is formed on the first insulating layer; S230: A first seed layer is formed on the side of the first insulating layer away from the first conductive layer and on the inner wall of the first interconnect hole; S240: A first electroplating protective film is formed on the side of the first insulating layer away from the first conductive layer, and exposed and developed to expose the area of ​​the first seed layer that needs to be electroplated and thickened. S250: The first seed layer is thickened by electroplating, the first electroplating protective film is removed, and the excess first seed layer is removed to form a first patterned circuit layer on the side of the first insulating layer away from the first conductive layer, and a first interconnect is formed in the first interconnect hole to connect the first conductive layer and the first patterned circuit layer. Repeat steps S210 to S250 until the target number of layers for the first layered structure is reached.

8. The processing method according to claim 7, characterized in that, After forming the last first pattern circuit layer, electroplating is performed on the surface of the last first pattern circuit layer.

9. The processing method according to claim 5, characterized in that, In S300, forming the second layered structure includes the following steps: S310: A second conductive layer is formed on the side of the ceramic plate away from the first conductive layer; S320: A second insulating layer is provided on the side of the second conductive layer away from the ceramic plate; S330: A second interconnect hole extending to the second conductive layer is processed on the second insulating layer; S340: A second seed layer is formed on the side of the second insulating layer away from the second conductive layer and on the inner wall of the second interconnect hole; S350: A second electroplating protective film is formed on the side of the second insulating layer away from the second conductive layer, and exposed and developed to expose the area of ​​the second seed layer that needs to be electroplated and thickened. S360: The second seed layer is thickened by electroplating, the second electroplating protective film is removed, and the excess second seed layer is removed to form a second patterned circuit layer on the side of the second insulating layer away from the second conductive layer, and a second interconnect is formed in the second interconnect hole to connect the second conductive layer and the second patterned circuit layer. Repeat steps S320 to S360 until the target number of layers for the second layered structure is reached.

10. The processing method according to claim 9, characterized in that, In S310, forming the second conductive layer includes the following steps: S311: A second conductive seed layer is formed on the side of the ceramic plate away from the first conductive layer; S312, a second conductive electroplating protective film is formed on the surface of the second seed layer, and exposed and developed to expose the area of ​​the second conductive seed layer that needs to be electroplated and thickened. S313: The second conductive seed layer is thickened by electroplating, the second conductive electroplating protective film is removed, the excess second conductive seed layer is removed, a second conductive layer is formed, and the second conductive layer is electrically connected to the conductive pillar.

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