Memory devices and methods of aging testing for memory devices

Abstract

Memory devices and methods for aging test of memory devices are provided. The method includes setting a word line isolation circuit to a standby mode, setting the word line isolation circuit to an off state and performing a first aging test by outputting a first test voltage from a sub word line driver circuit, and changing the word line isolation circuit to an on state and performing a second aging test by outputting a second test voltage lower than the first test voltage from the sub word line driver circuit.

Description

[0001] This application is based on and claims priority to Korean Patent Application No. 10-2025-0058321, filed on May 2, 2025, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] The exemplary embodiments of this disclosure described herein relate to semiconductor memory devices, and more specifically, to memory devices including word line isolation circuitry and aging test methods for memory devices. Background Technology

[0003] Semiconductor memories can be broadly categorized into volatile memories and non-volatile memories. Volatile memories (such as dynamic random access memory (DRAM) or static random access memory (SRAM)) have fast read and write speeds, but the data stored in them is lost when the power is turned off. In contrast, non-volatile memories retain data even when the power is off.

[0004] Before being shipped as a product, semiconductor memories undergo various tests, including aging tests, to improve yield and quality. During aging tests, the same drive voltage is applied to the core / peripheral circuitry and memory cell regions. Additionally, to save testing time, the test voltage used in aging tests may be higher than the normal operating voltage of the semiconductor memory. Therefore, during aging tests, memory cells that operate normally when the normal operating voltage is applied may be considered defective. Summary of the Invention

[0005] Example embodiments of this disclosure provide a memory device including word line isolation circuitry capable of isolating the memory cell array from the core / peripheral circuitry during aging tests.

[0006] According to one aspect of an example embodiment, an aging test method for a memory device is provided, the memory device including a memory cell array, a word line isolation circuit, and a sub-word line driver circuit, the aging test method comprising: performing a first aging test by controlling the word line isolation circuit to a cutoff state and outputting a first test voltage from the sub-word line driver circuit; and performing a second aging test by changing the word line isolation circuit to a conduction state and outputting a second test voltage lower than the first test voltage from the sub-word line driver circuit.

[0007] According to one aspect of an example embodiment, a memory device is provided, the memory device comprising: a memory cell array including a plurality of memory cells; a plurality of word lines connected to the plurality of memory cells; a line decoder configured to: send word line drive signals to a selected word line among the plurality of word lines; a sub-word line driver circuit configured to: send word line drive signals to the selected word line; and a word line isolation circuit configured to: selectively connect the plurality of word lines to the sub-word line driver circuit or disconnect the plurality of word lines from the sub-word line driver circuit based on an isolation signal during an aging test.

[0008] According to one aspect of an example embodiment, an aging test method for a memory device is provided. The memory device includes: a memory cell array; multiple word lines connected to a plurality of memory cells included in the memory cell array; sub-word line driver circuitry configured to send word line drive signals to the multiple word lines; and word line isolation circuitry configured to selectively connect or disconnect the multiple word lines from the sub-word line driver circuitry based on the isolation signals. The aging test method includes: disconnecting the multiple word lines from the sub-word line driver circuitry via the word line isolation circuitry based on the memory device being in a wafer fabrication process, and outputting a first test voltage via the sub-word line driver circuitry; disconnecting the multiple word lines from the sub-word line driver circuitry via the word line isolation circuitry based on the memory device being in a package fabrication process, and outputting a second test voltage lower than the first test voltage via the sub-word line driver circuitry; and connecting the multiple word lines to the sub-word line driver circuitry via the word line isolation circuitry based on the memory device being in a module fabrication process, and outputting a third test voltage lower than the second test voltage via the sub-word line driver circuitry. Attached Figure Description

[0009] The above and other objects and features of this disclosure will become clear from the detailed description of embodiments thereof with reference to the accompanying drawings.

[0010] Figure 1 This is a block diagram illustrating a storage device according to one or more example embodiments.

[0011] Figure 2 This illustrates one or more example embodiments. Figure 1 A diagram of a memory device.

[0012] Figure 3 It is shown Figure 2 A diagram illustrating an example embodiment of the arrangement between the sub-word line driver circuit and the word line isolation circuit.

[0013] Figure 4 This illustrates one or more example embodiments. Figure 3 A diagram illustrating the connection relationships of part A in the diagram.

[0014] Figure 5 This illustrates one or more example embodiments. Figure 3 A diagram illustrating the connection relationships of part B in the diagram.

[0015] Figure 6 It is shown in Figure 3 A diagram illustrating the operation of the word line isolation circuit during the first operating mode of the memory device.

[0016] Figure 7 It is shown in Figure 3 A diagram illustrating the operation of the word line isolation circuit during the second operating mode of the memory device.

[0017] Figure 8 It is shown in Figure 3 A diagram illustrating the operation of the word line isolation circuit during the standby mode of a memory device.

[0018] Figure 9 It is shown in Figure 3 A diagram illustrating the operation of the word line isolation circuit during the first test mode of the memory device.

[0019] Figure 10 It is shown in Figure 3 A diagram illustrating the operation of the word line isolation circuit during the second test mode of the memory device.

[0020] Figure 11 It is shown Figure 1 A flowchart of an example embodiment of an aging test method for a memory device.

[0021] Figure 12 It is shown Figure 1 A flowchart of another example embodiment of the aging test method for memory devices.

[0022] Figure 13 This illustrates one or more example embodiments. Figure 3 A diagram illustrating the connection relationships of part A in the diagram.

[0023] Figure 14 This illustrates one or more example embodiments. Figure 3 A diagram illustrating the connection relationships of part B in the diagram.

[0024] Figure 15 It is shown Figure 1 A block diagram of an example embodiment of a memory device.

[0025] Figure 16 It is shown Figure 1A block diagram of another example embodiment of the memory device. Detailed Implementation

[0026] Hereinafter, exemplary embodiments of the present disclosure will be described in detail and clearly to the extent that those skilled in the art can readily implement the present disclosure.

[0027] Figure 1 This is a block diagram illustrating a storage device according to an exemplary embodiment of the present disclosure. (Refer to...) Figure 1 The storage device 1000 may include a memory device 1100 and a memory controller 1200.

[0028] The memory device 1100 can receive input / output signals IO from the memory controller 1200 via input / output lines, receive control signals CTRL via control lines, and receive external power supply PWR via power lines. The memory device 1000 can store data in the memory device 1100 under the control of the memory controller 1200.

[0029] The memory device 1100 may include a memory cell array 1110 and core / peripheral circuitry 1115. The memory cell array 1110 may have a planar two-dimensional (2D) structure or a vertical three-dimensional (3D) structure. The memory cell array 1110 may include a plurality of memory cells. The memory cell array 1110 may be placed next to or above the core / peripheral circuitry 1115.

[0030] The memory device 1100 may be a volatile memory device (such as dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate (DDR) DRAM, DDR SDRAM, low power double data rate (LPDDR) SDRAM, graphics double data rate (GDDR) SDRAM, Rambus dynamic random access memory (RDRAM), and static random access memory (SRAM), etc.).

[0031] Alternatively, the memory device 1100 may be implemented as a non-volatile memory device (such as resistive RAM (RRAM), phase-change memory (PRAM), magnetoresistive memory (MRAM), ferroelectric memory (FRAM), spin-transfer torque RAM (STT-RAM), etc.). In this specification, exemplary embodiments of the present disclosure have been described with respect to DRAM, but the exemplary embodiments are not limited thereto.

[0032] The core / peripheral circuitry 1115 may include analog and / or digital circuitry configured to store data in and / or read data stored in the memory cell array 1110. The core / peripheral circuitry 1115 may receive an external power supply PWR via a power line and generate internal power at various levels based on the external power supply PWR.

[0033] The core / peripheral circuitry 1115 can receive data from the memory controller 1200 via input / output lines. The core / peripheral circuitry 1115 can store data in the memory cell array 1110 according to the control signal CTRL. Optionally or additionally, the core / peripheral circuitry 1115 can read data stored in the memory cell array 1110 and provide the read data to the memory controller 1200.

[0034] The core / peripheral circuitry 1115 may include sub-word line driver (SWD) circuitry 1190. For example, multiple memory cells included in the memory cell array 1110 may receive control signals from the row decoder included in the core / peripheral circuitry 1115 via multiple word lines. However, as the resistance of the word lines increases, the resistor-capacitor (RC) delay can increase, and the output stage of the row decoder configured to drive the word lines needs to be increased. Therefore, high power consumption is required to charge all word lines to a high voltage and discharge all word lines from the high voltage.

[0035] Therefore, optimization of word line length is necessary to reduce word line resistance, and multiple word lines can be divided into sub-word lines of appropriate length to have a hierarchical word line structure. Sub-word line driver circuit 1190 can send drive signals (e.g., word line drive signals) received from the line decoder to the sub-word lines in the hierarchical word line structure.

[0036] When the sub-word line driver circuit 1190 is connected to the sub-word line, the same test voltage can be applied to the core / peripheral circuitry 1115 and the memory cell array 1110 during burn-in testing. To save testing time and ensure the reliability of the core / peripheral circuitry 1115, a test voltage higher than the operating voltage (e.g., normal operating voltage) of the memory device 1100 can be applied during burn-in testing. However, the memory cells included in the memory cell array 1110 may require lower reliability than the core / peripheral circuitry 1115. Therefore, during burn-in testing, an excessive number of memory cells included in the memory cell array 1110 may be unnecessarily detected as defective.

[0037] The core / peripheral circuitry 1115 may include word line isolation (WL ISO) circuitry 100. Word line isolation circuitry 100 may connect sub-word lines to or isolate sub-word lines from sub-word line driver circuitry 1190 based on isolation signals (e.g., isolation control signals). For example, during aging tests, word line isolation circuitry 100 may isolate sub-word lines from sub-word line driver circuitry 1190. During normal operation (e.g., after product shipment), word line isolation circuitry 100 may connect sub-word lines to sub-word line driver circuitry 1190. Therefore, during aging tests, the number of memory cells in the memory device 1100 that could be unnecessarily considered defective may be reduced. Additionally, various and / or complex test environments may be configured for the core / peripheral circuitry 1115 and / or memory cell array 1110 during aging tests.

[0038] As an example, the core / peripheral circuitry 1115 may include core circuitry and peripheral circuitry. Sub-word line driver circuitry 1190 and word line isolation circuitry 100 may be included in the core circuitry. The remaining portion of the core / peripheral circuitry 1115, excluding the core circuitry (e.g., row decoder, column decoder, and / or control logic, etc.), may be referred to as peripheral circuitry.

[0039] Figure 2 This illustrates an example embodiment. Figure 1 A diagram of a memory device. (Refer to...) Figure 2 The memory device 1100 may include a memory cell array 1110, a row decoder 1121, and a column decoder 1122. Furthermore, the memory device 1100 may include a sub-word line driver circuit 1190 and a word line isolation circuit 100 disposed between the memory cell array 1110 and the row decoder 1121.

[0040] The memory cell array 1110 may include a plurality of memory cells arranged in a matrix of rows and columns. For example, the memory cell array 1110 may include a plurality of word lines WL and a plurality of bit lines BL connected to the memory cells. The plurality of word lines WL may be connected to rows of the memory cells, and the plurality of bit lines BL may be connected to columns of the memory cells.

[0041] The row decoder 1121 can be selectively connected to one of the multiple word lines WL of the memory cell array 1110. The row decoder 1121 can handle multiple word lines including those from... Figure 1 The memory controller 1200 decodes the row address received from the address, selects a word line corresponding to the row address, and activates the selected word line. In one embodiment, the row decoder 1121 can send a word line drive signal to the selected word line.

[0042] The column decoder 1122 can select one of the multiple bit lines BL of the memory cell array 1110. The column decoder 1122 can decode the column address included in the address received from the memory controller 1200 and select the bit line corresponding to the column address.

[0043] The multiple word lines (WLs) connected to the memory cell array 1110 may have a hierarchical structure. For example, the multiple word lines (WLs) may include a global word line (GWL), an intermediate word line (MWL), and a sub-word line (SWL). The global word line (GWL) may be connected between the row decoder 1121 and the sub-word line driver circuit 1190. The intermediate word line (MWL) may be connected between the sub-word line driver circuit 1190 and the word line isolation circuit 100. The sub-word line (SWL) may be connected between the word line isolation circuit 100 and the memory cell array 1110.

[0044] The sub-word line driver circuit 1190 may include multiple sub-word line drivers. For example, a portion of the multiple sub-word line drivers (e.g., eight) may be connected to a global word line GWL. The multiple sub-word line drivers may be connected one-to-one to multiple intermediate word lines MWL.

[0045] Word line isolation circuit 100 may include multiple word line isolation switches (or transistors). For example, the multiple word line isolation switches may be connected one-to-one with multiple intermediate word lines MWL. Each of the multiple intermediate word lines MWL (or multiple sub-word lines SWL) may be connected to multiple memory cells included in memory cell array 1110.

[0046] Figure 3 It is shown Figure 2 A diagram illustrating an example embodiment of the arrangement between the sub-word line driver circuit and the word line isolation circuit. Figure 4 This illustrates an example embodiment. Figure 3 A diagram illustrating the connection relationships of part A in the diagram. Figure 5 This illustrates an example embodiment. Figure 3 A diagram illustrating the connection relationships of part B in the diagram.

[0047] Reference Figures 3 to 5 , Figure 2 The memory cell array 1110 may include multiple memory cell (MC) blocks. As an example, the multiple memory cell blocks may include a first memory cell block 1111 and / or a second memory cell block 1112. The sub-word line driver circuit 1190 may include a first sub-word line driver circuit 1191 and / or a second sub-word line driver circuit 1192. The word line isolation circuit 100 may include a first word line isolation circuit 110, a second word line isolation circuit 120, and / or a third word line isolation circuit 130.

[0048] Reference Figure 3 and Figure 4The first sub-word line driver circuit 1191 may be disposed at the edge of the memory cell array 1110. For example, the first sub-word line driver circuit 1191 may be disposed on one side of the first memory cell block 1111. The first sub-word line driver circuit 1191 may provide word line drive signals to a portion of the sub-word lines connected to the first memory cell block 1111.

[0049] The first sub-word line driver circuit 1191 may include a plurality of sub-word line drivers, including the first sub-word line driver SWD_1. As an example, the first sub-word line driver SWD_1 may receive word line drive signals via a first global word line GWL_1. The first sub-word line driver SWD_1 may be connected to a first intermediate word line MWL_1.

[0050] The first word line isolation circuit 110 may include a plurality of word line isolation switches, including a first word line isolation switch ISO_SW_1. As an example, the first word line isolation switch ISO_SW_1 may be connected to a first intermediate word line MWL_1. Additionally, the first word line isolation switch ISO_SW_1 may be connected to a first sub-word line SWL_1. The first sub-word line SWL_1 may be connected to a portion of a memory cell included in the first memory cell block 1111. The first word line isolation switch ISO_SW_1 may isolate (or disconnect) the first sub-word line SWL_1 from the first intermediate word line MWL_1 and / or the first sub-word line driver SWD_1 based on a first isolation signal ISO1.

[0051] Reference Figure 3 and Figure 5 The second sub-word line driver circuit 1192 can be disposed between two memory cell blocks. For example, the second sub-word line driver circuit 1192 can be disposed between the first memory cell block 1111 and the second memory cell block 1112. The second sub-word line driver circuit 1192 can provide word line drive signals to a portion of the sub-word line connected to the first memory cell block 1111. Additionally, the second sub-word line driver circuit 1192 can provide word line drive signals to a portion of the sub-word line connected to the second memory cell block 1112.

[0052] The second sub-word line driver circuit 1192 may include a plurality of sub-word line drivers, including the second sub-word line driver SWD_2. As an example, the second sub-word line driver SWD_2 may receive word line drive signals via the second global word line GWL_2. The second sub-word line driver SWD_2 may be connected to the second intermediate word line MWL_2. Additionally, the second sub-word line driver SWD_2 may be connected to the third intermediate word line MWL_3. That is, the second sub-word line driver SWD_2 may send the word line drive signals received via the second global word line GWL_2 to the second intermediate word line MWL_2 and the third intermediate word line MWL_3.

[0053] The second word line isolation circuit 120 may include a plurality of word line isolation switches, including a second word line isolation switch ISO_SW_2. As an example, the second word line isolation switch ISO_SW_2 may be connected to a second intermediate word line MWL_2. Additionally, the second word line isolation switch ISO_SW_2 may be connected to a second sub-word line SWL_2. The second sub-word line SWL_2 may be connected to a portion of a memory cell included in the first memory cell block 1111. The second word line isolation switch ISO_SW_2 may isolate (or disconnect) the second sub-word line SWL_2 from the second intermediate word line MWL_2 and / or the second sub-word line driver SWD_2 based on a second isolation signal ISO2.

[0054] The third word line isolation circuit 130 may include a plurality of word line isolation switches, including a third word line isolation switch ISO_SW_3. As an example, the third word line isolation switch ISO_SW_3 may be connected to a third intermediate word line MWL_3. Additionally, the third word line isolation switch ISO_SW_3 may be connected to a third sub-word line SWL_3. The third sub-word line SWL_3 may be connected to a portion of a memory cell included in the second memory cell block 1112. The third word line isolation switch ISO_SW_3 may isolate (or disconnect) the third sub-word line SWL_3 from the third intermediate word line MWL_3 and / or the second sub-word line driver SWD_2 based on a third isolation signal ISO3.

[0055] Figure 6 It is shown in Figure 3 A diagram illustrating the operation of the word line isolation circuit during the first operating mode of the memory device. Figure 7 It is shown in Figure 3 A diagram illustrating the operation of the word line isolation circuit during the second operating mode of the memory device. (Refer to...) Figure 6 and Figure 7 The operation of the second word line isolation switch ISO_SW_2 and the third word line isolation switch ISO_SW_3 connected to the second sub-word line driver SWD_2 is described according to an example embodiment. However, the word line isolation switches included in the memory device 1100 may operate in the same way as the second word line isolation switch ISO_SW_2 and / or the third word line isolation switch ISO_SW_3.

[0056] As an example, the second word line isolation switch ISO_SW_2 may include a second word line isolation transistor ISO_TR_2. The third word line isolation switch ISO_SW_3 may include a third word line isolation transistor ISO_TR_3. The second word line isolation transistor ISO_TR_2 and / or the third word line isolation transistor ISO_TR_3 may be implemented as N-type transistors. However, this is just an example, and the second word line isolation transistor ISO_TR_2 and / or the third word line isolation transistor ISO_TR_3 may be implemented as P-type transistors.

[0057] Reference Figure 6 In the first operating mode, the second word line isolation switch ISO_SW_2 and the third word line isolation switch ISO_SW_3 can be turned on (e.g., "ON"). For example, a second isolation signal ISO2 with a first power supply voltage VPP1 can be input to the gate of the second word line isolation transistor ISO_TR_2. A third isolation signal ISO3 with a first power supply voltage VPP1 can be input to the gate of the third word line isolation transistor ISO_TR_3. Therefore, the voltage of the second intermediate word line MWL_2 (e.g., the first power supply voltage VPP1 or ground voltage VBB) can be transmitted to the second sub-word line SWL_2 as is. The voltage of the third intermediate word line MWL_3 (e.g., the first power supply voltage VPP1 or ground voltage VBB) can be transmitted to the third sub-word line SWL_3 as is.

[0058] Reference Figure 7 In the second operating mode, the second word line isolation switch ISO_SW_2 and the third word line isolation switch ISO_SW_3 are turned on. The output voltage of the second sub-word line driver SWD_2 (e.g., the first power supply voltage VPP1 or ground voltage VBB) can be transmitted more reliably in the second operating mode than in the first operating mode. For example, a second isolation signal ISO2 having a second power supply voltage VPP2 higher than the first power supply voltage VPP1 can be input to the gate of the second word line isolation transistor ISO_TR_2. A third isolation signal ISO3 having the second power supply voltage VPP2 can be input to the gate of the third word line isolation transistor ISO_TR_3. Therefore, the voltage of the second intermediate word line MWL_2 (e.g., the first power supply voltage VPP1 or ground voltage VBB) can be transmitted to the second sub-word line SWL_2 as is. The voltage of the third intermediate word line MWL_3 (e.g., the first power supply voltage VPP1 or ground voltage VBB) can be transmitted to the third sub-word line SWL_3 as is.

[0059] Figure 8 It is shown in Figure 3 A diagram illustrating the operation of the word line isolation circuit during the standby mode of a memory device. (Refer to...) Figure 8The operation of the second word line isolation switch ISO_SW_2 and the third word line isolation switch ISO_SW_3 connected to the second sub-word line driver SWD_2 is described according to an example embodiment. However, the word line isolation switches included in the memory device 1100 may operate in the same way as the second word line isolation switch ISO_SW_2 and / or the third word line isolation switch ISO_SW_3. During standby mode prior to aging tests, the second intermediate word line MWL_2 and the third intermediate word line MWL_3 may be set to ground voltage VBB.

[0060] During standby mode, the memory cell array 1110 can be isolated from or connected to the core / peripheral circuitry 1115. For example, during standby mode, the second word line isolation switch ISO_SW_2 and the third word line isolation switch ISO_SW_3 can be set differently.

[0061] For example, during standby mode, a second isolation signal ISO2 with a first ground bias voltage VBB1 can be input to the gate of the second word line isolation transistor ISO_TR_2. A third isolation signal ISO3 with a first ground bias voltage VBB1 can be input to the gate of the third word line isolation transistor ISO_TR_3.

[0062] As an example, the first ground bias voltage VBB1 can be set to be equal to or lower than the ground voltage VBB. Therefore, the second word line isolation transistor ISO_TR_2 and the third word line isolation transistor ISO_TR_3 can be turned off. The second sub-word line SWL_2 can be disconnected from the second intermediate word line MWL_2. The third sub-word line SWL_3 can be disconnected from the third intermediate word line MWL_3.

[0063] As another example, the first ground bias voltage VBB1 can be set higher than the ground voltage VBB. Therefore, during standby mode, the second word line isolation transistor ISO_TR_2 and the third word line isolation transistor ISO_TR_3 can be weakly turned on. The second sub-word line SWL_2 can be set to the same or similar voltage as the second intermediate word line MWL_2. The third sub-word line SWL_3 can be set to the same or similar voltage as the third intermediate word line MWL_3.

[0064] Figure 9 It is shown in Figure 3 A diagram illustrating the operation of the word line isolation circuit during the first test mode of the memory device. (Refer to...) Figure 9The operation of the second word line isolation switch ISO_SW_2 and the third word line isolation switch ISO_SW_3 connected to the second sub-word line driver SWD_2 is described according to an example embodiment. However, the word line isolation switches included in the memory device 1100 may operate in the same way as the second word line isolation switch ISO_SW_2 and / or the third word line isolation switch ISO_SW_3.

[0065] During the first test mode of the aging test, the second middle word line MWL_2 and the third middle word line MWL_3 can be set to be higher than... Figure 6 The first power supply voltage VPP1 is higher than the third power supply voltage VPP3. The third power supply voltage VPP3 may have a level set based on the reliability of the core / peripheral circuitry 1115. With the third power supply voltage VPP3, the core / peripheral circuitry 1115, including the sub-word line driver circuitry 1190, can perform aging tests using a test voltage (e.g., the third power supply voltage VPP3) that is higher than the normal operating voltage (e.g., the first power supply voltage VPP1).

[0066] During the first test mode, the memory device 1100 can isolate the memory cell array 1110 from the core / peripheral circuitry 1115. During the first test mode, the memory device 1100 can perform an aging test by driving the core / peripheral circuitry 1115 without driving the memory cell array 1110. For example, the second word line isolation switch ISO_SW_2 and the third word line isolation switch ISO_SW_3 can be turned off (e.g., "OFF"). A second isolation signal ISO2 with a second ground bias voltage VBB2 can be input to the gate of the second word line isolation transistor ISO_TR_2. A third isolation signal ISO3 with a second ground bias voltage VBB2 can be input to the gate of the third word line isolation transistor ISO_TR_3.

[0067] The second ground bias voltage VBB2 can be set to a voltage sufficient to turn off the second word line isolation switch ISO_SW_2 and the third word line isolation switch ISO_SW_3. As an example, the second ground bias voltage VBB2 can be set to be equal to or lower than the ground voltage VBB. As another example, to avoid leakage current in the GIDL (gate-induced drain leakage) region, the second ground bias voltage VBB2 can be set slightly higher than the ground voltage VBB. Therefore, the second word line isolation transistor ISO_TR_2 and the third word line isolation transistor ISO_TR_3 can be turned off. The second sub-word line SWL_2 can be isolated from the second intermediate word line MWL_2. The third sub-word line SWL_3 can be isolated from the third intermediate word line MWL_3.

[0068] Therefore, during aging tests, the number of memory cells in the memory device 1100 that could be unnecessarily considered defective can be reduced. Furthermore, various and / or complex test environments can be configured for the core / peripheral circuitry 1115 during aging tests.

[0069] Figure 10 It is shown in Figure 3 A diagram illustrating the operation of the word line isolation circuit during the second test mode of the memory device. (Refer to...) Figure 10 The operation of the second word line isolation switch ISO_SW_2 and the third word line isolation switch ISO_SW_3 connected to the second sub-word line driver SWD_2 is described according to an example embodiment. However, the word line isolation switches included in the memory device 1100 may operate in the same way as the second word line isolation switch ISO_SW_2 and / or the third word line isolation switch ISO_SW_3.

[0070] During the second test mode of the aging test, the second middle word line MWL_2 and the third middle word line MWL_3 can be set to be higher than... Figure 6 The first power supply voltage VPP1 is higher than the fourth power supply voltage VPP4. However, the fourth power supply voltage VPP4 can be set to be higher than... Figure 9 The third power supply voltage VPP3 is low. The fourth power supply voltage VPP4 may have a level set based on the reliability of the memory cells included in the memory cell array 1110.

[0071] During the second test mode, the memory device 1100 can perform an aging test using the memory cell array 1110 connected to the core / peripheral circuitry 1115. During the second test mode, the memory device 1100 can perform an aging test by driving both the memory cell array 1110 and the core / peripheral circuitry 1115. For example, the second word line isolation switch ISO_SW_2 and the third word line isolation switch ISO_SW_3 can be turned on.

[0072] During the second test mode, it has a higher performance than Figure 6 A second isolation signal ISO2, which is higher than the first power supply voltage VPP1 and the fifth power supply voltage VPP5, can be input to the gate of the second word line isolation transistor ISO_TR_2. A third isolation signal ISO3, which has the fifth power supply voltage VPP5, can be input to the gate of the third word line isolation transistor ISO_TR_3.

[0073] The fifth power supply voltage VPP5 can be set to a voltage sufficient to turn on the second word line isolation transistor ISO_TR_2 and the third word line isolation transistor ISO_TR_3. As an example, the fifth power supply voltage VPP5 can be set to be equal to the fourth power supply voltage VPP4. As another example, the fifth power supply voltage VPP5 can be set to be different from the fourth power supply voltage VPP4. Therefore, the second word line isolation transistor ISO_TR_2 and the third word line isolation transistor ISO_TR_3 can be turned on. The second sub-word line SWL_2 can be connected to the second intermediate word line MWL_2. The third sub-word line SWL_3 can be connected to the third intermediate word line MWL_3.

[0074] By using the fourth power supply voltage VPP4, the memory device 1100 can perform an aging test on the entire memory device 1100 using a test voltage (e.g., the fourth power supply voltage VPP4) that is higher than (or equal to) the normal operating voltage (e.g., the first power supply voltage VPP1) while preventing unnecessary defects in the memory cells. Therefore, during the aging test, the number of memory cells in the memory device 1100 that could be unnecessarily considered defective can be reduced. Furthermore, various and / or complex test environments can be configured for the core / peripheral circuitry 1115 and / or the memory cell array 1110 during the aging test.

[0075] Figure 11 It is shown Figure 1 A flowchart of an example embodiment of an aging test method for a memory device. (Refer to...) Figures 3 to 11 The memory device 1100 can perform aging tests in various test environments based on different reliability standards of the memory cell array 1110 and / or core / peripheral circuitry 1115.

[0076] In operation S110, the memory device 1100 can be set to a first standby mode. For example, refer to... Figure 8 In the first standby mode, the sub-word line driver circuit 1190 can output a first ground bias voltage VBB1, and the word line isolation circuit 100 can be turned on or off.

[0077] In operation S120, the memory device 1100 can perform an aging test in the first test mode. For example, refer to... Figure 9 The word line isolation circuit 100 can be turned off. Therefore, the memory cell array 1110 can be isolated from the core / peripheral circuitry 1115. In the first test mode, the core / peripheral circuitry 1115 can perform an aging test using a first test voltage (e.g., a third power supply voltage VPP3).

[0078] In operation S130, the memory device 1100 can be set to a second standby mode. For example, refer to... Figure 8The second standby mode can be configured in a substantially similar manner to the first standby mode. For example, in the second standby mode, the word line isolation circuit 100 can be turned on.

[0079] In operation S140, the memory device 1100 can perform an aging test in the second test mode. For example, refer to... Figure 10 The word line isolation circuit 100 can be turned on. Therefore, the memory cell array 1110 can be connected to the core / peripheral circuitry 1115. In the second test mode, the memory cell array 1110 and the core / peripheral circuitry 1115 can perform aging tests using a second test voltage (e.g., a fourth power supply voltage VPP4) that is lower than the first test voltage.

[0080] In operation S150, the memory device 1100 can be set to normal operating mode. For example, refer to... Figure 6 or Figure 7 The word line isolation circuit 100 can remain in the on state. The control voltage of the word line isolation circuit 100 can be changed in different ways.

[0081] Figure 12 It is shown Figure 1 A flowchart of another example embodiment of the aging test method for a memory device. See also... Figures 3 to 10 and Figure 12 The memory device 1100 can undergo aging tests in various test environments based on different reliability criteria of the memory cell array 1110 and / or core / peripheral circuitry 1115. Additionally, the memory device 1100 can undergo aging tests in various manufacturing processes.

[0082] In operation S210, the memory device 1100 can undergo aging tests at the wafer level. For example, in the wafer fabrication process, the memory device 1100 can be... Figure 11 The aging test method is used to perform the aging test. In the first test mode, the first wafer test voltage can be used as the first test voltage. In the second test mode, the second wafer test voltage can be used as the second test voltage.

[0083] In operation S220, memory device 1100 can perform aging tests at the package level. For example, during the process of manufacturing the package, memory device 1100 can... Figure 11 The aging test method is used to perform the aging test. In the first test mode, the first package test voltage can be used as the first test voltage. As an example, the first package test voltage can be set lower than the first wafer test voltage. In the second test mode, the second package test voltage can be used as the second test voltage. As an example, the second package test voltage can be set lower than the second wafer test voltage.

[0084] In operation S230, memory device 1100 can perform aging tests at the module level. For example, in the process of manufacturing the module, memory device 1100 can... Figure 11 The aging test method is used to perform the aging test. In the first test mode, the first module test voltage can be used as the first test voltage. As an example, the first module test voltage can be set to be lower than the first package test voltage.

[0085] In the second test mode, the second module test voltage can be used as the second test voltage. As an example, the second module test voltage can be set lower than the second package test voltage. As another example, the second module test voltage can be set equal to the normal operating voltage of the memory device 1100. The module-level second test mode can be configured to have a longer test time than the wafer-level or package-level second test modes.

[0086] Although presented as separate steps, Figure 11 or Figure 12 The steps in the flowchart may occur simultaneously or in a different order than that shown herein. In one embodiment, the steps may be rearranged, other steps may be included between the steps shown, steps may be omitted or replaced, etc.

[0087] Figure 13 This illustrates an example embodiment. Figure 3 A diagram illustrating the connection relationships of part A in the diagram. Figure 14 This illustrates an example embodiment. Figure 3 A diagram illustrating the connection relationships of part B in the diagram.

[0088] Reference Figure 3 , Figure 13 and Figure 14 The multiple memory cell blocks may include a first memory cell block 1111 and / or a second memory cell block 1112. The sub-word line driver circuit 1190 may include a first sub-word line driver circuit 1191 and / or a second sub-word line driver circuit 1192. The word line isolation circuit 100 may include a first word line isolation circuit 110, a second word line isolation circuit 120, and / or a third word line isolation circuit 130.

[0089] Reference Figure 3 and Figure 13 The first sub-word line driver circuit 1191 may be disposed at the edge of the memory cell array 1110. For example, the first sub-word line driver circuit 1191 may be disposed on one side of the first memory cell block 1111. The first sub-word line driver circuit 1191 may provide word line drive signals to a portion of the sub-word lines connected to the first memory cell block 1111.

[0090] The first sub-word line driver circuit 1191 may include a plurality of sub-word line drivers, including the first sub-word line driver SWD_1. As an example, the first sub-word line driver SWD_1 may receive word line drive signals via a first global word line GWL_1. The first sub-word line driver SWD_1 may be connected to a first intermediate word line MWL_1.

[0091] The first word line isolation circuit 110 can connect the intermediate word line and the sub-word line via multiple word line isolation switches. As an example, the eleventh word line isolation switch ISO_SW_11 can be connected to the first intermediate word line MWL_1. The eleventh word line isolation switch ISO_SW_11 can be connected in series with the twelfth word line isolation switch ISO_SW_12. The twelfth word line isolation switch ISO_SW_12 can be connected to the first sub-word line SWL_1.

[0092] The first sub-word line SWL_1 can be connected to a portion of the memory cells included in the first memory cell block 1111. The eleventh word line isolation switch ISO_SW_11 and the twelfth word line isolation switch ISO_SW_12 can isolate (or disconnect) the first sub-word line SWL_1 from the first intermediate word line MWL_1 and / or the first sub-word line driver SWD_1. For example, the eleventh word line isolation switch ISO_SW_11 can be turned on or off based on the eleventh isolation signal ISO11. The twelfth word line isolation switch ISO_SW_12 can be turned on or off based on the twelfth isolation signal ISO12. As an example, the eleventh isolation signal ISO11 and the twelfth isolation signal ISO12 can be set to the same voltage level. As another example, the eleventh isolation signal ISO11 and the twelfth isolation signal ISO12 can be set to different voltage levels.

[0093] Reference Figure 3 and Figure 14 The second sub-word line driver circuit 1192 can be disposed between two memory cell blocks. For example, the second sub-word line driver circuit 1192 can be disposed between the first memory cell block 1111 and the second memory cell block 1112. The second sub-word line driver circuit 1192 can provide word line drive signals to a portion of the sub-word line connected to the first memory cell block 1111. Additionally, the second sub-word line driver circuit 1192 can provide word line drive signals to a portion of the sub-word line connected to the second memory cell block 1112.

[0094] The second sub-word line driver circuit 1192 may include a plurality of sub-word line drivers, including the second sub-word line driver SWD_2. As an example, the second sub-word line driver SWD_2 may receive word line drive signals via the second global word line GWL_2. The second sub-word line driver SWD_2 may be connected to the second intermediate word line MWL_2. Additionally, the second sub-word line driver SWD_2 may be connected to the third intermediate word line MWL_3. That is, the second sub-word line driver SWD_2 may send the word line drive signals received via the second global word line GWL_2 to the second intermediate word line MWL_2 and the third intermediate word line MWL_3.

[0095] The second word line isolation circuit 120 can connect the intermediate word line and the sub-word line via multiple word line isolation switches. As an example, the twenty-first word line isolation switch ISO_SW_21 can be connected to the second intermediate word line MWL_2. The twenty-first word line isolation switch ISO_SW_21 can be connected in series with the twenty-second word line isolation switch ISO_SW_22. The twenty-second word line isolation switch ISO_SW_22 can be connected to the second sub-word line SWL_2.

[0096] The second sub-word line SWL_2 can be connected to a portion of the memory cell included in the first memory cell block 1111. The twenty-first word line isolation switch ISO_SW_21 and the twenty-second word line isolation switch ISO_SW_22 can isolate (or disconnect) the second sub-word line SWL_2 from the second intermediate word line MWL_2 and / or the second sub-word line driver SWD_2. For example, the twenty-first word line isolation switch ISO_SW_21 can be turned on or off based on the twenty-first isolation signal ISO21. The twenty-second word line isolation switch ISO_SW_22 can be turned on or off based on the twenty-second isolation signal ISO22. As an example, the twenty-first isolation signal ISO21 and the twenty-second isolation signal ISO22 can be set to the same voltage level. As another example, the twenty-first isolation signal ISO21 and the twenty-second isolation signal ISO22 can be set to different voltage levels.

[0097] The third word line isolation circuit 130 can connect the intermediate word line and the sub-word line via multiple word line isolation switches. As an example, the thirty-first word line isolation switch ISO_SW_31 can be connected to the third intermediate word line MWL_3. The thirty-first word line isolation switch ISO_SW_31 can be connected in series with the thirty-second word line isolation switch ISO_SW_32. The thirty-second word line isolation switch ISO_SW_32 can be connected to the third sub-word line SWL_3.

[0098] The third sub-word line SWL_3 can be connected to a portion of the memory cell included in the second memory cell block 1112. The thirty-first word line isolation switch ISO_SW_31 and the thirty-second word line isolation switch ISO_SW_32 can isolate (or disconnect) the third sub-word line SWL_3 from the third intermediate word line MWL_3 and / or the second sub-word line driver SWD_2. For example, the thirty-first word line isolation switch ISO_SW_31 can be turned on or off based on the thirty-first isolation signal ISO31. The thirty-second word line isolation switch ISO_SW_32 can be turned on or off based on the thirty-second isolation signal ISO32. As an example, the thirty-first isolation signal ISO31 and the thirty-second isolation signal ISO32 can be set to the same voltage level. As another example, the thirty-first isolation signal ISO31 and the thirty-second isolation signal ISO32 can be set to different voltage levels.

[0099] Figure 15 It is shown Figure 1 A block diagram of an example embodiment of a memory device. (Refer to...) Figure 1 and Figure 15 The memory device 1100 may include a memory cell array 1110 and core / peripheral circuitry 1115. Core / peripheral circuitry 1115 may include an address buffer 1120, a row decoder 1121, a column decoder 1122, a bit-line sense amplifier (BLSA) 1130, a command decoder 1140, control logic 1150, and input / output (I / O) circuitry 1160. Additionally, core / peripheral circuitry 1115 may include sub-word line driver circuitry 1190 and word line isolation circuitry 100.

[0100] The memory cell array 1110 may include a plurality of memory cells arranged in a matrix of rows and columns. For example, the memory cell array 1110 may include a plurality of word lines WL and a plurality of bit lines BL connected to the plurality of memory cells. The plurality of word lines WL may be connected to rows of memory cells, and the plurality of bit lines BL may be connected to columns of memory cells.

[0101] Address buffer 1120 can be from Figure 1 The memory controller 1200 receives an address ADDR. For example, the address ADDR may include a row address RA for addressing rows of the memory cell array 1110 and a column address CA for addressing columns of the memory cell array 1110. The address buffer 1120 may send the row address RA to the row decoder 1121 and the column address CA to the column decoder 1122.

[0102] The row decoder 1121 can select one of the multiple word lines WL connected to the memory cell array 1110. The row decoder 1121 can decode the row address RA received from the address buffer 1120, select the word line corresponding to the row address RA, and activate the selected word line.

[0103] The column decoder 1122 can select one of the multiple bit lines BL connected to the memory cell array 1110. The column decoder 1122 can decode the column address CA received from the address buffer 1120 and select the bit line BL corresponding to the column address CA.

[0104] Bit line sense amplifier 1130 can be connected to a bit line BL of memory cell array 1110. For example, bit line sense amplifier 1130 can detect voltage changes of selected bit lines among multiple bit lines BL, amplify the voltage changes, and output an amplified signal (e.g., amplified voltage changes).

[0105] Command decoder 1140 can decode write enable signals ( / WE), row address strobe signals ( / RAS), column address strobe signals ( / CAS), chip select signals ( / CS), etc., received from memory controller 1200, so that control signals corresponding to command CMD will be generated in control logic 1150. Command CMD may include activation requests, read requests, write requests, and / or precharge requests, etc.

[0106] Control logic 1150 can control the overall operation of bit line sense amplifier 1130 and / or input / output circuitry 1160 via control signals corresponding to command CMD. Additionally, control logic 1150 can control the overall operation of memory device 1100.

[0107] Input / output circuitry 1160 can output data DATA to memory controller 1200 via a data pad based on the sensed and amplified voltage from bit-line sense amplifier 1130. For example, input / output circuitry 1160 may include an input buffer or an output buffer. Input / output circuitry 1160 can perform serialization or deserialization operations on data DATA.

[0108] Sub-word line driver circuit 1190 receives word line drive signals from line decoder 1121. When sub-word line driver circuit 1190 is connected to a word line, the same test voltage can be applied to the core / peripheral circuitry 1115 and memory cell array 1110 during aging tests. To save test time and ensure the reliability of core / peripheral circuitry 1115, a test voltage higher than the operating voltage of memory device 1100 can be applied during aging tests. However, the memory cells included in memory cell array 1110 may require lower reliability than core / peripheral circuitry 1115. Therefore, during aging tests, an excessive number of memory cells included in memory cell array 1110 may be unnecessarily detected as defective.

[0109] The core / peripheral circuitry 1115 may include word line isolation circuitry 100. For example... Figures 3 to 14 As described, word line isolation circuit 100 can connect word lines to sub-word line driver circuit 1190 or isolate word lines from sub-word line driver circuit 1190. For example, during aging tests, word line isolation circuit 100 can isolate word lines from sub-word line driver circuit 1190. During normal operation (e.g., after product shipment), word line isolation circuit 100 can connect word lines to sub-word line driver circuit 1190. Therefore, during aging tests, the number of memory cells in the memory device 1100 that could be unnecessarily considered defective can be reduced. Additionally, during aging tests, various and / or complex test environments can be set for the core / peripheral circuitry 1115 and / or memory cell array 1110.

[0110] Figure 16 It is shown Figure 1 A block diagram of another example embodiment of the memory device. Figure 1 The storage device 1000 can be a flash memory-based flash memory device. For example, the storage device 1000 can be implemented as a solid-state drive (SSD), universal flash memory (UFS), memory card, etc.

[0111] Reference Figure 1 and Figure 16 The memory device 1100 may include a memory cell array 1110 and core / peripheral circuitry 1115. Core / peripheral circuitry 1115 may include an address decoder 1170, a page buffer circuitry 1180, an input / output circuitry 1160, a word line voltage generator 1151, and control logic 1150. Furthermore, core / peripheral circuitry 1115 may include sub-word line driver circuitry 1190 and word line isolation circuitry 100.

[0112] The memory cell array 1110 may include multiple memory blocks BLK1 to BLKn (where n is a natural number greater than 1). Each memory block may include multiple pages. Each page may include multiple memory cells. Each memory cell may store multiple bits of data. Each memory block may be an erase unit, and each page may be a read or write unit.

[0113] The memory cell array 1110 may be formed in a direction perpendicular to the substrate. Gate electrode layers and insulating layers may be alternately disposed on the substrate. Each memory block (e.g., BLK1) may be connected to one or more string select lines SSL, multiple word lines WL1 to WLm (where m is a natural number greater than 1), and one or more ground select lines GSL. WLk is the selected word line, and the remaining word lines WL1 to WLk-1 and WLk+1 to WLm are the unselected word lines.

[0114] Address decoder 1170 can be connected to memory cell array 1110 via serial select line SSL, ground select line GSL, and word lines WL1 to WLm. Address decoder 1170 can select word lines during programming or read operations. Address decoder 1170 can receive word line voltage VWL from word line voltage generator 1151 and supply word line voltage VWL (e.g., programming or read voltage) to the selected word line.

[0115] Page buffer circuit 1180 can be connected to memory cell array 1110 via bit lines BL1 to BLz (where z is a natural number greater than 1). Page buffer circuit 1180 can temporarily store data to be stored in or read from memory cell array 1110. Page buffer circuit 1180 may include page buffers PB1 to PBz connected to each bit line. Each page buffer may include multiple latches for storing or reading multi-bit data.

[0116] The input / output circuit 1160 can be internally connected to the page buffer circuit 1180 via data lines, and externally connected to the memory controller (e.g., ) via input / output lines IO1 to IOj (where j is a natural number greater than 1). Figure 1 (1200 in the original text). Input / output circuit 1160 can receive programming data from memory controller 1200 during programming operations. Moreover, input / output circuit 1160 can provide data read from memory cell array 1110 to memory controller 1200 during read operations.

[0117] The word line voltage generator 1151 receives internal power from the control logic 1150 and generates the word line voltage VWL required for reading or writing data. The word line voltage VWL can be provided to the selected word line sWL or the unselected word line uWL via the address decoder 1170.

[0118] The word line voltage generator 1151 may include a programming voltage generator and a pass voltage generator. The programming voltage generator generates a programming voltage supplied to the selected word line sWL during programming operations. The pass voltage generator generates a pass voltage supplied to the selected word line sWL and the unselected word line uWL.

[0119] Word line voltage generator 1151 may include a read voltage generator and a read pass voltage generator. The read voltage generator generates a selected read voltage for the selected word line sWL during a read operation. The read pass voltage generator generates a read pass voltage for the unselected word line uWL. The read pass voltage may be a voltage sufficient to turn on a memory cell connected to the unselected word line uWL during a read operation.

[0120] Control logic 1150 can use commands CMD, addresses ADDR, and / or control signals CTRL provided from memory controller 1200 to control the operation of memory device 1100 (such as reading, writing, and erasing). Address ADDR may include a block selection address for selecting a memory block, a row address for selecting a page, and / or a column address for selecting a memory cell.

[0121] Sub-word line driver circuit 1190 receives word line drive signals from address decoder 1170. When sub-word line driver circuit 1190 is connected to a word line, the same test voltage can be applied to core / peripheral circuitry 1115 and memory cell array 1110 during aging tests. To save test time and ensure the reliability of core / peripheral circuitry 1115, a test voltage higher than the operating voltage of memory device 1100 can be applied during aging tests. However, the memory cells included in memory cell array 1110 may require lower reliability than core / peripheral circuitry 1115. Therefore, during aging tests, an excessive number of defective memory cells among those included in memory cell array 1110 may be unnecessarily detected as defective.

[0122] The core / peripheral circuitry 1115 may include word line isolation circuitry 100. For example... Figures 3 to 14As described, word line isolation circuit 100 can connect word lines to sub-word line driver circuit 1190 or isolate word lines from sub-word line driver circuit 1190. For example, during aging tests, word line isolation circuit 100 can isolate word lines from sub-word line driver circuit 1190. During normal operation (e.g., after product shipment), word line isolation circuit 100 can connect word lines to sub-word line driver circuit 1190. Therefore, during aging tests, the number of memory cells in the memory device 1100 that could be unnecessarily considered defective can be reduced. Additionally, during aging tests, various and / or complex test environments can be set for the core / peripheral circuitry 1115 or the memory cell array 1110.

[0123] According to this disclosure, aging tests can be performed on core / peripheral circuits and memory cell arrays using different test voltages.

[0124] According to this disclosure, the number of memory cells that may be unnecessarily considered defective during aging tests can be reduced.

[0125] According to this disclosure, aging tests can be performed efficiently based on the characteristics of the core / peripheral circuitry and memory cell array.

[0126] Although this disclosure has been described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made to this disclosure without departing from the spirit and scope of this disclosure as set forth in the appended claims and their equivalents.

Claims

1. An aging test method for a memory device, the memory device comprising a memory cell array, word line isolation circuitry, and sub-word line driver circuitry, the aging test method comprising: The first aging test is performed by controlling the word line isolation circuit to the off state and outputting the first test voltage from the sub-word line driver circuit. as well as The second aging test is performed by changing the word line isolation circuit to the on state and outputting a second test voltage that is lower than the first test voltage from the sub-word line driver circuit.

2. The aging test method as described in claim 1, further comprising: After performing the second aging test: Normal operating mode is performed by keeping the word line isolation circuit in the on state.

3. The aging test method as described in claim 1, further comprising: After performing the first aging test: The word line isolation circuit is controlled to standby mode by changing the word line isolation circuit to the on state and outputting ground voltage from the sub-word line driver circuit.

4. The aging test method as described in claim 1, wherein, The second test voltage is higher than or equal to the operating voltage of the memory device.

5. The aging test method as described in claim 1, wherein, The step of outputting the first test voltage includes: outputting a first test voltage whose level is based on the reliability of the core / peripheral circuitry, including the sub-word line driver circuitry.

6. The aging test method as described in claim 1, wherein, The step of outputting the second test voltage includes: outputting a second test voltage whose level is based on the reliability of the memory cells in the memory cell array included in the memory device.

7. The aging test method as described in claim 1, wherein, Word line isolation circuitry is located between the sub-word line driver circuitry and the word lines connected to the memory cell array.

8. The aging test method according to any one of claims 1 to 7, wherein, The steps for performing the second aging test include: controlling the word line isolation circuit to be in an on state based on the isolation signal applied to the word line isolation circuit to transmit the second test voltage.

9. A memory device, comprising: A memory cell array, comprising multiple memory cells; Multiple word lines are connected to the multiple memory cells; The line decoder is configured to send word line drive signals to a selected word line among the plurality of word lines; The sub-word line driver circuit is configured to send a word line drive signal to the selected word line; as well as The word line isolation circuit is configured to selectively connect the plurality of word lines to the sub-word line driver circuit or disconnect the plurality of word lines from the sub-word line driver circuit based on the isolation signal during aging tests.

10. The memory device of claim 9, wherein, The word line isolation circuit is also configured to be turned on or off in the standby mode during aging tests.

11. The memory device of claim 9, wherein, In the first test mode of the aging test, the sub-word line driver circuit is also configured to output a first test voltage, and the word line isolation circuit is turned off to disconnect the multiple word lines from the sub-word line driver circuit.

12. The memory device of claim 11, wherein, The first test voltage is higher than the normal operating voltage of the sub-word line driver circuit.

13. The memory device of claim 11, wherein, The level of the first test voltage is based on the reliability of the core / peripheral circuitry, including the sub-word line driver circuitry.

14. The memory device of claim 11, wherein, In the second test mode of the aging test, the sub-word line driver circuit is also configured to output a second test voltage that is lower than the first test voltage, and the word line isolation circuit is turned on to connect the multiple word lines to the sub-word line driver circuit.

15. The memory device of claim 14, wherein, The second test voltage is higher than the normal operating voltage of the sub-word line driver circuit.

16. The memory device of claim 14, wherein, The level of the second test voltage is based on the reliability of the plurality of memory cells.

17. The memory device according to any one of claims 9 to 16, wherein, The word line isolation circuit is also configured to remain on during normal operation.

18. An aging test method for a memory device, the memory device comprising: Memory cell array; Multiple word lines connect to multiple memory cells included in the memory cell array; Sub-word line driver circuitry is configured to send word line drive signals to the plurality of word lines; And word line isolation circuits, configured to selectively connect or disconnect the multiple word lines from the sub-word line driver circuits based on isolation signals, wherein the aging test method includes: Since the memory device is in the process of manufacturing a wafer, the multiple word lines are disconnected from the sub-word line driver circuit through the word line isolation circuit, and the first test voltage is output through the sub-word line driver circuit. Since the memory device is in the process of manufacturing a package, the multiple word lines are disconnected from the sub-word line driver circuit through a word line isolation circuit, and a second test voltage lower than the first test voltage is output through the sub-word line driver circuit; and Since the memory device is in the module manufacturing process, the multiple word lines are connected to the sub-word line driver circuit through the word line isolation circuit, and the sub-word line driver circuit outputs a third test voltage that is lower than the second test voltage.

19. The aging test method as described in claim 18, wherein, The levels of the first and second test voltages are based on the reliability of the core / peripheral circuitry, including the sub-word line driver circuitry.

20. The aging test method as described in claim 18 or 19, wherein, The third test voltage is equal to the normal operating voltage of the sub-word line driver circuit.

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