A high voltage bipolar transistor and process control method thereof

Abstract

The application belongs to the technical field of semiconductor process flow processing, and discloses a high-voltage bipolar transistor and a process control method thereof, which comprises the following steps: performing pre-epitaxy cleaning on a wafer to obtain a cleaned wafer; transferring the cleaned wafer into an epitaxial furnace and performing surface polishing treatment on the cleaned wafer to obtain a surface-polished wafer; supplying process gas to the epitaxial furnace to deposit an intrinsic epitaxial layer on the surface-polished wafer; after the deposition of the intrinsic epitaxial layer is completed, stopping the supply of the process gas to the epitaxial furnace and performing exhaust operation on the epitaxial furnace; after the exhaust operation is completed, continuing to deposit a required epitaxial layer on the intrinsic epitaxial layer; after the deposition of the required epitaxial layer is completed, performing exhaust cooling on the epitaxial furnace to obtain an epitaxial structure on the surface-polished wafer, and the epitaxial structure is composed of the intrinsic epitaxial layer and the required epitaxial layer. The application can solve the technical problem that the selection of a conventional epitaxial layer material causes insufficient voltage resistance of a bipolar transistor.

Description

Technical Field

[0001] This application belongs to the field of semiconductor process technology, specifically relating to a high-voltage bipolar transistor and its process control method. Background Technology

[0002] In the design and manufacturing of discrete semiconductor devices (such as NPN bipolar transistors), voltage withstand capability is a core performance indicator that engineers focus on, directly affecting the device's high-voltage application capability and the economic efficiency of the finished circuit. Currently, in conventional transistor manufacturing processes, the voltage withstand capability of the device is generally achieved by selecting appropriate epitaxial layer materials.

[0003] However, as the application scenarios of high-voltage bipolar transistors continue to expand, the existing conventional epitaxial processes are gradually showing their limitations in dealing with higher voltage requirements. Relying solely on conventional epitaxial layer material selection is insufficient to effectively solve the bottleneck problem faced in further improving the voltage withstand capability of bipolar transistors. Summary of the Invention

[0004] This application addresses the technical problem that conventional epitaxial layer material selection leads to insufficient voltage withstand capability in bipolar transistors by providing a high-voltage bipolar transistor and its process control method.

[0005] To achieve the above objectives, this application adopts the following technical solution: In a first aspect, a process control method for a high-voltage bipolar transistor includes: The wafer is cleaned before epitaxy to obtain a cleaned wafer; The cleaned wafer is transferred into an epitaxial furnace and the surface of the cleaned wafer is polished to obtain a surface-polished wafer. Process gases are supplied to the epitaxial furnace to deposit an intrinsic epitaxial layer on the surface-polished wafer; After the intrinsic epitaxial layer is deposited, the supply of the process gas to the epitaxial furnace is stopped, and the epitaxial furnace is vented. After the venting operation is completed, the required epitaxial layer is deposited on the intrinsic epitaxial layer. After the required epitaxial layer is deposited, the epitaxial furnace is vented and cooled to obtain an epitaxial structure on the polished wafer. The epitaxial structure is composed of the intrinsic epitaxial layer and the required epitaxial layer superimposed.

[0006] In some embodiments, the wafer is N <111> The wafer has a crystal orientation and a resistivity of 0.001~0.004 Ω·cm, and the back side of the wafer is in an oxide back-sealed state.

[0007] In some embodiments, the step of cleaning the wafer before epitaxy specifically includes: First, the wafer is pre-rinsed with water. Then, the wafer is boiled with solution No. 3. After boiling, it is rinsed with water and then rinsed with hydrofluoric acid solution. After rinsing, it is rinsed again and boiled a second time with solution No. 1. Finally, the wafer is rinsed and spun dry.

[0008] In some embodiments, the third solution is a mixture of H2SO4 and H2O2 in a volume ratio of 3:1; the first solution is a mixture of NH4OH, H2O2 and H2O in a volume ratio of 1:2:7.

[0009] In some embodiments, the step of transferring the cleaned wafer into an epitaxial furnace and performing surface polishing on the cleaned wafer specifically includes: The cleaned wafer is transferred into an epitaxial furnace, hydrogen gas is introduced, and it is baked at high temperature. After high-temperature baking, the temperature inside the epitaxial furnace is increased, and HCl gas is introduced to polish the cleaned wafer, resulting in a surface-polished wafer.

[0010] In some embodiments, the high-temperature baking conditions are: hydrogen gas is introduced at a temperature of 790~810°C, and the baking time is 25~35 minutes; wherein the high-temperature baking conditions are preferably hydrogen gas introduced at a temperature of 800°C, and the baking time is 30 minutes. The polishing conditions are as follows: after raising the temperature of the epitaxial furnace to 1145~1155℃, HCl gas with a flow rate of 1.6~1.8 SLM is introduced, and the polishing time is 2~3 minutes. Preferably, after raising the temperature of the epitaxial furnace to 1150℃, HCl gas with a flow rate of 1.7 SLM is introduced; In some embodiments, supplying process gases to the epitaxial furnace to deposit an intrinsic epitaxial layer on the polished wafer specifically includes: The temperature of the epitaxial furnace is raised to 1175~1185℃, and SiCl4 gas is introduced as the process gas to deposit the intrinsic epitaxial layer; preferably, the temperature of the epitaxial furnace is raised to 1180℃. The thickness of the intrinsic epitaxial layer is 7% to 8% of the total epitaxial layer thickness.

[0011] In some embodiments, stopping the supply of the process gas to the epitaxial furnace and venting the epitaxial furnace specifically includes: After stopping the flow of the process gas, maintain the epitaxial furnace in its current state for 5 to 10 minutes to allow residual gas to escape from the furnace.

[0012] In some embodiments, the step of continuing to deposit the required epitaxial layer on the intrinsic epitaxial layer specifically includes: SiCl4 gas and PH3 gas are simultaneously introduced into the epitaxial furnace to deposit the desired epitaxial layer on the intrinsic epitaxial layer.

[0013] Secondly, a high-voltage bipolar transistor is obtained using the aforementioned process control method.

[0014] Compared with the prior art, this application has the following beneficial effects: This application provides a process control method for high-voltage bipolar transistors. Pre-epitaxy cleaning and surface polishing thoroughly remove micromechanical damage and oxide residues from the wafer surface, providing a defect-free underlying template for subsequent single-crystal growth and sealing off leakage channels prone to local breakdown under high-voltage electric fields. A high-resistivity intrinsic epitaxial layer is deposited first on the polished wafer, acting as an electric field buffer to effectively smooth the concentration step and electric field gradient at the interface between the underlying wafer and the required epitaxial layer, expanding the depletion region width to avoid electric field concentration. Simultaneously, a strict venting operation is implemented between the two epitaxial steps to remove residual gas and effectively suppress self-doping effects, ensuring an extremely low background carrier concentration in the intrinsic epitaxial layer and a clear, steep physical boundary between it and the required epitaxial layer. Finally, through a composite epitaxial structure composed of the intrinsic and required epitaxial layers, the voltage withstand bottleneck of traditional epitaxial material design is broken without sacrificing core electrical parameters such as transistor on-resistance, significantly improving the final breakdown voltage of the device.

[0015] Furthermore, the wafer is N <111> Crystal orientation, and resistivity of 0.001~0.004 Ω·cm. <111> The crystal plane family possesses an extremely high surface atomic density. This high-density atomic arrangement provides an extremely stable crystallization reference during subsequent high-temperature vapor phase epitaxial growth, significantly suppressing the proliferation of macroscopic and microscopic lattice defects such as stacking faults, microtwins, and penetrating dislocations. This provides a structurally robust and pure single-crystal foundation for withstanding high-voltage reverse electric fields. Simultaneously, the resistivity range of 0.001 to 0.004 Ω·cm indicates that the wafer, used as the collector terminal of the device, has undergone extremely high concentrations of N-type donor impurity doping. This heavily doped substrate can minimize the collector series resistance of the device in the on-state, thereby significantly reducing the saturation voltage drop from the collector to the emitter macroscopically, effectively suppressing conduction power consumption and heat accumulation under high-current operating conditions. Furthermore, the back side of the wafer is in an oxide back-sealed state, solving the problem of self-doping, which is prone to occur in high-temperature semiconductor processes. In the epitaxial furnace thermal field exceeding 1000 degrees Celsius, donor impurities inside the heavily doped substrate easily volatilize and escape from the back side of the wafer, and are re-incorporated into the high-resistivity epitaxial layer on the front side of the wafer through the gas flow circulation within the furnace cavity. The back-sealing oxide layer acts as an extremely dense physical barrier and chemical diffusion barrier, completely blocking the escape path of impurities in the underlying layer and ensuring the extreme purity of the epitaxial growth environment on the front side. This strictly guarantees that the subsequently deposited intrinsic epitaxial layer can maintain an extremely low background carrier concentration.

[0016] Furthermore, the wafer is first pre-rinsed with water, utilizing the hydrodynamic rinsing action of deionized water to quickly remove loose, free particles and dust physically attached to the wafer surface. Next, the wafer is boiled using solution No. 3, employing a high-temperature, strongly oxidizing liquid to thoroughly destroy and peel off the stubborn organic contamination film on the wafer surface, preventing it from carbonizing at subsequent high temperatures to form lethal silicon carbide nucleation centers. After boiling, the wafer is rinsed with water to block the chemical reaction, and then rinsed with hydrofluoric acid solution. Hydrofluoric acid can precisely and thoroughly peel off the natural silicon oxide layer on the silicon wafer surface with extremely high selectivity, removing hidden... Deep-level metallic impurities hidden at the bottom of or encapsulated within the oxide layer are released, exposing a highly active and pure bare silicon surface. After rinsing, the wafer is rinsed again to remove residual fluoride ions. Then, a second liquid boiling process is performed on the wafer using solution number one. This step cleverly utilizes a dual mechanism of surface potential regulation and micro-etching to complex and detach residual microparticles and free metal ions from the bare silicon surface, while simultaneously preventing secondary adsorption of particles using the principle of like charge repulsion. Finally, the wafer is rinsed and centrifuged, with centrifugal force rapidly removing residual liquid and avoiding localized spot contamination caused by watermarks. This rigorous and continuous wet chemical process provides a perfectly atomic-level substrate free of particles, organic matter, metal contamination, and oxide residues for subsequent epitaxial layers.

[0017] Furthermore, the third solution is a mixture of H2SO4 and H2O2 in a volume ratio of 3:1. This mixture can not only rapidly carbonize large molecular hydrocarbons such as photoresist residue and human oils on the wafer surface through dehydration, but also further oxidize and decompose them into carbon dioxide and water, thereby achieving thorough and destructive removal of various organic contaminants. Meanwhile, the first solution is defined as a mixture of NH4OH, H2O2, and H2O in a volume ratio of 1:2:7. Hydrogen peroxide slowly generates an extremely thin chemical oxide layer on the pure silicon surface, while a moderately concentrated ammonia solution simultaneously performs weak and uniform isotropic etching on this oxide layer. This not only efficiently removes surface particles and specific metal ions through complexation, but also controls the etching rate of the silicon surface. If the ammonia concentration is too high, it will cause anisotropic etching on the silicon wafer surface, resulting in micro-roughness, which is extremely detrimental to the voltage withstand capability of high-voltage devices. This ratio ensures that while thoroughly purifying the silicon, it perfectly protects the extreme flatness of the underlying lattice, avoiding the damage to the integrity of the subsequent epitaxial lattice caused by surface micro-roughness.

[0018] Further, the cleaned wafer is transferred to an epitaxial furnace, where hydrogen gas is introduced and it undergoes high-temperature baking. Although the wafer has undergone rigorous wet cleaning, during the brief exposure process in the epitaxial furnace, its highly reactive bare silicon surface will inevitably re-adsorb trace amounts of oxygen and form a very thin natural oxide layer. Simultaneously, the surface may harbor very shallow lattice damage left over from previous machining processes. The high-purity hydrogen gas introduced at high temperature possesses extremely strong reducing properties, capable of reducing the trace amounts of silicon oxide on the surface to volatile gaseous silicon monoxide and water vapor in situ, which are then carried away with the exhaust gas. Simultaneously, the thermal annealing effect enables the surface silicon atoms to acquire sufficient migration energy, spontaneously reconstructing the surface. After the high-temperature baking is completed, the temperature inside the epitaxial furnace is increased, and HCl gas is introduced to polish the cleaned wafer, resulting in a polished wafer. At high temperatures, hydrogen chloride gas undergoes a vigorous displacement reaction with surface silicon atoms, generating gaseous chlorosilane byproducts. This uniformly removes the damaged layer on the outermost layer of the wafer, which contains mechanical stress, lattice dislocations, or fine scratches. After this vapor-phase polishing, the wafer surface is truly exposed to the regularly arranged, intact bulk single-crystal silicon atoms, fundamentally eliminating the breeding ground for stacking faults and dislocations at the epitaxial interface, and providing a solid guarantee for the reliability of materials under high-voltage electric fields.

[0019] Furthermore, the high-temperature baking conditions are as follows: hydrogen gas is introduced at a temperature of 790~810℃, and the baking time is 25~35 minutes. The temperature of 790~810℃ not only exceeds the energy threshold for activating hydrogen reduction activity, which can thoroughly remove natural oxides and complete degassing, but also cleverly avoids the thermal stress slip line defects that are easily caused in heavily doped wafers at extremely high temperatures. The sufficient baking time of 30 minutes ensures uniform heat conduction across the entire large-size wafer, establishing an extremely pure and stable reducing atmosphere inside the entire reaction chamber. Secondly, the polishing conditions are defined as follows: after raising the temperature of the epitaxial furnace to 1145~1155℃, HCl gas with a flow rate of 1.6~1.8 SLM is introduced, and the polishing time is 2~3 minutes. The high temperature of 1145~1155℃ ensures that the reaction between HCl and silicon is in the mass transfer control region rather than the surface reaction control region, so that the etching rate is not affected by the differences in the microscopic energy state of the local surface, ensuring the macroscopic uniformity of the entire wafer surface. The precise flow rate of 1.6~1.8 SLM, combined with a short processing time of 2~3 minutes, strictly and precisely limits the etching depth to an extremely shallow range that just removes the damaged layer. This parameter setting perfectly avoids the risks of surface selective etching and pitting caused by excessive flow rate or excessive time, allowing the wafer surface to maintain an extremely smooth, mirror-like finish at the microscale.

[0020] Furthermore, the temperature of the epitaxial furnace is raised to 1175~1185℃, and SiCl4 gas is introduced as the process gas to deposit the intrinsic epitaxial layer. The high-temperature thermodynamic environment of 1175~1185℃ allows silicon tetrachloride molecules to undergo efficient thermal decomposition and hydrogen reduction reactions on a perfect single-crystal silicon template. The released free silicon atoms are perfectly and regularly arranged along the lattice orientation of the underlying layer, achieving high-speed film formation of extremely high-quality single-crystal silicon. The thickness of the intrinsic epitaxial layer is explicitly defined as 7%~8% of the total epitaxial layer thickness. In traditional high-voltage bipolar transistors, there is a huge impurity concentration step between the heavily doped low-resistivity substrate and the lightly doped drift region above it. Under reverse bias, a strong electric field concentration effect is easily induced at this physical interface, leading to premature avalanche breakdown of the device. Using an undoped intrinsic layer with a thickness of 7% to 8% as an extremely effective high-resistivity electric field buffer band not only physically separates the high and low concentration regions, but also greatly smooths the electric field gradient in the band structure, enabling the space charge depletion region to expand more widely and uniformly into the buffer band.

[0021] Furthermore, SiCl4 gas and PH3 gas are simultaneously introduced into the epitaxial furnace to deposit the desired epitaxial layer on the intrinsic epitaxial layer. Silicon tetrachloride serves as the silicon source gas, responsible for the continuous growth of the crystal lattice framework, while phosphine, as an N-type gaseous dopant source, undergoes thermal decomposition simultaneously with the silicon source in the same high-temperature gas phase environment. Because phosphorus atoms and silicon atoms have similar atomic radii and extremely high reaction kinetic matching, phosphorus atoms can be in situ substituted into the growing single-crystal silicon lattice nodes with extremely high uniformity. This in-situ co-deposition process, which combines epitaxial growth and impurity doping, ensures that the impurity concentration distribution of the desired epitaxial layer is extremely uniform in both the longitudinal thickness and lateral radial direction. Because this doped layer grows continuously immediately after the intrinsic epitaxial layer, which has undergone rigorous venting, the two share a completely continuous and unbroken single-crystal lattice framework microscopically, but achieve functional differentiation in macroscopic electrical properties through a steep concentration step. By precisely controlling the flow ratio of SiCl4 gas and PH3 gas as well as the growth time, the resistivity and drift region thickness of high-voltage bipolar transistors can be tailored to fully meet the design requirements. Ultimately, in synergy with the intrinsic buffer band at the bottom, a core structure of a high-voltage semiconductor device with excellent voltage withstand capability and superior conduction characteristics can be perfectly created without increasing any additional wafer fabrication and photolithography costs. Attached Figure Description

[0022] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a flowchart illustrating a process control method for a high-voltage bipolar transistor provided in an embodiment of this application. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0025] In one embodiment of this application, such as Figure 1As shown, a process control method for high-voltage bipolar transistors is provided, using an initial carrier substrate of N. <111> A single-crystal silicon wafer with a crystal orientation and resistivity of 0.001~0.004 Ω·cm, wherein the back side of the wafer is sealed with an oxide layer to prevent impurity volatilization and self-doping during subsequent high-temperature processes, the method includes the following steps: S1, perform pre-epitaxy cleaning on the wafer to obtain a cleaned wafer; Specifically, the wafer is first pre-rinsed with water, i.e., QDR (Quick Dump Rinse) pre-rinse 10 times; the wafer is then boiled with solution No. 3, which is a mixture of 96% H2SO4 and 30% H2O2 in a volume ratio of 3:1. The boiling temperature is controlled at 110~130℃ and the boiling time is 5 minutes, wherein the preferred boiling temperature is 120℃. After boiling, the product is rinsed with water, and then rinsed 10 times with QDR. Subsequently, the wafer was rinsed with a hydrofluoric acid solution (HF) in which H2O and hydrofluoric acid were mixed at a volume ratio of 50:1 for 1 minute to completely remove the oxide layer on the surface. After rinsing, the wafer is rinsed again, i.e., QDR rinsing is performed 10 times; the wafer is then subjected to a second liquid boiling using solution No. 1, which is a mixture of 25% NH4OH and 30% H2O2 in a volume ratio of 1:2:7. The liquid boiling temperature is controlled at 65~75℃ and the liquid boiling time is 5 minutes, wherein the liquid boiling temperature is preferably 70℃. Finally, the wafer was rinsed with water (i.e., QDR rinsing 10 times) and spun dry in a nitrogen atmosphere to obtain a cleaned wafer; the spin-drying speed was 2000 rpm and the time was 10 min.

[0026] S2, the cleaned wafer is transferred into an epitaxial furnace and the cleaned wafer is subjected to surface polishing to obtain a surface-polished wafer; Specifically, the cleaned wafer is transferred into an epitaxial furnace, hydrogen gas is introduced, and high-temperature baking is performed. The baking conditions are as follows: hydrogen gas with a flow rate of 88-92 SLM (preferably 90 SLM) is introduced at a temperature of 790-810°C, and the baking time is 25-35 minutes (preferably 30 minutes) to fully remove residual moisture from the wafer surface and replace the furnace chamber gas. After the high-temperature baking is completed, the temperature inside the epitaxial furnace is increased to 1145-1155°C, and then HCl gas with a flow rate of 1.6-1.8 SLM is introduced to polish the cleaned wafer for 2-3 minutes. The mechanical damage layer on the wafer surface is removed by vapor phase micro-etching to obtain a surface-polished wafer.

[0027] S3, process gas is supplied to the epitaxial furnace to deposit an intrinsic epitaxial layer on the surface-polished wafer; Specifically, the temperature of the epitaxial furnace is further increased to 1175~1185℃, and SiCl4 gas with a flow rate of 9.8 SLM is introduced as the process gas to deposit the intrinsic epitaxial layer on the surface of the single-crystal silicon wafer. During this process, the deposition time is calculated according to the preset epitaxial deposition rate, and the thickness of the intrinsic epitaxial layer is strictly controlled so that it accounts for 7%~8% of the total thickness of the final epitaxial structure. This undoped intrinsic layer will serve as a high-resistivity electric field buffer band for subsequent devices.

[0028] S4, after the intrinsic epitaxial layer is deposited, the supply of the process gas to the epitaxial furnace is stopped, and the epitaxial furnace is vented. Specifically, after stopping the flow of the process gas (SiCl4 gas), the epitaxial furnace is kept in its current state (temperature remains constant) for 5 minutes to fully expel the residual silicon source gas and reaction byproducts from the epitaxial furnace, completely cut off the doping memory effect, and prevent cross-contamination between epitaxial layers.

[0029] S5, after the exhaust operation is completed, the required epitaxial layer is deposited on the intrinsic epitaxial layer; Specifically, after the exhaust is completely cleared, SiCl4 gas with a flow rate of 9.7~9.9 SLM (preferably 9.8 SLM) and PH3 gas with a flow rate of 15.5~15.7 SLM (preferably 15.6 SLM) are simultaneously introduced into the epitaxial furnace to continuously deposit the required epitaxial layer on the intrinsic epitaxial layer to achieve the target resistivity and target thickness.

[0030] S6, after the required epitaxial layer is deposited, the epitaxial furnace is vented and cooled to obtain an epitaxial structure on the polished wafer. The epitaxial structure is composed of the intrinsic epitaxial layer and the required epitaxial layer superimposed.

[0031] Specifically, after cooling and exiting the furnace, a complete double-layer epitaxial structure is obtained on the wafer. The high-voltage bipolar transistor fabricated using the process control method of this embodiment significantly improves the bulk electric field distribution by utilizing the 7%~8% thickness of the intrinsic epitaxial buffer band at the bottom layer without changing the device's on-resistance, thereby greatly improving the breakdown voltage of the bipolar transistor.

[0032] A high-voltage bipolar transistor is obtained using the process control method provided in the above embodiments.

[0033] In summary, the high-voltage bipolar transistor and its process control method provided in this application first prepare a defect-free ideal single-crystal growth template by liquid boiling and HF rinsing combined with high-temperature HCl vapor-phase polishing. Then, a high-resistivity intrinsic epitaxial layer with a thickness of 7%~8% is deposited between the polished wafer and the conventional doped epitaxial layer. Simultaneously, a strict venting and cleaning operation is implemented between the two epitaxial deposition processes to completely remove residual process gases. This method utilizes a specific intrinsic epitaxial layer as a bulk electric field buffer, effectively smoothing the concentration step at the interface between the underlying low-resistivity wafer and the doped epitaxial layer, allowing the depletion region to expand more uniformly and avoiding electric field concentration. The strict intermediate venting operation cuts off the self-doping and cross-contamination effects during epitaxial growth, ensuring an extremely low background concentration of the high-resistivity layer and a steep physical boundary between it and the doped layer. The defect-free polished interface seals off leakage channels that are prone to local breakdown from the bottom layer. Ultimately, without changing the core physical dimensions of the device or sacrificing key electrical parameters such as low on-resistance, this application fundamentally overcomes the bottleneck of insufficient voltage withstand capability caused by conventional epitaxial layer material design, achieving a significant leap in the breakdown voltage index and high-voltage reliability of high-voltage bipolar transistors, and improving the chip's voltage withstand parameter index by 10% while keeping the epitaxial layer thickness basically unchanged.

[0034] The various embodiments in this specification are described in a progressive manner. For directly identical or similar parts of the embodiments, refer to each other. Each embodiment focuses on its differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments. It should be noted that the technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification.

[0035] The above-described embodiments are merely preferred embodiments of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various improvements and substitutions without departing from the principles of the present invention, and these improvements and substitutions should also be considered within the scope of protection of the present invention. Therefore, the scope of protection of this invention should be determined by the scope of the claims.

Claims

1. A process control method for a high-voltage bipolar transistor, characterized in that, include: The wafer is cleaned before epitaxy to obtain a cleaned wafer; The cleaned wafer is transferred into an epitaxial furnace and the surface of the cleaned wafer is polished to obtain a surface-polished wafer. Process gases are supplied to the epitaxial furnace to deposit an intrinsic epitaxial layer on the surface-polished wafer; After the intrinsic epitaxial layer is deposited, the supply of the process gas to the epitaxial furnace is stopped, and the epitaxial furnace is vented. After the venting operation is completed, the required epitaxial layer is deposited on the intrinsic epitaxial layer. After the required epitaxial layer is deposited, the epitaxial furnace is vented and cooled to obtain an epitaxial structure on the polished wafer. The epitaxial structure is composed of the intrinsic epitaxial layer and the required epitaxial layer superimposed.

2. The process control method for a high-voltage bipolar transistor according to claim 1, characterized in that, The wafer is N <111> The wafer has a crystal orientation and a resistivity of 0.001~0.004 Ω·cm, and the back side of the wafer is in an oxide back-sealed state.

3. The process control method for a high-voltage bipolar transistor according to claim 1, characterized in that, The step of cleaning the wafer before epitaxy specifically includes: First, the wafer is pre-rinsed with water. Then, the wafer is boiled with solution No.

3. After boiling, it is rinsed with water and then rinsed with hydrofluoric acid solution. After rinsing, it is rinsed again and boiled a second time with solution No.

1. Finally, the wafer is rinsed and spun dry.

4. The process control method for a high-voltage bipolar transistor according to claim 3, characterized in that, The third solution is a mixture of H2SO4 and H2O2 in a volume ratio of 3:1; the first solution is a mixture of NH4OH, H2O2 and H2O in a volume ratio of 1:2:

7.

5. The process control method for a high-voltage bipolar transistor according to claim 1, characterized in that, The step of transferring the cleaned wafer into an epitaxial furnace and performing surface polishing on the cleaned wafer specifically includes: The cleaned wafer is transferred into an epitaxial furnace, hydrogen gas is introduced, and it is baked at high temperature. After high-temperature baking, the temperature inside the epitaxial furnace is increased, and HCl gas is introduced to polish the cleaned wafer, resulting in a surface-polished wafer.

6. The process control method for a high-voltage bipolar transistor according to claim 5, characterized in that, The conditions for high-temperature baking are: hydrogen gas is introduced at a temperature of 790~810℃, and the baking time is 25~35 minutes. The polishing conditions are as follows: after raising the temperature of the epitaxial furnace to 1145~1155℃, HCl gas with a flow rate of 1.6~1.8SLM is introduced, and the polishing time is 2~3min.

7. The process control method for a high-voltage bipolar transistor according to claim 1, characterized in that, The process of supplying process gas to the epitaxial furnace and depositing an intrinsic epitaxial layer on the polished wafer specifically includes: The temperature of the epitaxial furnace is raised to 1175~1185℃, and SiCl4 gas is introduced as the process gas to deposit the intrinsic epitaxial layer. The thickness of the intrinsic epitaxial layer is 7% to 8% of the total epitaxial layer thickness.

8. The process control method for a high-voltage bipolar transistor according to claim 1, characterized in that, The step of stopping the supply of the process gas to the epitaxial furnace and venting the epitaxial furnace specifically includes: After stopping the flow of the process gas, maintain the epitaxial furnace in its current state for 5 to 10 minutes to allow residual gas to escape from the furnace.

9. The process control method for a high-voltage bipolar transistor according to claim 1, characterized in that, The step of further depositing the required epitaxial layer on the intrinsic epitaxial layer specifically includes: SiCl4 gas and PH3 gas are simultaneously introduced into the epitaxial furnace to deposit the desired epitaxial layer on the intrinsic epitaxial layer.

10. A high-voltage bipolar transistor, characterized in that, It is obtained by using the process control method described in any one of claims 1 to 9.

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