A silicon-based readout circuit thinning method

Abstract

The application discloses a silicon-based readout circuit thinning method. The silicon-based readout circuit thinning method comprises the following steps: preparing a dense circular hole pattern on a substrate wafer surface; performing deep hole etching on the substrate wafer surface according to the circular hole pattern to form deep holes; after cleaning the substrate wafer, reversely placing the substrate wafer in a grinding and polishing equipment, and making the surface of the substrate wafer, on which the deep holes are formed, contact with a wafer supporting table of the grinding and polishing equipment; thinning the substrate wafer until a through hole appears on the surface of the substrate wafer; the vacuum adsorption force of the grinding and polishing equipment acts on the readout circuit wafer through the through hole on the surface of the substrate wafer, so that the readout circuit wafer is adsorbed on the surface of the substrate wafer, the fixation of the readout circuit wafer on the wafer supporting table is realized, and the readout circuit wafer is thinned until the thickness of the readout circuit wafer is reduced to a target thickness. According to the embodiment of the application, the problem that the thickness consistency of the readout circuit wafer is too large after the readout circuit wafer is thinned by using the grinding and polishing equipment is solved.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and in particular relates to a method for thinning silicon-based readout circuits. Background Technology

[0002] Infrared focal plane array (FLA) detection technology boasts significant advantages such as a wide spectral response band, the ability to acquire more information about ground targets, and the capacity for day and night operation. It is widely used in fields such as agricultural and pastoral surveys, development and management of forest resources, weather forecasting, geothermal distribution, earthquake and volcanic activity detection, and space astronomical exploration. Mercury cadmium telluride (MDT) infrared detectors are fabricated by flip-chip interconnection of a MDT chip and a readout circuit. To reduce thermal stress between the silicon-based readout circuit and the MDT chip during low-temperature operation of the MDT infrared detector and to prevent thermal stress from affecting detector performance, an ultra-thin readout circuit with a thickness of approximately 100 micrometers is typically used for flip-chip interconnection with the MDT chip. Therefore, the 8-inch silicon-based readout circuit wafer needs to be thinned to approximately 100 micrometers, and to ensure uniform stress distribution at low temperatures, the thickness uniformity (TTV) of the 8-inch readout circuit wafer must be controlled within 1 micrometer. This technology is a core technology required for fabricating high-performance MDT infrared detectors.

[0003] During the thickness reduction process of 8-inch readout circuit wafers using grinding and polishing equipment, the thickness uniformity is limited by the grinding and polishing profile of the equipment and the surface undulations of the wafer stage. Because the wafer stage needs to be designed with reliability in mind, it is made of ceramic, making it difficult to achieve a surface flatness of less than 1 micrometer. This factor, combined with the grinding and polishing profile, ultimately means that when the thickness of the 8-inch readout circuit wafer is reduced to approximately 100 micrometers, the wafer thickness uniformity (TTV) cannot be controlled within 1 micrometer. Summary of the Invention

[0004] This application provides a method for thinning silicon-based readout circuits, which at least solves the problem in the related art where the thickness uniformity (TTV) of an 8-inch readout circuit wafer is affected by the grinding profile of the grinding wheel and the surface undulation of the wafer stage after the thickness is reduced using a grinding wheel polishing equipment, resulting in excessive differences in thickness uniformity.

[0005] This application provides a method for thinning a silicon-based readout circuit, including: A densely arranged pattern of circular holes is fabricated on the surface of a substrate wafer; According to the circular hole pattern, deep hole etching is performed on the surface of the substrate wafer to form a deep hole; After cleaning, the substrate wafer with the deep holes is inverted and placed in a grinding and polishing equipment, with the surface of the substrate wafer with the deep holes in contact with the wafer support stage of the grinding and polishing equipment. The substrate wafer is thinned until through holes appear on the surface of the substrate wafer; The vacuum adsorption force of the grinding and polishing equipment acts on the readout circuit wafer through the through hole on the surface of the substrate wafer, so as to adsorb the readout circuit wafer onto the surface of the substrate wafer, thereby fixing the readout circuit wafer on the wafer support stage and thinning the readout circuit wafer until the thickness of the readout circuit wafer is reduced to the target thickness.

[0006] Optionally, the depth of the deep hole is matched with the target thickness of the readout circuit wafer.

[0007] Optionally, the fabrication of a densely arranged pattern of circular holes on the surface of the substrate wafer includes: The circular hole pattern is fabricated on the surface of the substrate wafer using a photolithography device; The step of performing deep hole etching on the substrate wafer surface according to the circular hole pattern includes: Deep hole etching is performed using an inductively coupled plasma etching apparatus according to the circular hole pattern.

[0008] Optionally, the thinning process parameters corresponding to the substrate wafer are the same as those corresponding to the readout circuit wafer.

[0009] Optionally, the substrate wafer is an 8-inch silicon substrate wafer; the readout circuit wafer is an 8-inch silicon-based readout circuit wafer; and the grinding and polishing equipment is an 8-inch grinding and polishing equipment.

[0010] Optionally, after placing the readout circuit wafer to be thinned on the substrate wafer with the through-hole, and thinning the readout circuit wafer until the thickness of the readout circuit wafer is reduced to the target thickness, the method further includes: The thinned readout circuit wafer is then flip-chip interconnected with the mercury cadmium telluride chip.

[0011] The silicon-based readout circuit thinning method of this application embodiment first prepares deep holes on a substrate wafer, then flips the substrate wafer so that the surface with the deep holes contacts the substrate stage and performs thinning until through holes appear on the surface of the substrate wafer. The vacuum adsorption force of the grinding and polishing equipment acts on the readout circuit wafer through the through holes on the surface of the substrate wafer to adsorb the readout circuit wafer onto the surface of the substrate wafer, thereby fixing the readout circuit wafer on the substrate stage. When thinning the readout circuit wafer, since the substrate wafer uses the same thinning process parameters as the readout circuit wafer, the undulation state of the upper surface of the substrate wafer is the same as the surface of the readout circuit wafer after thinning by the equipment. After the readout circuit wafer is adsorbed onto the surface of the substrate wafer for thinning, the undulation state of the upper and lower surfaces of the readout circuit wafer can be made completely identical, thus the thickness uniformity of the readout circuit wafer can be controlled within 1µm. This improves the uniformity of thermal stress distribution during low-temperature operation of the readout circuit, thereby improving the performance of the infrared detector. Attached Figure Description

[0012] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is an exemplary schematic diagram of a related technology readout circuit where the wafer thickness uniformity is limited by the grinding and polishing profile of the equipment's grinding wheel and the surface undulations of the wafer stage, making it impossible to control within 1 micrometer. Figure 2 This is a schematic flowchart of a silicon-based readout circuit thinning method provided in an embodiment of this application; Figure 3 This is a schematic diagram of a densely arranged circular hole pattern on the surface of a substrate wafer, provided in an embodiment of this application. Figure 4 This is a schematic diagram of deep hole etching on the surface of a substrate wafer provided in an embodiment of this application; Figure 5 This is a schematic diagram of placing a substrate wafer in a grinding and polishing device by inverting it according to an embodiment of this application; Figure 6 This is a schematic diagram of substrate wafer thinning provided in an embodiment of this application; Figure 7 This is a schematic diagram of wafer thinning for the readout circuit provided in an embodiment of this application. Detailed Implementation

[0014] The features and exemplary embodiments of various aspects of this application will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain this application and not to limit it. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples.

[0015] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0016] Infrared focal plane array (FLA) detection technology boasts significant advantages such as a wide spectral response band, the ability to acquire more information about ground targets, and the capacity for day and night operation. It is widely used in fields such as agricultural and pastoral surveys, development and management of forest resources, weather forecasting, geothermal distribution, earthquake and volcanic activity detection, and space astronomical exploration. Mercury cadmium telluride (MDT) infrared detectors are fabricated by flip-chip interconnection of a MDT chip and a readout circuit. To reduce thermal stress between the silicon-based readout circuit and the MDT chip during low-temperature operation of the MDT infrared detector and to prevent thermal stress from affecting detector performance, an ultra-thin readout circuit with a thickness of approximately 100 micrometers is typically used for flip-chip interconnection with the MDT chip. Therefore, the 8-inch silicon-based readout circuit wafer needs to be thinned to approximately 100 micrometers, and to ensure uniform stress distribution at low temperatures, the thickness uniformity (TTV) of the 8-inch readout circuit wafer must be controlled within 1 micrometer. This technology is a core technology required for fabricating high-performance MDT infrared detectors.

[0017] Figure 1 This is an illustration of related technologies, such as Figure 1 As shown, during the thickness reduction process of 8-inch readout circuit wafers using a grinding and polishing equipment, the thickness uniformity is limited by the grinding and polishing profile of the equipment and the surface undulations of the wafer stage. Because the wafer stage needs to be designed with reliability in mind, it is made of ceramic, making it difficult to achieve a surface flatness below 1 micrometer. This factor, combined with the grinding and polishing profile, ultimately means that when the thickness of the 8-inch readout circuit wafer is reduced to approximately 100 micrometers, the wafer thickness uniformity (TTV) cannot be controlled within 1 micrometer.

[0018] To address the problems in the related technologies, this application provides a method for thinning a silicon-based readout circuit.

[0019] The silicon-based readout circuit thinning method provided in this application will be described in detail below with reference to the accompanying drawings, through specific embodiments and application scenarios.

[0020] refer to Figure 2This is a schematic flowchart illustrating a silicon-based readout circuit thinning method according to an embodiment of this application. Figure 2 As shown, the silicon-based readout circuit thinning method may specifically include the following steps: S101. A densely arranged pattern of circular holes is prepared on the surface of a substrate wafer; S102. According to the circular hole pattern, deep hole etching is performed on the surface of the substrate wafer to form a deep hole; S103. After cleaning, the substrate wafer with the deep hole formed is reversed and placed in a grinding and polishing equipment, and the surface of the substrate wafer with the deep hole formed is in contact with the wafer support stage of the grinding and polishing equipment. S104. Thin the substrate wafer until through holes appear on the surface of the substrate wafer; S105. The vacuum adsorption force of the grinding and polishing equipment acts on the readout circuit wafer through the through hole on the surface of the substrate wafer to adsorb the readout circuit wafer onto the surface of the substrate wafer, thereby fixing the readout circuit wafer on the wafer support stage and thinning the readout circuit wafer until the thickness of the readout circuit wafer is reduced to the target thickness.

[0021] Therefore, deep holes are first fabricated on the substrate wafer. Then, the substrate wafer is flipped so that the surface with the deep holes contacts the substrate stage and is thinned until through-holes appear on the substrate wafer surface. The vacuum adsorption force of the grinding and polishing equipment acts on the readout circuit wafer through the through-holes on the substrate wafer surface, adsorbing the readout circuit wafer onto the substrate wafer surface and fixing it on the substrate stage. During the thinning of the readout circuit wafer, since the substrate wafer uses the same thinning process parameters as the readout circuit wafer, the undulation state of the upper surface of the substrate wafer is the same as the surface of the readout circuit wafer after thinning. After the readout circuit wafer is adsorbed onto the substrate wafer surface for thinning, the undulation state of the upper and lower surfaces of the readout circuit wafer can be made completely identical, thus controlling the thickness uniformity of the readout circuit wafer within 1µm. This improves the uniformity of thermal stress distribution during low-temperature operation of the readout circuit, thereby enhancing the performance of the infrared detector.

[0022] The specific implementation methods of each of the above steps are explained in detail below.

[0023] Figure 3 This is a schematic diagram illustrating the fabrication of a densely arranged pattern of circular holes on the surface of a substrate wafer, as provided in an embodiment of this application. Figure 3As shown, a substrate wafer is provided, which can be a silicon substrate wafer, preferably an 8-inch silicon substrate wafer. A densely arranged pattern of circular holes is fabricated on the surface of the substrate wafer using photolithography equipment. This pattern of circular holes provides an etching mask pattern for subsequent deep hole etching. The densely arranged pattern of circular holes facilitates the uniform formation of through-holes during subsequent thinning processes, thereby effectively compensating for the grinding wheel profile and surface undulations of the wafer stage.

[0024] Optionally, the circular hole patterns can be arranged in an array, such as a rectangular array or a ring array, on the surface of the substrate wafer. The aperture and spacing of the circular holes can be designed according to actual process requirements, and this application does not impose specific limitations on them.

[0025] Figure 4 This is a schematic diagram of deep hole etching on the surface of a substrate wafer, provided as an embodiment of this application. Figure 4 As shown, the circular hole pattern prepared in step S101 is used as an etching mask to perform deep hole etching on the substrate wafer, forming deep holes on the surface of the substrate wafer, and the position and distribution of the deep holes correspond to the circular hole pattern.

[0026] In practice, inductively coupled plasma (ICP) etching equipment can be used to perform deep hole etching according to the circular hole pattern. Inductively coupled plasma etching has the advantages of high etching rate, good anisotropy, and large aspect ratio, which can meet the process requirements of deep hole etching.

[0027] It should be noted that, in this embodiment, the depth of the deep via matches the target thickness of the readout circuit wafer. The target thickness of the readout circuit wafer is 80 micrometers to 120 micrometers, preferably about 100 micrometers. Accordingly, the depth of the deep via is comparable to the aforementioned target thickness, for example, it can be set to be slightly greater than or equal to the target thickness, to ensure that through-holes can appear on the surface of the substrate wafer after subsequent thinning.

[0028] Figure 5 This is a schematic diagram illustrating the inversion of a substrate wafer within a grinding and polishing apparatus, as provided in an embodiment of this application. Figure 5 As shown, the substrate wafer with deep holes is cleaned to remove residues and contaminants generated during the etching process. After cleaning, the substrate wafer is inverted and placed into a grinding and polishing equipment. That is, in the inverted substrate wafer, the surface with deep holes faces down and contacts the stage of the grinding and polishing equipment, while the surface of the substrate wafer without deep holes faces up, serving as the surface for subsequent thinning processing.

[0029] Optionally, the grinding and polishing equipment is an 8-inch grinding and polishing equipment, which matches the size of the 8-inch substrate wafer and readout circuit wafer.

[0030] Figure 6This is a schematic diagram illustrating substrate wafer thinning as provided in an embodiment of this application. Figure 6 As shown, the substrate wafer is thinned according to preset process parameters. An abrasive wheel polishes and thins the upward-facing surface of the substrate wafer (i.e., the surface without deep holes). As the thinning process progresses, the thickness of the substrate wafer gradually decreases. When the thinning reaches the bottom of the deep hole, the deep hole becomes a through hole, meaning a through hole appears on the surface of the substrate wafer. At this point, the thinning of the substrate wafer stops. It can be understood that the appearance of the through hole creates a through-hole structure in the thickness direction of the substrate wafer. The vacuum adsorption force of the abrasive wheel polishing equipment acts on the readout circuit wafer through the through hole on the surface of the substrate wafer, adsorbing the readout circuit wafer onto the surface of the substrate wafer, thus fixing the readout circuit wafer on the wafer support stage. When thinning the readout circuit wafer, since the substrate wafer uses the same thinning process parameters as the readout circuit wafer, the undulation state of the upper surface of the substrate wafer is the same as the surface of the readout circuit wafer after thinning by the equipment. After the readout circuit wafer is thinned by adsorbing it onto the surface of the substrate wafer, the undulations of the upper and lower surfaces of the readout circuit wafer can be made completely identical. Therefore, the thickness uniformity of the readout circuit wafer can be controlled within 1µm. This improves the uniformity of thermal stress distribution during low-temperature operation of the readout circuit, thereby enhancing the performance of the infrared detector.

[0031] Optionally, the thinning process parameters for the substrate wafer include, but are not limited to, grinding wheel speed, feed rate, and polishing pressure. These parameters can be preset and adjusted according to the material and thickness of the substrate wafer.

[0032] Figure 7 This is a schematic diagram of wafer thinning for the readout circuit provided in an embodiment of this application. (See attached diagram.) Figure 7 As shown, the readout circuit wafer to be thinned is placed on a substrate wafer with through-holes. The lower surface of the readout circuit wafer is in contact with the upper surface of the substrate wafer (i.e., the surface where the through-holes appear after thinning). Then, the readout circuit wafer is thinned using a grinding wheel polishing device until the thickness of the readout circuit wafer is reduced to the target thickness.

[0033] The readout circuit wafer is an 8-inch silicon-based readout circuit wafer. The target thickness is 80 micrometers to 120 micrometers, preferably about 100 micrometers.

[0034] Specifically, the thinning process parameters for the substrate wafer are consistent with those for the readout circuit wafer. That is, when thinning the readout circuit wafer, the same grinding wheel speed, feed rate, and polishing pressure are used as for the substrate wafer. This ensures that the thinning process of the readout circuit wafer is consistent with that of the substrate wafer, thereby better utilizing the compensation effect of the through-holes and achieving better thickness consistency.

[0035] In some embodiments, after the readout circuit wafer is thinned to the target thickness, the method further includes: performing a flip-chip interconnect between the thinned readout circuit wafer and the mercury cadmium telluride (HCd) chip to fabricate a HCd infrared detector. The thinned readout circuit wafer has a uniform thickness, and the thermal stress generated at low temperatures can be evenly distributed, thereby improving the performance and reliability of the infrared detector.

[0036] It should be noted that the above description describes some embodiments of this application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in a different order than that shown in the above embodiments and still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0037] In this application, the reference to "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment that is mutually exclusive with other embodiments.

[0038] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "attachment" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0039] In the embodiments of this application, the same reference numerals denote the same components, and for the sake of brevity, detailed descriptions of the same components are omitted in different embodiments. It should be understood that the thickness, length, width, and other dimensions of various components in the embodiments of this application shown in the accompanying drawings, as well as the overall thickness, length, width, and other dimensions of the integrated device, are merely illustrative and should not constitute any limitation on this application.

[0040] In this application, "multiple" means two or more (including two).

[0041] Although this application has been described with reference to preferred embodiments, various modifications can be made thereto and components can be replaced with equivalents without departing from the scope of this application. In particular, the technical features mentioned in the various embodiments can be combined in any manner, provided there is no structural conflict. This application is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

[0042] It should also be noted that the exemplary embodiments mentioned in this application describe methods or systems based on a series of steps or apparatus. However, this application is not limited to the order of the above steps; that is, the steps can be performed in the order mentioned in the embodiments, or in a different order, or several steps can be performed simultaneously.

[0043] The above description is merely a specific implementation of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, modules, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the protection scope of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the protection scope of this application.

Claims

1. A method for thinning a silicon-based readout circuit, characterized in that, include: A densely arranged pattern of circular holes is fabricated on the surface of a substrate wafer; According to the circular hole pattern, deep hole etching is performed on the surface of the substrate wafer to form a deep hole; After cleaning, the substrate wafer with the deep holes is inverted and placed in a grinding and polishing equipment, with the surface of the substrate wafer with the deep holes in contact with the wafer support stage of the grinding and polishing equipment. The substrate wafer is thinned until through holes appear on the surface of the substrate wafer; The vacuum adsorption force of the grinding and polishing equipment acts on the readout circuit wafer through the through hole on the surface of the substrate wafer, so as to adsorb the readout circuit wafer onto the surface of the substrate wafer, thereby fixing the readout circuit wafer on the wafer support stage and thinning the readout circuit wafer until the thickness of the readout circuit wafer is reduced to the target thickness.

2. The method according to claim 1, characterized in that, The depth of the deep hole is matched with the target thickness of the readout circuit wafer.

3. The method according to claim 1, characterized in that, The process of fabricating a densely arranged pattern of circular holes on the surface of a substrate wafer includes: The circular hole pattern is fabricated on the surface of the substrate wafer using a photolithography device; The step of performing deep hole etching on the substrate wafer surface according to the circular hole pattern includes: Deep hole etching is performed using an inductively coupled plasma etching apparatus according to the circular hole pattern.

4. The method according to claim 1, characterized in that, The thinning process parameters corresponding to the substrate wafer are the same as those corresponding to the readout circuit wafer.

5. The method according to claim 1, characterized in that, The substrate wafer is an 8-inch silicon substrate wafer; the readout circuit wafer is an 8-inch silicon-based readout circuit wafer; and the grinding and polishing equipment is an 8-inch grinding and polishing equipment.

6. The method according to claim 1, characterized in that, After placing the readout circuit wafer to be thinned on the substrate wafer with the through-hole, and thinning the readout circuit wafer until the thickness of the readout circuit wafer is reduced to the target thickness, the method further includes: The thinned readout circuit wafer is then flip-chip interconnected with the mercury cadmium telluride chip.

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