A method for manufacturing a silicon-on-insulator wafer and a silicon-on-insulator wafer

Abstract

The present disclosure relates to the technical field of semiconductor manufacturing. The present disclosure provides a preparation method of a silicon-on-insulator wafer and the silicon-on-insulator wafer. The preparation method of the silicon-on-insulator wafer comprises: performing ion implantation on a donor wafer substrate to form an ion implantation layer in the donor wafer substrate; bonding the ion implantation surface of the donor wafer substrate to a support wafer substrate through an insulating layer to form a bonding structure; and performing separation annealing on the bonding structure to evolve the ion implantation layer into a bubble layer and cause cracks to penetrate through the ion implantation layer, so that the donor wafer substrate is separated along the ion implantation layer to obtain a silicon-on-insulator wafer; wherein the separation annealing process adopts multi-stage temperature control, and the multi-stage temperature control at least comprises a first temperature rising stage, a second temperature rising stage and a third temperature rising stage performed in sequence. Thus, the surface roughness of the silicon layer after separation can be reduced.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing technology, and in particular to a method for preparing silicon-on-insulator (SiI) wafers and the SiI wafers themselves. Background Technology

[0002] Silicon on Insulator (SOI) wafers are a type of semiconductor material that can be fabricated through ion implantation and thin-film lift-off processes. For example, an ion implantation layer can be formed within a donor wafer substrate, the donor wafer substrate can be bonded to a support wafer substrate, and annealing can be used to lift the donor wafer substrate along the ion implantation layer, thereby transferring some silicon material to the support wafer substrate side.

[0003] During the stripping annealing process, when the stripping states of different areas of the wafer are not synchronized, the stripping surface may have height differences in different areas, resulting in a large surface roughness of the silicon layer after stripping. Summary of the Invention

[0004] In a first aspect, this disclosure provides a method for fabricating silicon-on-insulator (SCI) wafers. The method includes: ion implantation into a donor wafer substrate to form an ion implantation layer within the donor wafer substrate; bonding the implantation surface of the donor wafer substrate to a supporting wafer substrate through an insulating layer to form a bonding structure; and performing a peeling annealing process on the bonding structure, causing the ion implantation layer to evolve into a bubble layer and cracks to penetrate along the ion implantation layer, thereby peeling the donor wafer substrate along the ion implantation layer to obtain a SCI wafer; wherein the peeling annealing process employs multi-stage temperature control, which includes at least a first temperature stage and a second temperature stage performed sequentially. The process includes a first heating stage and a third heating stage. The first heating stage involves heating from the starting temperature to a first ending temperature in the range of 180℃ to 220℃ at a first heating rate of 2℃ / min to 3℃ / min. The second heating stage involves heating from the first ending temperature to a second ending temperature in the range of 380℃ to 420℃ at a second heating rate of 4℃ / min to 6℃ / min. The third heating stage involves heating from the second ending temperature to a third ending temperature in the range of 450℃ to 520℃ at a third heating rate of 8℃ / min to 12℃ / min.

[0005] Secondly, this disclosure provides a silicon-on-insulator (SCI) wafer. The SCI wafer includes: a supporting wafer substrate, an insulating layer, and a silicon layer. The insulating layer is disposed on one side of the supporting wafer substrate. The silicon layer is disposed on the side of the insulating layer away from the supporting wafer substrate, and the side of the silicon layer away from the insulating layer is a release surface. The silicon layer is formed by peeling a donor wafer substrate along an ion-implanted layer through a peel annealing process. The ion-implanted layer is formed by ion implantation, and the donor wafer substrate is bonded to the supporting wafer substrate via the insulating layer before peel annealing. The peeling annealing process employs multi-stage temperature control, which includes at least a first heating stage, a second heating stage, and a third heating stage performed sequentially. The first heating stage raises the temperature from the initial temperature to a first termination temperature within the range of 180℃ to 220℃ at a first heating rate of 2℃ / min to 3℃ / min. The second heating stage raises the temperature from the first termination temperature to a second termination temperature within the range of 380℃ to 420℃ at a second heating rate of 4℃ / min to 6℃ / min. The third heating stage raises the temperature from the second termination temperature to a third termination temperature within the range of 450℃ to 520℃ at a third heating rate of 8℃ / min to 12℃ / min. The root mean square roughness of the peeled surface obtained after peeling annealing is no greater than 0.4 nm within a 10 μm × 10 μm measurement area, and the thickness of the subsurface damage region of the peeled surface is 40 nm to 60 nm.

[0006] This disclosure, by sequentially setting a first heating stage, a second heating stage, and a third heating stage in the same peeling annealing process, and using multi-stage heating control, enables the annealing equipment to adopt different set heating rates in different temperature ranges. This allows the hydrogen recombination, microcavity formation, bubble growth, and crack propagation processes in the ion implantation layer to proceed sequentially according to the corresponding thermal history. This helps to reduce the differences in microcavity formation and crack propagation between different regions of the wafer, reduce crack deflection and local tearing, thereby reducing the height fluctuation of the peeling surface and reducing the surface roughness of the silicon layer after peeling. Attached Figure Description

[0007] Figure 1 This is a flowchart of the method for fabricating silicon-on-insulator wafers disclosed herein.

[0008] Figure 2 for Figure 1 The flowchart for stripping annealing.

[0009] Figure 3(a) shows the adoption of Figure 1 A schematic diagram of the donor wafer substrate after ion implantation using the method described above.

[0010] Figure 3(b) shows the adoption of Figure 1 A schematic diagram of the bonding structure after bonding using the method.

[0011] Figure 3(c) shows the adoption of Figure 1A schematic diagram of the silicon wafer on the insulator after the method of stripping.

[0012] Figure 4 This is a schematic diagram of the microcavity distribution within the ion implantation layer after the first heating stage.

[0013] Figure 5 This is a schematic diagram showing the distribution of bubbles and silicon junctions after the second heating stage.

[0014] Figure 6 This is a schematic diagram showing the crack penetration and silicon layer formation during the third heating stage.

[0015] Figure 7(a) shows the roughness distribution of the peeled surface after three-stage peeling annealing.

[0016] Figure 7(b) shows the surface roughness distribution after annealing at a single heating rate.

[0017] Figure 8(a) shows the three-dimensional morphology of the peeled surface obtained by three-stage peeling annealing in a 10 μm × 10 μm measurement area using atomic force microscopy.

[0018] Figure 8(b) shows the two-dimensional height map of the peeled surface obtained by three-stage peeling annealing in a 10 μm × 10 μm measurement area obtained by atomic force microscopy.

[0019] Figure 8(c) shows the three-dimensional morphology of the exfoliated surface obtained by annealing at a single heating rate within a 10 μm × 10 μm measurement area using atomic force microscopy.

[0020] Figure 8(d) shows the two-dimensional height map of the peeled surface obtained by annealing at a single heating rate within a 10 μm × 10 μm measurement area obtained by atomic force microscopy. Detailed Implementation

[0021] The technical solutions in this disclosure will now be clearly and completely described with reference to the accompanying drawings.

[0022] During the exfoliation annealing process, hydrogen recombination, microcavity formation, bubble growth, and crack propagation occur sequentially within the ion-implanted layer. These processes occur within different temperature ranges and are affected by the heating rate and the residence time within the corresponding temperature range. When the temperature change process of exfoliation annealing does not match the microscopic evolution process, the formation of microcavities and crack propagation in different regions of the wafer may be asynchronous, resulting in height differences on the exfoliated surface in different regions, thus leading to a larger surface roughness on the exfoliated surface.

[0023] This disclosure provides a method for fabricating silicon-on-insulator (SCI) wafers and the SCI wafers themselves. By sequentially setting a first heating stage, a second heating stage, and a third heating stage in the same lift-off annealing process, the hydrogen recombination, microcavity formation, bubble growth, and crack propagation processes within the ion implantation layer can proceed sequentially according to their respective thermal histories. This helps to reduce the differences in microcavity formation and crack propagation between different regions of the wafer, reduce crack deflection and local tearing, thereby reducing the height undulation of the lift-off surface and the surface roughness of the silicon layer after lift-off. The following is a detailed description: The silicon-on-insulator wafer 200 disclosed herein refers to a layered wafer with an insulating layer 240 disposed between a supporting wafer substrate 260 and a silicon layer 220; the donor wafer substrate 280 is a wafer that provides the silicon layer 220, and the supporting wafer substrate 260 is a substrate that carries the insulating layer 240 and the silicon layer 220 after bonding and peeling.

[0024] In this embodiment, the peeling annealing refers to the bonded structure undergoing multiple heating stages sequentially within the same annealing process, without removing the bonded structure between stages or cooling it to room temperature before starting the next heating stage. The temperature and heating rate in the peeling annealing are controlled by the set temperature of the annealing equipment. In some embodiments, a holding stage can be set after each heating stage.

[0025] This disclosure utilizes the different migration and defect evolution rates of hydrogen in different temperature zones to divide the exfoliation annealing into three stages. The first heating stage provides time for microcavity nucleation, the second heating stage promotes bubble growth and relaxes local stress, and the third heating stage increases the crack driving force and enables the crack to penetrate along the ion implantation layer 210. The following detailed description is provided in conjunction with the accompanying drawings: See Figure 1 The method for preparing silicon-on-insulator wafer 200 includes steps S110, S120, S130, S140, S150 and S160.

[0026] In step S110, an insulating layer 240 is formed on the bonding surface of the donor wafer substrate 280. The insulating layer 240 may be a silicon dioxide layer, specifically formed by thermal oxidation, with a thickness of less than 300 nm; in one embodiment, the thickness of the thermally oxidized layer may be 100 nm, and it is formed before ion implantation. The donor wafer substrate 280 and the support wafer substrate 260 may be made of silicon material, and the wafer diameter may be 300 mm.

[0027] In step S120, ion implantation is performed on the donor wafer substrate 280 to form an ion implantation layer 210 inside the donor wafer substrate 280. Ion implantation can be performed using hydrogen ions alone, helium ions alone, or a combination of hydrogen and helium ions. In this embodiment, hydrogen ion implantation is used as an example. The ion implantation layer 210 extends along the in-plane direction of the donor wafer substrate 280, and its depth determines the thickness of the silicon material subsequently transferred from the donor wafer substrate 280 to the insulating layer 240 side.

[0028] Ion implantation energy can range from 50 keV to 100 keV, for example, 75 keV; the implantation dose can be 4 × 10¹. 6 cm - ² (cm) - ²)~8×10¹ 6 cm - ², for example 6 × 10¹ 6 cm - ²; During implantation, the donor wafer substrate 280 is at room temperature, wherein, in this disclosure, the room temperature is 25 ± 2 °C (degrees Celsius). Ion implantation can be performed from the side where a 100 nm thermal oxide layer is formed, starting from the surface of the thermal oxide layer away from the donor wafer substrate 280, and the implantation depth can be approximately 680 nm.

[0029] In step S130, the side of the donor wafer substrate 280 with the insulating layer 240 is placed opposite the supporting wafer substrate 260 and hydrophilically directly bonded to form a bonded structure. The hydroxyl groups on the hydrophilic surface can form an initial bond upon contact and improve the bond strength during subsequent peeling annealing.

[0030] In step S140, the bonded structure is placed in an annealing apparatus for peel annealing. The annealing apparatus can be a vertical or horizontal resistance heating furnace with a furnace tube diameter of 300 mm. During peel annealing, nitrogen or other inert gases (such as argon) can be used as a protective atmosphere to reduce the influence of external oxygen and moisture on the surface of the bonded structure.

[0031] After the bonded structure enters the annealing equipment, the paddle carrying the bonded structure is first positioned at a predetermined location, and nitrogen gas is continuously introduced into the furnace tube before the first heating stage begins. Nitrogen gas is introduced into the annealing equipment at a flow rate of 5 SLM (Standard Liters per Minute). The nitrogen gas flows from the inlet to the outlet to replace the existing gas in the furnace tube, ensuring that the exposed surface of the bonded structure is in a nitrogen protective atmosphere during the peeling annealing process.

[0032] A horizontal resistance heating furnace can have multiple heating zones along the axial direction of the furnace tube. Each heating zone's heating power is adjusted by a controller based on temperature feedback from a corresponding temperature detection device. The bonding structure is placed within the furnace tube area covered by these multiple heating zones, and there may still be time differences in temperature response at different locations. Therefore, the set heating rate is the target change in the set temperature of the annealing equipment per unit time, and does not mean that the actual temperature at each location of the bonding structure changes synchronously according to this set heating rate.

[0033] During the execution of the three-stage procedure, the controller records the initial set temperature, the final set temperature, the moment when the set temperature reaches the final set temperature, and the moment when the holding time ends for each stage. When setting the temperature stability criterion for the annealing equipment, the controller determines whether the current stage has reached a temperature stable state based on the temperature measurement values ​​of different areas of the paddle, and starts calculating the holding time after the temperature stable state is reached.

[0034] The annealing equipment executes heating and holding procedures according to the set temperature, and detects the temperature of the paddle carrying the bonded structure through a temperature sensor. The paddle temperature is used for temperature feedback control of the annealing equipment. During peeling annealing, the absolute value of the difference between the furnace temperature and the set temperature is no greater than 0.5℃, where the furnace temperature can be characterized by the paddle temperature.

[0035] Reference Figure 2 Step S140 may further include steps S141, S142, and S143. The three steps are executed sequentially in the same annealing process, and the next stage is directly entered from the termination temperature of the adjacent stage, without setting an intermediate cooling process to return to room temperature.

[0036] The boundary between adjacent stages is determined by the set temperature reaching the corresponding termination temperature. After reaching the first termination temperature, the controller maintains the set temperature and begins accumulating the first holding time; after the first holding time ends, the controller switches the target rate of change to the second set heating rate; the second stage and the third stage are connected in the same way. Under this switching mode, the first holding platform, the second holding platform, and the third holding platform are all part of the stripping annealing process, and the bonded structure does not move out of the furnace tube between the holding platforms.

[0037] In step S141, the set temperature of the annealing equipment is raised to 180°C to 220°C at a set heating rate of 2°C / min to 3°C / min, and held at the termination temperature of the first heating stage for 15 min to 25 min. The lower heating rate and the first holding plateau allow for a longer local recombination time of the injected hydrogen within the nucleation temperature region.

[0038] The termination temperature of the first heating stage is 180°C to 220°C. Within this temperature range, microcavities are formed in the ion implantation layer 210, and cracks extending continuously along the ion implantation layer 210 have not yet formed. If the termination temperature is close to 180°C, the nucleation time can be supplemented by a longer holding time; if the termination temperature is close to 220°C, the thermal budget before entering the bubble growth stage can be limited by a shorter holding time. At the end of the first heating stage, the silicon interconnects between adjacent microcavities remain connected.

[0039] In step S142, the set temperature of the annealing equipment is raised from the end temperature of the first heating stage to 380°C to 420°C at a set heating rate of 4°C / min to 6°C / min, and held at the end temperature of the second heating stage for 25 min to 35 min. The second holding platform is used to further concentrate the bubble size and release some local stress at the silicon connection between the bubbles.

[0040] The second heating stage has a higher heating rate than the first heating stage, allowing the microcavities that have completed the main nucleation process to enter the bubble growth process, while shortening the residence time in the intermediate temperature region. The second termination temperature and its holding time together determine the degree of hydrogen absorption by the bubbles, the bubble spacing, and the remaining thickness of the silicon interconnect.

[0041] In step S143, the set temperature of the annealing equipment is raised from the end temperature of the second heating stage to 450°C to 520°C at a set heating rate of 8°C / min to 12°C / min, and then held at the end temperature of the third heating stage for 8 min to 12 min. The heating rate of the third heating stage is higher than that of the first two stages, so that the quasi-fracture surface formed can obtain the driving force required for crack penetration while shortening the residence time in the high-temperature zone.

[0042] The third stage does not rely on rapid heating to form cracks in isolation. If the first two stages do not form bubbles with relatively concentrated size and spacing, rapid heating may widen the fracture time difference between different regions; in the peeling annealing of this disclosure, the third stage starts from the quasi-fracture surface formed in the first two stages, so a higher heating rate is used to promote the penetration of the already formed bubbles and silicon interconnect structure.

[0043] In step S150, after the holding period of the third heating stage is completed, the set temperature of the annealing equipment is reduced. The method of reducing the set temperature can be natural cooling, controlled cooling at a set cooling rate, or other cooling methods suitable for the annealing equipment, and this disclosure does not limit this method.

[0044] In step S160, the formed silicon layer 220 may undergo repair annealing and sacrificial oxidation. The repair annealing temperature may be 900°C and maintained for 1 hour; the sacrificial oxidation process forms a sacrificial oxide on the surface of the silicon layer 220, which is then removed to thin and flatten the silicon layer 220.

[0045] Through the above steps, a silicon-on-insulator wafer 200 can be formed. The following is combined with... Figures 3(a) to 3(c) The bonding, stripping, and silicon layer formation processes are further explained.

[0046] Reference Figures 3(a) to 3(c) Figure 3(a) shows the donor wafer substrate 280 after completing steps S110 and S120. An insulating layer 240 is located on the surface of the donor wafer substrate 280, and hydrogen and / or helium are injected from the injection surface of the donor wafer substrate 280 along its thickness direction to form an ion implantation layer 210 within the donor wafer substrate 280.

[0047] Figure 3(b) shows the bonding structure after step S130. The insulating layer 240 is sandwiched between the donor wafer substrate 280 and the support wafer substrate 260, the ion implantation layer 210 is located in the donor wafer substrate 280, and the silicon material of the ion implantation layer 210 near the insulating layer 240 is retained as silicon layer 220 after peeling.

[0048] Figure 3(c) shows the silicon-on-insulator wafer 200 after stripping and annealing. The donor wafer substrate 280 is separated along the ion implantation layer 210, and the silicon material retained on the insulating layer 240 forms the silicon layer 220; the side of the silicon layer 220 away from the insulating layer 240 forms the stripping surface 250.

[0049] The peel surface 250 is located within the depth range of the ion implantation layer 210. Bubbles and implantation damage in the ion implantation layer 210 are distributed within a certain depth range along the thickness direction of the donor wafer substrate 280, and cracks propagate and penetrate within this depth range. Therefore, a subsurface damage region may remain below the peel surface 250 formed after peeling, which can be thinned or repaired through post-processing.

[0050] Figure 4 The diagram shows the local structure after the first heating stage. Hydrogen in the ion-implanted layer 210 exists as interstitial H (hydrogen) atoms, Si-H bonded states (silicon-hydrogen bonded states), and V... n H m It exists in the form of a vacancy (compound vacancy defect). V n H mIn the vacancy section, V represents a vacancy, n represents the number of vacancyes in the composite defect, H represents a hydrogen atom, and m represents the number of hydrogen atoms in the composite defect. Upon heating, adjacent silicon-hydrogen bonds undergo local recombination and release molecular hydrogen, which then aggregates at the vacancy clusters to form microcavities.

[0051] Within the 25℃–100℃ range, hydrogen is mainly retained near the sites of ion implantation, and no visible changes are observed on the outer surface of the donor wafer substrate 280. Within the 100℃–150℃ range, adjacent Si-H bonds recombine and release H2 (hydrogen) molecules. Within the 150℃–200℃ range, H2 molecules aggregate at vacancy clusters and form microcavities, which gradually reach a stable state.

[0052] The nucleation location of the microcavity is influenced by both the hydrogen concentration distribution and the implantation damage distribution. The hydrogen concentration and defect density are higher near the center of the ion implantation layer 210, making it easier for the microcavity to form first; the hydrogen concentration is lower on both sides, requiring a longer time to complete local reorganization, so a lower set heating rate is used in the first heating stage.

[0053] The first thermal plateau allows regions where Si-H bond recombination has not yet occurred to continue releasing H2 molecules, and these molecules continue to aggregate at vacancy clusters to form microcavities, thereby reducing the density and size differences of microcavities at different locations in the ion implantation layer 210. At the temperature corresponding to the first thermal plateau, the silicon interconnects remain connected, and no continuously extending cracks have formed. The first thermal plateau is mainly used to promote the formation and uniform distribution of microcavities, while subsequent thermal plateaus at higher temperatures are mainly used to promote bubble growth and release stress in the silicon interconnects.

[0054] When the temperature is increased to 200℃ at a rate of 2℃ / min and held for 20 min, the residence time within the nucleation window is longer than that of the scheme involving continuous heating at 7℃ / min without holding. The longer residence time allows the later-formed microcavities to still absorb and grow neighboring molecular hydrogen, reducing the size difference between the earlier and later-formed microcavities.

[0055] The surface density of the microcavity after the first insulation period is approximately 8 × 10¹. 0 cm - ², with diameters concentrated in the range of 10 nm to 20 nm, a standard deviation of approximately ±3 nm, and an in-plane spacing of approximately 30 nm to 40 nm.

[0056] The first heating stage creates microcavities with small size differences within the ion implantation layer 210, allowing each microcavity to grow from a similar size during subsequent heating processes. Reducing the size difference between microcavities inhibits the migration of H2 from smaller to larger microcavities, slows down the shrinkage process of smaller microcavities, and maintains consistent microcavity density at different locations within the ion implantation layer 210, which is beneficial for the continuous propagation of cracks along the ion implantation layer 210.

[0057] When the heating rate is high or no holding process is set in the first heating stage, microcavities at different locations in the ion implantation layer 210 may form at different times. Microcavities formed earlier have a longer time to absorb H2 and are relatively larger in size; microcavities formed later have a shorter time to absorb H2 and are relatively smaller in size. During subsequent heating processes, H2 migrates from small-sized microcavities to large-sized microcavities, further increasing the size difference between microcavities and bubbles. Using a lower heating rate in the first stage and setting a first holding platform can reduce the difference in microcavity formation time and size, allowing subsequently formed bubbles to have a more consistent growth state, which is beneficial for continuous crack propagation.

[0058] Figure 5 The diagram shows a local structure after the second heating stage has ended. As the temperature rises from the first termination temperature to the second termination temperature, the microcavity absorbs the diffused hydrogen and transforms it into bubbles; the silicon material retained between adjacent bubbles forms silicon interconnects, which gradually thin as the bubbles grow.

[0059] Within the temperature range of 200℃ to 250℃, hydrogen in the ion-implanted layer 210 migrates towards and enters the microcavities, causing the microcavities to gradually transform from a flat, disc-like shape into bubbles that bulge along the thickness direction. Within the temperature range of 250℃ to 300℃, the bubbles continue to absorb hydrogen and grow larger. Because the initial size differences between the microcavities are relatively small, there is less hydrogen migration between different bubbles due to size differences, allowing each bubble to maintain a similar growth process.

[0060] Within the 300℃ to 350℃ range, bubbles continue to grow, and the silicon junctions between adjacent bubbles gradually narrow. The internal pressure of the bubbles and the stress fields generated by adjacent bubbles work together on the silicon junctions. Within the 350℃ to 400℃ range, the silicon junctions continue to narrow. A set heating rate of 5℃ / min causes microscopic deformation of the silicon junctions through silicon atom diffusion during the heating process, reducing stress concentration.

[0061] Holding the temperature at 400℃ for 30 minutes allows smaller bubbles to continue absorbing hydrogen and further converges their size distribution. This heat treatment also relaxes the local elastic stress in the silicon connectors, resulting in more similar thickness and stress states at different locations when entering the third heating stage.

[0062] As bubbles grow, their curvature and internal pressure change with size, and hydrogen migration may occur between larger and smaller bubbles. When the size distribution of the preceding microcavities is narrow, the curvature difference between bubbles is small, and holding at 400℃ is more likely to result in most bubbles continuing to grow, rather than a small number of bubbles continuously engulfing surrounding smaller bubbles.

[0063] The silicon interconnect is the silicon material that remains connected between adjacent bubbles. As the bubbles grow, the thickness of the silicon interconnect decreases, and the local stress increases. The 400℃ heat treatment provides time for local diffusion and creep, allowing the high-stress locations to be adjusted before entering the third stage, thereby reducing premature local fracture.

[0064] After the second heat preservation period, the bubble diameter was approximately 180 nm to 220 nm, and the areal density was approximately 2 × 10⁻⁶. 9 cm - ²~3×10 9 cm - ², the thickness of the silicon interconnect is approximately 8 nm to 12 nm, and the warpage increase of the 300 mm wafer is approximately 2 μm to 5 μm.

[0065] After the second heating stage, the bubbles form in-plane continuous quasi-fracture surfaces near the ion implantation layer 210. The reduced dispersion in bubble size and silicon interconnect thickness decreases the possibility of premature fracture of local silicon interconnects while other areas are not yet mature.

[0066] The quasi-fracture surface represents a weak region formed by multiple bubbles and their inter-bubbles silicon connections, and does not indicate that macroscopic separation has been completed at this point. This state still maintains partial connectivity between the donor wafer substrate 280 and the silicon layer 220, but the stress conditions required for the connection tend to be similar in-plane.

[0067] Figure 6 This illustrates the further propagation of the crack during the third heating stage. During the second heating stage, some silicon interconnects may have already partially fractured, but the crack has not yet penetrated the ion-implanted layer 210. As the set temperature of the annealing apparatus rises from the second termination temperature to the third termination temperature, the unfractured silicon interconnects continue to fracture, and the already formed crack segments gradually connect near the depth of the ion-implanted layer 210 until the crack penetrates.

[0068] The third heating stage uses a set heating rate of 8℃ / min to 12℃ / min, which can shorten the residence time in the high-temperature zone. The first two stages have already made the in-plane state of the microcavities and bubbles more consistent. The faster heating in the third stage is mainly used to increase the crack driving force, rather than to compensate for the nucleation or bubble growth that was not completed in the previous stages.

[0069] Under the annealing conditions of Example 1, the silicon interconnects can begin to fracture at approximately 420°C, and the crack can complete in-plane penetration at approximately 480°C to 490°C. The temperature range from the onset of fracture to complete penetration is approximately 60°C to 70°C. The silicon interconnects begin to fracture at relatively thin locations, releasing local elastic strain energy and altering the stress state of adjacent silicon interconnects. As the temperature continues to rise, more fracture segments form and connect with each other, and the crack gradually transforms from discrete segments into a continuous crack surface.

[0070] As the crack propagates along the ion implantation layer 210, the silicon connections between adjacent bubbles break sequentially, gradually connecting the cracks. When the bubbles formed in the first and second heating stages have relatively consistent size and spacing, the width difference between the silicon connections is small, allowing the crack to propagate continuously along the distribution of the bubbles and reducing the possibility of the crack deviating from the ion implantation layer 210.

[0071] After the crack penetrates, the remaining portion of the donor wafer substrate 280 separates from the silicon layer 220 retained on the insulating layer 240. After holding at 500°C for 10 minutes, the set temperature of the annealing equipment is lowered. Holding at 500°C for 10 minutes allows the regions that have reached the separation conditions to be completely separated.

[0072] The uniform quasi-fracture surface formed in the first two stages, combined with the rapid heating in the third stage, makes the crack propagation path closer to the plane of the ion implantation layer 210. This reduces steps and deep pits caused by localized early fracture, crack deflection, or forced tearing. The first two insulation platforms are used for nucleation and bubble maturation, respectively, while the third insulation platform, after the crack driving force has reached a high level, provides completion time for localized areas that have not yet completed connection.

[0073] The following examples and comparative examples illustrate the relevant numerical ranges of this disclosure: Example 1 In all embodiments and comparative examples, a 100 nm thermal oxide layer was pre-formed on the surface of the donor wafer substrate 280, with an implantation energy of 75 keV and a 6 × 10¹⁰ nm anode. 6 cm - Ion implantation was performed using an implantation dose of 2, followed by hydrophilic direct bonding to the supporting wafer substrate 260. The bonded structure was placed in a horizontal resistance furnace and subjected to a three-stage stripping annealing process under a nitrogen protective atmosphere. The nitrogen flow rate was set to 5 standard liters per minute, and the absolute value of the temperature difference between the furnace and the set temperature was controlled within 0.5°C.

[0074] In Example 1, the first heating stage started at 25°C and increased to 200°C at a set heating rate of 2°C / min, then held at 200°C for 20 min. The second heating stage increased from 200°C to 400°C at a set heating rate of 5°C / min, then held at 400°C for 30 min. The third heating stage increased from 400°C to 500°C at a set heating rate of 10°C / min, then held at 500°C for 10 min. The total time for the three heating stages and three holding stages was 197.5 min. After the third holding stage, the set temperature of the annealing equipment was lowered.

[0075] After the first insulation platform is completed, the microcavity surface density formed within the ion implantation layer 210 is approximately 8 × 10¹. 0 cm -², the microcavity diameters are concentrated in the range of 10 nm to 20 nm, with a dimensional standard deviation of approximately ±3 nm and an in-plane spacing of approximately 30 nm to 40 nm. After the second insulation platform is completed, the bubble diameter is approximately 180 nm to 220 nm, and the areal density is approximately 2 × 10⁻⁶. 9 cm - ²~3×10 9 cm - ², the thickness of the silicon interconnect is approximately 8 nm to 12 nm.

[0076] In Example 1, the silicon interconnects began to fracture at approximately 420°C, and the crack completed its penetration at approximately 480°C to 490°C. The temperature range from the initial formation of the crack segment to its completion was approximately 60°C to 70°C. After peeling, the root mean square (RMS) roughness of the peeled surface 250 within a 10 μm × 10 μm measurement area was 0.28 nm, the thickness of the subsurface damage region was 40 nm to 60 nm, and the peak residual hydrogen concentration was approximately 3 × 10¹. 8 cm - ³. In the 49-point ellipsometric measurement results of Example 1, the average thickness of silicon layer 220 was 580 nm, with a standard deviation of ±1.8 nm. Figures 7(a), 8(a), and 8(b) show the roughness distribution and atomic force microscopy morphology corresponding to Example 1.

[0077] Example 2 In Example 2, the first heating stage involved raising the temperature to 180°C at a rate of 2°C / min and holding for 25 min; the second heating stage involved raising the temperature to 380°C at a rate of 4°C / min and holding for 35 min; and the third heating stage involved raising the temperature to 450°C at a rate of 8°C / min and holding for 12 min. This parameter combination employed a relatively low termination temperature and selected a longer holding time within the range of holding times for each stage. The remaining process conditions and testing methods were the same as in Example 1.

[0078] In Example 2, the silicon interconnect began to fracture at approximately 375°C, and the crack completed its penetration at approximately 440°C to 450°C. The temperature range from the initial formation of the crack segment to its completion was approximately 65°C to 75°C. After peeling, the root mean square roughness of the peeled surface 250 within a 10 μm × 10 μm measurement area was 0.31 nm, and the thickness of the subsurface damage region was 45 nm to 65 nm. In the 49-point ellipsometric measurement results of Example 2, the average thickness of the silicon layer 220 was 578 nm, with a standard deviation of ±2.5 nm.

[0079] Example 3 In Example 3, the first heating stage involved raising the temperature to 220°C at a rate of 3°C / min and holding it for 15 min; the second heating stage involved raising the temperature to 420°C at a rate of 6°C / min and holding it for 25 min; and the third heating stage involved raising the temperature to 520°C at a rate of 12°C / min and holding it for 8 min. This parameter combination employed a higher termination temperature and selected shorter holding times within the range of holding times for each stage. The remaining process conditions and testing methods were the same as in Example 1.

[0080] In Example 3, the silicon interconnect began to fracture at approximately 440°C, and the crack completed its penetration at approximately 495°C to 505°C. The temperature range from the initial formation of the crack segment to its completion was approximately 55°C to 65°C. After peeling, the root mean square roughness of the peeled surface 250 within a 10 μm × 10 μm measurement area was 0.35 nm, and the thickness of the subsurface damage region was 55 nm to 70 nm. In the 49-point ellipsometric measurement results of Example 3, the average thickness of the silicon layer 220 was 582 nm, with a standard deviation of ±3.2 nm.

[0081] Comparative Example 1 Comparative Example 1 started at 25°C and heated to 500°C at a single set heating rate of 7°C / min. No holding plateaus were set at 200°C and 400°C, and no third holding was performed after reaching 500°C. The theoretical heating time from 25°C to 500°C was approximately 67.9 min. Except for the temperature program, the other process conditions and testing methods were the same as in Example 1.

[0082] Comparative Example 1 takes less time to pass through the 100℃~200℃ range than Example 1, resulting in a greater time difference and size difference in the formation of microcavities at different locations of the ion implantation layer 210. After entering the 200℃~400℃ range, H2 migration between bubbles of different sizes causes the bubble size difference to continue to increase, and silicon interconnects at different locations break at different temperatures, with cracks connecting at different depths in the ion implantation layer 210.

[0083] The root mean square roughness of the peeled surface 250 in Comparative Example 1 within a 10 μm × 10 μm measurement area is 0.52 nm, and the thickness of the subsurface damage region ranges from 80 nm to 120 nm. The average silicon layer thickness obtained by 49-point ellipsometry is 582 nm, with a standard deviation of ±4.5 nm. Figures 7(b), 8(c), and 8(d) show the roughness distribution and atomic force microscopy morphology corresponding to Comparative Example 1.

[0084] Comparative Example 2 The heating rate and termination temperature for the three heating stages in Comparative Example 2 were the same as in Example 1. In the first heating stage, after reaching 200°C, no holding time was applied; the temperature was directly increased to 400°C at 5°C / min and held for 30 min. Subsequently, the temperature was increased to 500°C at 10°C / min and held for 10 min. This comparative example was used to compare the impact of the first holding platform on the microcavity density, microcavity size distribution, and final product parameters.

[0085] In Comparative Example 2, the root mean square roughness of the peeled surface 250 within a 10 μm × 10 μm measurement area is 0.41 nm, and the thickness of the subsurface damage region ranges from 70 nm to 100 nm. The average silicon layer thickness obtained by 49-point ellipsometry measurement is 581 nm, with a standard deviation of ±3.8 nm.

[0086] Comparative Example 3 The heating rate and termination temperature for the three heating stages in Comparative Example 3 were the same as in Example 1. In the first heating stage, after reaching 200°C, the temperature was held for 20 minutes. In the second heating stage, after reaching 400°C, no holding was performed; the temperature was directly increased to 500°C at a rate of 10°C / min and held for 10 minutes. This comparative example was used to compare the impact of the second holding platform on bubble size distribution, stress state of the silicon connector, and final product parameters.

[0087] In Comparative Example 3, the root mean square roughness of the peeled surface 250 within a 10 μm × 10 μm measurement area was 0.46 nm, and the thickness of the subsurface damage region ranged from 75 nm to 110 nm. The average silicon layer thickness obtained by 49-point ellipsometry measurement was 583 nm, with a standard deviation of ±4.2 nm.

[0088] Comparative Example 4 The heating rate and termination temperature for the three heating stages in Comparative Example 4 were the same as in Example 1. In the first heating stage, the temperature was held at 200°C for 20 minutes; in the second heating stage, the temperature was held at 400°C for 30 minutes; and in the third heating stage, the temperature was not held at 500°C and cooling began. This comparative example was used to compare the impact of the third holding platform on crack penetration and final product parameters.

[0089] In Comparative Example 4, the root mean square roughness of the peeled surface 250 within a 10 μm × 10 μm measurement area was 0.38 nm, and the thickness of the subsurface damage region ranged from 55 nm to 80 nm. The average silicon layer thickness obtained by 49-point ellipsometry measurement was 579 nm, with a standard deviation of ±2.9 nm.

[0090] The results of Example 1 and Comparative Example 1 show that the three-stage exfoliation annealing not only changes the time required to reach 500°C, but also alters the dwell time during microcavity formation, bubble growth, and crack propagation. The root mean square roughness, subsurface damage region thickness, residual hydrogen concentration, and standard deviation of silicon layer thickness in Example 1 are all lower than those in Comparative Example 1, corresponding to the aforementioned effects of improved bubble size and spacing consistency, and continuous crack propagation along the depth of the ion implantation layer 210.

[0091] Examples 2 and 3, as well as Comparative Examples 2 to 4, are used to further evaluate the range of parameters and the function of the insulation platform. The product parameters of Examples 2 and 3 can be used to illustrate whether the same technical effects as in Example 1 can be obtained at both ends of the temperature, heating rate, and insulation time ranges. Comparative Examples 2 to 4, by changing one insulation platform respectively, can be used to distinguish the function of each insulation platform and verify the coordination relationship between the three stages.

[0092] Table 1. Peeling annealing parameters for the examples and comparative examples.

[0093] Table 2. Product parameters and process results of the examples and comparative examples.

[0094] Referring to Figure 3(c), this disclosure also provides a silicon-on-insulator (SBI) wafer 200, which can be fabricated by the method provided in this disclosure. The SBI wafer 200 comprises a supporting wafer substrate 260, an insulating layer 240, and a silicon layer 220. The insulating layer 240 is disposed on one side of the supporting wafer substrate 260, and the silicon layer 220 is disposed on the side of the insulating layer 240 away from the supporting wafer substrate 260. A release surface 250 is located on the side of the silicon layer 220 away from the insulating layer 240.

[0095] The silicon layer 220 is formed by peeling off the donor wafer substrate 280 along the ion implantation layer 210 formed by ion implantation. The ion implantation layer 210 determines the peeling depth. The insulating layer 240 constitutes the electrical isolation layer between the silicon layer 220 and the supporting wafer substrate 260.

[0096] In the silicon layer 220, there is a subsurface damage region formed by ion implantation and crack propagation in the direction from the peeling surface 250 toward the insulating layer 240. As a set of characterization results of the foregoing embodiments and comparative examples, the thickness of the subsurface damage region in Example 1 is 40 nm to 60 nm, and in Comparative Example 1 it is 80 nm to 120 nm. Example 1 has a smaller subsurface damage region than Comparative Example 1.

[0097] Subsurface damage regions can be observed using cross-sectional transmission electron microscopy (TEM) to detect dislocation loops, stacking faults, and residual voids. Secondary ion mass spectrometry (SIMS) can also be used to analyze the residual hydrogen distribution near the exfoliation surface. When using cross-sectional TEM to determine the thickness of the subsurface damage region, the exfoliation surface 250 can be used as the depth starting point. Under the same sample preparation conditions, cross-sectional orientation, and imaging conditions, regions with higher defect densities than the bulk silicon can be identified along the thickness direction of the silicon layer 220. The sample preparation position, cross-sectional orientation, and field of view should be consistent. When using SIMS to analyze residual hydrogen, the hydrogen concentration as a function of depth can be recorded, with the exfoliation surface 250 or the surface of the silicon layer 220 used as the depth reference. The residual hydrogen peak value given by SIMS is not directly equivalent to the damage thickness observed by TEM, but both can respectively illustrate the changes in residual injected hydrogen and lattice defects. When using ellipsometry to measure the thickness of the silicon layer 220, multiple measurement points can be preset within the wafer surface, and the average and standard deviation of the measurements within the same edge exclusion width can be calculated.

[0098] In a set of residual hydrogen and film thickness characterization results, the peak residual hydrogen concentration in Example 1 was approximately 3 × 10¹. 8 cm - ³ (cm) - ³), compared to Example 1, approximately 8 × 10¹ 8 cm - ³; The mean thickness of the silicon layer measured by 49-point ellipsometry in Example 1 was 580 nm with a standard deviation of ±1.8 nm, while the mean thickness in Comparative Example 1 was 582 nm with a standard deviation of ±4.5 nm.

[0099] The apparent activation energy of crack propagation can be used to describe the batch stability of the peeling temperature. In one set of results, the apparent activation energy of Example 1 was 2.52 ± 0.08 eV (eV) with a linear fit coefficient of determination of 0.998, and the apparent activation energy of Comparative Example 1 was 2.52 ± 0.45 eV.

[0100] Implementation methods within the parameter range: The heating rate for the first heating stage can be selected from 2℃ / min to 3℃ / min, the termination temperature can be selected from 180℃ to 220℃, and the holding time can be selected from 15 min to 25 min. The specific values ​​can be matched according to the ion implantation dose, the thermal capacity of the donor wafer substrate 280, and the temperature field response of the annealing equipment.

[0101] The heating rate for the second heating stage can be selected from 4℃ / min to 6℃ / min, the termination temperature from 380℃ to 420℃, and the holding time from 25 min to 35 min. The values ​​for this stage should allow the bubbles to grow completely while minimizing the possibility of the silicon connector breaking before entering the third heating stage.

[0102] The heating rate for the third heating stage can be selected from 8℃ / min to 12℃ / min, the termination temperature can be selected from 450℃ to 520℃, and the holding time can be selected from 8 min to 12 min. The termination temperature and holding time for this stage should allow the crack to penetrate along the ion implantation layer 210.

[0103] The control target for each stage of the stripping annealing process is the set temperature of the annealing equipment. If the equipment uses multi-zone temperature control, the controller can adjust the heating power according to the temperature measurement results of different zones of the furnace tube, so that the area where the wafer-bearing paddle is located follows the set program. This control does not change the sequence of the three heating stages.

[0104] The three heating stages use the microstructure formed in the previous stage as the initial state for the next stage, thereby achieving phased control of microcavity formation, bubble maturation, and crack penetration, respectively.

[0105] It should be noted that the technical solutions described in this disclosure can be combined arbitrarily as long as they do not conflict.

[0106] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A method for fabricating a silicon-on-insulator wafer, characterized in that, include: Ion implantation is performed on the donor wafer substrate to form an ion implantation layer within the donor wafer substrate; The injection surface of the donor wafer substrate is bonded to the supporting wafer substrate through an insulating layer to form a bonding structure; as well as The bonding structure is subjected to peeling annealing, which causes the ion implantation layer to evolve into a bubble layer and cracks to penetrate along the ion implantation layer, so that the donor wafer substrate is peeled off along the ion implantation layer to obtain silicon-on-insulator wafer. The peeling annealing process employs multi-stage temperature control, which includes at least a first temperature stage, a second temperature stage, and a third temperature stage performed sequentially. The first heating stage is carried out at a first heating rate of 2℃ / min to 3℃ / min from the starting temperature to a first ending temperature in the range of 180℃ to 220℃. The second heating stage is carried out at a second heating rate of 4℃ / min to 6℃ / min from the first termination temperature to a second termination temperature in the range of 380℃ to 420℃. The third heating stage involves heating from the second termination temperature to a third termination temperature within the range of 450°C to 520°C at a third heating rate of 8°C / min to 12°C / min.

2. The method for fabricating silicon-on-insulator wafers according to claim 1, characterized in that, The multi-stage heating control further includes: setting a first heat preservation platform located at the first termination temperature, with a heat preservation time ranging from 15 min to 25 min; setting a second heat preservation platform located at the second termination temperature, with a heat preservation time ranging from 25 min to 35 min; and setting a third heat preservation platform located at the third termination temperature, with a heat preservation time ranging from 8 min to 12 min.

3. The method for preparing a silicon-on-insulator wafer according to claim 2, characterized in that, The heating rate of the first heating stage is 2℃ / min, the first termination temperature is 200℃, and the holding time of the first heat preservation platform is 20min; the heating rate of the second heating stage is 5℃ / min, the second termination temperature is 400℃, and the holding time of the second heat preservation platform is 30min; the heating rate of the third heating stage is 10℃ / min, the third termination temperature is 500℃, and the holding time of the third heat preservation platform is 10min.

4. The method for fabricating silicon-on-insulator wafers according to claim 1, characterized in that, The insulating layer is a thermal oxide layer formed on the surface of the donor wafer substrate. The thermal oxide layer is formed before the ion implantation and has a thickness of 100 nm.

5. The method for fabricating silicon-on-insulator wafers according to claim 1, characterized in that, The ion implantation is hydrogen ion implantation, with an implantation energy of 50 to 100 keV and an implantation dose of 4 × 10¹. 6 Up to 8×10¹ 6 cm - ², the injection temperature is 23℃~27℃.

6. The method for fabricating silicon-on-insulator wafers according to claim 1, characterized in that, The side of the donor wafer substrate with the insulating layer formed thereon is hydrophilically directly bonded to the supporting wafer substrate to form the bonding structure.

7. The method for fabricating silicon-on-insulator wafers according to claim 1, characterized in that, The stripping annealing is carried out in a vertical or horizontal resistance heating furnace under a nitrogen or other inert gas protective atmosphere, and the temperature difference between the heating furnace and the set temperature is controlled within ±0.5℃.

8. The method for fabricating silicon-on-insulator wafers according to claim 1, characterized in that, After obtaining the silicon-on-insulator wafer, the silicon layer of the silicon-on-insulator wafer is subjected to repair annealing and sacrificial oxidation treatment. The repair annealing treatment is performed at a temperature of 900°C for a duration of 1 hour.

9. A silicon-on-insulator wafer, characterized in that, include: Supporting wafer substrate; An insulating layer is disposed on one side of the supporting wafer substrate; as well as A silicon layer is disposed on the side of the insulating layer away from the supporting wafer substrate, and the side of the silicon layer away from the insulating layer is the release surface; The silicon layer is formed by peeling off the donor wafer substrate along the ion implantation layer through peeling annealing. The ion implantation layer is formed by ion implantation. The donor wafer substrate is bonded to the supporting wafer substrate through the insulating layer before the peeling annealing. The peeling annealing process employs multi-stage temperature control, which includes at least a first temperature stage, a second temperature stage, and a third temperature stage performed sequentially. The first heating stage is carried out at a first heating rate of 2℃ / min to 3℃ / min from the starting temperature to a first ending temperature in the range of 180℃ to 220℃. The second heating stage is carried out at a second heating rate of 4℃ / min to 6℃ / min from the first termination temperature to a second termination temperature in the range of 380℃ to 420℃. The third heating stage is carried out at a third heating rate of 8℃ / min to 12℃ / min, raising the temperature from the second termination temperature to a third termination temperature in the range of 450℃ to 520℃. The root mean square roughness of the peeled surface obtained after the peeling annealing is no greater than 0.4 nm in a measurement area of ​​10 μm × 10 μm, and the thickness of the subsurface damage region of the peeled surface is 40 nm to 60 nm.

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