Solid-state imaging device and electronic apparatus

Abstract

The present disclosure relates to a solid-state imaging device configured to be capable of further miniaturizing a pixel size and an electronic apparatus. A first series active region is a single active region provided by forming an active region constituting a first gate and an active region constituting a second gate in a continuous linear shape and disposing the first gate and the second gate in series; a second series active region is a single active region provided by forming an active region constituting a second amplification gate and an active region constituting a selection gate in a continuous linear shape and disposing the second amplification gate and the selection gate in series. The first series active region and the second series active region are arranged in parallel with each other. The present technology can be applied to, for example, a voltage domain global shutter type CMOS image sensor.

Description

Technical Field

[0001] This disclosure relates to solid-state imaging devices and electronic devices, and more specifically, to solid-state imaging devices and electronic devices capable of further miniaturizing pixel size. Background Technology

[0002] In recent years, with the increase in pixel count, there is a need for global shutter complementary metal-oxide-semiconductor (CMOS) image sensors (which do not produce focal plane distortion during imaging) to achieve finer pixel sizes. Furthermore, in global shutter complementary metal-oxide-semiconductor (CMOS) image sensors, voltage domain configurations have been proposed as a method for achieving simultaneous charge accumulation.

[0003] For example, Patent Document 1 discloses a voltage-domain global shutter type complementary metal-oxide-semiconductor (CMOS) image sensor, in which transistors are used as first-stage source followers.

[0004] Reference List

[0005] Patent documents

[0006] Patent Document 1: Japanese Patent Application Publication No. 2022-45912 Summary of the Invention

[0007] The problem to be solved by the present invention

[0008] Meanwhile, in voltage-domain global shutter complementary metal-oxide-semiconductor (CMOS) image sensors, when examining the configuration of capacitive elements used for the first-stage source follower, it is necessary to miniaturize the pixel size by improving layout efficiency.

[0009] This disclosure is made in view of this situation, and is intended to enable further miniaturization of pixel size.

[0010] Solution to the problem

[0011] A solid-state imaging device according to one aspect of this disclosure includes a pixel, the pixel comprising: a pixel circuit having at least one photoelectric conversion unit and outputting a pixel signal to a first node; and a sample-and-hold circuit comprising at least: a first capacitor having one end connected to the first node and maintaining the voltage of the pixel signal at a reset level output from the pixel circuit; a second capacitor having one end connected to the first node and maintaining the voltage of the pixel signal at a pixel signal level output from the pixel circuit; and a third capacitor having one end connected to the first capacitor and the other end connected to a signal line, one end of the first capacitor and one end of the second capacitor being connected to a junction point through which a ramp signal is supplied, the third capacitor forming a source follower circuit together with a first amplification gate of the pixel circuit, and a second amplification gate generating a charge phase with the charge accumulated in a second node connected to a gate electrode. The corresponding pixel signal; a selection gate, which selects a pixel to output the pixel signal generated by the second amplification gate; a first gate, which connects the third node and the second node, the third node serving as a connection point to the other end of the first capacitor; a second gate, which connects the fourth node and the second node, the fourth node serving as a connection point to the other end of the second capacitor; and a third gate, which resets the charge accumulated in the second node, the third node, and the fourth node, wherein the first series active region and the second series active region are arranged parallel to each other, the first series active region is a single active region, in the first series active region, the active region constituting the first gate and the active region constituting the second gate are formed as a continuous straight line and the first gate and the second gate are connected in series, and the second series active region is a single active region, in the second series active region, the active region constituting the second amplification gate and the active region constituting the selection gate are formed as a continuous straight line and the second amplification gate and the selection gate are connected in series.

[0012] An electronic device according to one aspect of this disclosure includes a solid-state imaging device, the solid-state imaging device including a pixel, the pixel including: a pixel circuit having at least one photoelectric conversion unit and outputting a pixel signal to a first node; and a sample-and-hold circuit including at least: a first capacitor having one end connected to the first node and maintaining the voltage of the pixel signal at a reset level output from the pixel circuit; a second capacitor having one end connected to the first node and maintaining the voltage of the pixel signal at a pixel signal level output from the pixel circuit; a third capacitor having one end connected to a connection point and the other end connected to a signal line, one end of the first capacitor and one end of the second capacitor being connected to the connection point, through which a ramp signal is supplied; the third capacitor forming a source follower circuit together with a first amplification gate of the pixel circuit; and a second amplification gate generating and accumulating at a second node connected to a gate electrode. The signal is a pixel signal corresponding to the charge in the second amplification gate; a selection gate selects a pixel to output the pixel signal generated by the second amplification gate; a first gate connects the third node and the second node, the third node serving as a connection point to the other end of the first capacitor; a second gate connects the fourth node and the second node, the fourth node serving as a connection point to the other end of the second capacitor; and a third gate resets the charge accumulated in the second node, the third node, and the fourth node, wherein the first series active region and the second series active region are arranged parallel to each other, the first series active region is a single active region, in the first series active region, the active region constituting the first gate and the active region constituting the second gate are formed as a continuous straight line and the first gate and the second gate are connected in series, and the second series active region is a single active region, in the second series active region, the active region constituting the second amplification gate and the active region constituting the gate are formed as a continuous straight line and the second amplification gate and the selection gate are connected in series.

[0013] In one aspect of this disclosure, a solid-state imaging device includes a pixel comprising: a pixel circuit having at least one photoelectric conversion unit and outputting a pixel signal to a first node; and a sample-and-hold circuit including at least a first capacitor having one end connected to the first node and maintaining the voltage of the pixel signal at a reset level output from the pixel circuit; a second capacitor having one end connected to the first node and maintaining the voltage of the pixel signal at a pixel signal level output from the pixel circuit; a third capacitor having one end connected to the first capacitor and the other end connected to a signal line; a connection point where one end of the first capacitor and one end of the second capacitor are connected, through which a ramp signal is supplied; the third capacitor forming a source follower circuit together with a first amplification gate of the pixel circuit; a second amplification gate generating a pixel signal corresponding to a charge accumulated in a second node connected to a gate electrode; a selection gate selecting a pixel to output the pixel signal generated by the second amplification gate; a first gate connecting the third node and the second node, the third node serving as a connection point to the other end of the first capacitor; a second gate connecting the fourth node and the second node, the fourth node serving as a connection point to the other end of the second capacitor; and a third gate resetting the charge accumulated in the second node, the third node, and the fourth node. Then, the first series active area and the second series active area are arranged parallel to each other. The first series active area is a single active area. In the first series active area, the active area constituting the first gate and the active area constituting the second gate are formed as a continuous straight line and the first gate and the second gate are connected in series. The second series active area is a single active area. In the second series active area, the active area constituting the second amplifying gate and the active area constituting the selection gate are formed as a continuous straight line and the second amplifying gate and the selection gate are connected in series. Attached Figure Description

[0014] Figure 1 A block diagram illustrating a configuration example of an imaging apparatus that applies this technology.

[0015] Figure 2 This is a circuit diagram showing a first configuration example of pixels.

[0016] Figure 3 This is a diagram showing a first cross-sectional configuration example of a solid-state imaging device.

[0017] Figure 4 This is a diagram showing an example of a second cross-sectional configuration of a solid-state imaging device.

[0018] Figure 5 This is a diagram showing an example of a first planar layout of pixels.

[0019] Figure 6 This is a diagram illustrating an example of a second-plane layout of pixels.

[0020] Figure 7 This is a diagram illustrating an example of a first planar layout of pixels arranged in a 2×2 configuration.

[0021] Figure 8 This is a diagram illustrating an example of a second planar layout of pixels arranged in a 2×2 configuration.

[0022] Figure 9 This is a diagram illustrating an example of a planar layout of a MIM layer with pixels arranged in a 2×2 configuration.

[0023] Figure 10 This is a diagram illustrating an example of a third-plane layout of pixels arranged in a 2×2 configuration.

[0024] Figure 11 This is a diagram illustrating an example of a fourth-plane layout of pixels arranged in a 2×2 configuration.

[0025] Figure 12 It is shown Figure 2 A circuit diagram of a configuration example of a 4-pixel shared structure.

[0026] Figure 13 This is a diagram illustrating an example of a fifth-plane layout of pixels arranged in a 2×2 configuration with a 4-pixel shared structure.

[0027] Figure 14 This is a diagram illustrating an example of a sixth-plane layout of pixels arranged in a 2×2 configuration with a 4-pixel shared structure.

[0028] Figure 15 This is a diagram illustrating an example of a seventh-plane layout in which pixels are arranged in a 2×2 configuration with a 4-pixel shared structure.

[0029] Figure 16 This is a diagram illustrating an example of an eighth-plane layout of pixels arranged in a 2×1 arrangement with a 2-pixel shared structure.

[0030] Figure 17 This is a diagram illustrating an example of a ninth-plane layout in which pixels are arranged in a 2×1 configuration with a 2-pixel shared structure.

[0031] Figure 18 This is a diagram illustrating an example of a tenth-plane layout of pixels arranged in a 2×1 arrangement with a 2-pixel shared structure.

[0032] Figure 19 This is a circuit diagram showing a second configuration example of pixels.

[0033] Figure 20 It is shown Figure 19 The circuit diagram shows a configuration example of a 4-pixel shared structure for the pixels in the diagram.

[0034] Figure 21 This is a diagram illustrating an example of an eleventh-plane layout of pixels arranged in a 2×2 configuration with a 4-pixel shared structure.

[0035] Figure 22 This is a diagram illustrating an example of a twelfth-plane layout of pixels arranged in a 2×2 configuration with a 4-pixel shared structure.

[0036] Figure 23 This is a diagram illustrating an example of the thirteenth floor plan layout.

[0037] Figure 24 This is a circuit diagram showing a third configuration example of pixels.

[0038] Figure 25 This is a diagram illustrating an example of the fourteenth floor plan layout.

[0039] Figure 26 This is a diagram illustrating an example of the layout of the fifteenth floor plan.

[0040] Figure 27 This is a diagram illustrating an example of the sixteenth plan layout.

[0041] Figure 28 This is a diagram illustrating an example of the seventeenth plan layout.

[0042] Figure 29 This is a diagram showing an example of the eighteenth floor plan layout.

[0043] Figure 30 This is a diagram illustrating an example of the nineteenth floor plan layout.

[0044] Figure 31 This is a circuit diagram showing a fourth configuration example of pixels.

[0045] Figure 32 This is a circuit diagram showing a fifth configuration example of pixels.

[0046] Figure 33 This is a circuit diagram showing the sixth configuration example of the pixels.

[0047] Figure 34 This is a circuit diagram showing a seventh configuration example of pixels.

[0048] Figure 35 This is a circuit diagram showing the eighth configuration example of the pixels.

[0049] Figure 36 This is a circuit diagram showing a ninth configuration example of pixels.

[0050] Figure 37 This is a circuit diagram showing the tenth configuration example of the pixels.

[0051] Figure 38This is a diagram illustrating an application example of an image sensor. Detailed Implementation

[0052] The specific implementation methods of this technology will be described in detail with reference to the accompanying drawings.

[0053] <Imaging Device Configuration Example>

[0054] Figure 1 A block diagram illustrating a configuration example of an imaging apparatus that applies this technology.

[0055] like Figure 1 As shown, the imaging device 11 includes an optical system 12, a solid-state imaging device 13, an imaging control circuit 14, a signal processing circuit 15, a monitor 16, and a memory 17. For example, the imaging device 11 can be applied to various electronic devices, such as imaging systems including digital still cameras and digital video cameras, mobile phones with imaging capabilities, or other devices with imaging capabilities, and is capable of capturing still images and moving images.

[0056] The optical system 12 includes one or more lenses that collect incident light from an object entering the imaging device 11, guide the light to the solid-state imaging device 13, and form an image of the object on the light-receiving surface (sensor unit) of the solid-state imaging device 13.

[0057] Under the control of the imaging control circuit 14, the solid-state imaging device 13 captures an image of an object formed on a light-receiving surface via the optical system 12 and provides the captured image signal to the signal processing circuit 15.

[0058] The imaging control circuit 14 controls the acquisition of the solid-state imaging device 13. For example, the imaging control circuit 14 provides the solid-state imaging device 13 with an imaging control signal including a vertical synchronization signal VSYNC, which is a periodic signal of a constant frequency (such as 60 Hz) indicating the timing of the acquisition.

[0059] The signal processing circuit 15 performs various signal processing on the image signal output from the solid-state imaging device 13, and provides the image data obtained as a processing result to the monitor 16 or the memory 17.

[0060] Monitor 16 displays an image corresponding to the image data provided from signal processing circuit 15, and memory 17 stores (records) the image data provided from signal processing circuit 15. It should be noted that if solid-state imaging device 13 includes a communication interface, the image data can be transmitted to an external source.

[0061] The solid-state imaging device 13 includes a pixel array unit 21, a timing control circuit 22, a vertical scanning circuit 23, a digital-to-analog converter (DAC) 24, a load complementary metal-oxide (MOS) circuit block 25, and a column signal processing circuit 26.

[0062] In pixel array unit 21, a plurality of pixels 31 are arranged in an array. Hereinafter, a group of pixels 31 arranged in the horizontal direction is called a "row", and a group of pixels 31 arranged in the direction perpendicular to the row is called a "column". In pixel array unit 21, each pixel 31 performs photoelectric conversion of incident light to generate an analog pixel signal, and outputs the pixel signal in parallel in the column direction for each row selected by vertical scanning circuit 23.

[0063] The timing control circuit 22 controls the operating timing of each of the vertical scanning circuit 23, DAC 24 and column signal processing circuit 26 in sync with the vertical synchronization signal VSYNC provided from the imaging control circuit 14.

[0064] The vertical scanning circuit 23 sequentially selects the rows to be scanned in the vertical direction, supplies various control signals to the pixels 31 set in each selected row, and causes the pixels 31 to output analog pixel signals.

[0065] DAC 24 generates a sawtooth waveform ramp signal through DA conversion and provides the ramp signal to column signal processing circuit 26.

[0066] The load MOS circuit block 25 is provided with MOS transistors that supply a constant current to each column (e.g., Figure 2 (44) Constant current source in the middle.

[0067] The column signal processing circuit 26 references the ramp signal supplied from the DAC 24, performs analog-to-digital (AD) conversion on the analog pixel signal output from the pixel 31 via the load MOS circuit block 25, and removes noise by performing correlated double sampling (CDS) processing on the digital pixel signal.

[0068] Then, the image data obtained as a result of the signal processing performed on the pixel signals by the column signal processing circuit 26 is output from the solid-state imaging device 13.

[0069] <First Configuration Example of Pixels>

[0070] Reference Figures 2 to 18 Describes the first configuration instance of pixel 31.

[0071] Figure 2 An example of a circuit diagram for pixel 31 as a first configuration example is shown.

[0072] like Figure 2As shown, pixel 31 includes a pixel circuit 41 that generates a pixel signal based on the amount of incident light and a sample-and-hold circuit 42 that samples the pixel signal generated in the pixel circuit 41 and holds the pixel signal at a constant voltage level, and is connected to a constant current source 44 via a vertical signal line 43.

[0073] Pixel circuit 41 includes photoelectric conversion unit 51, transmission gate 52, FD gate 53, reset gate 54, capacitor 55, amplification gate 56, and switching gate 57. Sample and hold circuit 42 includes capacitor 61, capacitor 62, SR gate 63, SD gate 64, RB gate 65, amplification gate 66, selection gate 67, and capacitor 68. Furthermore, when pixel 31 is disposed on a semiconductor substrate with a two-layer structure, pixel circuit 41 is disposed in the first semiconductor substrate, and sample and hold circuit 42 is disposed in the second semiconductor substrate. Figure 2 In the diagram, the rectangle shown between pixel circuit 41 and sample-and-hold circuit 42 represents the connection point (e.g., Cu-Cu connection) where the two semiconductor substrates of the two-layer structure are connected to each other.

[0074] The anode of photoelectric conversion unit 51 is grounded, and the cathode of photoelectric conversion unit 51 is connected to the source of transmission gate 52. The drain of transmission gate 52 is connected to the source of FD gate 53 and the gate electrode of amplification gate 56, and this connection point is called the floating diffusion (FD) node. The drain of FD gate 53 is connected to the source of reset gate 54 and one end of capacitor 55. The drain of reset gate 54 is connected to power supply VDD, and the other end of capacitor 55 is grounded. The drain of amplification gate 56 is connected to power supply AMD, and the source of amplification gate 56 is connected to the drain of switching gate 57. The source of switching gate 57 is connected to capacitor 68 of sample-and-hold circuit 42.

[0075] The connection point between one end of capacitor 61 and one end of capacitor 62 is called node V1, and the source of switching gate 57 and one end of capacitor 68 are connected to node V1. The other end of capacitor 61 is connected to the source of SR gate 63, and the other end of capacitor 62 is connected to the source of SD gate 64. The drains of SR gate 63 and SD gate 64 are connected at a point called node V2. The gate electrode of amplifier gate 66 and the source of RB gate 65 are connected to node V2. The drain of RB gate 65 is connected to power supply VREG, and the drain of amplifier gate 66 is connected to power supply VDD. The source of amplifier gate 66 is connected to the drain of select gate 67, and the source of select gate 67 is connected to vertical signal line 43. The other end of capacitor 68 is connected to the signal line supplying ramp signal RAMP.

[0076] The photoelectric conversion unit 51 includes a photodiode that performs photoelectric conversion on incident light entering the pixel 31 and accumulates the charge generated by the photoelectric conversion.

[0077] The transmission gate 52 is driven by the control signal TRG provided from the vertical scanning circuit 23, and the charge accumulated in the photoelectric conversion unit 51 is transferred to the FD node at the timing when the transmission gate 52 is turned on.

[0078] The FD gate 53 is driven by the control signal FDG provided from the vertical scanning circuit 23, and the capacitor 55 is connected to the FD node during the period when the transmission gate 52 is turned on. For example, by connecting the capacitor 55 to the FD node via the FD gate 53, the holding capacitance for retaining the charge transferred from the photoelectric conversion unit 51 can be increased, and imaging with high dynamic range (HDR) can be performed.

[0079] The reset gate 54 is driven by the control signal RST provided from the vertical scanning circuit 23, and when the reset gate 54 is opened, the charge accumulated in the capacitor 55 and the charge accumulated in the FD node are released to the power supply VDD via the FD gate 53 to reset the charge.

[0080] The capacitor 55, together with the FD node, retains the charge transferred from the photoelectric conversion unit 51 during the period when the capacitor 55 is connected to the FD node via the FD gate 53.

[0081] Amplifying gate 56 generates a pixel signal based on the charge accumulated in the FD node or the charge accumulated in the FD node and capacitor 55. Amplifying gate 56, together with capacitor 68 connected via switching gate 57, forms a source follower circuit and outputs the generated pixel signal to the V1 node.

[0082] The switching gate 57 is driven by the control signal SW provided from the vertical scanning circuit 23, and during the period when the switching gate 57 is on, the magnifying gate 56 is connected to the V1 node. Then, the pixel signal generated in the magnifying gate 56 is output to the V1 node via the switching gate 57.

[0083] Capacitor 61 maintains the pixel signal voltage at the reset level (hereinafter also referred to as the P-phase signal) of the FD node at the signal holding capacitor C, where the FD node has already been reset. The signal holding node that maintains the charge of the P-phase signal between capacitor 61 and SR gate 63 is called the VCR node.

[0084] Capacitor 62 maintains the pixel signal voltage at the signal holding capacitor C according to the charge generated in the photoelectric conversion unit 51 and maintains it at the pixel signal level in the FD node (or FD node and capacitor 55) (hereinafter also referred to as the D-phase signal). The signal holding node that maintains the charge according to the D-phase signal between capacitor 62 and SD gate 64 is called the VCD node.

[0085] The SR gate 63 is driven by the control signal SR provided from the vertical scanning circuit 23, and when the SR gate 63 is turned on, the VCR node is connected to the V2 node. With this arrangement, the VCR node and the V2 node maintain the charge according to the P-phase signal held in the VCR node.

[0086] SD gate 64 is driven by the control signal SD provided from the vertical scanning circuit 23, and when SD gate 64 is turned on, it connects the VCD node to the V2 node. Therefore, the charge of the D-phase signal held in the VCD node is held by the VCD node and the V2 node.

[0087] According to the control signal RB provided from the vertical scanning circuit 23, the RB gate 65 is driven, and when the RB gate 65 is turned on, the charge held by the VCR node and the V2 node, as well as the charge held by the VCD node and the V2 node, are released to the power supply VREG to reset the charge.

[0088] Amplifying gate 66 generates a P-phase signal and a D-phase signal. The P-phase signal is a pixel signal based on the charge held by the VCR node and V2 node, and the D-phase signal is a pixel signal based on the charge held by the VCD node and V2 node. Amplifying gate 56, together with constant current source 44 connected via selector gate 67, forms a source follower circuit and outputs the P-phase signal and D-phase signal to vertical signal line 43.

[0089] Selection gate 67 is driven by the control signal SEL provided from the vertical scanning circuit 23, and during the row period when one row is selected to read the pixel signal from it and selection gate 67 is turned on, amplification gate 66 is connected to the vertical signal line 43. Then, the pixel signals (P-phase signal and D-phase signal) generated in amplification gate 66 are read out to the vertical signal line 43 via selection gate 67.

[0090] When the charge accumulates at a constant rate according to the ramp signal RAMP, capacitor 68 is used as a constant current source to supply a constant current sink to node V1.

[0091] Solid-state imaging device 13 may employ a metal-insulator-metal (MIM) structure as capacitors 61, 62, and 68, wherein the insulator is sandwiched between the upper and lower electrodes. Furthermore, the global shutter type solid-state imaging device 13 can further improve image quality by employing a capacitive current source configuration using the MIM structure capacitor 68 as the constant current source of the first-stage source follower in a voltage-domain configuration.

[0092] For example, in conventional circuit structures that do not employ a capacitor-current-source configuration, there is a concern that the writing of pixel signals into the MIM structure is affected by transistor variations. Conversely, the solid-state imaging device 13 employing a capacitor-current-source configuration can suppress transistor variations by supplying the ramp signal RAMP to the capacitor 68.

[0093] Figure 3 A first cross-sectional configuration example of the solid-state imaging device 13 is shown.

[0094] like Figure 3 As shown, the solid-state imaging device 13 has a three-layer structure, wherein a first semiconductor substrate 101, a second semiconductor substrate 102 and a third semiconductor substrate 103 are stacked, and a plurality of pixels 31 are arranged in the pixel array unit 21.

[0095] The first semiconductor substrate 101 is provided with a wiring layer 112 stacked on the front surface of the semiconductor layer 111, and an on-chip lens 113 for converging the light of each pixel 31 is stacked on a light-receiving surface that serves as the rear surface of the semiconductor layer 111.

[0096] The semiconductor layer 111 is provided with a photoelectric conversion unit 51 for each pixel 31 and various components constituting the pixel circuit 41 (e.g., transmission gate 52, FD gate 53, etc.). In addition, the semiconductor layer 111 is provided with a component isolation unit 121 that optically and electrically isolates adjacent pixels 31 from each other.

[0097] For each pixel 31, the wiring layer 112 is provided with a plurality of wirings and a plurality of through electrodes for electrical connection to the second semiconductor substrate 102. In addition, pads 122 for connecting the solid-state imaging device 13 to the outside are provided in the peripheral region of the wiring layer 112 (the region outside the pixel array unit 21), and openings 123 are provided for performing wire bonding to the pads 122.

[0098] The second semiconductor substrate 102 is configured with a wiring layer 132 stacked on the front surface of the semiconductor layer 131 and a bonding layer 133 stacked on the rear surface of the semiconductor layer 131.

[0099] The semiconductor layer 131 is provided with various components constituting the sample-and-hold circuit 42 (SR gate 63, SD gate 64, RB gate 65, amplification gate 66 and selection gate 67) of each pixel 31.

[0100] For each pixel 31, the wiring layer 132 is provided with a plurality of wirings and a plurality of through electrodes for electrical connection to the first semiconductor substrate 101. In addition, for each pixel 31, the wiring layer 132 is provided with a metal-insulator-metal (MIM) structure constituting capacitors 61, 62 and 68 of the sample-and-hold circuit 42.

[0101] A bonding layer 133 is provided to bond the second semiconductor substrate 102 to the third semiconductor substrate 103.

[0102] Here, in the following description, the layer in which SR gate 63, SD gate 64, RB gate 65, amplification gate 66, and selection gate 67 are disposed in the semiconductor layer 131 of the second semiconductor substrate 102 is referred to as the substrate layer 141. Furthermore, the layer in which the MIM structure constituting capacitors 61, 62, and 68 is disposed in the wiring layer 132 of the second semiconductor substrate 102 is referred to as the MIM layer 142.

[0103] The third semiconductor substrate 103 is provided with a wiring layer 152 stacked on the front surface of the semiconductor layer 151. The semiconductor layer 151 is provided with various elements constituting the logic circuit for driving the solid-state imaging device 13, and the wiring layer 132 is provided with a plurality of wirings and a plurality of through electrodes.

[0104] Solid-state imaging device 13 has this stacked structure, and as in Figure 3 In the configuration example shown, the first semiconductor substrate 101 and the second semiconductor substrate 102 have a configuration in which the front surface side of semiconductor layer 111 and the front surface side of semiconductor layer 131 are bonded to each other, and the second semiconductor substrate 102 and the third semiconductor substrate 103 have a configuration in which the rear surface side of semiconductor layer 131 and the front surface side of semiconductor layer 151 are bonded to each other.

[0105] Figure 4 A second cross-sectional configuration example of the solid-state imaging device 13 is shown. It should be noted that... Figure 4 In the solid-state imaging device 13A shown, and in Figure 3 The same components of the solid-state imaging device 13 shown are indicated by the same reference numerals, and their detailed descriptions will not be repeated.

[0106] like Figure 4 As shown, the solid-state imaging device 13A has a three-layer structure, wherein a first semiconductor substrate 101, a second semiconductor substrate 102A, and a third semiconductor substrate 103 are stacked, and are arranged in a manner consistent with... Figure 3 The solid-state imaging device 13 in the middle is configured with a first semiconductor substrate 101 and a third semiconductor substrate 103 in a similar manner.

[0107] The second semiconductor substrate 102A is used in conjunction with Figure 3 The second semiconductor substrate 102 is configured in a similar manner, wherein a wiring layer 132 is stacked on the front surface of the semiconductor layer 131, and a bonding layer 133 is stacked on the rear surface of the semiconductor layer 131, but in the same orientation as... Figure 3The second semiconductor substrate 102 is different. That is, the side on the front surface of the semiconductor layer 131 where the wiring layer 132 is stacked faces the third semiconductor substrate 103, and the side on the rear surface of the semiconductor layer 131 where the bonding layer 133 is stacked faces the first semiconductor substrate 101.

[0108] Therefore, in the solid-state imaging device 13A, as in Figure 4 In the configuration example shown, the first semiconductor substrate 101 and the second semiconductor substrate 102A have a configuration in which the front surface side of semiconductor layer 111 and the rear surface side of semiconductor layer 131 are bonded to each other, and the second semiconductor substrate 102A and the third semiconductor substrate 103 have a configuration in which the front surface side of semiconductor layer 131 and the front surface side of semiconductor layer 151 are bonded to each other.

[0109] Reference Figure 5 Describe the first planar layout of pixel 31.

[0110] Figure 5 Figure A shows an example of the first planar layout of the base layer 141 of pixel 31, and Figure 5 Figure B shows an example of the planar layout of the MIM layer 142 of pixel 31. Note that in the planar layout of the base layer 141 of pixel 31 described below, the area with dotted lines is called the active region, and the active region is provided with semiconductor layers forming the source and drain of transistors. Furthermore, the rectangles shown in dashed lines represent contacts connected to the source, drain, and gate electrodes of the transistors.

[0111] like Figure 5 As shown in Figure A, the SR gate 63, SD gate 64, RB gate 65, amplification gate 66, and selection gate 67 constituting the sample-and-hold circuit 42 are disposed in the base layer 141 of a single pixel region of pixel 31. In addition to these components, a well contact WC is provided to fix the potential of the semiconductor layer.

[0112] Pixel 31 has a configuration in which the drains of SR gate 63 and SD gate 64 are connected to each other, and uses a layout in which SR gate 63 and SD gate 64 are arranged in series. Therefore, the active regions constituting SR gate 63 and the active regions constituting SD gate 64 form a continuous straight line, and a single active region that connects SR gate 63 and SD gate 64 in series is called a first series active region 201.

[0113] In pixel 31, the source of the magnifying gate 66 and the drain of the selecting gate 67 are connected to each other, and the layout in which the magnifying gate 66 and the selecting gate 67 are connected in series is used. Therefore, the active region constituting the magnifying gate 66 and the active region constituting the selecting gate 67 are formed as a continuous straight line, and the single active region provided by the series connection of the magnifying gate 66 and the selecting gate 67 is called the second series active region 202.

[0114] like Figure 5 As shown in B, capacitors 61, 62 and 68 are disposed in the MIM layer 142 of a single pixel region of pixel 31.

[0115] Capacitors 61, 62, and 68 can share an upper electrode 81 formed to cover the entire surface of the area where they are disposed. Each of capacitors 61, 62, and 68 is composed of an insulator sandwiched between the corresponding lower electrode and the upper electrode 81, and is provided with a plurality of MIM holes 82 as shown by the dashed rectangle.

[0116] In the first planar layout of pixels 31, pixels 31 are arranged in an array within pixel array unit 21, wherein Figure 5 The single pixel region of the basal layer 141 shown in A is used as a repeating unit and Figure 5 A single pixel region of the MIM layer 142 shown in B is used as a repeating unit. At this time, the first planar layout of the pixel 31 is configured such that the repeating units in the base layer 141 and the repeating units in the MIM layer 142 are substantially aligned with each other in the planar diagram.

[0117] In the first planar layout of pixel 31, as Figure 5 As shown in Figure A, the first cascaded active region 201, in which SR gate 63 and SD gate 64 are provided, and the second cascaded active region 202, in which amplification gate 66 and selection gate 67 are provided, are arranged parallel to each other. With this arrangement, the pixel 31 can achieve a more efficient layout.

[0118] Reference Figure 6 This will describe the second planar layout of pixel 31.

[0119] Figure 6 Figure A shows an example of the second planar layout of the base layer 141 of pixel 31, and Figure 6 Figure B shows an example of the planar layout of the MIM layer 142 of pixel 31. It is important to note that in... Figure 6 In the second planar layout shown, with Figure 5 The same components in the first planar layout are represented by the same reference numerals, and their detailed descriptions are not repeated.

[0120] As in Figure 6 As shown in A, in the second planar layout of pixel 31, the arrangement of SR gate 63, SD gate 64, RB gate 65 and well contact WC is similar to... Figure 5 The first planar layout is the same. Furthermore, the second planar layout of pixel 31 is the same as... Figure 5The first planar layouts are similar in that the first series active region 201, which is provided with SR gate 63 and SD gate 64, and the second series active region 202, which is provided with amplification gate 66 and selection gate 67, are arranged parallel to each other.

[0121] In the second planar layout of pixel 31, the arrangement of the second cascaded active region 202, which includes a magnification gate 66 and a selection gate 67, is consistent with... Figure 5 The first plan layout is different. That is, in Figure 5 In the first planar layout, the first series active region 201 and the second series active region 202 are arranged to be aligned at both ends in the horizontal direction.

[0122] Conversely, in the second planar layout of pixel 31, the second tandem active region 202 is arranged at a horizontally offset position, such that the amplification gate 66 is arranged on a straight line (represented by the dotted line) passing through the midpoint between the SR gate 63 and the SD gate 64 and orthogonal to the vertical direction of the SR gate 63 and the SD gate 64 arranged in series. Therefore, as Figure 6 As shown, the individual pixel region of pixel 31 has such a shape that the left surface of the individual pixel region of pixel 31 protrudes to the left due to the left end portion of the second series active region 202, and the right surface of the individual pixel region of pixel 31 is recessed to the left due to the right end portion of the second series active region 202.

[0123] In addition, such as Figure 6 As shown, the source of RB gate 65 can be located on a straight line that passes through the midpoint between SR gate 63 and SD gate 64 and is orthogonal to the longitudinal direction of SR gate 63 and SD gate 64 connected in series.

[0124] In the second planar layout of pixels 31, multiple pixels 31 are arranged in an array in pixel array unit 21, wherein Figure 6 A single pixel region of the base layer 141 shown in Figure A is used as a repeating unit, and Figure 6 A single pixel region of the MIM layer 142 shown in B is used as a repeating unit. At this time, the second planar layout of the pixel 31 is configured such that the repeating units in the base layer 141 and the repeating units in the MIM layer 142 are not consistent with each other in the planar view, with the left surface protruding and the right surface recessed.

[0125] In this way, in the second planar layout of pixel 31, as in Figure 6As shown in Figure A, the first cascaded active region 201, in which SR gate 63 and SD gate 64 are disposed, and the second cascaded active region 202, in which amplification gate 66 and selection gate 67 are disposed, are arranged parallel to each other. Furthermore, in the second planar layout of pixel 31, the V2 node can be connected via the shortest path by placing the sources of amplification gate 66 and RB gate 65 on a straight line (represented by the dotted line) that passes through the midpoint between SR gate 63 and SD gate 64 and is orthogonal to the longitudinal direction of the cascaded arrangement of SR gate 63 and SD gate 64. Using this arrangement, pixel 31 can achieve a more efficient layout.

[0126] Figure 7 An example of a first planar layout of four pixels 31[0] to 31[3] arranged in a 2×2 configuration is shown (i.e., the planar layout of each individual pixel 31 is the same as described above). Figure 5 (The planar layout of A is the same). In the following text, i is used to identify a given pixel 31 among a plurality of pixels 31, and each pixel 31 is distinguished by i=1, 2, 3, 4.

[0127] Figure 8 An example of a second planar layout is shown, in which four pixels 31[0] to 31[3] are arranged in a 2×2 configuration (i.e., the planar layout of each individual pixel 31 is the same as described above). Figure 6 (The plan layout of A is the same).

[0128] Figure 9 An example of a planar layout of a MIM layer 142 with four pixels 31[0] to 31[3] arranged in a 2×2 configuration is shown (i.e., the planar layout of each individual pixel 31 is the same as described above). Figure 5 B and Figure 6 (The plan layout of B is the same).

[0129] like Figure 7 and Figure 9 As shown, the first planar layout of pixel 31 is configured such that the repeating units in the base layer 141 and the repeating units in the MIM layer 142 are substantially aligned with each other in the planar diagram.

[0130] like Figure 8 and Figure 9 As shown, the second planar layout of pixel 31 is configured such that the repeating units in the base layer 141 and the repeating units in the MIM layer 142 are not consistent with each other in the planar view, with the left surface protruding and the right surface recessed.

[0131] Figure 10 An example of a third-plane layout of four pixels 31[0] to 31[3] arranged in a 2×2 configuration is shown.

[0132] like Figure 10As shown, in the third-plane layout, the sink contact WC can share adjacent pixels 31 in the horizontal direction. Figure 10 In the example shown, the trap contact WC is used between horizontally adjacent pixels 31[0] and 31[1], and the trap contact WC is used between horizontally adjacent pixels 31[2] and 31[1].

[0133] In this way, in the third plane layout, a more efficient layout can be achieved by sharing the well contact WC between pixels 31.

[0134] Figure 11 An example of a fourth-plane layout of four pixels 31[0] to 31[3] arranged in a 2×2 configuration is shown.

[0135] like Figure 11 As shown, in the fourth plane layout, the drain of RB gate 65 (connected to the drain of power supply VREG) can be shared, and the drain of amplification gate 66 (connected to the drain of power supply VDD) can be shared between adjacent pixels 31 in the horizontal direction. Figure 11 In the example shown, the drains of RB gate 65[0] and RB gate 65[1] of adjacent pixels 31[0] and 31[1] are shared, as are the drains of amplifying gate 66[0] and amplifying gate 66[1] of adjacent pixels 31[0] and 31[1]. Similarly, the drains of RB gate 65[2] and RB gate 65[3] of adjacent pixels 31[2] and 31[3] are shared, as are the drains of amplifying gate 66[2] and amplifying gate 66[3] of adjacent pixels 31[2].

[0136] In this way, in the fourth plane layout, a more efficient layout can be achieved by sharing the drain of RB gate 65 among pixels 31 and sharing the drain of amplification gate 66 among pixels 31. Note that an even more efficient layout can also be achieved by simply sharing the drain of RB gate 65 or the drain of amplification gate 66.

[0137] like Figure 12 As shown, the solid-state imaging device 13 can employ a 4-pixel shared structure, wherein four pixels 31[0] to 31[3] arranged in a 2×2 configuration share a V2 node. In the 4-pixel shared structure, the RB gate 65, the magnification gate 66, and the selection gate 67 are shared. Note that the pixel circuit 41 is omitted from the illustrations of the 4-pixel shared structure described below.

[0138] Figure 13This is a diagram illustrating an example of a fifth-plane layout of four pixels 31[0] to 31[3] arranged in a 2×2 configuration with a 4-pixel shared structure.

[0139] exist Figure 13 In the 4-pixel shared structure shown, in the fifth plane layout, the first series active regions 201[0] to 201[3] and the second series active region 202 are arranged parallel to each other. Furthermore, in the fifth plane layout, a pair of first series active regions 201[0] and 201[1] are arranged in series on a straight line, and a pair of first series active regions 201[2] and 201[3] are arranged in series on a straight line. Using this arrangement, pixel 31 can achieve a more efficient layout.

[0140] It should be noted that, Figure 13 In this configuration, all the first series active regions 201[0] to 201[3] are arranged parallel to the second series active region 202; however, by arranging at least one of the first series active regions 201[0] to 201[3] in parallel with the second series active region 202, pixel 31 can achieve a more efficient layout. Furthermore, by arranging at least one pair of the first series active regions 201[0] to 201[3] in series on a straight line, pixel 31 can achieve a more efficient layout.

[0141] Figure 14 This is a diagram illustrating an example of a sixth-plane layout of four pixels 31[0] to 31[3] arranged in a 2×2 configuration with a 4-pixel shared structure.

[0142] exist Figure 14 In the 4-pixel shared structure shown, in the sixth plane layout, the first series active regions 201[0] to 201[3] and the second series active region 202 are arranged parallel to each other. Furthermore, in the sixth plane layout, a pair of first series active regions 201[0] and 201[1] are arranged parallel to each other, and a pair of first series active regions 201[2] and 201[3] are arranged parallel to each other. Using this arrangement, pixel 31 can achieve a more efficient layout.

[0143] Note that pixels 31 can achieve a more efficient layout by arranging at least one pair of first series active regions 201[0] to first series active regions 201[3] in parallel with each other.

[0144] Figure 15 This is a diagram illustrating an example of a seventh-plane layout of four pixels 31[0] to 31[3] arranged in a 2×2 configuration with a 4-pixel shared structure.

[0145] exist Figure 15 In the 4-pixel shared structure shown, in the seventh plane layout, the first series active regions 201[0] to 201[3] and the second series active region 202 are arranged parallel to each other. Then, in the seventh plane layout, all midpoints between the sources of SR gate 63 and SD gate 64, and amplification gate 66 and RB gate 65 are arranged to be aligned on a straight line as indicated by the dotted line. With this arrangement, pixel 31 can achieve a more efficient layout.

[0146] Figure 16 This is a diagram illustrating an example of an eighth-plane layout of two pixels 31[0] and 31[1] arranged in a 2×1 configuration with a 2-pixel shared structure. It should be noted that, also in the 2-pixel shared structure, the same as described above... Figure 12 The 4-pixel shared structure shown is similar, with RB gate 65, magnification gate 66 and selection gate 67 shared by pixels 31[0] and 31[1] of the shared V2 node.

[0147] exist Figure 16 In the 2-pixel shared structure shown, in the eighth plane layout, the first series active region 201[0], the first series active region 201[1], and the second series active region 202 are arranged parallel to each other. With this arrangement, the pixel 31 can achieve a more efficient layout.

[0148] Note that in Figure 16 In the eighth planar layout shown, the first series active region 201[0], the first series active region 201[1], and the second series active region 202 are located in the center, the RB gate 65 is located below them, and the trap contact WC is located above them.

[0149] Figure 17 This is a diagram illustrating an example of a ninth-plane layout of two pixels 31[0] and 31[1] with a 2×1 arrangement and a 2-pixel shared structure.

[0150] exist Figure 17 In the 2-pixel shared structure shown, in the ninth plane layout, the first series active region 201[0], the first series active region 201[1], and the second series active region 202 are arranged parallel to each other. With this arrangement, the pixel 31 can achieve a more efficient layout.

[0151] Note that in Figure 17 In the ninth planar layout shown, the first series active region 201[0], the first series active region 201[1], and the second series active region 202 are disposed on the upper side, and the RB gate 65 and the trap contact WC are disposed vertically on the lower side.

[0152] Figure 18This is a diagram illustrating an example of a tenth-plane layout of two pixels 31[0] and 31[1] with a 2×1 arrangement and a 2-pixel shared structure.

[0153] exist Figure 18 In the 2-pixel shared structure shown, in the tenth plane layout, the first tandem active region 201[0], the first tandem active region 201[1], and the second tandem active region 202 are arranged parallel to each other. Furthermore, all midpoints between the sources of SR gate 63 and SD gate 64, and amplification gate 66 and RB gate 65 are arranged aligned on a straight line as indicated by the dotted line. With this arrangement, pixel 31 can achieve a more efficient layout.

[0154] <Second Configuration Example of Pixels>

[0155] Reference Figures 19 to 21 This will describe the second configuration instance of pixel 31.

[0156] Figure 19 An example of a circuit diagram for pixel 31a, as a second configuration example, is shown. It should be noted that... Figure 19 In pixel 31a shown, with Figure 2 The same parts as pixel 31 are represented by the same reference numerals, and their detailed descriptions will not be repeated.

[0157] like Figure 19 As shown, pixel 31a has the same Figure 2 The same components as pixel 31a, wherein pixel 31a includes pixel circuit 41 and sample-and-hold circuit 42a and is connected to constant current source 44 via vertical signal line 43.

[0158] The sample-and-hold circuit 42a has the same characteristics as... Figure 2 The sample-and-hold circuit 42a has a similar configuration to the sample-and-hold circuit 42a, as it includes capacitor 61, capacitor 62, SR gate 63, SD gate 64, RB gate 65, amplification gate 66, selection gate 67, and capacitor 68. Furthermore, the sample-and-hold circuit 42a further includes a DIFF gate 69.

[0159] like Figure 19 As shown, the drain of DIFF gate 69 is connected to node V1, the connection point between the source of switch gate 57 and one end of capacitor 61. The source of DIFF gate 69 is connected to the connection point between one end of capacitor 62 and one end of capacitor 68, and this connection point is referred to as node V3.

[0160] Using this arrangement, pixel 31a can reduce leakage during the period when the pixel signal is held in capacitors 61 and 62 by setting DIFF gate 69. For example, DIFF gate 69 is driven according to the control signal DIFF, and capacitors 61 and 62 can be isolated by turning off DIFF gate 69 during the readout standby period after the global operation period. On the other hand, capacitors 61 and 62 are connected by turning on DIFF gate 69 during the readout period, or the entire global operation period and / or the entire line readout period.

[0161] In addition, such as Figure 20 As shown, the solid-state imaging device 13 can adopt a 4-pixel shared structure, wherein four pixels 31a[0] to 31a[3] arranged in a 2×2 configuration share the V2 node.

[0162] Figure 21 This is a diagram illustrating an example of an eleventh-plane layout of four pixels 31a[0] to 31a[3] arranged in a 2×2 configuration with a 4-pixel shared structure.

[0163] exist Figure 21 In the 4-pixel shared structure shown, in the eleventh plane layout, the first series active regions 201[0] to 201[3] and the second series active region 202 are arranged parallel to each other. Furthermore, in the eleventh plane layout, a pair of first series active regions 201[0] and 201[1] are arranged in series on a straight line, and a pair of first series active regions 201[2] and 201[3] are arranged in series on a straight line. Using this configuration, pixel 31a can achieve a more efficient layout.

[0164] Furthermore, in the eleventh plane layout, the DIFF gate 69 is arranged such that its positional relationship with respect to the SR gate 63 and SD gate 64 is linearly symmetrical. That is, the center of the DIFF gate 69 is set on a straight line (represented by the dotted line) that passes through the midpoint between the SR gate 63 and SD gate 64 and is orthogonal to the longitudinal direction of the SR gate 63 and SD gate 64, which are connected in series with them. With this configuration, the pixel 31a can achieve a more efficient layout.

[0165] <Configuration Example Using MOS Capacitors>

[0166] Figure 22 This is a diagram illustrating an example of a twelfth-plane layout of four pixels 31[0] to 31[3] arranged in a 2×2 configuration with a 4-pixel shared structure.

[0167] Figure 22 The twelfth planar layout shown has the following characteristics as described above. Figure 12The 4-pixel shared structure shown includes a metal-oxide-semiconductor (MOS) capacitor that can be used as capacitor 68, and capacitor 68 is disposed in the substrate layer 141.

[0168] In this way, in the twelfth-plane layout using MOS capacitors as capacitor 68, the first series active regions 201[0] to 201[3] and the second series active region 202 are arranged parallel to each other. Furthermore, in the twelfth-plane layout, a pair of first series active regions 201[0] and 201[1] are arranged in series on a straight line, and a pair of first series active regions 201[2] and 201[3] are arranged in series on a straight line. With this configuration, pixel 31a can achieve a more efficient layout.

[0169] Furthermore, in the twelfth plane layout, capacitor 68 is arranged such that its positional relationship with respect to SR gate 63 and SD gate 64 is linearly symmetrical. That is, the center of capacitor 68 is arranged on a straight line (represented by the dotted line) that passes through the midpoint between SR gate 63 and SD gate 64 and is orthogonal to the longitudinal direction of SR gate 63 and SD gate 64 arranged in series. With this configuration, pixel 31a can achieve a more efficient layout.

[0170] <Planar layout of single-layer pixel structure>

[0171] refer to Figures 23 to 30 This will describe the planar layout of pixel 31 with a single-layer structure.

[0172] As mentioned above Figure 3 and Figure 4 In the cross-sectional configuration example shown, pixel 31 is not limited to a two-layer structure in which various elements constituting pixel circuit 41 are disposed in the first semiconductor substrate 101 and various elements constituting sample-and-hold circuit 42 are disposed in the second semiconductor substrate 102. That is, pixel 31 may adopt a single-layer structure in which various elements constituting pixel circuit 41 disposed in the first semiconductor substrate 101 and various elements constituting sample-and-hold circuit 42 disposed in the second semiconductor substrate 102 are disposed in a single semiconductor substrate.

[0173] Figure 23 This is a diagram illustrating an example of a thirteenth-plane layout of pixels 31 with a single-layer structure.

[0174] like Figure 23 As shown, the transmission gate 52, FD gate 53, reset gate 54, amplification gate 56 and switching gate 57 constituting the pixel circuit 41, and the SR gate 63, SD gate 64, RB gate 65, amplification gate 66 and selection gate 67 constituting the sample and hold circuit 42 are disposed in a single pixel area of ​​the pixel 31.

[0175] In the thirteenth plane layout of pixel 31, the first cascaded active region 201, in which SR gate 63 and SD gate 64 are disposed, and the second cascaded active region 202, in which magnification gate 66 and selection gate 67 are disposed, are arranged parallel to each other. Furthermore, in the thirteenth plane layout of pixel 31, magnification gate 66 is arranged on a straight line (represented by the dotted line) passing through the midpoint between SR gate 63 and SD gate 64 and orthogonal to the longitudinal direction of the cascaded arrangement of SR gate 63 and SD gate 64. Using this arrangement, pixel 31 can achieve a more efficient layout.

[0176] Figure 24 An example of a circuit diagram for pixel 31b, as a third configuration example, is shown. It should be noted that... Figure 24 In pixel 31b shown, with Figure 2 The same parts as pixel 31 are represented by the same reference numerals, and their detailed descriptions will not be repeated.

[0177] like Figure 24 As shown, pixel 31b has the same Figure 2 The same components as pixel 31 are that pixel 31b includes pixel circuit 41b and sample-and-hold circuit 42 and is connected to constant current source 44 via vertical signal line 43.

[0178] Pixel circuit 41b has the same as Figure 2 The pixel circuit 41b has a similar configuration to the pixel circuit 41b, as it includes a photoelectric conversion unit 51, a transmission gate 52, an FD gate 53, a reset gate 54, a capacitor 55, an amplification gate 56, and a switching gate 57. Additionally, the pixel circuit 41b also includes an overflow gate 58.

[0179] Overflow gate 58 is connected between photoelectric conversion unit 51 and power supply VDD, and releases the charge overflowing from photoelectric conversion unit 51 to power supply VDD. In addition, overflow gate 58 is driven according to the control signal OFG provided from vertical scanning circuit 23, and when overflow gate 58 is turned on, the charge accumulated in photoelectric conversion unit 51 is discharged to power supply VDD and reset, and exposure of pixel 31b begins.

[0180] Figure 25 This is a diagram showing an example of the fourteenth plane layout of pixel 31b.

[0181] like Figure 25 As shown, in the fourteenth plane layout of pixel 31b, a more efficient layout can be achieved by sharing the drain of overflow gate 58 and the drain of amplification gate 66.

[0182] Furthermore, also in the fourteenth plane layout of pixel 31b, the first tandem active region 201 and the second tandem active region 202 are arranged parallel to each other. Additionally, the magnifying gate 66 is arranged on a straight line (represented by the dotted line) passing through the midpoint between the SR gate 63 and the SD gate 64 and orthogonal to the longitudinal direction of the SR gate 63 and the SD gate 64 arranged in series. Using this configuration, pixel 31b can achieve a more efficient layout.

[0183] Figure 26 This is a diagram showing an example of the layout of the fifteenth plane of pixel 31b.

[0184] like Figure 26 As shown, in the fifteenth plane layout of pixel 31b, a more efficient layout can be achieved by sharing the drain of reset gate 54 and the drain of amplification gate 66.

[0185] Furthermore, also in the fifteenth plane layout of pixel 31b, the first tandem active region 201 and the second tandem active region 202 are arranged parallel to each other. Additionally, the magnifying gate 66 is arranged on a straight line (represented by the dotted line) passing through the midpoint between the SR gate 63 and the SD gate 64 and orthogonal to the longitudinal direction of the SR gate 63 and the SD gate 64 arranged in series. Using this configuration, pixel 31b can achieve a more efficient layout.

[0186] Figure 27 This is a diagram showing an example of the sixteenth plane layout of pixel 31b.

[0187] like Figure 27 As shown, in the sixteenth plane layout of pixel 31b, a more efficient layout can be achieved by sharing the drain of reset gate 54 and the drain of overflow gate 58.

[0188] Furthermore, also in the sixteenth plane layout of pixel 31b, the first tandem active region 201 and the second tandem active region 202 are arranged parallel to each other. Additionally, the magnifying gate 66 is arranged on a straight line (represented by the dotted line) passing through the midpoint between the SR gate 63 and the SD gate 64 and orthogonal to the longitudinal direction of the SR gate 63 and the SD gate 64 arranged in series. Using this configuration, pixel 31b can achieve a more efficient layout.

[0189] Figure 28 This is a diagram showing an example of the seventeenth plane layout of pixel 31b.

[0190] like Figure 28 As shown, in the seventeenth plane layout of pixel 31b, a more efficient layout can be achieved by sharing the drain of reset gate 54, overflow gate 58 and the drain of amplification gate 66.

[0191] Furthermore, also in the seventeenth plane layout of pixel 31b, the first tandem active region 201 and the second tandem active region 202 are arranged parallel to each other. Additionally, the magnifying gate 66 is arranged on a straight line (represented by the dotted line) passing through the midpoint between the SR gate 63 and the SD gate 64 and orthogonal to the longitudinal direction of the SR gate 63 and the SD gate 64 arranged in series. Using this configuration, pixel 31b can achieve a more efficient layout.

[0192] Figure 29 This is a diagram showing an example of an eighteenth-plane layout of four pixels 31b[0] to 31b[3] arranged in a 2×2 configuration.

[0193] exist Figure 29 In the eighteenth planar layout shown, the above Figure 25 The layout of pixel 31b shown is similar to that of the fourteenth plane, where the drain of overflow gate 58 and the drain of amplification gate 66 are shared. Furthermore, in the eighteenth plane layout, a more efficient layout can be achieved by sharing the drain of overflow gate 58 and the drain of amplification gate 66 between adjacent pixels 31b in the vertical direction. Additionally, as... Figure 27 As shown, the drain of reset gate 54 can also be shared.

[0194] Furthermore, also in the eighteenth plane layout, the first tandem active region 201 and the second tandem active region 202 are arranged parallel to each other. Additionally, the magnifying gate 66 is arranged on a straight line (represented by the dotted line) that passes through the midpoint between the SR gate 63 and the SD gate 64 and is orthogonal to the longitudinal direction of the SR gate 63 and the SD gate 64 arranged in series. Using this configuration, pixel 31b can achieve a more efficient layout.

[0195] Figure 30 This is a diagram showing an example of the nineteenth plane layout of pixel 31b.

[0196] exist Figure 30 The nineteenth plan layout shown is similar to the one described above. Figure 27 The sixteenth plane layout of pixel 31b shows that the drain of reset gate 54 and the drain of overflow gate 58 are shared. Furthermore, in the nineteenth plane layout, a more efficient layout can be achieved by sharing the drain of reset gate 54 and the drain of overflow gate 58 between horizontally adjacent pixels 31b, and by sharing the well contact WC between horizontally adjacent pixels 31b. Furthermore, as... Figure 28 As shown, the drain of the amplifier gate 66 can also be shared.

[0197] Furthermore, also in the nineteenth-plane layout, the first tandem active region 201 and the second tandem active region 202 are arranged parallel to each other. Additionally, the magnifying gate 66 is arranged on a straight line (represented by the dotted line) that passes through the midpoint between the SR gate 63 and the SD gate 64 and is orthogonal to the longitudinal direction of the SR gate 63 and the SD gate 64 arranged in series. Using this configuration, pixel 31b can achieve a more efficient layout.

[0198] <Configuration Examples 4 through 10 of Pixels>

[0199] Reference Figures 31 to 37 The fourth to tenth configuration instances describe pixel 31.

[0200] Figure 31 An example of a circuit diagram for pixel 31c, as a fourth configuration example, is shown. It should be noted that... Figure 31 In pixel 31c shown, with Figure 2 The same parts as pixel 31 are represented by the same reference numerals, and their detailed descriptions will not be repeated.

[0201] like Figure 31 As shown, pixel 31c has the same Figure 2 The same components as pixel 31 are present in pixel 31c, except that pixel 31c includes pixel circuit 41c and sample-and-hold circuit 42c, and is connected to constant current source 44 via vertical signal line 43. Sample-and-hold circuit 42c has the same... Figure 2 The sampling and holding circuit 42c has a similar configuration to the sampling and holding circuit 42c, since the sampling and holding circuit 42c includes capacitor 61, capacitor 62, SR gate 63, SD gate 64, RB gate 65, amplification gate 66, selection gate 67 and capacitor 68.

[0202] Pixel circuit 41c has the same as Figure 2 The pixel circuit 41c has a similar configuration to the pixel circuit 41c, as it includes a photoelectric conversion unit 51, a transmission gate 52, a reset gate 54, an amplification gate 56, and a switching gate 57. Furthermore, the pixel circuit 41c also includes an overflow gate 58 and a CLP gate 74.

[0203] like Figure 31 As shown, CLP gate 74 is connected in parallel to amplifier gate 56 and forms a source follower circuit in a similar manner to amplifier gate 56.

[0204] In the global shutter solid-state imaging device 13 using a voltage domain type configuration including pixels 31c configured in this manner, a more efficient layout can also be achieved by employing each of the above-described planar layouts.

[0205] Figure 32 An example of a circuit diagram for pixel 31d as a fifth configuration example is shown. It should be noted that... Figure 32In pixel 31d shown, with Figure 2 The same parts as pixel 31 are represented by the same reference numerals, and their detailed descriptions will not be repeated.

[0206] like Figure 32 As shown, pixel 31d has the same Figure 2 The same components as pixel 31 are included in pixel 31d, which includes pixel circuit 41d and sample-and-hold circuit 42d and is connected to constant current source 44 via vertical signal line 43.

[0207] Pixel circuit 41d with Figure 2 The pixel circuit 41 is configured in a similar manner to the pixel circuit 41d, because the pixel circuit 41d includes a photoelectric conversion unit 51, a transmission gate 52, an FD gate 53, a reset gate 54, a capacitor 55, and an amplification gate 56, and is similar to... Figure 2 The difference between pixel circuit 41 and pixel circuit 41 is that it does not provide a switch gate 57. Note that pixel circuit 41d is different from... Figure 2 The difference in the pixel circuit 41 is that the drain of the amplifier gate 56 and the drain of the reset gate 54 are connected together to the power supply VDD.

[0208] The sample-and-hold circuit 42d includes a switching gate 57, a capacitor 61, a capacitor 62, an SR gate 63, an SD gate 64, an amplification gate 66, a selection gate 67, and a capacitor 68.

[0209] The drain of switch gate 57 is connected to the source of amplifier gate 56 and one end of capacitor 68, and this connection point serves as node V1. The source of switch gate 57 is connected to node V2, and the drains of SR gate 63, SD gate 64, and the gate electrode of amplifier gate 66 are also connected to node V2. The source of SR gate 63 is connected to one end of capacitor 61, with the other end of capacitor 61 grounded. The source of SD gate 64 is connected to one end of capacitor 62, with the other end of capacitor 62 grounded. The drain of amplifier gate 66 is connected to power supply VDD, the source of amplifier gate 66 is connected to the drain of select gate 67, and the source of select gate 67 is connected to vertical signal line 43.

[0210] In the global shutter type solid-state imaging device 13 using a voltage domain type configuration including pixels 31d configured in this way, a more efficient layout can also be achieved by employing each of the above-described planar layouts.

[0211] Figure 33 An example of a circuit diagram for pixel 31e, as a sixth configuration example, is shown. It should be noted that... Figure 33 In pixel 31e shown, with Figure 2 The same parts as pixel 31 are represented by the same reference numerals, and their detailed descriptions will not be repeated.

[0212] like Figure 33As shown, pixel 31e has the same Figure 2 The same components as pixel 31e are included, wherein pixel 31e includes pixel circuit 41 and sample-and-hold circuit 42e. In addition, pixel 31e is connected to constant current source 44-1 via vertical signal line 43-1 and to constant current source 44-2 via vertical signal line 43-2.

[0213] The sample-and-hold circuit 42e includes capacitor 61, capacitor 62, SR gate 63, SD gate 64, amplifier gates 66-1 and 66-2, selector gates 67-1 and 67-2, and capacitor 68.

[0214] The drain of SR gate 63 is connected to node V1, and the source of SR gate 63 is connected to one end of capacitor 61 and the gate electrode of amplifier gate 66-1. The drain of amplifier gate 66-1 is connected to power supply VDD, and the source of amplifier gate 66-1 is connected to the drain of select gate 67-1, and the source of select gate 67-1 is connected to vertical signal line 43-1. The drain of SD gate 64 is connected to node V1, and the source of SD gate 64 is connected to one end of capacitor 62 and the gate electrode of amplifier gate 66-2. The drain of amplifier gate 66-2 is connected to power supply VDD, and the source of amplifier gate 66-2 is connected to the drain of select gate 67-2, and the source of select gate 67-2 is connected to vertical signal line 43-2.

[0215] In the global shutter type solid-state imaging device 13 using a voltage domain type configuration including pixels 31e configured in this way, a more efficient layout can also be achieved by employing each of the above-described planar layouts.

[0216] Figure 34 An example of a circuit diagram for pixel 31f, as a seventh configuration example, is shown. It should be noted that... Figure 34 In pixel 31f shown, with Figure 2 The same parts as pixel 31 are represented by the same reference numerals, and their detailed descriptions will not be repeated.

[0217] like Figure 34 As shown, pixel 31f has the same Figure 2 The same components as pixel 31, wherein pixel 31f includes pixel circuit 41 and sample-and-hold circuit 42f and is connected to constant current source 44 via vertical signal line 43.

[0218] The sample-and-hold circuit 42f includes capacitor 61, capacitor 62, SR gate 63, SD gate 64, amplifier gate 66, selector gate 67, and capacitor 68.

[0219] The drain of SR gate 63 is connected to node V1, and one end of capacitor 68 is also connected to node V1. The source of SR gate 63 is connected to one end of capacitor 61 and one end of capacitor 62. The other end of capacitor 62 is connected to node V2, and the drain of SD gate 64 and the gate of amplifier gate 66 are connected to node V2. The drain of amplifier gate 66 is connected to power supply VDD, the source of amplifier gate 66 is connected to the drain of select gate 67, and the source of select gate 67 is connected to vertical signal line 43.

[0220] In the global shutter solid-state imaging device 13 using a voltage domain type configuration including pixels 31f configured in this manner, a more efficient layout can also be achieved by employing each of the above-described planar layouts.

[0221] Figure 35 An example of a circuit diagram for pixel 31g, as an eighth configuration example, is shown. It should be noted that... Figure 35 In the pixel 31g shown, with Figure 2 The same parts as pixel 31 are represented by the same reference numerals, and their detailed descriptions will not be repeated.

[0222] like Figure 35 As shown, pixel 31g has the same Figure 2 The same components as pixel 31g, wherein pixel 31g includes pixel circuit 41g and sample-and-hold circuit 42g, and is connected to constant current source 44 via vertical signal line 43.

[0223] Pixel circuit 41g with Figure 2 The pixel circuit 41g is configured in a similar manner to the pixel circuit 41 in the image. The pixel circuit 41g includes a photoelectric conversion unit 51, a transmission gate 52, an FD gate 53, a reset gate 54, a capacitor 55, and an amplification gate 56, and is similar to... Figure 2 The difference in pixel circuit 41 is that it does not provide a door 57 for opening and closing.

[0224] The sample-and-hold circuit 42g includes a switch gate 57, a capacitor 61, a capacitor 62, an SR gate 63, an SD gate 64, an amplifier gate 66, a selector gate 67, and a capacitor 68.

[0225] The drain of switch gate 57 is connected to the source of amplifier gate 56 and one end of capacitor 68, and this connection point serves as node V1. The source of switch gate 57 is connected to node V2, and the drains of SR gate 63, SD gate 64, and the gate electrode of amplifier gate 66 are also connected to node V2. The source of SR gate 63 is connected to one end of capacitor 61, with the other end of capacitor 61 grounded. The source of SD gate 64 is connected to one end of capacitor 62, with the other end of capacitor 62 grounded. The drain of amplifier gate 66 is connected to power supply VDD, the source of amplifier gate 66 is connected to the drain of select gate 67, and the source of select gate 67 is connected to vertical signal line 43.

[0226] In the global shutter type solid-state imaging device 13 using a voltage domain type configuration including pixels 31g configured in this way, a more efficient layout can also be achieved by employing each of the above-described planar layouts.

[0227] Figure 36 An example of a circuit diagram for pixel 31h, as a ninth configuration example, is shown. It should be noted that... Figure 36 In the pixel 31h shown, with Figure 2 The same parts as pixel 31 are represented by the same reference numerals, and their detailed descriptions will not be repeated.

[0228] like Figure 36 As shown, pixel 31h has the same Figure 2 The same components as pixel 31, because pixel 31h includes pixel circuit 41 and sample-and-hold circuit 42h and is connected to constant current source 44 via vertical signal line 43.

[0229] The sample-and-hold circuit 42h includes capacitor 61, capacitor 62, SR gate 63, SD gate 64, amplifier gate 66, selector gate 67, and capacitor 68.

[0230] The drain of SR gate 63 is connected to node V1, and one end of capacitor 68 is also connected to node V1. The source of SR gate 63 is connected to the drain of SD gate 64 and one end of capacitor 61. The source of SD gate 64 is connected to the gate electrode of amplifier gate 66 and one end of capacitor 62. The drain of amplifier gate 66 is connected to power supply VDD, the source of amplifier gate 66 is connected to the drain of select gate 67, and the source of select gate 67 is connected to vertical signal line 43.

[0231] In the global shutter solid-state imaging device 13 using a voltage domain type configuration including pixels 31h configured in this manner, a more efficient layout can also be achieved by employing each of the above-described planar layouts.

[0232] Figure 37 An example of a circuit diagram for pixel 31i, as an eleventh configuration example, is shown. It should be noted that... Figure 37 In the pixel 31i shown, with Figure 2 The same parts as pixel 31 are represented by the same reference numerals, and their detailed descriptions will not be repeated.

[0233] like Figure 37 As shown, pixel 31i has the same Figure 2 The same components as pixel 31i, because pixel 31i includes pixel circuit 41 and sample-and-hold circuit 42i and is connected to constant current source 44 via vertical signal line 43.

[0234] The sample-and-hold circuit 42i includes capacitor 61, capacitor 62, RB gate 65, amplifier gate 66, selector gate 67, and capacitor 68.

[0235] One end of capacitor 61 is connected to node V1, and one end of capacitor 68 is also connected to node V1. The other end of capacitor 61 is connected to one end of capacitor 62, the source of RB gate 65, and the gate electrode of amplifier gate 66. The drain of RB gate 65 is connected to power supply VREG, and the drain of amplifier gate 66 is connected to power supply VDD. The source of amplifier gate 66 is connected to the drain of select gate 67, and the source of select gate 67 is connected to vertical signal line 43.

[0236] In the global shutter type solid-state imaging device 13 using a voltage domain type configuration including pixels 31i configured in this way, a more efficient layout can also be achieved by employing each of the above-described planar layouts.

[0237] It should be noted that pixel 31 can be used in addition to... Figures 31 to 37 Various configurations other than those shown are available, and any configuration employing each of the above-described planar layouts can be used.

[0238] As described above, in the sample-and-hold circuit 42 of the global shutter-type solid-state imaging device 13 using a voltage-domain configuration, a more efficient layout can be achieved by employing a planar layout of the substrate layer 141 as described above in the pixel 31, which has a capacitor 68 as a first-stage source follower. With this arrangement, the pixel 31 can achieve a finer pixel size.

[0239] Therefore, the global shutter type solid-state imaging device 13 using a voltage domain configuration including such pixel 31 can reduce the size while keeping the number of pixels constant, and can improve the image quality by increasing the number of pixels while keeping the size constant.

[0240] <Application Examples of Image Sensors>

[0241] Figure 38 A diagram illustrating an example of the use of the aforementioned image sensor (imaging device).

[0242] For example, the image sensor described above can be used in various situations to sense light such as visible light, infrared light, ultraviolet light, and X-rays, as described below.

[0243] Devices that image images provided for viewing purposes, such as digital cameras and mobile devices with camera functions. Devices provided for traffic purposes, such as onboard sensors that image the front, rear, surrounding environment, and interior of a vehicle; surveillance cameras used to monitor moving vehicles and roads; and distance measuring sensors that measure distances between vehicles, are used for safe driving, such as automatic stopping and driver status recognition. A device for capturing user gestures and operating household appliances such as televisions, refrigerators, and air conditioners based on those gestures. Devices for medical and healthcare purposes, such as endoscopes, and apparatuses that perform angiography by receiving infrared light. Security-related devices, such as security surveillance cameras and separate authentication cameras. Devices for cosmetic purposes, such as skin measurement instruments for imaging the skin and microscopes for imaging the scalp. Devices designed for sports, such as action cameras or wearable cameras for sports applications, etc. Devices provided for agriculture, such as cameras used to monitor the conditions of fields and crops. <Configuration Combination Example> It should be noted that this technology may also have the following configurations. (1)

[0245] A solid-state imaging device, comprising: Pixels, including: Pixel circuit, having at least one photoelectric conversion unit and outputting pixel signal to a first node; and A sample-and-hold circuit, which includes at least: A first capacitor has one end connected to the first node and maintains the voltage of the pixel signal at a reset level output from the pixel circuit. The second capacitor has one end connected to the first node and maintains the voltage of the pixel signal at the pixel signal level output from the pixel circuit. The third capacitor has one end connected to the connection point and the other end connected to the signal line. One end of the first capacitor and one end of the second capacitor are connected to the connection point. The ramp signal is supplied through the signal line. The third capacitor, together with the first amplification gate of the pixel circuit, forms a source follower circuit. The second amplification gate generates a pixel signal corresponding to the charge accumulated in the second node connected to the gate electrode. Select a gate, select a pixel to output the pixel signal generated by the second amplification gate. The first gate connects to the third node and the second node, with the third node serving as a connection point to the other end of the first capacitor. The second gate connects the fourth node and the second node. The fourth node serves as a connection point to the other end of the second capacitor. The third gate resets the charge accumulated in the second, third, and fourth nodes, where... The first series active region and the second series active region are set to be parallel to each other. The first series active region is a single active region. In the first series active region, the active region constituting the first gate and the active region constituting the second gate are formed as a continuous straight line and the first gate and the second gate are connected in series. The second series active region is a single active region. In the second series active region, the active region constituting the second amplifying gate and the active region constituting the selection gate are formed as a continuous straight line and the second amplifying gate and the selection gate are connected in series. (2)

[0247] According to the solid-state imaging device of (1), wherein

[0248] The source of the second or third amplifying gate is located on a straight line that passes through the midpoint between the first and second gates and is orthogonal to the longitudinal direction of the first and second gates connected in series. (3)

[0250] According to the solid-state imaging device in (2), where

[0251] The repeating cells in the layer containing the first capacitor, the second capacitor, and the third capacitor are not the same as the repeating cells in the layer containing the second amplification gate, the selection gate, the first gate, the second gate, and the third gate. (4)

[0253] According to any one of (1) to (3), the solid-state imaging device, wherein

[0254] The well contacts shared between adjacent pixels are configured to fix the potential of the semiconductor layer. (5)

[0256] According to any one of (1) to (4), the solid-state imaging device, wherein

[0257] Adjacent pixels share the drain of the third gate and the drain of the second amplification gate. (6)

[0259] According to any one of (1) to (5), the solid-state imaging device, wherein

[0260] Using a pixel-sharing structure, multiple pixels share a second node, and

[0261] In adjacent pixels, at least one pair of cascaded active regions in the first cascaded active region is arranged on a straight line. (7)

[0263] According to any one of (1) to (6), the solid-state imaging device, wherein

[0264] Using a pixel-sharing structure, multiple pixels share a second node, and

[0265] In adjacent pixels, at least one pair of the first contiguous active regions are set to be parallel to each other. (8)

[0267] A solid-state imaging device according to any one of (1) to (7), wherein

[0268] Metal-oxide-semiconductor (MOS) capacitors are used as third capacitors, and

[0269] The third capacitor is set to be symmetrical with respect to the positional relationship line of the first and second gates. (9)

[0271] According to any one of (1) to (8), the solid-state imaging device, wherein

[0272] The pixel has a two-layer structure, in which a first substrate containing elements constituting the pixel circuit and a second substrate containing elements constituting the sample-and-hold circuit are stacked. (10)

[0274] According to any one of (1) to (9), the solid-state imaging device, wherein

[0275] The pixel has a single-layer structure in which the elements constituting the pixel circuit and the elements constituting the sample-and-hold circuit are disposed in a single substrate. (11)

[0277] According to the solid-state imaging device of (10), in which

[0278] As components constituting a pixel circuit, the pixel circuit includes: an FD gate that changes the holding capacitance used to hold the charge transferred from the photoelectric conversion unit; a reset gate that resets the floating diffusion (FD) node that holds the charge transferred from the photoelectric conversion unit; and an overflow gate that releases the charge overflowing from the photoelectric conversion unit. (12)

[0280] According to the solid-state imaging device of (11), in which

[0281] Two or three of the drains of the overflow gate, the second amplification gate, and the reset gate are shared. (13)

[0283] According to the solid-state imaging device of (12), in which

[0284] Between adjacent pixels, two or three of the drains of the overflow gate, the second amplification gate, and the reset gate are shared, or well contacts configured to fix the potential of the semiconductor layer are shared. (14)

[0286] An electronic device, comprising: Solid-state imaging device, including: pixels, including: A pixel circuit has at least one photoelectric conversion unit and outputs a pixel signal to a first node; A first capacitor has one end connected to a first node and maintains the voltage of the pixel signal at a reset level output from the pixel circuit. The second capacitor has one end connected to the first node and maintains the voltage of the pixel signal at the pixel signal level output from the pixel circuit. The third capacitor has one end connected to the connection point and the other end connected to the signal line. One end of the first capacitor and one end of the second capacitor are connected to the connection point. A ramp signal is supplied through the signal line. The third capacitor, together with the amplification gate of the pixel circuit, forms a source follower circuit. A sample-and-hold circuit, which has at least the following features: The amplification gate generates a pixel signal corresponding to the charge accumulated in the second node connected to the gate electrode. Select the gate, select the pixel to output the pixel signal generated by the magnification gate. The first gate connects to the third node and the second node, with the third node serving as a connection point to the other end of the first capacitor. The second gate connects the fourth node and the second node. The fourth node serves as a connection point to the other end of the second capacitor. The third gate resets the charges accumulated in the second, third, and fourth nodes, among which... The first series active region and the second series active region 202 are set to be parallel to each other. The first series active region is a single active region. In the first series active region, the active region constituting the first gate and the active region constituting the second gate form a continuous straight line and the first gate and the second gate are connected in series. The second series active region 202 is a single active region. In the second series active region, the active region constituting the amplifying gate and the active region constituting the selecting gate form a continuous straight line and the amplifying gate and the selecting gate are connected in series.

[0287] It should be noted that this embodiment is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of this disclosure. Moreover, the effects described herein are merely examples and are not intended to be limiting, and other effects can also be achieved.

[0288] Reference Symbol List

[0289] 11 Imaging Device

[0290] 12 Optical System

[0291] 13 Solid-state imaging devices

[0292] 14 Imaging Control Circuit

[0293] 15. Signal Processing Circuit

[0294] 16 monitors

[0295] 17. Memory

[0296] 21-pixel array unit

[0297] 22 Timing control circuit

[0298] 23 Vertical Scanning Circuit

[0299] 24 DAC

[0300] 25 Load MOS circuit block

[0301] 26-column signal processing circuits

[0302] 31 pixels

[0303] 41-pixel circuit

[0304] 42 Sample and Hold Circuit

[0305] 43 Vertical signal line

[0306] 44 Constant Current Source

[0307] 51 Photoelectric Conversion Unit

[0308] 52 Transmission Gate

[0309] 53 FD gate

[0310] 54 Reset Gate

[0311] 55 capacitor

[0312] 56 Enlarged Door

[0313] 57 Opening and closing doors

[0314] 61 Capacitor

[0315] 62 capacitors

[0316] 63 SR Gate

[0317] 64 SD Gate 64

[0318] 65 RB Gate

[0319] 66 Enlarged Door

[0320] 67 Select Door

[0321] 68 capacitors

Claims

1. A solid-state imaging device, comprising: Pixels, including: Pixel circuit, having at least one photoelectric conversion unit and outputting pixel signals to a first node; and A sample-and-hold circuit, wherein the sample-and-hold circuit includes at least: A first capacitor has one end connected to the first node and maintains the voltage of the pixel signal at a reset level output from the pixel circuit. The second capacitor has one end connected to the first node and maintains the voltage of the pixel signal at the pixel signal level output from the pixel circuit. A third capacitor has one end connected to a connection point and the other end connected to a signal line. One end of the first capacitor and one end of the second capacitor are connected to the connection point. A ramp signal is supplied through the signal line. The third capacitor, together with the first amplification gate of the pixel circuit, forms a source follower circuit. The second amplification gate generates a pixel signal corresponding to the charge accumulated in the second node connected to the gate electrode. Select a gate, select a pixel to output the pixel signal generated by the second amplification gate. The first gate connects the third node and the second node, the third node serving as a connection point to the other end of the first capacitor. The second gate connects the fourth node and the second node, the fourth node serving as a connection point to the other end of the second capacitor, and The third gate resets the charge accumulated in the second node, the third node, and the fourth node, wherein... The first series active region and the second series active region are configured to be parallel to each other. The first series active region is a single active region. In the first series active region, the active region constituting the first gate and the active region constituting the second gate are formed as a continuous straight line and the first gate and the second gate are connected in series. The second series active region is a single active region. In the second series active region, the active region constituting the second amplifying gate and the active region constituting the selection gate are formed as a continuous straight line and the second amplifying gate and the selection gate are connected in series.

2. The solid-state imaging device according to claim 1, wherein... The source of the second amplifying gate or the third gate is located on a straight line that passes through the midpoint between the first gate and the second gate and is orthogonal to the longitudinal direction of the first gate and the second gate connected in series.

3. The solid-state imaging device according to claim 2, wherein... The repeating cells in the layer containing the first capacitor, the second capacitor, and the third capacitor are not the same as the repeating cells in the layer containing the second amplification gate, the selection gate, the first gate, the second gate, and the third gate.

4. The solid-state imaging device according to claim 1, wherein... The well contacts shared between adjacent pixels are configured to fix the potential of the semiconductor layer.

5. The solid-state imaging device according to claim 1, wherein... Adjacent pixels share the drain of the third gate and the drain of the second amplification gate.

6. The solid-state imaging device according to claim 1, wherein... Using a pixel-sharing structure, in which multiple pixels share the second node, and In adjacent pixels, at least one pair of the first tandem active regions are arranged in a straight line.

7. The solid-state imaging device according to claim 1, wherein... Using a pixel-sharing structure, in which multiple pixels share the second node, and In adjacent pixels, at least one pair of the first contiguous active regions are set to be parallel to each other.

8. The solid-state imaging device according to claim 1, wherein Metal-oxide-semiconductor (MOS) capacitors are used as the third capacitor, and The third capacitor is configured to be symmetrical with respect to the positional relationship line between the first gate and the second gate.

9. The solid-state imaging device according to claim 1, wherein... The pixel has a two-layer structure, in which a first substrate, in which elements constituting the pixel circuit are disposed, and a second substrate, in which elements constituting the sample-and-hold circuit are disposed, are stacked.

10. The solid-state imaging device according to claim 1, wherein The pixel has a single-layer structure in which the elements constituting the pixel circuit and the elements constituting the sample-and-hold circuit are disposed in a single substrate.

11. The solid-state imaging device according to claim 10, wherein As an element constituting the pixel circuit, the pixel circuit includes: The system includes an FD gate, which changes the holding capacitance used to retain the charge transferred from the photoelectric conversion unit; a reset gate, which resets the floating diffusion (FD) node that retains the charge transferred from the photoelectric conversion unit; and an overflow gate, which releases the charge that overflows from the photoelectric conversion unit.

12. The solid-state imaging device according to claim 11, wherein... Two or three of the drains of the overflow gate, the second amplification gate, and the reset gate are shared.

13. The solid-state imaging device according to claim 12, wherein... Between adjacent pixels, two or three of the drains of the overflow gate, the second amplification gate, and the reset gate are shared, or the well contacts configured to fix the potential of the semiconductor layer are shared.

14. An electronic device including a solid-state imaging apparatus, the solid-state imaging apparatus comprising: Pixels, including: Pixel circuit, having at least one photoelectric conversion unit and outputting pixel signals to a first node; and A sample-and-hold circuit, wherein the sample-and-hold circuit includes at least: A first capacitor has one end connected to the first node and maintains the voltage of the pixel signal at a reset level output from the pixel circuit. The second capacitor has one end connected to the first node and maintains the voltage of the pixel signal at the pixel signal level output from the pixel circuit. A third capacitor has one end connected to a connection point and the other end connected to a signal line. One end of the first capacitor and one end of the second capacitor are connected to the connection point. A ramp signal is supplied through the signal line. The third capacitor, together with the first amplification gate of the pixel circuit, forms a source follower circuit. The second amplification gate generates a pixel signal corresponding to the charge accumulated in the second node connected to the gate electrode. Select a gate, select a pixel to output the pixel signal generated by the second amplification gate. The first gate connects the third node and the second node, the third node serving as a connection point to the other end of the first capacitor. The second gate connects the fourth node and the second node, the fourth node serving as a connection point to the other end of the second capacitor, and The third gate resets the charge accumulated in the second node, the third node, and the fourth node, wherein... The first series active region and the second series active region are set to be parallel to each other. The first series active region is a single active region. In the first series active region, the active region constituting the first door and the active region constituting the second door are formed as a continuous straight line and the first door and the second door are arranged in series. The second series active region is a single active region. In the second series active region, the active region constituting the second amplifying door and the active region constituting the selection door are formed as a continuous straight line and the second amplifying door and the selection door are arranged in series.

Images