Power supply circuit with low power supply noise in audio system
By using operational amplifiers, NMOS tubes and CNC resistor array power supply circuits in SOCs, dynamically match the working current of the digital circuit, solving the problem of high noise affecting ADCs and DACs, realizing low-noise power supply, reducing chip cost and volume. Improves signal-to-noise ratio and competitiveness.
Patent Information
- Application Number
- CN202420763251.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-12
- Publication Date
- 2024-12-10
- Estimated Expiration
- 2034-04-12
AI Technical Summary
In highly integrated SOCs, high-noise digital circuits share power with ADCs and DACs, resulting in power supply noise affecting the clarity and quality of audio signals. The prior art is difficult to effectively reduce noise, increasing chip cost and volume.
The power supply circuit including an operational amplifier, NMOS tube and a CNC resistor array is adopted. By dynamically matching the working current of the digital circuit, the current is approximately constant, the power supply noise is reduced, and the resistance value is controlled through the CNC resistor array to reduce noise interference.
It effectively reduces the noise of the shared power supply, improves the signal-to-noise ratio of ADC and DAC, reduces the number of chip pins and the capacitance value of filter capacitors, reduces the system cost, and improves the chip competitiveness.
Smart Images
Figure CN222147414U_ABST
Abstract
Description
Technical Field
[0001] The utility model belongs to the technical field of power supply, and in particular relates to a power supply circuit with low power supply noise in an audio system. Background Art
[0002] High-precision audio ADC (analog-to-digital converter) and DAC (digital-to-analog converter) have high bit counts and are sensitive to power supply noise. Power supply noise may limit the dynamic range of ADC and DAC, causing a decrease in the signal-to-noise ratio of ADC and DAC, causing distortion of ADC and DAC, resulting in distortion and distortion of audio signals, etc., affecting the clarity and quality of audio signals.
[0003] However, in a highly integrated SOC (system on chip), providing separate power supplies for ADC and DAC will increase the number of chip pins, thereby increasing chip costs. When ADC and DAC do not have separate power pins, high-noise digital circuits share the power supply with ADC and DAC. High-noise digital circuits such as USB interfaces will generate low-frequency current fluctuations due to periodic working modes, resulting in low-frequency high-amplitude fluctuations in the power supply voltage, thereby affecting the ADC and DAC using the same power supply.
[0004] The common method to alleviate the power supply voltage fluctuation of ADC and DAC systems is to use LDO (low dropout linear regulator) or DCDC (direct current converter) and other circuits to power the ADC and DAC systems separately. However, it is not applicable to highly integrated SOCs. Moreover, LDO has poor power supply suppression for noise above KHz. It is impossible to completely remove the noise. Another method is to connect a large-capacity decoupling capacitor to the power supply, but the large-capacity decoupling capacitor is expensive and large in size, and has poor decoupling ability for KHz-level noise. Summary of the invention
[0005] The utility model aims to provide a power supply circuit with low power supply noise in an audio system in view of the situation that a high-noise digital circuit in an existing SOC shares a power supply with an ADC and a DAC.
[0006] The utility model includes an operational amplifier, an NMOS tube, five resistors and a digitally controlled resistor array; the details are as follows:
[0007] One end of the first resistor R1, the second resistor R2 and the third resistor R3 are connected to the input power supply VDDin, the other end of the first resistor R1 and one end of the fourth resistor R4 are connected to the drain of the NMOS tube N, the other end of the fourth resistor R4 and one end of the fifth resistor R5 are connected to the positive input end of the operational amplifier A, the gate of the NMOS tube N is connected to the output end of the operational amplifier A, the negative input end of the operational amplifier A and the other end of the second resistor R2 are connected to the input end of the digitally controlled resistor array, the source of the NMOS tube N is connected to the output end of the digitally controlled resistor array, and the other ends of the third resistor R3 and the fifth resistor R5 are connected to the power supply terminal VDDd of the digital circuit.
[0008] The digitally controlled resistor array includes a resistor RA0 and multiple gate resistors, each gate resistor includes a load resistor and an NMOS tube; one end of the resistor RA0 is connected to all the load resistors RA1, RA2, ··· , one end of RAN is connected as the input end of the digital controlled resistor array; the other end of the load resistor is connected to the drain of the corresponding NMOS tube. All NMOS tubes E1, E2, ··· , the source of EN is connected to the other end of the resistor RA0 and grounded, serving as the output end of the digitally controlled resistor array; multiple NMOS tubes E1, E2, ··· ,The gate of EN is the multiple resistance control terminals of the digitally controlled resistor array, which is connected to the digital circuit.
[0009] The utility model is suitable for the situation that the ADC and DAC in the SOC are highly integrated with the high-noise digital circuit and are powered by a common power supply. It does not increase the cost of the system power supply voltage stabilization circuit. By dynamically matching the working current of the high-noise digital circuit, the current drawn from the power supply is approximately constant, reducing the voltage noise of the common power supply, thereby ensuring that the ADC and DAC of the common power supply have a low-noise power supply, thereby improving the signal-to-noise ratio of the ADC and DAC. Since the high-noise digital circuit can share the power supply with the ADC and DAC, the number of pins of the SOC chip is reduced, the chip packaging volume and cost are reduced, the capacitance of the filter capacitor is reduced, and the system cost is reduced, thereby improving the competitiveness of the chip. BRIEF DESCRIPTION OF THE DRAWINGS
[0010] Figure 1 This is a circuit diagram of the utility model. DETAILED DESCRIPTION
[0011] The utility model is further described below in conjunction with the accompanying drawings and embodiments.
[0012] At present, the input power supply VDDin is directly connected to the audio system and the power supply terminal VDDd of the digital circuit. Since the power supply VDDin has a certain internal resistance, the current fluctuation of the system will generate voltage fluctuation on the internal resistance of the power supply VDDin, generate power supply noise, and interfere with the audio system. The present invention sets a power supply circuit between the input power supply VDDin and the power supply terminal VDDd of the digital circuit, such as Figure 1 As shown:
[0013] A power supply circuit with low power supply noise in an audio system includes an operational amplifier, an NMOS tube, five resistors and a digitally controlled resistor array. The first resistor R1 and the third resistor R3 are sampling resistors with the same resistance value, which is less than 10 ohms; the second resistor R2 is a bias resistor with a resistance value greater than or equal to 10 times the resistance value of the first resistor R1; the fourth resistor R4 and the fifth resistor R5 are sampling common mode resistors with the same resistance value, which is greater than or equal to 100 times the resistance value of the first resistor R1.
[0014] One end of the first resistor R1 (1 ohm), the second resistor R2 (100 ohms) and the third resistor R3 (1 ohm) are connected to the input power supply VDDin, the other end of the first resistor R1 and one end of the fourth resistor R4 (1000 ohms) are connected to the drain of the NMOS tube N, the other end of the fourth resistor R4 and one end of the fifth resistor R5 (1000 ohms) are connected to the positive input terminal of the operational amplifier A, the gate of the NMOS tube N is connected to the output terminal of the operational amplifier A, the negative input terminal of the operational amplifier A and the other end of the second resistor R2 are connected to the input terminal of the digitally controlled resistor array, the source of the NMOS tube N is connected to the output terminal of the digitally controlled resistor array, and the other ends of the third resistor R3 and the fifth resistor R5 are connected to the power supply terminal VDDd of the digital circuit.
[0015] Digitally controlled resistor array ( Figure 1 The dashed box in the middle includes a resistor RA0 and multiple gate resistors, each of which includes a load resistor and an NMOS tube. The resistance value of resistor RA0 is configured according to needs, and the load resistors RA1, RA2, ··· ,RAN's resistance. One end of resistor RA0 is connected to all load resistors RA1, RA2, ··· , one end of RAN is connected as the input end of the digital controlled resistor array; the other end of the load resistor is connected to the drain of the corresponding NMOS tube. All NMOS tubes E1, E2, ··· , the source of EN is connected to the other end of the resistor RA0 and grounded, serving as the output end of the digitally controlled resistor array; multiple NMOS tubes E1, E2, ··· ,The gate of EN is the multiple resistance control terminals of the digitally controlled resistor array, which is connected to the digital circuit.
[0016] When the digital circuit increases the current by 10mA, an additional 10mV voltage drop is added to the 1-ohm R3, and the voltage of the power supply terminal VDDd of the digital circuit drops by 10mV, causing the voltage at the connection terminal of R4 and R5 to drop by 5mV. The voltage at the output terminal of the operational amplifier A decreases, which will reduce the current of N, and at the same time, the voltage at the connection terminal of R1 and R4 increases. When the current of N decreases by 10mA, the 10mA current reduced by N offsets the 10mA increase of the digital circuit, and the total current remains the same as the current before the digital circuit increases by 10mA, thereby eliminating the voltage fluctuation on the internal resistance of the power supply VDDin caused by the increase of 10mA current in the digital circuit, and reducing the power supply noise of the audio system.
[0017] When the digital circuit reduces the current by 10mA, the voltage drop on 1 ohm R3 is reduced by an additional 10mV, and the voltage at the power supply terminal VDDd of the digital circuit rises by 10mV, causing the voltage at the connection terminal of R4 and R5 to rise by 5mV. The voltage at the output terminal of operational amplifier A rises, which will increase the current of N, while the voltage at the connection terminal of R1 and R4 decreases. When the current of N increases by 10mA, the 10mA current increased by N offsets the 10mA current reduced by the digital circuit, and the total current remains the same as the current before the digital circuit reduces the current by 10mA, thereby eliminating the voltage fluctuation on the internal resistance of the power supply VDDin caused by the digital circuit reducing the current by 10mA, and reducing the power supply noise of the audio system.
[0018] According to the maximum power consumption of the digital circuit, the NMOS tubes E1, E2, ··· , EN switch, the load resistance corresponding to the turned-on NMOS tube and the resistor RA0 form the total load resistance of the digital control resistor array. R2 is connected in series with the total load to divide the voltage, and the maximum current of the NMOS tube N is controlled through the operational amplifier A.
[0019] It should be understood that the above examples are merely illustrations of the present invention, rather than limitations of the present invention, and any inventions that do not exceed the essential spirit of the present invention shall fall within the protection scope of the present invention.
Claims
1. A power supply circuit with low power supply noise in an audio system, It is characterized in that It includes an operational amplifier, an NMOS tube, five resistors and a digitally controlled resistor array; the details are as follows: One end of the first resistor R1, the second resistor R2 and the third resistor R3 is connected to the input power supply VDDin, the other end of the first resistor R1 and one end of the fourth resistor R4 are connected to the drain of the NMOS tube N, the other end of the fourth resistor R4 and one end of the fifth resistor R5 are connected to the positive input end of the operational amplifier A, the gate of the NMOS tube N is connected to the output end of the operational amplifier A, the negative input end of the operational amplifier A and the other end of the second resistor R2 are connected to the input end of the digital control resistor array, the source of the NMOS tube N is connected to the output end of the digital control resistor array, and the other end of the third resistor R3 and the fifth resistor R5 are connected to the power supply end VDDd of the digital circuit; The digitally controlled resistor array includes a resistor RA0 and multiple gate resistors, each gate resistor includes a load resistor and an NMOS tube; one end of the resistor RA0 is connected to all the load resistors RA1, RA2, ··· , one end of RAN is connected as the input end of the digital controlled resistor array; the other end of the load resistor is connected to the drain of the corresponding NMOS tube. All NMOS tubes E1, E2, ··· , the source of EN is connected to the other end of the resistor RA0 and grounded, serving as the output end of the digitally controlled resistor array; multiple NMOS tubes E1, E2, ··· ,The gate of EN is the multiple resistance control terminals of the digitally controlled resistor array, which is connected to the digital circuit.
2. A power supply circuit with low power supply noise in an audio system as claimed in claim 1, Features: The first resistor R1 and the third resistor R3 are sampling resistors with the same resistance value, which is less than 10 ohms; the second resistor R2 is a bias resistor with a resistance value greater than or equal to 10 times the resistance value of the first resistor R1; the fourth resistor R4 and the fifth resistor R5 are sampling common-mode resistors with the same resistance value, which is greater than or equal to 100 times the resistance value of the first resistor R1.