Display substrate and display device

Abstract

The utility model discloses a display substrate and a display device. The display substrate comprises a driving structure layer and a light-emitting structure layer, the driving structure layer comprises a plurality of circuit units, each circuit unit comprises a pixel driving circuit, a power supply connecting line and a first power line, the pixel driving circuit at least comprises a power supply connecting electrode, and the power supply connecting electrode is connected with the power supply connecting line. The first power line is connected with the power connecting line or the power connecting electrode through the power via hole; the light-emitting structure layer comprises a plurality of light-emitting units, at least one light-emitting unit comprises an anode and a pixel definition layer, the anode is connected with the pixel driving circuit of the corresponding circuit unit, and the pixel definition layer is provided with a pixel opening exposing the anode. The orthographic projection of at least one pixel opening on the substrate is not overlapped with the orthographic projection of the power supply via hole on the substrate. According to the invention, no power supply via hole is arranged in the range of the pixel opening, so that color cast can be effectively improved, and display quality is improved.

Description

Technical Field

[0001] The present invention relates to but is not limited to the field of display technology, and specifically to a display substrate and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diode (QLED) are active light-emitting display devices with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, bendability and low cost. With the continuous development of display technology, flexible display devices (Flexible Display) using OLED or QLED as light-emitting devices and thin film transistors (TFT) for signal control have become the mainstream products in the current display field.

[0003] Currently, existing display devices have problems such as color shift. Summary of the invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] The technical problem to be solved by the embodiments of the present disclosure is to provide a display substrate and a display device to solve the problems of color shift and the like in the existing display devices.

[0006] On the one hand, the present disclosure provides a display substrate, including a driving structure layer arranged on a substrate and a light-emitting structure layer arranged on a side of the driving structure layer away from the substrate; on a plane parallel to the display substrate, the driving structure layer includes a plurality of circuit units, at least one circuit unit includes a pixel driving circuit, a power connection line extending along a first direction, and a first power line extending along a second direction, the first direction and the second direction intersect, the pixel driving circuit at least includes a power connection electrode, the power connection electrode is connected to the power connection line, and the first power line is connected to the power connection line or the power connection electrode through a power via; the light-emitting structure layer includes a plurality of light-emitting units, at least one light-emitting unit includes an anode and a pixel definition layer arranged on a side of the anode away from the substrate, the anode is connected to the pixel driving circuit of the corresponding circuit unit, the pixel definition layer is provided with a pixel opening exposing the anode, and the orthographic projection of at least one pixel opening on the substrate does not overlap with the orthographic projection of the power via on the substrate.

[0007] In an exemplary embodiment, a plurality of light-emitting units include at least a first light-emitting unit emitting a first color light, a second light-emitting unit emitting a second color light, and a third light-emitting unit emitting a third color light, the first light-emitting unit includes at least a first anode and a first pixel opening exposing the first anode, the second light-emitting unit includes at least a second anode and a second pixel opening exposing the second anode, and the third light-emitting unit includes at least a third anode and a third pixel opening exposing the third anode; the second anode is arranged on one side of the first anode in the second direction, and the third anode is arranged on one side of the first anode in the first direction; the orthographic projections of the first pixel opening and the second pixel opening on the substrate at least partially overlap with the orthographic projection of the first power line on the substrate, and the orthographic projection of the third pixel opening on the substrate does not overlap with the orthographic projection of the first power line on the substrate.

[0008] In an exemplary embodiment, orthographic projections of the first pixel opening and the second pixel opening on the substrate are located within a range of orthographic projections of the first power line on the substrate.

[0009] In an exemplary embodiment, in at least one circuit unit and a circuit unit adjacent to the first direction, the first power lines in the two circuit units are an integrated structure connected to each other.

[0010] In an exemplary embodiment, at least one circuit unit further includes a data signal line, and in at least one circuit unit and the circuit units adjacent to each other in the first direction, the data signal line in one circuit unit is arranged on a side of the first power line in the opposite direction of the first direction, and the data signal line in another circuit unit is arranged on a side of the first power line in the first direction; the orthographic projections of the first pixel opening and the second pixel opening on the substrate do not overlap with the orthographic projections of the data signal line on the substrate, and the orthographic projection of the third pixel opening on the substrate at least partially overlaps with the orthographic projection of the data signal line on the substrate.

[0011] In an exemplary embodiment, the pixel driving circuit further includes a fourth transistor and a data connection electrode, the fourth transistor includes at least a fourth active layer, and the data signal line is connected to the data connection electrode through a data via; in at least one circuit unit and the circuit units adjacent in the first direction, the data connection electrode in one circuit unit is connected to the first area of ​​the fourth active layer through a via, and the data connection electrode in another circuit unit is connected to the first area of ​​the fourth active layer through a data connection line.

[0012] In an exemplary embodiment, the pixel driving circuit further includes a shielding electrode and a second transistor of a dual-gate structure, the shielding electrode being connected to the first power line, the orthographic projection of the shielding electrode on the substrate at least partially overlapping with the orthographic projection of the second active layer between the two gate electrodes of the second transistor on the substrate, and the orthographic projection of the shielding electrode on the substrate at least partially overlapping with the orthographic projection of the data connection line on the substrate.

[0013] In an exemplary embodiment, the pixel driving circuit also includes a fourth node electrode and an anode connecting electrode, and the anode in at least one light-emitting unit is connected to the anode connecting electrode through an anode via; in at least one circuit unit and the circuit units adjacent in the first direction, the anode connecting electrode in one circuit unit is connected to the fourth node electrode through a via, and the anode connecting electrode in another circuit unit is connected to the fourth node electrode through an anode connecting line; the orthographic projections of the first pixel opening and the second pixel opening on the substrate do not overlap with the orthographic projections of the anode connecting line on the substrate, and the orthographic projections of the third pixel opening on the substrate at least partially overlap with the orthographic projections of the anode connecting line on the substrate.

[0014] In an exemplary embodiment, the third pixel opening has an opening center line, which is a straight line extending along the second direction and passing through the geometric center of the third pixel opening; in at least one third pixel opening, the anode connection line has a first distance from the opening center line, and the data signal line has a second distance from the opening center line, and the ratio of the first distance to the second distance is 0.8 to 1.2.

[0015] In an exemplary embodiment, at least one circuit unit further includes at least one initial signal line extending along the first direction, and a second power line and an initial connection line extending along the second direction, the initial connection line being connected to the initial signal line, the orthographic projections of the first pixel opening and the second pixel opening on the substrate do not overlap with the orthographic projections of the second power line and the initial connection line on the substrate, and the orthographic projection of the third pixel opening on the substrate at least partially overlaps with the orthographic projections of the second power line and the initial connection line on the substrate.

[0016] In an exemplary embodiment, the third pixel opening has an opening center line, which is a straight line extending along the second direction and passing through the geometric center of the third pixel opening; in at least one third pixel opening, the second power line has a third distance from the opening center line, and the initial connection line has a fourth distance from the opening center line, and the ratio of the third distance to the fourth distance is 0.8 to 1.2.

[0017] In an exemplary embodiment, the pixel driving circuit further includes a storage capacitor, and at least one circuit unit further includes a first scanning signal line, a second scanning signal line, a third scanning signal line, a light-emitting signal line, a first initial signal line, a second initial signal line, and a third initial signal line extending along the first direction and connected to the pixel driving circuit, the first scanning signal line is arranged on a side of the storage capacitor in the opposite direction of the second direction, the third scanning signal line is arranged on a side of the first scanning signal line away from the storage capacitor, the first initial signal line is arranged on a side of the third scanning signal line away from the storage capacitor, the light-emitting signal line is arranged on one side of the storage capacitor in the second direction, and the second scanning signal line is arranged on a side of the light-emitting signal line away from the storage capacitor. on one side of the storage capacitor, the second initial signal line is arranged on the side of the second scanning signal line away from the storage capacitor, and the third initial signal line is arranged on the side of the second initial signal line away from the storage capacitor; the orthographic projection of at least one first pixel opening on the substrate at least partially overlaps with the orthographic projection of the power connection line on the substrate, the orthographic projection of at least one second pixel opening on the substrate at least partially overlaps with the orthographic projections of the first initial signal line, the second initial signal line and the third initial signal line on the substrate, and the orthographic projection of at least one third pixel opening on the substrate at least partially overlaps with the orthographic projections of the second scanning signal line, the light-emitting signal line, the second initial signal line and the power connection line on the substrate.

[0018] In an exemplary embodiment, the orthographic projection of at least one first pixel opening on the substrate does not overlap with the orthographic projection of the first initial signal line on the substrate, the orthographic projection of at least one second pixel opening on the substrate does not overlap with the orthographic projections of the first scan signal line and the power connection line on the substrate, and the orthographic projection of at least one third pixel opening on the substrate does not overlap with the orthographic projections of the first scan signal line and the third scan signal line on the substrate.

[0019] In an exemplary embodiment, the plurality of light-emitting units include at least a first light-emitting unit emitting a first color light, a second light-emitting unit emitting a second color light, and a third light-emitting unit emitting a third color light, the first light-emitting unit includes at least a first anode and a first pixel opening exposing the first anode, the second light-emitting unit includes at least a second anode and a second pixel opening exposing the second anode, and the third light-emitting unit includes at least a third anode and a third pixel opening exposing the third anode; the second anode is arranged on one side of the first anode in the second direction, and the third anode is arranged on one side of the first anode in the first direction; the pixel driving circuit also includes a data connection electrode, and at least one circuit unit also includes a data signal line, and the data signal line is connected to the data connection electrode through a data via; the orthographic projections of the first pixel opening, the second pixel opening, and the third pixel opening on the substrate do not overlap with the orthographic projections of the data via on the substrate.

[0020] In an exemplary embodiment, the plurality of circuit units include at least a first circuit unit, a second circuit unit, and a third circuit unit sequentially arranged along the first direction, the first circuit unit including at least a first pixel driving circuit and a first data signal line connected to a data connection electrode in the first pixel driving circuit through a first data via, the second circuit unit including at least a second pixel driving circuit and a second data signal line connected to a data connection electrode in the second pixel driving circuit through a second data via, the third circuit unit including at least a third pixel driving circuit and a third data signal line connected to a data connection electrode in the third pixel driving circuit through a third data via; the orthographic projections of the first pixel opening and the second pixel opening on the substrate at least partially overlap with the orthographic projections of the first data signal line on the substrate, and the orthographic projections of the third pixel opening on the substrate do not overlap with the orthographic projections of the first data signal line, the second data signal line, and the third data signal line on the substrate.

[0021] In an exemplary embodiment, in the first direction, a spacing between the first data signal line and the second data signal line is smaller than a spacing between the second data signal line and the third data signal line, and a spacing between the first data via and the second data via is smaller than a spacing between the second data via and the third data via.

[0022] In an exemplary embodiment, in the first direction, the second data via hole and the third data via hole are disposed at both sides of the third pixel opening, and in the second direction, the first data via hole is disposed between the first pixel opening and the second pixel opening.

[0023] In an exemplary embodiment, the pixel driving circuit includes at least a storage capacitor, and at least one circuit unit further includes a first scanning signal line, a second scanning signal line, a third scanning signal line, a light-emitting signal line, a first initial signal line, a second initial signal line, and a third initial signal line extending along the first direction and connected to the pixel driving circuit, the first scanning signal line is arranged on a side of the storage capacitor in the opposite direction of the second direction, the third scanning signal line is arranged on a side of the first scanning signal line away from the storage capacitor, the first initial signal line is arranged on a side of the third scanning signal line away from the storage capacitor, the light-emitting signal line is arranged on one side of the storage capacitor in the second direction, and the second scanning signal line is arranged on a side of the storage capacitor in the opposite direction of the second direction. The line is arranged on a side of the light-emitting signal line away from the storage capacitor, the second initial signal line is arranged on a side of the second scanning signal line away from the storage capacitor, and the third initial signal line is arranged on a side of the second initial signal line away from the storage capacitor; the orthographic projection of at least one first pixel opening on the substrate at least partially overlaps with the orthographic projection of the first initial signal line on the substrate, the orthographic projection of at least one second pixel opening on the substrate at least partially overlaps with the orthographic projections of the first scanning signal line and the power connection line on the substrate, and the orthographic projection of at least one third pixel opening on the substrate at least partially overlaps with the orthographic projections of the first scanning signal line and the third scanning signal line on the substrate.

[0024] In an exemplary embodiment, the orthographic projection of at least one first pixel opening on the substrate does not overlap with the orthographic projection of the power connection line on the substrate, the orthographic projection of at least one second pixel opening on the substrate does not overlap with the orthographic projections of the first initial signal line, the second initial signal line and the third initial signal line on the substrate, and the orthographic projection of at least one third pixel opening on the substrate does not overlap with the orthographic projections of the second scanning signal line, the light-emitting signal line, the power connection line and the second initial signal line on the substrate.

[0025] On the other hand, the present disclosure further provides a display device, comprising the aforementioned display substrate.

[0026] The embodiments of the present disclosure provide a display substrate and a display device. By arranging the area where the pixel opening is located without a power via, the anode exposed by the pixel opening has good flatness, which can effectively avoid defects such as off-screen watermarks caused by poor anode flatness, effectively improve color deviation, and enhance display quality.

[0027] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution of the present disclosure.

[0029] Figure 1 is a structural schematic diagram of a display device;

[0030] Figure 2 It is a schematic diagram of a planar structure of a display substrate;

[0031] Figure 3 A schematic diagram of a cross-sectional structure of a display substrate;

[0032] Figure 4 is a schematic diagram of an equivalent circuit of a pixel driving circuit;

[0033] Figure 5 A schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0034] Figure 6 This is a schematic diagram of a display substrate after a shielding layer pattern is formed on the display substrate of the present disclosure;

[0035] Fig. 7A and Figure 7B This is a schematic diagram of a display substrate after a semiconductor layer pattern is formed on the display substrate of the present disclosure;

[0036] Fig. 8A and Figure 8B This is a schematic diagram of a display substrate after a first conductive layer pattern is formed on the display substrate of the present disclosure;

[0037] Fig.9A and Fig. 9B This is a schematic diagram of a display substrate after a second conductive layer pattern is formed on the display substrate of the present disclosure;

[0038] Fig.10 This is a schematic diagram of a display substrate after a fourth insulating layer pattern is formed on the display substrate of the present disclosure;

[0039] Fig.11A and Fig. 11B This is a schematic diagram of a display substrate after a third conductive layer pattern is formed on the display substrate of the present disclosure;

[0040] Fig.12 This is a schematic diagram of a display substrate after a first flat layer pattern is formed in the present disclosure;

[0041] Fig.13A and Fig. 13B This is a schematic diagram of a display substrate after a fourth conductive layer pattern is formed on the display substrate of the present disclosure;

[0042] Fig.14 This is a schematic diagram of a display substrate after a second flat layer pattern is formed on the display substrate of the present disclosure;

[0043] Fig.15A and Fig. 15B This is a schematic diagram of a display substrate after an anode conductive layer pattern is formed in the present disclosure;

[0044] Fig.16 This is a schematic diagram of a display substrate after a pixel definition layer pattern is formed on the display substrate of the present disclosure;

[0045] Fig.17 is a schematic diagram of the positional relationship between the third pixel opening and the signal line according to the embodiment of the present disclosure;

[0046] Fig.18 It is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure;

[0047] Fig.19 It is a schematic diagram of another display substrate of the present disclosure after a shielding layer pattern is formed;

[0048] Fig. 20A and Fig. 20B It is a schematic diagram of another display substrate disclosed in the present invention after a semiconductor layer pattern is formed;

[0049] Fig.21A and Fig.21B It is a schematic diagram of another display substrate of the present disclosure after a first conductive layer pattern is formed;

[0050] Fig.22A and Fig. 22B It is a schematic diagram of another display substrate of the present disclosure after a second conductive layer pattern is formed;

[0051] Fig.23 It is a schematic diagram of another display substrate of the present disclosure after a fourth insulating layer pattern is formed;

[0052] Fig.24A and Fig. 24B It is a schematic diagram of another display substrate of the present disclosure after a third conductive layer pattern is formed;

[0053] Fig.25 It is a schematic diagram of another display substrate of the present disclosure after a first flat layer pattern is formed;

[0054] Fig.26A and Fig.26B It is a schematic diagram of another display substrate of the present disclosure after a fourth conductive layer pattern is formed;

[0055] Fig. 27 It is a schematic diagram of another display substrate of the present disclosure after a second flat layer pattern is formed;

[0056] Fig.28A and Fig.28B It is a schematic diagram of another display substrate after forming an anode conductive layer pattern in the present disclosure;

[0057] Fig.29 It is a schematic diagram of another display substrate after forming a pixel definition layer pattern according to the present disclosure.

[0058] Description of reference numerals:

[0059] 11—first active layer; 12—second active layer; 13—third active layer;

[0060] 14—fourth active layer; 15—fifth active layer; 16—sixth active layer;

[0061] 17—seventh active layer; 18—eighth active layer; 21—first gate electrode;

[0062] 22—second gate electrode; 24—fourth gate electrode; 31—first scanning signal line;

[0063] 32—second scanning signal line; 33—third scanning signal line; 34—light emitting signal line;

[0064] 35—shielding electrode; 41—first initial signal line; 42—second initial signal line;

[0065] 43—third initial signal line; 44—power connection line; 45—auxiliary scanning signal line;

[0066] 46—data connection line; 51—first connection electrode; 52—second connection electrode;

[0067] 53—third connecting electrode; 54—fourth connecting electrode; 55—fifth connecting electrode;

[0068] 56—sixth connecting electrode; 61—data signal line; 62—anode connecting electrode;

[0069] 63—anode connection line; 64—extension electrode; 71—first power line;

[0070] 72—second power line; 73—initial connection line; 81—first electrode plate;

[0071] 82—second electrode plate; 83—plate-level connecting strip; 84—opening;

[0072] 90—shielding electrode; 91—first shielding connecting strip; 92—second shielding connecting strip;

[0073] 93—third shielding connecting strip; 94—first shielding block; 95—second shielding block;

[0074] 101 - substrate; 102 - driving structure layer; 103 - light emitting structure layer;

[0075] 104 —Encapsulation structure layer. DETAILED DESCRIPTION

[0076] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail in conjunction with the accompanying drawings below. Note that the embodiments can be implemented in multiple different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0077] The proportions of the drawings in this disclosure can be used as a reference in the actual process, but are not limited to this. For example: the width-to-length ratio of the channel, the thickness and spacing of each film layer, the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The drawings described in this disclosure are only structural schematic diagrams, and one method of this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0078] In the present specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0079] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the situation.

[0080] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this disclosure can be understood according to specific circumstances.

[0081] In this specification, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region where current mainly flows.

[0082] In this specification, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" may be interchanged, and the "source terminal" and the "drain terminal" may be interchanged.

[0083] In this specification, "electrical connection" includes the case where components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0084] In this specification, "parallel" means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.

[0085] In this specification, "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced by "conductive film". Similarly, "insulating film" may be replaced by "insulating layer".

[0086] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, and may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0087] The term "about" in the present disclosure refers to a numerical value that is not strictly limited to allow for process and measurement errors.

[0088] Figure 1 FIG. 1 is a schematic diagram of the structure of a display device. Figure 1As shown, the display device may include a timing controller, a data driver, a scan driver, a light emitting driver and a pixel array, the timing controller is respectively connected to the data driver, the scan driver and the light emitting driver, the data driver is respectively connected to a plurality of data signal lines (D1 to Dn), the scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm), and the light emitting driver is respectively connected to a plurality of light emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, at least one sub-pixel Pxij may include a circuit unit and a light emitting unit, the circuit unit may include at least a pixel driving circuit, the pixel driving circuit is respectively connected to the scan signal line, the light emitting signal line and the data signal line, the light emitting unit may include a light emitting device, and the light emitting device is connected to the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller may provide a grayscale value and a control signal suitable for the specification of the data driver to the data driver, may provide a clock signal suitable for the specification of the scan driver, a scan start signal, etc. to the scan driver, and may provide a clock signal suitable for the specification of the light emitting driver, an emission stop signal, etc. to the light emitting driver. The data driver can generate data voltages to be provided to data signal lines D1, D2, D3, ... and Dn using grayscale values ​​and control signals received from the timing controller. For example, the data driver can sample grayscale values ​​using a clock signal, and apply data voltages corresponding to grayscale values ​​to data signal lines D1 to Dn in units of pixel rows, where n can be a natural number. The scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ... and Sm by receiving clock signals, scan start signals, etc. from the timing controller. For example, the scan driver can sequentially provide scan signals with conduction level pulses to scan signal lines S1 to Sm. For example, the scan driver can be constructed in the form of a shift register, and can sequentially transmit scan start signals provided in the form of conduction level pulses to the next level circuit under the control of the clock signal to generate scan signals, where m can be a natural number. The light-emitting driver can generate emission signals to be provided to light-emitting signal lines E1, E2, E3, ... and Eo by receiving clock signals, emission stop signals, etc. from the timing controller. For example, the light emitting driver may sequentially provide an emission signal having a cut-off level pulse to the light emitting signal lines E1 to Eo. For example, the light emitting driver may be configured in the form of a shift register, and may generate an emission signal in a manner of sequentially transmitting an emission stop signal provided in the form of a cut-off level pulse to a next stage circuit under the control of a clock signal, and o may be a natural number. In an exemplary embodiment, a pixel array may be provided on a display substrate.

[0089] Figure 2 FIG. 1 is a schematic diagram of a planar structure of a display substrate. Figure 2As shown, the display substrate may include a plurality of pixel units P arranged in a matrix, and at least one pixel unit P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. Each sub-pixel may include a circuit unit and a light-emitting unit, and the circuit unit may include at least a pixel driving circuit, and the pixel driving circuit is respectively connected to the scanning signal line, the data signal line, and the light-emitting signal line, and the pixel driving circuit is configured to receive the data voltage transmitted by the data signal line under the control of the scanning signal line and the light-emitting signal line, and output a corresponding current to the light-emitting unit. The light-emitting unit in each sub-pixel is respectively connected to the pixel driving circuit of the sub-pixel, and the light-emitting unit is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel.

[0090] In an exemplary embodiment, the first sub-pixel P1 may be a red sub-pixel (R) emitting red light, the second sub-pixel P2 may be a green sub-pixel (G) emitting green light, and the third sub-pixel P3 may be a blue sub-pixel (B) emitting blue light. In an exemplary embodiment, the shape of the sub-pixels may be rectangular, rhombus, pentagonal or hexagonal, and the three sub-pixels may be arranged in a horizontal parallel, vertical parallel or triangular manner, which is not limited in the present disclosure.

[0091] In other exemplary embodiments, the pixel unit may include four sub-pixels, and the four sub-pixels may be arranged in parallel horizontally, in parallel vertically, or in a square, etc., which is not limited in the present disclosure.

[0092] Figure 3 FIG. 1 is a schematic diagram of a cross-sectional structure of a display substrate, illustrating the structure of three sub-pixels. Figure 3 As shown, on a plane perpendicular to the display substrate, the display substrate may include a driving structure layer 102 disposed on a substrate 101, a light emitting structure layer 103 disposed on a side of the driving structure layer 102 away from the substrate 101, and an encapsulation structure layer 104 disposed on a side of the light emitting structure layer 103 away from the substrate 101. In some possible implementations, the display substrate may include other film layers, such as a touch structure layer, etc., which is not limited in the present disclosure.

[0093] In an exemplary embodiment, the substrate 101 may be a flexible substrate, or may be a rigid substrate. The driving structure layer 102 may include a plurality of circuit units, each of which may include at least a pixel driving circuit composed of a plurality of transistors and a storage capacitor. The light-emitting structure layer 103 may include a plurality of light-emitting units, each of which may include at least an anode, an organic light-emitting layer and a cathode, the anode is connected to the pixel driving circuit, the organic light-emitting layer is connected to the anode, the cathode is connected to the organic light-emitting layer, and the organic light-emitting layer emits light of corresponding colors under the drive of the anode and the cathode. The encapsulation structure layer 104 may include a first encapsulation layer, a second encapsulation layer and a third encapsulation layer stacked, the first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to form an inorganic material / organic material / inorganic material stacked structure, which can ensure that external water vapor cannot enter the light-emitting structure layer 103.

[0094] Figure 4 FIG. 1 is a schematic diagram of an equivalent circuit of a pixel driving circuit. Figure 4 As shown, the pixel driving circuit may include 8 transistors (first transistor T1 to eighth transistor T8) and 1 storage capacitor C, and the pixel driving circuit is respectively connected to 9 signal lines (first scanning signal line S1, second scanning signal line S2, third scanning signal line S3, light emitting signal line EM, first initial signal line INIT1, second initial signal line INIT2, third initial signal line INIT3, data signal line DATA and first power line VDD).

[0095] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is respectively connected to the second electrode of the first transistor T1, the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first end of the storage capacitor C, the second node N2 is respectively connected to the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, the second electrode of the fifth transistor T5, and the second electrode of the eighth transistor T8, the third node N3 is respectively connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6, and the fourth node N4 is respectively connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7.

[0096] In an exemplary embodiment, a first end of the storage capacitor C is connected to the first node N1 , and a second end of the storage capacitor C is connected to the first power line VDD.

[0097] In an exemplary embodiment, the first transistor T1 may be referred to as a first initialization transistor, a gate electrode of the first transistor T1 is connected to the third scan signal line S3 , a first electrode of the first transistor T1 is connected to the first initial signal line INIT1 , and a second electrode of the first transistor T1 is connected to the first node N1 .

[0098] In an exemplary embodiment, the second transistor T2 may be referred to as a compensation transistor, a gate electrode of the second transistor T2 is connected to the first scan signal line S1 , a first electrode of the second transistor T2 is connected to the first node N1 , and a second electrode of the second transistor T2 is connected to the third node N3 .

[0099] In an exemplary embodiment, the third transistor T3 may be referred to as a driving transistor, a gate electrode of the third transistor T3 is connected to the first node N1, a first electrode of the third transistor T3 is connected to the second node N2, and a second electrode of the third transistor T3 is connected to the third node N3.

[0100] In an exemplary embodiment, the fourth transistor T4 may be referred to as a data writing transistor, a gate electrode of the fourth transistor T4 is connected to the first scan signal line S1, a first electrode of the fourth transistor T4 is connected to the data signal line DATA, and a second electrode of the fourth transistor T4 is connected to the second node N2.

[0101] In an exemplary embodiment, the fifth transistor T5 may be referred to as a first light emission control transistor, a gate electrode of the fifth transistor T5 is connected to the light emission signal line EM, a first electrode of the fifth transistor T5 is connected to the first power line VDD, and a second electrode of the fifth transistor T5 is connected to the second node N2.

[0102] In an exemplary embodiment, the sixth transistor T6 may be referred to as a second light emission control transistor, a gate electrode of the sixth transistor T6 is connected to the light emission signal line EM, a first electrode of the sixth transistor T6 is connected to the third node N3, and a second electrode of the sixth transistor T6 is connected to the fourth node N4.

[0103] In an exemplary embodiment, the seventh transistor T7 may be referred to as a second initialization transistor, a gate electrode of the seventh transistor T7 is connected to the second scan signal line S2, a first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2, and a second electrode of the seventh transistor T7 is connected to the fourth node N4.

[0104] In an exemplary embodiment, the eighth transistor T8 may be referred to as a third initialization transistor, a gate electrode of the eighth transistor T8 is connected to the second scan signal line S2, a first electrode of the eighth transistor T8 is connected to the third initial signal line INIT3, and a second electrode of the eighth transistor T8 is connected to the second node N2.

[0105] In an exemplary embodiment, a first electrode of the light emitting device EL is connected to the fourth node N4, and a second electrode of the light emitting device EL is connected to the second power supply line VSS. The light emitting device EL may be an OLED including a stacked first electrode (anode), an organic light emitting layer, and a second electrode (cathode), or may be a QLED including a stacked first electrode (anode), a quantum dot light emitting layer, and a second electrode (cathode).

[0106] In an exemplary embodiment, the signal of the first power line VDD is a high level signal that is continuously provided, and the signal of the second power line VSS is a low level signal that is continuously provided.

[0107] In an exemplary embodiment, the first transistor T1 to the eighth transistor T8 may be a P-type transistor, or may be an N-type transistor. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementations, the first transistor T1 to the eighth transistor T8 may include a P-type transistor and an N-type transistor.

[0108] In an exemplary embodiment, the first transistor T1 to the eighth transistor T8 may be a low-temperature polysilicon transistor, or an oxide transistor, or a low-temperature polysilicon transistor and an oxide transistor. The active layer of the low-temperature polysilicon transistor is low-temperature polysilicon (LTPS), and the active layer of the oxide transistor is oxide semiconductor (Oxide). Low-temperature polysilicon transistors have advantages such as high mobility and fast charging, and oxide transistors have advantages such as low leakage current. Low-temperature polysilicon transistors and oxide transistors are integrated on a display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate, which can take advantage of the advantages of both, can achieve low-frequency driving, can reduce power consumption, and can improve display quality.

[0109] The inventors of the present application have found through research that the main reason for the color cast and other problems in the existing display devices is due to the poor flatness of the anode.

[0110] The exemplary embodiment of the present disclosure provides a display substrate. In an exemplary embodiment, on a plane perpendicular to the display substrate, the display substrate may include a driving structure layer disposed on a substrate and a light-emitting structure layer disposed on a side of the driving structure layer away from the substrate; on a plane parallel to the display substrate, the driving structure layer includes a plurality of circuit units, at least one circuit unit includes a pixel driving circuit, a power connection line extending along a first direction, and a first power line extending along a second direction, the first direction and the second direction intersect, the pixel driving circuit includes at least a power connection electrode, the power connection electrode is connected to the power connection line, and the first power line is connected to the power connection line or the power connection electrode through a power via; the light-emitting structure layer includes a plurality of light-emitting units, at least one light-emitting unit includes an anode and a pixel definition layer disposed on a side of the anode away from the substrate, the anode is connected to the pixel driving circuit of the corresponding circuit unit, the pixel definition layer is provided with a pixel opening exposing the anode, and the orthographic projection of at least one pixel opening on the substrate does not overlap with the orthographic projection of the power via on the substrate.

[0111] In an exemplary embodiment, the circuit unit mentioned in the present disclosure refers to an area divided according to a pixel driving circuit, and the light-emitting unit mentioned in the present disclosure refers to an area divided according to a light-emitting device. In an exemplary embodiment, the position and shape of the orthographic projection of the light-emitting unit on the substrate may correspond to the position and shape of the orthographic projection of the circuit unit on the substrate, or the position and shape of the orthographic projection of the light-emitting unit on the substrate may not correspond to the position and shape of the orthographic projection of the circuit unit on the substrate.

[0112] In an exemplary embodiment, a plurality of light-emitting units include at least a first light-emitting unit emitting a first color light, a second light-emitting unit emitting a second color light, and a third light-emitting unit emitting a third color light, the first light-emitting unit includes at least a first anode and a first pixel opening exposing the first anode, the second light-emitting unit includes at least a second anode and a second pixel opening exposing the second anode, and the third light-emitting unit includes at least a third anode and a third pixel opening exposing the third anode; the second anode is arranged on one side of the first anode in the second direction, and the third anode is arranged on one side of the first anode in the first direction; the orthographic projections of the first pixel opening and the second pixel opening on the substrate at least partially overlap with the orthographic projection of the first power line on the substrate, and the orthographic projection of the third pixel opening on the substrate does not overlap with the orthographic projection of the first power line on the substrate.

[0113] In an exemplary embodiment, orthographic projections of the first pixel opening and the second pixel opening on the substrate are located within a range of orthographic projections of the first power line on the substrate.

[0114] In an exemplary embodiment, at least one circuit unit further includes a data signal line, and in at least one circuit unit and the circuit units adjacent to each other in the first direction, the data signal line in one circuit unit is arranged on a side of the first power line in the opposite direction of the first direction, and the data signal line in another circuit unit is arranged on a side of the first power line in the first direction; the orthographic projections of the first pixel opening and the second pixel opening on the substrate do not overlap with the orthographic projections of the data signal line on the substrate, and the orthographic projection of the third pixel opening on the substrate at least partially overlaps with the orthographic projection of the data signal line on the substrate.

[0115] In an exemplary embodiment, the plurality of light-emitting units include at least a first light-emitting unit emitting a first color light, a second light-emitting unit emitting a second color light, and a third light-emitting unit emitting a third color light, the first light-emitting unit includes at least a first anode and a first pixel opening exposing the first anode, the second light-emitting unit includes at least a second anode and a second pixel opening exposing the second anode, and the third light-emitting unit includes at least a third anode and a third pixel opening exposing the third anode; the second anode is arranged on one side of the first anode in the second direction, and the third anode is arranged on one side of the first anode in the first direction; the pixel driving circuit also includes a data connection electrode, and at least one circuit unit also includes a data signal line, and the data signal line is connected to the data connection electrode through a data via; the orthographic projections of the first pixel opening, the second pixel opening, and the third pixel opening on the substrate do not overlap with the orthographic projections of the data via on the substrate.

[0116] In an exemplary embodiment, the plurality of circuit units include at least a first circuit unit, a second circuit unit, and a third circuit unit sequentially arranged along the first direction, the first circuit unit including at least a first pixel driving circuit and a first data signal line connected to the first pixel driving circuit through a first data via, the second circuit unit including at least a second pixel driving circuit and a second data signal line connected to the second pixel driving circuit through a second data via, the third circuit unit including at least a third pixel driving circuit and a third data signal line connected to the third pixel driving circuit through a third data via; the orthographic projections of the first pixel opening and the second pixel opening on the substrate at least partially overlap with the orthographic projections of the first data signal line on the substrate, and the orthographic projections of the third pixel opening on the substrate do not overlap with the orthographic projections of the first data signal line, the second data signal line, and the third data signal line on the substrate.

[0117] In an exemplary embodiment, a spacing between the first data signal line and the second data signal line is smaller than a spacing between the second data signal line and the third data signal line, and a spacing between the first data via and the second data via is smaller than a spacing between the second data via and the third data via.

[0118] Figure 5 The schematic diagram of the planar structure of a display substrate of an exemplary embodiment of the present disclosure is shown in FIG. In an exemplary embodiment, on a plane perpendicular to the display substrate, the display substrate may include a driving structure layer disposed on a substrate and a light emitting structure layer disposed on a side of the driving structure layer away from the substrate. On a plane parallel to the display substrate, the driving structure layer includes a plurality of circuit units, and the light emitting structure layer includes a plurality of light emitting units.

[0119] In an exemplary embodiment, the plurality of circuit units may form a plurality of unit rows and a plurality of unit columns, the plurality of circuit units in each unit row being sequentially arranged along a first direction X, and the plurality of circuit units in each unit column being sequentially arranged along a second direction Y, to form an array of circuit units arranged in an array, wherein the first direction X intersects with the second direction Y.

[0120] In an exemplary embodiment, at least one circuit unit may include at least a pixel driving circuit, the pixel driving circuit may include at least a storage capacitor and a plurality of transistors, and the pixel driving circuit is respectively connected to a first scanning signal line 31, a second scanning signal line 32, a third scanning signal line 33, a light emitting signal line 34, a first initial signal line 41, a second initial signal line 42, a third initial signal line 43, a data signal line 61, and a first power line 71. The first scanning signal line 31, the second scanning signal line 32, and the third scanning signal line 33 are configured to provide the first scanning signal, the second scanning signal, and the third scanning signal to the pixel driving circuit, respectively, the light emitting signal line 34 is configured to provide the light emitting control signal to the pixel driving circuit, the first initial signal line 41, the second initial signal line 42, and the third initial signal line 43 are configured to provide the first initial signal, the second initial signal, and the third initial signal to the pixel driving circuit, respectively, the data signal line 61 is configured to provide the data signal to the pixel driving circuit, and the first power line 71 is configured to provide the first power signal to the pixel driving circuit.

[0121] In an exemplary embodiment, the shapes of the first scan signal line 31, the second scan signal line 32, the third scan signal line 33, the light-emitting signal line 34, the first initial signal line 41, the second initial signal line 42 and the third initial signal line 43 can be straight lines or folded lines with the main parts extending along the first direction X, and the shapes of the data signal line 61 and the first power line 71 can be straight lines or folded lines with the main parts extending along the second direction Y.

[0122] In the present disclosure, A extends along direction B means that A may include a main part and a secondary part connected to the main part, the main part is a line, a line segment or a strip-shaped body, the main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions. In the following description, "A extends along direction B" means "the main part of A extends along direction B".

[0123] In an exemplary embodiment, in the second direction Y, the first scan signal line 31 may be located on a side of the storage capacitor in the opposite direction of the second direction Y, the third scan signal line 33 may be located on a side of the first scan signal line 31 away from the storage capacitor, and the first initial signal line 41 may be located on a side of the third scan signal line 33 away from the storage capacitor. The light emitting signal line 34 may be located on a side of the storage capacitor in the second direction Y, the second scan signal line 32 may be located on a side of the light emitting signal line 34 away from the storage capacitor, the second initial signal line 42 may be located on a side of the second scan signal line 32 away from the storage capacitor, and the third initial signal line 43 may be located on a side of the second initial signal line 42 away from the storage capacitor.

[0124] In an exemplary embodiment, at least one circuit unit may further include a power connection line 44, the shape of the power connection line 44 may be a straight line or a broken line with a main part extending along the first direction X, the power connection line 44 may be located between the first scanning signal line 31 and the light emitting signal line 34, and the positive projection of the power connection line 44 on the substrate overlaps at least partially with the positive projection of the storage capacitor on the substrate. In an exemplary embodiment, the first power line 71 may be connected to the power connection line 44 through the power via K1, so that the first power line 71 and the power connection line 44 form a meshed meshed connection structure for transmitting the first power signal on the display substrate. In an exemplary embodiment, the power connection line 44 is connected to the second plate of the storage capacitor in the pixel driving circuit. In an exemplary embodiment, the pixel driving circuit further includes a power connection electrode, which is connected to the power connection line 44.

[0125] In an exemplary embodiment, the first power line 71 may be provided in some circuit units. For example, the first power line 71 may be provided in the circuit units of the Nth unit column, the N+1th unit column, the N+3th unit column, and the N+4th unit column, and the first power line 71 is not provided in the circuit units of the N+2th unit column and the N+5th unit column.

[0126] In an exemplary embodiment, in at least one circuit unit and the adjacent circuit unit in the first direction X, the first power lines 71 in the two circuit units are interconnected as an integrated structure. For example, the first power line 71 in the Nth unit column and the first power line 71 in the N+1th unit column can be interconnected as an integrated structure, so that the first power lines 71 in the two unit columns are an integrated whole-surface structure. For another example, the first power line 71 in the N+3th unit column and the first power line 71 in the N+4th unit column can be interconnected as an integrated structure, so that the first power lines 71 in the two unit columns are an integrated whole-surface structure.

[0127] In an exemplary embodiment, in at least one circuit unit and an adjacent circuit unit in the first direction X, the data signal line 61 in one circuit unit may be arranged on the side of the first power line 71 in the circuit unit in the opposite direction of the first direction X, and the data signal line 61 in another circuit unit may be arranged on the side of the first power line 71 in the circuit unit in the first direction X. For example, in the Nth unit column, the data signal line 61 may be located on the side of the first power line 71 in the opposite direction of the first direction X, and in the N+1th unit column, the data signal line 61 may be located on the side of the first power line 71 in the first direction X. Since the first power lines 71 in the Nth unit column and the N+1th unit column are an integrated structure connected to each other, the two data signal lines 61 in the two adjacent unit columns are respectively located on both sides of the first power line 71 of the integrated structure. For another example, in the N+3th unit column, the data signal line 61 may be located on the side of the first power line 71 in the opposite direction of the first direction X, and in the N+4th unit column, the data signal line 61 may be located on the side of the first power line 71 in the first direction X. Since the first power lines 71 in the N+3th unit column and the N+4th unit column are interconnected in an integrated structure, the two data signal lines 61 in two adjacent unit columns are respectively located on both sides of the first power line 71 of the integrated structure.

[0128] In an exemplary embodiment, in at least one circuit unit and an adjacent circuit unit in the first direction X, the positions of the data signal lines 61 in the two circuit units may be symmetrical with respect to a column center line, and the column center line may be a straight line located between adjacent circuit units in the first direction X and extending along the second direction Y.

[0129] In an exemplary embodiment, at least one pixel driving circuit may include at least a fourth transistor and a data connection electrode, the fourth transistor may include at least a fourth active layer, the data signal line 61 is connected to the data connection electrode through the data via K2, and the data connection electrode is connected to the first region of the fourth active layer.

[0130] In an exemplary embodiment, in at least one circuit unit and an adjacent circuit unit in the first direction X, the data signal line 61 in one circuit unit is connected to the data connection electrode in the circuit unit through the data via K2, and the data connection electrode is connected to the first region of the fourth active layer in the circuit unit through the via; the data signal line 61 in another circuit unit is connected to the data connection electrode in the circuit unit through the data via K2, and the data connection electrode is connected to the first region of the fourth active layer in the circuit unit through the data connection line. The data connection electrode is connected to the first end of the data connection line, and the second end of the data connection line is connected to the first region of the fourth active layer through the via after extending along the first direction X, so that the two data signal lines 61 in the two adjacent circuit units are respectively located on both sides of the first power line 71.

[0131] In an exemplary embodiment, at least one pixel driving circuit may further include a sixth transistor, a seventh transistor, a fourth node electrode and an anode connecting electrode, the sixth transistor may include at least a sixth active layer, the seventh transistor may include at least a seventh active layer, the anode in at least one light-emitting unit is connected to the anode connecting electrode through the anode via K3, the anode connecting electrode is connected to the fourth node electrode, and the fourth node electrode is connected to the second region of the sixth active layer and the second region of the seventh active layer through a via.

[0132] In an exemplary embodiment, in at least one circuit unit and an adjacent circuit unit in the first direction X, the anode connection electrode in one circuit unit is connected to the fourth node electrode in the circuit unit through a via hole, and the fourth node electrode is connected to the second area of ​​the sixth active layer and the second area of ​​the seventh active layer through a via hole, and the anode connection electrode in another circuit unit is connected to the fourth node electrode in the circuit unit through an anode connection line 63, and the fourth node electrode is connected to the second area of ​​the sixth active layer and the second area of ​​the seventh active layer through a via hole. The shape of the anode connection line 63 can be a straight line or a fold line extending along the second direction Y, and the anode connection electrode is connected to the first end of the anode connection line 63, and the second end of the anode connection line 63 is connected to the fourth node electrode through a via hole after extending along the second direction Y. In an exemplary embodiment, the anode connection line 63 is configured to improve the flatness of the anode.

[0133] In an exemplary embodiment, at least one circuit unit may further include an initial connection line 73, the shape of which may be a straight line or a broken line extending along the second direction Y, and the initial connection line 73 is connected to the first initial signal line 41, the second initial signal line 42 and / or the third initial signal line 43, so that the initial connection line 73 and the initial signal line form a mesh-like interconnected structure for transmitting the initial signal on the display substrate.

[0134] In an exemplary embodiment, at least one circuit unit may further include a second power line 72, and the shape of the second power line 72 may be a straight line or a broken line extending along the second direction Y. The second power line 72 is configured to provide a second power signal to the cathode in the light-emitting unit to realize the VSS in pixel structure.

[0135] In an exemplary embodiment, the plurality of light-emitting units may include a first light-emitting unit emitting a first color light, a second light-emitting unit emitting a second color light, and a third light-emitting unit emitting a third color light, the first light-emitting unit may include at least a first anode 90A and a first pixel opening 100A exposing the first anode 90A, the second light-emitting unit may include at least a second anode 90B and a second pixel opening 100B exposing the second anode 90B, the third light-emitting unit may include at least a third anode 90C and a third pixel opening 100C exposing the third anode 90C, the first anode 90A, the second anode 90B, and the third anode 90C may be disposed in an anode conductive layer, and the first pixel opening 100A, the second pixel opening 100B, and the third pixel opening 100C may be disposed in a pixel definition layer.

[0136] In an exemplary embodiment, the second anode 90B can be disposed on one side of the first anode 90A in the second direction Y, and the third anode 90C can be disposed on one side of the first direction X of the first anode 90A and the second anode 90B, that is, the second pixel opening 100B is disposed on one side of the first pixel opening 100A in the second direction Y, and the third pixel opening 100C is disposed on one side of the first direction X of the first pixel opening 100A and the second pixel opening 100B.

[0137] In an exemplary embodiment, the orthographic projection of any one or more of the first pixel opening 100A, the second pixel opening 100B, and the third pixel opening 100C on the substrate does not overlap with the orthographic projection of the power via K1 on the substrate.

[0138] In an exemplary embodiment, the orthographic projections of the first pixel opening 100A and the second pixel opening 100B on the substrate at least partially overlap with the orthographic projection of the first power line 71 on the substrate, and the orthographic projection of the third pixel opening 100C on the substrate does not overlap with the orthographic projection of the first power line 71 on the substrate.

[0139] In an exemplary embodiment, the orthographic projections of the first pixel opening 100A and the second pixel opening 100B on the substrate do not overlap with the orthographic projection of the second power line 72 on the substrate, and the orthographic projection of the third pixel opening 100C on the substrate at least partially overlaps with the orthographic projection of the second power line 72 on the substrate.

[0140] In an exemplary embodiment, the orthographic projections of the first pixel opening 100A and the second pixel opening 100B on the substrate do not overlap with the orthographic projection of the data signal line 61 on the substrate, and the orthographic projection of the third pixel opening 100C on the substrate at least partially overlaps with the orthographic projection of the data signal line 61 on the substrate.

[0141] In an exemplary embodiment, the orthographic projections of the first pixel opening 100A and the second pixel opening 100B on the substrate do not overlap with the orthographic projection of the initial connection line 63 on the substrate, and the orthographic projection of the third pixel opening 100C on the substrate at least partially overlaps with the orthographic projection of the initial connection line 63 on the substrate.

[0142] In an exemplary embodiment, the orthographic projections of the first pixel opening 100A and the second pixel opening 100B on the substrate are located within the range of the orthographic projection of the first power line 71 on the substrate.

[0143] In an exemplary embodiment, the third pixel opening 100C may have an opening center line, which is an imaginary line, and is a straight line extending along the second direction Y and passing through the geometric center of the third pixel opening 100C. In at least one third pixel opening 100C, the data signal line 61 and the anode connection line 63 may be symmetrically arranged with respect to the opening center line, and the second power supply line 72 and the initial connection line 73 may be symmetrically arranged with respect to the opening center line.

[0144] In an exemplary embodiment, any one or more of the first pixel opening 100A, the second pixel opening 100B and the third pixel opening 100C have their orthographic projections on the substrate not overlapping with the orthographic projections of the data via K2 on the substrate, and their orthographic projections on the substrate do not overlap with the orthographic projections of the anode via K3 on the substrate.

[0145] In an exemplary embodiment, in the second direction Y, the first pixel opening 100A, the second pixel opening 100B, and the third pixel opening 100C may be disposed at a region of the corresponding circuit unit close to a next unit row.

[0146] In an exemplary embodiment, the orthographic projection of the first pixel opening 100A on the substrate at least partially overlaps with the orthographic projection of the power connection line 44 on the substrate, and the orthographic projection of the first pixel opening 100A on the substrate does not overlap with the orthographic projection of the first initial signal line 41 on the substrate.

[0147] In an exemplary embodiment, the orthographic projection of the second pixel opening 100B on the substrate at least partially overlaps with the orthographic projections of the first initial signal line 41, the second initial signal line 42, and the second initial signal line 43 on the substrate, and the orthographic projection of the second pixel opening 100B on the substrate does not overlap with the orthographic projections of the first scanning signal line 31 and the power connection line 44 on the substrate.

[0148] In an exemplary embodiment, the orthographic projection of the third pixel opening 100C on the substrate at least partially overlaps with the orthographic projections of the second scanning signal line 32, the light emitting signal line 34, the second initial signal line 42 and the power connection line 44 on the substrate, and the orthographic projection of the third pixel opening 100C on the substrate does not overlap with the orthographic projections of the first scanning signal line 31 and the third scanning signal line 33 on the substrate.

[0149] In an exemplary embodiment, on a plane perpendicular to the display substrate, the driving structure layer may include at least: a shielding layer disposed on the substrate, a first insulating layer disposed on the shielding layer away from the substrate, a semiconductor layer disposed on the first insulating layer away from the substrate, a second insulating layer disposed on the semiconductor layer away from the substrate, a first conductive layer disposed on the second conductive layer away from the substrate, a third insulating layer disposed on the first conductive layer away from the substrate, a second conductive layer disposed on the third insulating layer away from the substrate, a fourth insulating layer disposed on the second conductive layer away from the substrate, a third conductive layer disposed on the fourth insulating layer away from the substrate, a first flat layer disposed on the third conductive layer away from the substrate, a fourth conductive layer disposed on the first flat layer away from the substrate, and a second flat layer disposed on the fourth conductive layer away from the substrate. The light emitting structure layer may include at least: an anode conductive layer disposed on the second flat layer away from the substrate, a pixel definition layer disposed on the anode conductive layer away from the substrate, an organic light emitting layer disposed on the pixel definition layer away from the substrate, and a cathode layer disposed on the organic light emitting layer away from the substrate.

[0150] In an exemplary embodiment, the blocking layer may include at least a blocking electrode, the semiconductor layer may include at least an active layer of multiple transistors and a first initial signal line, the first conductive layer may include at least a second scanning signal line, a light emitting signal line and a first plate of a storage capacitor, the second conductive layer may include at least a shielding electrode and a second plate of a storage capacitor, the third conductive layer may include at least a first scanning signal line, a third scanning signal line, a second initial signal line, a third initial signal line, a power connection line and a plurality of connection electrodes, and the fourth conductive layer may include at least a data signal line, a first power line, a second power line and an initial connection line.

[0151] The following is an exemplary explanation through the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes deposition of film layers, coating of photoresist on the film layers, mask exposure, development, etching, stripping of photoresist and other processes for metal materials, inorganic materials or transparent conductive materials, and includes coating of organic materials, mask exposure and development and other processes for organic materials. Deposition can be any one or more of sputtering, evaporation, chemical vapor deposition, coating can be any one or more of spraying, spin coating and inkjet printing, and etching can be any one or more of dry etching and wet etching, which are not limited in the present disclosure. "Thin film" refers to a layer of thin film made of a certain material on a substrate by deposition, coating or other processes. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged in the same layer" in the present disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0152] In an exemplary embodiment, taking 12 circuit units (the Mth unit row and the M+1th unit row, and the Nth unit column to the N+5th unit column) as an example, the preparation process of the display substrate of this embodiment may include the following operations.

[0153] (11) Forming a shielding layer pattern. In an exemplary embodiment, forming a shielding layer pattern may include: depositing a shielding film on a substrate, patterning the shielding film through a patterning process, and forming a shielding layer pattern on the substrate, such as Figure 6 In an exemplary embodiment, the shielding layer may be referred to as a bottom metal (LS) layer.

[0154] In an exemplary embodiment, the shielding layer pattern of each circuit unit may include at least a shielding electrode 90 , a first shielding connection bar 91 , a second shielding connection bar 92 , a third shielding connection bar 93 , a first shielding block 94 , and a second shielding block 95 .

[0155] In an exemplary embodiment, the shielding electrode 90 may be rectangular in shape, corners of the rectangle may be chamfered or grooved, and the shielding electrode 90 may be disposed in a middle region of the circuit unit in the first direction X and the second direction Y.

[0156] In an exemplary embodiment, the shape of the first shielding connection strip 91 can be a straight line or a broken line with the main part extending along the first direction X. The first shielding connection strip 91 can be arranged on one side of the shielding electrode 90 in the first direction X or on the side of the shielding electrode 90 in the opposite direction of the first direction X. The first end of the first shielding connection strip 91 is connected to the shielding electrode 90 of the current circuit unit, and the second end of the first shielding connection strip 91 is connected to the shielding electrode 90 of the adjacent circuit unit in the first direction X.

[0157] In an exemplary embodiment, in at least one cell row, the shielding electrode 90 and the first shielding connection bar 91 may be an integrated structure connected to each other.

[0158] In an exemplary embodiment, the shape of the second shielding connection strip 92 can be a straight line or a broken line with the main part extending along the second direction Y. The second shielding connection strip 92 can be arranged on one side of the shielding electrode 90 in the second direction Y. The first end of the second shielding connection strip 92 is connected to the shielding electrode 90 of the circuit unit, and the second end of the second shielding connection strip 92 is connected to the second shielding block 95 of the adjacent circuit unit in the second direction Y.

[0159] In an exemplary embodiment, the shape of the third shielding connection strip 93 can be a straight line or a broken line with the main part extending along the second direction Y. The third shielding connection strip 93 can be arranged on the side of the shielding electrode 90 in the opposite direction of the second direction Y. The first end of the third shielding connection strip 93 is connected to the shielding electrode 90, and the second end of the third shielding connection strip 93 is connected to the first shielding block 94.

[0160] In an exemplary embodiment, the first blocking block 94 can be block-shaped (such as rectangular) and can be arranged on the side opposite to the second direction Y of the blocking electrode 90. The first end of the first blocking block 94 is connected to the third blocking connecting strip 93, and the second end of the first blocking block 94 is connected to the second blocking block 95.

[0161] In an exemplary embodiment, the second blocking block 95 can be in a block shape (such as a rectangle) and can be arranged on a side of the second blocking block 95 away from the blocking electrode 90. The first end of the second blocking block 95 is connected to the first blocking block 94, and the second end of the second blocking block 95 is connected to the second blocking connecting strip 92 of the adjacent circuit unit in the opposite direction of the second direction Y.

[0162] In an exemplary embodiment, in at least one unit column, the second shielding block 95, the first shielding block 94, the third shielding connection bar 93, the shielding electrode 90 and the second shielding connection bar 92 are sequentially connected to form an interconnected integral structure.

[0163] In an exemplary embodiment, the shielding layers in multiple unit rows and multiple unit columns can be an integrated structure that is interconnected, which can ensure that the shielding layers in the display substrate have the same electric potential, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.

[0164] In an exemplary embodiment, the position and shape of the shielding layer in a plurality of cell rows may be substantially the same, and the position and shape of the shielding layer in a plurality of cell columns may be substantially the same.

[0165] (12) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: depositing a first insulating film and a semiconductor film in sequence on a substrate having the aforementioned pattern, patterning the semiconductor film through a patterning process to form a first insulating layer covering the shielding layer, and a semiconductor layer pattern disposed on the first insulating layer, such as Fig. 7A and Figure 7B As shown, Figure 7B for Fig. 7A Schematic diagram of the semiconductor layer in the figure.

[0166] In an exemplary embodiment, the semiconductor layer pattern of each circuit unit may include at least the first active layer 11 of the first transistor T1 to the eighth active layer 18 of the eighth transistor T8, and the first initial signal line 41, and the first active layer 11 to the seventh active layer 17 and the first initial signal line 41 are an integrated structure connected to each other, and the eighth active layer 18 may be provided separately.

[0167] In an exemplary embodiment, in the first direction X, the second active layer 12, the sixth active layer 16, and the seventh active layer 17 may be located on a side of the third active layer 13 in the opposite direction of the first direction X, and the fourth active layer 14 and the eighth active layer 18 may be located on a side of the third active layer 13 in the first direction X. In the second direction Y, the first active layer 11, the second active layer 12, the fourth active layer 14, and the first initial signal line 41 may be located on a side of the third active layer 13 in the opposite direction of the second direction Y, and the fifth active layer 15, the sixth active layer 16, the seventh active layer 17, and the eighth active layer 18 may be located on a side of the third active layer 13 in the second direction Y.

[0168] In an exemplary embodiment, the shape of the third active layer 13 may be an "Ω" shape, the shape of the first active layer 11, the fourth active layer 14, the sixth active layer 16, the seventh active layer 17 and the eighth active layer 18 may be an "I" shape, the shape of the second active layer 12 and the fifth active layer 15 may be an "L" shape, and the shape of the first initial signal line 41 may be a straight line or a broken line with the main portion extending along the first direction X.

[0169] In an exemplary embodiment, the first to eighth active layers 11 to 18 may each include a first region, a second region, and a channel region between the first and second regions. In an exemplary embodiment, the second region 11-2 of the first active layer and the first region 12-1 of the second active layer may be connected to each other, and the second region 11-2 of the first active layer may serve as the first region 12-1 of the second active layer. The first region 13-1 of the third active layer, the second region 14-2 of the fourth active layer, and the second region 15-2 of the fifth active layer may be connected to each other, and the first region 13-1 of the third active layer may serve as the second region 14-2 of the fourth active layer and the second region 15-2 of the fifth active layer at the same time. The second region 12-1 of the second active layer, the second region 13-2 of the third active layer, and the first region 16-1 of the sixth active layer may be connected to each other, and the second region 12-1 of the second active layer may serve as the second region 13-2 of the third active layer and the first region 16-1 of the sixth active layer at the same time. The second area 16-2 of the sixth active layer and the second area 17-2 of the seventh active layer may be connected to each other, and the second area 16-2 of the sixth active layer may serve as the second area 17-2 of the seventh active layer. The first area 11-1 of the first active layer and the first initial signal line 41 may be connected to each other, and the first area 14-1 of the fourth active layer, the first area 15-1 of the fifth active layer, the first area 17-1 of the seventh active layer, the first area 18-1 of the eighth active layer, and the second area 18-2 of the eighth active layer may be separately provided.

[0170] In an exemplary embodiment, the shape of the first initial signal line 41 can be a zigzag shape or a zigzag shape with the main part extending along the first direction X, and can be located on the side of the first active layer 11 away from the third active layer 13, and the first initial signal line 41 is connected to the first region 11-1 of the first active layer of multiple circuit units in a unit row.

[0171] In an exemplary embodiment, the first initial signal line 41 and the first active layer of the plurality of circuit units in one unit row may be an integral structure with each other. Since the first region of the first active layer and the first initial signal line 41 are an integral structure connected to each other, not only can the reliable connection between the first initial signal line and the first electrode of the first transistor be improved, but also the number of vias can be reduced, and the occupied space of the pixel driving circuit can be reduced, which is conducive to achieving high resolution (PPI) display.

[0172] In an exemplary embodiment, in at least one circuit unit, a first initial connection block may be provided on the first initial signal line, and the first initial connection block is configured to be connected to an initial connection line formed subsequently, so that the first initial signal line extending along the first direction and the initial connection line extending along the second direction form a meshed connection structure for transmitting the first initial signal, and the present disclosure is not limited thereto.

[0173] In an exemplary embodiment, the orthographic projection of the third active layer 13 on the substrate at least partially overlaps with the orthographic projection of the shielding electrode 90 on the substrate, and the shielding electrode 90 can serve as a shielding layer of the third transistor T3 to shield the channel region of the third transistor T3 and ensure the electrical performance of the third transistor T3.

[0174] In an exemplary embodiment, an orthographic projection of the channel region of the third active layer 13 on the substrate is located within a range of an orthographic projection of the shielding electrode 90 on the substrate.

[0175] In an exemplary embodiment, the orthographic projection of the second active layer 12 on the substrate at least partially overlaps with the orthographic projection of the first blocking block 94 on the substrate, and the first blocking block 94 can serve as a blocking layer for the second transistor T2 to block the channel region of the second transistor T2 and ensure the electrical performance of the second transistor T2.

[0176] In an exemplary embodiment, the orthographic projection of the channel region of the second active layer 12 on the substrate is located within the range of the orthographic projection of the first blocking block 94 on the substrate.

[0177] In an exemplary embodiment, the orthographic projection of the first active layer 11 on the substrate at least partially overlaps with the orthographic projection of the second blocking block 95 on the substrate, and the second blocking block 95 can serve as a blocking layer of the first transistor T1 to block the channel region of the first transistor T1 and ensure the electrical performance of the first transistor T1.

[0178] In an exemplary embodiment, an orthographic projection of the channel region of the first active layer 11 on the substrate is located within a range of an orthographic projection of the second blocking block 95 on the substrate.

[0179] In example embodiments, positions and shapes of semiconductor layers in a plurality of cell rows may be substantially the same, and positions and shapes of semiconductor layers in a plurality of cell columns may be substantially the same.

[0180] In an exemplary embodiment, the semiconductor layer may be made of polycrystalline silicon (p-Si), that is, the third transistor to the seventh transistor are LTPS transistors. In an exemplary embodiment, patterning the semiconductor film by a patterning process may include: first forming an amorphous silicon (a-si) film on the first insulating film, dehydrogenating the amorphous silicon film, and crystallizing the amorphous silicon film after the dehydrogenation to form a polycrystalline silicon film. Subsequently, the polycrystalline silicon film is patterned to form a semiconductor layer pattern.

[0181] (13) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: depositing a second insulating film and a first conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the first conductive film through a patterning process to form a second insulating layer covering the semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer, such as Fig. 8A and Figure 8B As shown, Figure 8B for Fig. 8A In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0182] In an exemplary embodiment, the first conductive layer pattern of each circuit unit includes at least a first gate electrode 21 , a second gate electrode 22 , a fourth gate electrode 24 , a second scan signal line 32 , a light emitting signal line 34 and a first plate 81 of a storage capacitor.

[0183] In an exemplary embodiment, the shape of the first electrode plate 81 may be rectangular, and the corners of the rectangle may be provided with chamfers or grooves, and the orthographic projection of the first electrode plate 81 on the substrate at least partially overlaps with the orthographic projection of the third active layer of the third transistor T3 on the substrate. In an exemplary embodiment, the first electrode plate 81 may simultaneously serve as a plate of the storage capacitor and a gate electrode of the third transistor T3.

[0184] In an exemplary embodiment, the orthographic projection of the channel region of the third active layer on the substrate is located within the range of the orthographic projection of the first electrode plate 81 on the substrate.

[0185] In an exemplary embodiment, an orthographic projection of the first electrode plate 81 on the substrate at least partially overlaps an orthographic projection of the shielding electrode 90 on the substrate.

[0186] In an exemplary embodiment, the first gate electrode 21 may be in a "C" shape and may be located on one side of the first electrode plate 81 in the opposite direction of the second direction Y. The positive projection of the first gate electrode 21 on the substrate at least partially overlaps with the positive projection of the first active layer on the substrate, and the overlapping region of the first gate electrode 21 and the first active layer may serve as the gate electrode of the first transistor T1 of the dual-gate structure. In an exemplary embodiment, the first gate electrode 21 is configured to be connected to a third scanning signal line formed subsequently.

[0187] In an exemplary embodiment, the second gate electrode 22 may be in an "L" shape and may be located between the first electrode plate 81 and the first gate electrode 21. The orthographic projection of the second gate electrode 22 on the substrate at least partially overlaps with the orthographic projection of the second active layer on the substrate, and the overlapping region of the second gate electrode 22 and the second active layer may serve as the gate electrode of the second transistor T2 of the dual-gate structure. In an exemplary embodiment, the second gate electrode 22 is configured to be connected to a first scan signal line formed subsequently.

[0188] In an exemplary embodiment, the fourth gate electrode 24 may be in the shape of a strip extending along the first direction X, and may be located between the first electrode plate 81 and the first gate electrode 21. The orthographic projection of the fourth gate electrode 24 on the substrate at least partially overlaps with the orthographic projection of the fourth active layer on the substrate, and the region where the fourth gate electrode 24 overlaps with the fourth active layer may serve as the gate electrode of the fourth transistor T4. In an exemplary embodiment, the second gate electrode 22 is configured to be connected to a first scan signal line formed subsequently.

[0189] In an exemplary embodiment, the fourth gate electrode 24 in the present circuit unit and the second gate electrode 22 in the adjacent circuit unit in the first direction X may be an integrated structure connected to each other. For example, in a cell row, the fourth gate electrode 24 in the Nth cell column and the second gate electrode 22 in the N+1th cell column may be an integrated structure connected to each other.

[0190] In an exemplary embodiment, the shape of the second scan signal line 32 can be a straight line or a broken line with the main part extending along the first direction X. The second scan signal line 32 can be located on one side of the first electrode 81 in the second direction Y. The area where the second scan signal line 32 overlaps with the seventh active layer can be used as the gate electrode of the seventh transistor T7, and the area where the second scan signal line 32 overlaps with the eighth active layer can be used as the gate electrode of the eighth transistor T8.

[0191] In an exemplary embodiment, a second scan connection block 32-1 may be provided on the second scan signal line 32. The shape of the second scan connection block 32-1 may be a block shape (such as a rectangle), a first end of the second scan connection block 32-1 is connected to a side of the second scan signal line 32 close to the first electrode plate 81, a second end of the second scan connection block 32-1 extends toward the direction of the first electrode plate 81, and the second scan connection block 32-1 is configured to be connected to a subsequently formed auxiliary scan signal line.

[0192] In an exemplary embodiment, the shape of the light-emitting signal line 34 can be a straight line or a broken line with the main part extending along the first direction X. The light-emitting signal line 34 can be located between the first electrode 81 and the second scanning signal line 32. The area where the light-emitting signal line 34 overlaps with the fifth active layer can be used as the gate electrode of the fifth transistor T5, and the area where the light-emitting signal line 34 overlaps with the sixth active layer can be used as the gate electrode of the sixth transistor T6.

[0193] In example embodiments, positions and shapes of the first conductive layers in a plurality of cell rows may be substantially the same, and positions and shapes of the first conductive layers in a plurality of cell columns may be substantially the same.

[0194] In an exemplary embodiment, after forming the first conductive layer pattern, the first conductive layer can be used as a shield to perform conductorization on the semiconductor layer. The semiconductor layer in the area shielded by the first conductive layer forms the channel region of the first transistor T1 to the eighth transistor T8, and the semiconductor layer in the area not shielded by the first conductive layer is conductorized, that is, the first initial signal line 41 and the first and second areas of the first transistor T1 to the eighth transistor T8 are all conductorized.

[0195] (14) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: depositing a third insulating film and a second conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the second conductive film using a patterning process to form a third insulating layer covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer, such as Fig.9A and Fig. 9B As shown, Fig. 9B for Fig.9A In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0196] In an exemplary embodiment, the second conductive layer pattern of each circuit unit includes at least: a second plate 82 of the storage capacitor and a shielding electrode 35 .

[0197] In an exemplary embodiment, the outline of the second plate 82 of the storage capacitor can be rectangular, and the corners of the rectangle can be provided with chamfers or grooves. The orthographic projection of the second plate 82 on the substrate at least partially overlaps with the orthographic projection of the first plate 81 on the substrate. The second plate 82 can serve as another plate of the storage capacitor, and the first plate 81 and the second plate 82 constitute the storage capacitor of the pixel driving circuit.

[0198] In an exemplary embodiment, the second electrode plate 82 may be provided with a board-level connecting bar 83. The board-level connecting bar 83 may be in the shape of a straight line or a broken line extending along the first direction X. The board-level connecting bar 83 may be provided on one side of the second electrode plate 82 in the first direction X or on the side opposite to the first direction X. The first end of the board-level connecting bar 83 is connected to the second electrode plate 82 in the circuit unit, and the second end of the board-level connecting bar 83 is connected to the second electrode plate 82 in the adjacent circuit unit in the first direction X. Since the second electrode plate 82 in each circuit unit is connected to the first power line formed subsequently, by connecting the second electrode plates 82 of adjacent circuit units to each other, the second electrode plate 82 and the board-level connecting bar 83 may be reused as a power signal line, which may ensure that a plurality of second electrode plates in a unit row have the same potential, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.

[0199] In an exemplary embodiment, the second electrode plates 82 and the board-level connecting bars 83 in a plurality of circuit cells in one cell row may be an integral structure connected to each other.

[0200] In an exemplary embodiment, an opening 84 is provided on the second electrode plate 82. The opening 84 may be rectangular and may be located in the middle region of the second electrode plate 82, so that the second electrode plate 82 forms a ring structure. The opening 84 exposes the third insulating layer covering the first electrode plate 81, and the orthographic projection of the first electrode plate 81 on the substrate includes the orthographic projection of the opening 84 on the substrate. In an exemplary embodiment, the opening 84 is configured to accommodate a ninth via hole formed subsequently, and the ninth via hole is located in the opening 84 and exposes the first electrode plate 81, so that the first connecting electrode formed subsequently is connected to the first electrode plate 81.

[0201] In an exemplary embodiment, the shielding electrode 35 may be in an inverted "U" shape and may be located on a side of the second electrode plate 82 close to the second transistor T2, and the orthographic projection of the shielding electrode 35 on the substrate at least partially overlaps with the orthographic projection of the second active layer (the node between the two gate electrodes) between the two gate electrodes of the second transistor T2 on the substrate. In an exemplary embodiment, the shielding electrode 35 is configured to shield the influence of the data voltage jump on the first transistor T1 and the second transistor T2, so as to prevent the data voltage jump from affecting the normal operation of the pixel driving circuit and improve the display effect.

[0202] In an exemplary embodiment, the shielding electrode 35 may be provided in each circuit unit. The shielding electrode 35 in the shape of an inverted "U" may include a first extension section 35-1, a second extension section 35-2, and a third extension section 35-3 connected in sequence. The first end of the first extension section 35-1 is connected to the second electrode plate 82, and the second end of the first extension section 35-1 is connected to the first end of the second extension section 35-2 after extending along the second direction Y in a direction away from the second electrode plate 82, and the positive projection of the first extension section 35-1 on the substrate overlaps at least partially with the positive projection of the first active layer on the substrate. The second end of the second extension section 35-2 is extended along the first direction X in a direction close to the second transistor T2, and is connected to the first end of the third extension section 35-3, and the second extension section 35-2 is configured to overlap with the data connection line formed subsequently to prevent the data voltage jump from affecting the first transistor T1. The second end of the third extension segment 35-3 extends along the second direction Y toward the direction close to the second electrode 82, and the orthographic projection of the third extension segment 35-3 on the substrate at least partially overlaps with the orthographic projection of the semiconductor layer between the two gate electrodes of the second transistor T2 on the substrate, and the third extension segment 35-3 is configured to shield the influence of the data voltage jump on the second transistor T2.

[0203] In an exemplary embodiment, in at least one circuit unit, the shielding electrode 35 and the second electrode plate 82 may be an integral structure connected to each other. Since the second electrode plate 82 is connected to a first power line formed later, the shielding electrode 35 has the potential of the first power line.

[0204] In an exemplary embodiment, positions and shapes of the second conductive layers in a plurality of cell rows may be substantially the same, and positions and shapes of the second conductive layers in a plurality of cell columns may be substantially the same.

[0205] (15) Forming a fourth insulating layer pattern. In an exemplary embodiment, forming the fourth insulating layer pattern may include: depositing a fourth insulating film on the substrate on which the aforementioned pattern is formed, patterning the fourth insulating film using a patterning process to form a fourth insulating layer covering the second conductive layer, wherein a plurality of via holes are disposed on the fourth insulating layer, such as Fig.10 shown.

[0206] In an exemplary embodiment, the multiple vias of each circuit unit include at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11 and a twelfth via V12.

[0207] In an exemplary embodiment, the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the second area of ​​the first active layer (also the first area of ​​the second active layer) on the substrate, the fourth insulating layer, the third insulating layer, and the second insulating layer in the first via hole V1 are etched away to expose the surface of the second area of ​​the first active layer (also the first area of ​​the second active layer), and the first via hole V1 is configured to connect a subsequently formed first connecting electrode to the second area of ​​the first active layer (also the first area of ​​the second active layer) through the via hole.

[0208] In an exemplary embodiment, the orthographic projection of the second via hole V2 on the substrate is located within the range of the orthographic projection of the first area of ​​the third active layer (also the second area of ​​the fourth active layer and the second area of ​​the fifth active layer) on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the second via hole V2 are etched away to expose the surface of the first area of ​​the third active layer (also the second area of ​​the fourth active layer and the second area of ​​the fifth active layer), and the second via hole V2 is configured to connect a subsequently formed second connecting electrode to the first area of ​​the third active layer (also the second area of ​​the fourth active layer and the second area of ​​the fifth active layer) through the via hole.

[0209] In an exemplary embodiment, the orthographic projection of the third via hole V3 on the substrate is located within the range of the orthographic projection of the first area of ​​the fourth active layer on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the third via hole V3 are etched away to expose the surface of the first area of ​​the fourth active layer, and the third via hole V3 is configured to connect a subsequently formed third connecting electrode to the first area of ​​the fourth active layer through the via hole.

[0210] In an exemplary embodiment, the orthographic projection of the fourth via hole V4 on the substrate is located within the range of the orthographic projection of the first area of ​​the fifth active layer on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the fourth via hole V4 are etched away to expose the surface of the first area of ​​the fifth active layer, and the fourth via hole V4 is configured to connect a subsequently formed fourth connecting electrode to the first area of ​​the fifth active layer through the via hole.

[0211] In an exemplary embodiment, the orthographic projection of the fifth via hole V5 on the substrate is located within the range of the orthographic projection of the second area of ​​the sixth active layer (also the second area of ​​the seventh active layer) on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the fifth via hole V5 are etched away to expose the surface of the second area of ​​the sixth active layer (also the second area of ​​the seventh active layer), and the fifth via hole V5 is configured to connect a subsequently formed fifth connecting electrode to the second area of ​​the sixth active layer (also the second area of ​​the seventh active layer) through the via hole.

[0212] In an exemplary embodiment, the orthographic projection of the sixth via hole V6 on the substrate is located within the range of the orthographic projection of the first region of the seventh active layer on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the sixth via hole V6 are etched away to expose the surface of the first region of the seventh active layer, and the sixth via hole V6 is configured to connect a subsequently formed second initial signal line to the first region of the seventh active layer through the via hole.

[0213] In an exemplary embodiment, the orthographic projection of the seventh via hole V7 on the substrate is located within the range of the orthographic projection of the first region of the eighth active layer on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the seventh via hole V7 are etched away to expose the surface of the first region of the eighth active layer, and the seventh via hole V7 is configured to connect a subsequently formed third initial signal line to the first region of the eighth active layer through the via hole.

[0214] In an exemplary embodiment, the orthographic projection of the eighth via hole V8 on the substrate is located within the range of the orthographic projection of the second region of the eighth active layer on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the eighth via hole V8 are etched away to expose the surface of the second region of the eighth active layer, and the eighth via hole V8 is configured to connect a subsequently formed second connecting electrode to the second region of the eighth active layer through the via hole.

[0215] In an exemplary embodiment, the orthographic projection of the ninth via hole V9 on the substrate is located within the range of the orthographic projection of the opening 84 on the substrate, the fourth insulating layer and the third insulating layer in the ninth via hole V9 are etched away to expose the surface of the first electrode plate 81, and the ninth via hole V9 is configured to connect a subsequently formed first connecting electrode to the first electrode plate 81 through the via hole.

[0216] In an exemplary embodiment, the orthographic projection of the tenth via hole V10 on the substrate is within the range of the orthographic projection of the second electrode plate 82 on the substrate, the fourth insulating layer in the tenth via hole V10 is etched away, exposing the surface of the second electrode plate 82, and the tenth via hole V10 is configured to allow a subsequently formed power connection line to be connected to the second electrode plate 82 through the via hole. In an exemplary embodiment, there may be a plurality of tenth via holes V10, and the plurality of tenth via holes V10 may be sequentially arranged along the first direction X to improve connection reliability.

[0217] In an exemplary embodiment, the orthographic projection of the eleventh via hole V11 on the substrate is located within the range of the orthographic projection of the first gate electrode 21 on the substrate, the fourth insulating layer and the third insulating layer in the eleventh via hole V11 are etched away to expose the surface of the first gate electrode 21, and the eleventh via hole V11 is configured to connect a subsequently formed third scanning signal line to the first gate electrode 21 through the via hole.

[0218] In an exemplary embodiment, the orthographic projection of the twelfth via hole V12 on the substrate is located within the range of the orthographic projection of the second gate electrode 22 (also the fourth gate electrode 24) on the substrate, the fourth insulating layer and the third insulating layer in the twelfth via hole V12 are etched away to expose the surface of the second gate electrode 22 (also the fourth gate electrode 24), and the twelfth via hole V12 is configured to connect a subsequently formed first scanning signal line to the second gate electrode 22 (also the fourth gate electrode 24) through the via hole.

[0219] In an exemplary embodiment, the fourth insulating layer of at least one circuit unit may further include a thirteenth via hole V13 .

[0220] In an exemplary embodiment, the orthographic projection of the thirteenth via hole V13 on the substrate is located within the range of the orthographic projection of the second scan connection block 32-1 of the second scan signal line 32 on the substrate, the fourth insulating layer and the third insulating layer in the thirteenth via hole V13 are etched away to expose the surface of the second scan connection block 32-1, and the thirteenth via hole V13 is configured to connect a subsequently formed auxiliary scan signal line to the second scan connection block 32-1 through the via hole.

[0221] In an exemplary embodiment, positions and shapes of the plurality of via holes in the plurality of cell rows may be substantially the same, and positions and shapes of the plurality of via holes in the plurality of cell columns may be substantially the same.

[0222] (16) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer may include: depositing a third conductive film on the substrate having the aforementioned pattern, patterning the third conductive film using a patterning process, and forming a third conductive layer disposed on the fourth insulating layer, such as Fig.11A and Fig. 11B As shown, Fig. 11B for Fig.11A In an exemplary embodiment, the third conductive layer may be referred to as a first source-drain metal (SD1) layer.

[0223] In an exemplary embodiment, the third conductive layer of each circuit unit includes at least: a first scan signal line 31, a third scan signal line 33, a second initial signal line 42, a third initial signal line 43, a power connection line 44, an auxiliary scan signal line 45, a first connection electrode 51, a second connection electrode 52, a third connection electrode 53, a fourth connection electrode 54 and a fifth connection electrode 55.

[0224] In an exemplary embodiment, the shape of the first scanning signal line 31 can be a straight line or a broken line with the main part extending along the first direction X. The first scanning signal line 31 can be located on the side of the second electrode 82 in the opposite direction of the second direction Y. The first scanning signal line 31 is connected to the second gate electrode 22 (also the fourth gate electrode 24) in each circuit unit through the twelfth via V12 in each circuit unit, so that the first scanning signal line 31 writes the first scanning signal into the gate electrode of the second transistor T2 and the gate electrode of the fourth transistor T4 respectively.

[0225] In an exemplary embodiment, the shape of the third scan signal line 33 can be a straight line or a broken line with the main part extending along the first direction X. The first scan signal line 33 can be located on the side of the first scan signal line 31 away from the second electrode 82. The third scan signal line 33 is connected to the first gate electrode 21 in each circuit unit through the eleventh via V11 in each circuit unit, so that the third scan signal line 33 writes the third scan signal into the gate electrode of the first transistor T1.

[0226] In an exemplary embodiment, the shape of the second initial signal line 42 can be a straight line or a broken line with the main part extending along the first direction X. The second initial signal line 42 can be located on one side of the second electrode plate 82 in the second direction Y. The second initial signal line 42 is connected to the first area of ​​the seventh active layer in each circuit unit through the sixth via V6 in each circuit unit, so that the second initial signal line 42 writes the second initial signal into the first electrode of the seventh transistor T7.

[0227] In an exemplary embodiment, in at least one circuit unit, a second initial connection block may be provided on the second initial signal line, and the second initial connection block is configured to be connected to the subsequently formed initial connection line, so that the second initial signal line extending along the first direction and the initial connection line extending along the second direction form a meshed interconnected structure for transmitting the second initial signal, and the present disclosure is not limited thereto.

[0228] In an exemplary embodiment, the shape of the third initial signal line 43 can be a straight line or a broken line with the main part extending along the first direction X. The third initial signal line 43 can be located on the side of the second initial signal line 42 away from the second electrode plate 82. The third initial signal line 43 is connected to the first area of ​​the eighth active layer in each circuit unit through the seventh via V7 in each circuit unit, so that the third initial signal line 43 writes the third initial signal into the first electrode of the eighth transistor T7.

[0229] In an exemplary embodiment, in at least one circuit unit, a third initial connection block may be provided on the third initial signal line, and the third initial connection block is configured to be connected to the subsequently formed initial connection line, so that the third initial signal line extending along the first direction and the initial connection line extending along the second direction form a meshed connection structure for transmitting the third initial signal, and the present disclosure is not limited thereto.

[0230] In an exemplary embodiment, the power connection line 44 may be in the shape of a straight line or a folded line with the main part extending along the first direction X. The power connection line 44 may be located between the first scanning signal line 31 and the light emitting signal line 34. The positive projection of the power connection line 44 on the substrate overlaps at least partially with the positive projection of the second electrode plate 82 on the substrate. The power connection line 44 is connected to the second electrode plate 82 in each circuit unit through the tenth via hole V10 in each circuit unit. Since the power connection line 44 is configured to be connected to the first power line formed subsequently, the first power line writes the first power signal to the second electrode plate 82 of the storage capacitor.

[0231] In an exemplary embodiment, the power connection line 44 in a part of the circuit unit may be provided with a power connection block 44-1. The shape of the power connection block 44-1 may be a block shape (such as a rectangle), a first end of the power connection block 44-1 is connected to a side of the power connection line 44 close to the first scan signal line 31, and a second end of the power connection block 44-1 extends toward a direction close to the first scan signal line 31. In an exemplary embodiment, the power connection block 44-1 is configured to be connected to a first power line formed later.

[0232] In an exemplary embodiment, the power connection block 44 - 1 may be disposed in a plurality of circuit cells of the N+1th cell column and the N+4th cell column.

[0233] In an exemplary embodiment, the power connection line 44 and the power connection block 44 - 1 may be an integral structure connected to each other.

[0234] In an exemplary embodiment, the auxiliary scanning signal line 45 may be in the shape of a straight line or a folded line with a main portion extending along the first direction X. The positive projection of the auxiliary scanning signal line 45 on the substrate at least partially overlaps with the positive projection of the second scanning signal line 32 on the substrate. The auxiliary scanning signal line 45 is connected to the second scanning connection block 32-1 through the thirteenth via hole V13. Since the second scanning connection block 32-1 is connected to the second scanning signal line 32, the second scanning signal line 32 and the auxiliary scanning signal line 45 constitute a scanning signal line with a double-layer structure, which can effectively reduce the resistance of the scanning signal line and reduce the voltage drop of the scanning signal.

[0235] In an exemplary embodiment, the first connection electrode 51 may be in the shape of a strip extending along the second direction Y. The first end of the first connection electrode 51 is connected to the second region of the first active layer (also the first region of the second active layer) through the first via hole V1. The second end of the first connection electrode 51 is connected to the first electrode plate 81 through the ninth via hole V9 after extending along the second direction Y. In an exemplary embodiment, since the first electrode plate 81 also serves as the gate electrode of the third transistor T3, the first connection electrode 51 enables the second electrode of the first transistor T1, the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first electrode plate 81 to have the same potential, thereby forming a first node N1 of the pixel driving circuit.

[0236] In an exemplary embodiment, the second connection electrode 52 may be in the shape of a strip extending along the second direction Y. The first end of the second connection electrode 52 is connected to the first region of the third active layer (also the second region of the fourth active layer and the second region of the fifth active layer) through the second via hole V2. The second end of the second connection electrode 52 is connected to the second region of the eighth active layer through the eighth via hole V8 after extending along the second direction Y. In an exemplary embodiment, the second connection electrode 52 enables the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, the second electrode of the fifth transistor T5, and the second electrode of the eighth transistor T8 to have the same potential, forming a second node N2 of the pixel driving circuit.

[0237] In an exemplary embodiment, the third connection electrode 53 in each circuit unit may be in a block shape (eg, rectangular) and is configured to be connected to a subsequently formed data signal line. In an exemplary embodiment, the third connection electrode 53 may be referred to as a data connection electrode.

[0238] In an exemplary embodiment, the third connection electrode 53 of the circuit units in the N+1th unit column, the N+2th unit column, the N+4th unit column and the N+5th unit column can be arranged on one side of the first direction X of the first connection electrode 51 in the circuit unit, and the third connection electrode 53 is connected to the first region of the fourth active layer through the third via hole V3.

[0239] In an exemplary embodiment, positions and shapes of the third connection electrodes 53 in the N+1th cell column, the N+2th cell column, the N+4th cell column, and the N+5th cell column may be substantially the same.

[0240] In an exemplary embodiment, the third connection electrode 53 of the circuit unit in the Nth unit column and the N+3th unit column can be arranged on the side opposite to the first direction X of the first connection electrode 51 in the circuit unit, and the third connection electrode 53 is connected to the first region of the fourth active layer through the data connection line 46.

[0241] In an exemplary embodiment, the third conductive layer of the circuit unit in the Nth unit column and the N+3th unit column may further include a data connection line 46, and the shape of the data connection line 46 may be a strip shape extending along the first direction X, and the first end of the data connection line 46 is connected to the third connection electrode 53, and the second end of the data connection line 46 extends along the first direction X and is connected to the first area of ​​the fourth active layer through the third via hole V3.

[0242] In an exemplary embodiment, in at least one circuit unit, the third connection electrode 53 and the data connection line 46 may be an integral structure connected to each other.

[0243] In an exemplary embodiment, the orthographic projection of the data connection line 46 on the substrate at least partially overlaps with the orthographic projection of the second extension section 35-2 of the shielding electrode 35 on the substrate. Since the data connection line transmits a data signal, by providing a shielding electrode having a first power line potential under the data connection line, the data voltage jump can be effectively prevented from affecting the first transistor T1.

[0244] In an exemplary embodiment, positions and shapes of the third link electrodes 53 and the data link lines 46 in the Nth cell column and the N+3th cell column may be substantially the same.

[0245] In an exemplary embodiment, the fourth connection electrode 54 may be in the shape of a strip having a main portion extending along the second direction Y, a first end of the fourth connection electrode 54 is connected to the power connection line 44, and a second end of the fourth connection electrode 54 is connected to the first region of the fifth active layer through a fourth via hole V4 after extending along the second direction Y. Since the power connection line 44 is configured to be connected to a first power line formed subsequently, the first power line writes the first power signal to the first electrode of the fifth transistor T5. In an exemplary embodiment, the fourth connection electrode 54 may be referred to as a power connection electrode.

[0246] In an exemplary embodiment, in at least one unit row, the power connection line 44 and the plurality of fourth connection electrodes 54 may be an integrated structure connected to each other, which can ensure that the first electrode of the fifth transistor T5 of the plurality of circuit units in one unit row and the second electrode 82 of the storage capacitor have the same potential, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.

[0247] In an exemplary embodiment, the shape of the fifth connection electrode 55 may be a block shape (such as a rectangle), the fifth connection electrode 55 is connected to the second region of the sixth active layer (also the second region of the seventh active layer) through the fifth via hole V5, and the fifth connection electrode 55 is configured to be connected to the anode connection electrode formed subsequently. In an exemplary embodiment, the fifth connection electrode 55 may be referred to as a fourth node electrode.

[0248] In an exemplary embodiment, the shapes of the fifth connection electrodes 55 in the N+1th cell column, the N+2th cell column, the N+4th cell column, and the N+5th cell column may be substantially the same, the shapes of the fifth connection electrodes 55 in the Nth cell column and the N+3th cell column may be substantially the same, but the shapes of the fifth connection electrodes 55 in the Nth cell column and the N+1th cell column may be different.

[0249] (17) Forming a first planar layer pattern. In an exemplary embodiment, forming the first planar layer pattern may include: coating a first planar film on the substrate on which the aforementioned pattern is formed, patterning the first planar film using a patterning process to form a first planar layer covering the third conductive layer, wherein a plurality of via holes are disposed on the first planar layer, such as Fig.12 shown.

[0250] In an exemplary embodiment, the plurality of via holes of each circuit unit includes at least a twenty-first via hole V21 and a twenty-second via hole V22 .

[0251] In an exemplary embodiment, the orthographic projection of the twenty-first via hole V21 on the substrate is within the range of the orthographic projection of the third connection electrode 53 on the substrate, the first flat layer in the twenty-first via hole V21 is removed, exposing the surface of the third connection electrode 53, and the twenty-first via hole V21 is configured to allow a subsequently formed data signal line to be connected to the third connection electrode 53 through the via hole. In an exemplary embodiment, the twenty-first via hole V21 may be referred to as a data via hole.

[0252] In an exemplary embodiment, the positions of the data vias in some adjacent unit columns may be mirror-symmetrical with respect to the column center line, and the column center line may be a straight line located between adjacent unit columns and extending along the second direction Y. For example, the positions of the data vias in the Nth unit column and the positions of the data vias in the N+1th unit column may be mirror-symmetrical with respect to the column center line. For another example, the positions of the data vias in the N+3th unit column and the positions of the data vias in the N+4th unit column may be mirror-symmetrical with respect to the column center line.

[0253] In an exemplary embodiment, the orthographic projection of the twenty-second via hole V22 on the substrate is located within the range of the orthographic projection of the fifth connecting electrode 55 on the substrate, the first flat layer in the twenty-second via hole V22 is removed to expose the surface of the fifth connecting electrode 55, and the twenty-second via hole V22 is configured to connect a subsequently formed anode connecting electrode to the fifth connecting electrode 55 through the via hole.

[0254] In an exemplary embodiment, a twenty-third via V23 may also be provided on the first flat layer of a part of the circuit unit. The orthographic projection of the twenty-third via V23 on the substrate is located within the range of the orthographic projection of the power connection block 44-1 of the power connection line 44 on the substrate, the first flat layer in the twenty-third via V23 is removed, exposing the surface of the power connection block 44-1, and the twenty-third via V23 is configured to connect the first power line formed subsequently to the power connection block 44-1 through the via. In an exemplary embodiment, the twenty-third via V23 may be referred to as a power via.

[0255] In an exemplary embodiment, the twenty-third via hole V23 may be disposed in a plurality of circuit cells of the N+1th cell column and the N+4th cell column.

[0256] (18) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer may include: depositing a fourth conductive film on the substrate having the aforementioned pattern, patterning the third conductive film using a patterning process, and forming a fourth conductive layer disposed on the first planar layer, such as Fig.13A and Fig. 13B As shown, Fig. 13B for Fig.13A In an exemplary embodiment, the fourth conductive layer may be referred to as a second source-drain metal (SD2) layer.

[0257] In an exemplary embodiment, the fourth conductive layer of each circuit unit includes at least a data signal line 61 and an anode connection electrode 62 .

[0258] In an exemplary embodiment, the shape of the data signal line 61 may be a straight line or a folded line extending along the second direction Y, and the data signal line 61 is connected to the third connection electrode 53 as the data connection electrode through the twenty-first via hole V21. Since the third connection electrode 53 is connected to the first region of the fourth active layer, the data signal line 61 can write the data signal to the first electrode of the fourth transistor T4.

[0259] In an exemplary embodiment, the positions of the data signal lines 61 in different unit columns may be different. The data signal lines 61 in the Nth unit column and the N+3th unit column may be located on one side of the first connection electrode 51 (first power line 71) in the opposite direction of the first direction X, and the data signal lines 61 in the N+1th unit column, the N+2th unit column, the N+4th unit column, and the N+5th unit column may be located on one side of the first connection electrode 51 (first power line 71) in the first direction X.

[0260] In an exemplary embodiment, the data signal line 61 may include a main body portion and a connection portion, the main body portion is a straight line extending along the second direction Y, the connection portion is connected to the main body portion, and the connection portion is connected to the third connection electrode 53 through the twenty-first via hole V21. The position of the main body portion of the data signal line 61 in some adjacent unit columns may be mirror-symmetrical with respect to the column center line A1, the column center line A1 may be a straight line located between adjacent unit columns and extending along the second direction Y, and the column center line A11 is a virtual line. For example, the position of the main body portion of the data signal line 61 in the Nth unit column and the position of the main body portion of the data signal line 61 in the N+1th unit column may be mirror-symmetrical with respect to the column center line A1. For another example, the position of the main body portion of the data signal line 61 in the N+3th unit column and the position of the main body portion of the data signal line 61 in the N+4th unit column may be mirror-symmetrical with respect to the column center line A1.

[0261] In an exemplary embodiment, the shape of the anode connection electrode 62 in each circuit unit may be a block shape (eg, a rectangle), and the anode connection electrode 62 is configured to be connected to an anode to be formed subsequently.

[0262] In an exemplary embodiment, the anode connection electrode 62 of the circuit units in the Nth unit column, the N+1th unit column, the N+3th unit column and the N+4th unit column can be arranged on one side of the second direction Y of the power connection line 44 in the circuit unit, and the anode connection electrode 62 is connected to the fifth connection electrode 55 through the twenty-second via hole V22.

[0263] In an exemplary embodiment, positions and shapes of the anode connection electrodes 62 in the Nth cell column, the N+1th cell column, the N+3th cell column, and the N+4th cell column may be substantially the same.

[0264] In an exemplary embodiment, the anode connecting electrode 62 of the circuit unit in the N+2th unit column and the N+5th unit column can be arranged on the side opposite to the second direction Y of the power connection line 44 in the circuit unit, and the anode connecting electrode 62 is connected to the fifth connecting electrode 55 serving as the fourth node electrode through the anode connecting line 63.

[0265] In an exemplary embodiment, the fourth conductive layer of the circuit units in the N+2th unit column and the N+5th unit column may further include an anode connecting line 63, the shape of the anode connecting line 63 may be a strip shape extending along the second direction Y, the first end of the anode connecting line 63 is connected to the anode connecting electrode 62, and the second end of the anode connecting line 63 is extended along the first direction X and then connected to the fifth connecting electrode 55 through the twenty-second via hole V22.

[0266] In an exemplary embodiment, the anode connection line 63 may include a first connection sub-line 63-1 and a second connection sub-line 63-2, wherein a first end of the first connection sub-line 63-1 is connected to the anode connection electrode 62, and a second end of the first connection sub-line 63-1 is connected to the fifth connection electrode 55 through a twenty-second via hole V22 after extending along the second direction Y toward a direction close to the fifth connection electrode 55. A first end of the second connection sub-line 63-2 is connected to a second end of the first connection sub-line 63-1, and a second end of the second connection sub-line 63-2 is extended along the second direction Y toward a direction close to the anode connection electrode 62 in the next cell row.

[0267] In an exemplary embodiment, the anode connection line 63 is configured to change the position of the anode via hole so that the anode connection electrode 62 is connected to the fifth connection electrode 55 through the anode connection line 63 and to improve the flatness of the anode.

[0268] In an exemplary embodiment, positions and shapes of the anode connection electrodes 62 and the anode connection lines 63 in the N+2 th cell column and the N+5 th cell column may be substantially the same.

[0269] In an exemplary embodiment, in at least one circuit unit of the N+2 th unit column and the N+5 th unit column, the anode connection electrode 62 and the anode connection line 63 may be an integral structure connected to each other.

[0270] In an exemplary embodiment, the fourth conductive layer of the partial circuit unit may further include a first power line 71. The first power line 71 may be in a straight line shape or a zigzag line shape extending along the second direction Y.

[0271] In an exemplary embodiment, the first power line 71 may be disposed in the circuit units of the Nth unit column, the N+1th unit column, the N+3th unit column, and the N+4th unit column, and the circuit units of the N+2th unit column and the N+5th unit column are not provided with the first power line 71. A groove 71-1 may be disposed on the first power line 71, and the shape of the groove 71-1 may be a block shape (such as a rectangle). The groove 71-1 may be disposed on one side of the first power line 71 in the opposite direction of the first direction X, and the groove 71-1 is configured to accommodate the anode connection electrode 62 in the unit column.

[0272] In an exemplary embodiment, the first power lines 71 of the circuit units in the N+1th unit column and the N+4th unit column are connected to the power connection block 44-1 through the twenty-third via hole V23. Since the power connection block 44-1 is connected to the power connection line 44, the power connection line 44 extending along the first direction X of the main body and the first power line 71 extending along the second direction Y of the main body are connected to each other, so that the first power line 71 and the power connection line 44 form a meshed meshed connection structure for transmitting the first power signal on the display substrate, which can not only effectively reduce the resistance of the first power line 71 and reduce the voltage drop of the first power signal, but also effectively improve the uniformity of the first power signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality.

[0273] In an exemplary embodiment, the positions of the first power lines 71 in adjacent unit columns may be mirror-symmetrical with respect to the column center line A1. For example, the positions of the first power lines 71 in the Nth unit column and the positions of the first power lines 71 in the N+1th unit column may be mirror-symmetrical with respect to the column center line A1. For another example, the positions of the first power lines 71 in the N+3th unit column and the positions of the first power lines 71 in the N+4th unit column may be mirror-symmetrical with respect to the column center line A1.

[0274] In an exemplary embodiment, the first power lines 71 of the Nth unit column and the N+1th unit column may be an integrated structure connected to each other, so that the first power lines 71 in the Nth unit column and the N+1th unit column are an integrated whole-surface structure. The first power lines 71 of the N+3th unit column and the N+4th unit column may be an integrated structure connected to each other, so that the first power lines 71 in the N+3th unit column and the N+4th unit column are an integrated whole-surface structure.

[0275] In an exemplary embodiment, in the Nth unit column, the N+1th unit column, the N+3th unit column, and the N+4th unit column, the orth projection of the first power line 71 on the substrate at least partially overlaps with the orth projection of the first connection electrode 51 on the substrate. Since the first connection electrode 51 serves as the first node N1 in the pixel driving circuit, the first power line 71 with a constant voltage can effectively shield the influence of other signals in the pixel driving circuit on the first node N1, thereby preventing other signals (such as data voltage jump) from affecting the potential of the first node N1 of the pixel driving circuit, thereby improving the display effect.

[0276] In an exemplary embodiment, an orthographic projection of the first power line 71 on the substrate may include an orthographic projection of the first connection electrode 41 on the substrate.

[0277] In an exemplary embodiment, the fourth conductive layer of a portion of the circuit units may further include a second power line 72 . The second power line 72 may be in a straight line shape or a zigzag line shape extending along the second direction Y.

[0278] In an exemplary embodiment, the second power line 72 can be arranged in the N+2th unit column and the N+5th unit column. On the one hand, it can ensure the symmetry of the signal line under the anode and improve the flatness and symmetry of the anode. On the other hand, it can realize the VSS in pixel structure, which can greatly reduce the width of the power lead in the border area and reduce the border width, which is conducive to realizing full-screen display.

[0279] In an exemplary embodiment, in the N+2th unit column and the N+5th unit column, the positive projection of the second power line 72 on the substrate at least partially overlaps with the positive projection of the first connection electrode 51 on the substrate. Since the first connection electrode 51 serves as the first node N1 in the pixel driving circuit, the second power line 72 with a constant voltage can effectively shield the influence of other signals in the pixel driving circuit on the first node N1, thereby preventing other signals (such as data voltage jump) from affecting the potential of the first node N1 of the pixel driving circuit, thereby improving the display effect.

[0280] In an exemplary embodiment, the fourth conductive layer of a portion of the circuit units may further include an initial connection line 73 , and the initial connection line 73 may be in a straight line shape or a zigzag line shape extending along the second direction Y.

[0281] In an exemplary embodiment, the initial connection line 73 may be disposed in the N+2th unit column and the N+5th unit column, and may be disposed on one side of the second power line 72 in the first direction X. The initial connection line 73 may ensure the symmetry of the signal line under the anode, improve the flatness and symmetry of the anode, and may form a mesh connection structure for transmitting the initial signal.

[0282] In one embodiment, in at least one unit column, the initial connection line can be connected to the first initial connection block on the first initial signal line through a via, so that the first initial signal line whose main part extends along the first direction X and the initial connection line whose main part extends along the second direction Y form a mesh-like interconnected structure for transmitting the first initial signal on the display substrate, which can not only effectively reduce the resistance of the first initial signal line and reduce the voltage drop of the first initial signal, but also effectively improve the uniformity of the first initial signal, effectively improve the display uniformity, and improve the display quality and display quality.

[0283] In another embodiment, in at least one unit column, the initial connection line can be connected to the second initial connection block on the second initial signal line through a via, so that the second initial signal line whose main part extends along the first direction X and the initial connection line whose main part extends along the second direction Y form a mesh-like interconnected structure for transmitting the second initial signal on the display substrate, which can not only effectively reduce the resistance of the second initial signal line and reduce the voltage drop of the second initial signal, but also effectively improve the uniformity of the second initial signal, effectively improve the display uniformity, and improve the display quality and display quality.

[0284] In another embodiment, in at least one unit column, the initial connection line can be connected to the third initial connection block on the third initial signal line through a via, so that the third initial signal line whose main part extends along the first direction X and the initial connection line whose main part extends along the second direction Y form a mesh-like interconnected structure for transmitting the third initial signal on the display substrate, which can not only effectively reduce the resistance of the third initial signal line and reduce the voltage drop of the third initial signal, but also effectively improve the uniformity of the third initial signal, effectively improve the display uniformity, and improve the display quality and display quality.

[0285] In one possible implementation, the initial connection line 73 in a unit column (such as the N+2th unit column) can be connected to the first initial signal line 41, the initial connection line 73 in another unit column (such as the N+5th unit column) can be connected to the second initial signal line 42, and the initial connection line 73 in yet another unit column (such as the N+8th unit column) can be connected to the third initial signal line 43, forming a first meshed connection structure for transmitting the first initial signal, a second meshed connection structure for transmitting the second initial signal, and a third meshed connection structure for transmitting the third initial signal on the display substrate.

[0286] In an exemplary embodiment, in at least one unit column, the positions of the second power line 72 and the initial connection line 73 can be interchanged, and the second power line 72 can be arranged on one side of the initial connection line 73 in the first direction X, which is not limited in the present disclosure.

[0287] (19) Forming a second planar layer pattern. In an exemplary embodiment, forming the second planar layer pattern may include: coating a second planar film on the substrate on which the aforementioned pattern is formed, patterning the first planar film using a patterning process to form a second planar layer covering the fourth conductive layer, and providing a plurality of via holes on the second planar layer, such as Fig.14 shown.

[0288] In an exemplary embodiment, the plurality of vias of each circuit unit includes at least an anode via V30. The orthographic projection of the anode via V30 on the substrate is within the range of the orthographic projection of the anode connection electrode 62 on the substrate, the second flat layer in the anode via V30 is removed, exposing the surface of the anode connection electrode 62, and the anode connection electrode is configured to connect a subsequently formed anode to the anode connection electrode 62 through the via.

[0289] At this point, the drive structure layer is prepared on the substrate. In a plane parallel to the display substrate, the drive structure layer may include a plurality of circuit units, each of which may include a pixel drive circuit, and a first scan signal line, a second scan signal line, a third scan signal line, a light-emitting signal line, a first initial signal line, a second initial signal line, a third initial signal line, a data signal line, and a first power supply line connected to the pixel drive circuit. In a plane perpendicular to the display substrate, the drive structure layer may include at least a shielding layer, a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a third conductive layer, a first planar layer, a fourth conductive layer, and a second planar layer sequentially arranged on the substrate. The blocking layer may include at least a blocking electrode, the semiconductor layer may include at least a first initial signal line, an active layer of the first transistor to the eighth transistor, the first conductive layer may include at least a second scanning signal line, a light-emitting signal line and a first electrode plate of the storage capacitor, the second conductive layer may include at least a shielding electrode and a second electrode plate of the storage capacitor, the third conductive layer may include at least a first scanning signal line, a third scanning signal line, a second initial signal line, a third initial signal and a plurality of connecting electrodes, and the fourth conductive layer may include at least a data signal line and a first power line.

[0290] In an exemplary embodiment, the substrate may be a flexible substrate, or may be a rigid substrate. The rigid substrate may include, but is not limited to, one or more of glass and quartz, and the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked. The materials of the first and second flexible material layers may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the materials of the first and second inorganic material layers may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., for improving the water and oxygen resistance of the substrate, and the first and second inorganic material layers are also referred to as barrier layers, and the material of the semiconductor layer may be amorphous silicon (a-si).

[0291] In an exemplary embodiment, the shielding layer, the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer may be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may be a single layer structure, or a multi-layer composite structure, such as Mo / Cu / Mo, etc. The first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multi-layer or a composite layer. The first planar layer and the second planar layer may be made of organic materials, such as resin, etc.

[0292] In an exemplary embodiment, after the driving structure layer is prepared, a light emitting structure layer is prepared on the driving structure layer. The preparation process of the light emitting structure layer may include the following operations.

[0293] (20) Forming an anode conductive layer pattern. In an exemplary embodiment, forming the anode conductive layer pattern may include: depositing an anode conductive film on the substrate formed with the aforementioned pattern, patterning the anode conductive film using a patterning process to form an anode conductive layer disposed on the second flat layer, wherein the anode conductive layer includes at least a plurality of anode patterns, such as Fig.15A and Fig. 15B As shown, Fig. 15B for Fig.15A Schematic diagram of the plan view of the anode conductive layer.

[0294] In an exemplary embodiment, the plurality of anodes may include at least a first anode 90A located in the first light emitting cell, a second anode 90B located in the second light emitting cell, and a third anode 90C located in the third light emitting cell.

[0295] In an exemplary embodiment, the first light emitting unit may be a red light emitting unit emitting red light, the second light emitting unit may be a green light emitting unit emitting green light, and the third light emitting unit may be a blue light emitting unit emitting blue light.

[0296] In an exemplary embodiment, the second anode 90B may be disposed on one side of the first anode 90A in the second direction Y, and the third anode 90C may be disposed on one side of the first direction X of the first anode 90A and the second anode 90B.

[0297] In an exemplary embodiment, the first anode 90A, the second anode 90B, and the third anode 90C may be connected to the anode connection electrode 62 of the corresponding circuit unit through the anode via hole V30 , respectively.

[0298] In an exemplary embodiment, at least one of the first anode 90A, the second anode 90B and the third anode 90C may include an anode body portion and an anode connecting portion connected to each other, the anode connecting portion being connected to the anode body portion on one hand and to the anode connecting electrode 62 through the anode via V30 on the other hand.

[0299] In an exemplary embodiment, the first anode 90A may include a first anode main body and a first anode connecting portion connected to each other, the shape of the first anode main body may be rectangular, the corners of the rectangle may be provided with arc-shaped chamfers, the shape of the first anode connecting portion may be a strip shape extending in a direction away from the first anode main body, and the end of the first anode connecting portion away from the first anode main body is connected to the anode connecting electrode 62 through the anode via V30.

[0300] In an exemplary embodiment, the orthographic projection of the first anode body portion of the first anode 90A on the substrate at least partially overlaps with the orthographic projection of the first power line 71 on the substrate, and the orthographic projection of the first anode body portion of the first anode 90A on the substrate does not overlap with the orthographic projections of the data signal line 61, the anode connection line 63, the second power line 72 and the initial connection line 73 on the substrate.

[0301] In an exemplary embodiment, an orthographic projection of the first anode body portion of the first anode 90A on the substrate may be located within a range of an orthographic projection of the first power line 71 on the substrate.

[0302] In an exemplary embodiment, the second anode 90B may include a second anode main body portion and a second anode connecting portion connected to each other, the shape of the second anode main body portion may be rectangular, the corners of the rectangle may be provided with arc-shaped chamfers, the shape of the second anode connecting portion may be a strip shape extending in a direction away from the second anode main body portion, and the end of the second anode connecting portion away from the second anode main body portion is connected to the anode connecting electrode 62 through the anode via V30.

[0303] In an exemplary embodiment, the orthographic projection of the second anode body portion of the second anode 90B on the substrate at least partially overlaps with the orthographic projection of the first power line 71 on the substrate, and the orthographic projection of the second anode body portion of the second anode 90B on the substrate does not overlap with the orthographic projections of the data signal line 61, the anode connection line 63, the second power line 72 and the initial connection line 73 on the substrate.

[0304] In an exemplary embodiment, an orthographic projection of the second anode body portion of the second anode 90B on the substrate may be located within a range of an orthographic projection of the first power line 71 on the substrate.

[0305] In an exemplary embodiment, the third anode 90C may include a third anode main body and a third anode connecting portion which are connected to each other. The shape of the third anode main body may be rectangular, and the corners of the rectangle may be provided with arc-shaped chamfers. The shape of the third anode connecting portion may be a strip shape extending in a direction away from the third anode main body, and the end of the third anode connecting portion away from the third anode main body is connected to the anode connecting electrode 62 through the anode via V30.

[0306] In an exemplary embodiment, the orthographic projection of the third anode body portion of the third anode 90C on the substrate at least partially overlaps with the orthographic projections of the data signal line 61, the anode connection line 63, the second power line 72 and the initial connection line 73 on the substrate, and the orthographic projection of the third anode body portion of the third anode 90C on the substrate does not overlap with the orthographic projection of the first power line 71 on the substrate.

[0307] In an exemplary embodiment, the orthographic projections of the first anode body portion, the second anode body portion, and the third anode body portion on the substrate do not overlap with the orthographic projections of the power via on the substrate and do not overlap with the orthographic projections of the anode via on the substrate.

[0308] In an exemplary embodiment, the anode conductive layer may have a single-layer structure, such as indium tin oxide ITO or indium zinc oxide IZO, or may have a multi-layer composite structure, such as ITO / Ag / ITO.

[0309] In an exemplary embodiment, in the second direction Y, the first anode 90A, the second anode 90B, and the third anode 90C may be disposed at a region close to a next cell row of a corresponding circuit cell.

[0310] In an exemplary embodiment, the orthographic projection of the first anode 90A on the substrate at least partially overlaps with the orthographic projection of the power connection line 44 on the substrate, and does not overlap with the orthographic projection of the first initial signal line 41 on the substrate.

[0311] In an exemplary embodiment, the orthographic projection of the second anode 90B on the substrate at least partially overlaps with the orthographic projections of the first initial signal line 41, the second initial signal line 42, and the second initial signal line 43 on the substrate, and the orthographic projection of the second anode 90B on the substrate does not overlap with the orthographic projections of the first scanning signal line 31 and the power connection line 44 on the substrate.

[0312] In an exemplary embodiment, the orthographic projection of the third anode 90C on the substrate at least partially overlaps with the orthographic projections of the power connection line 44, the light-emitting signal line 34, the second scanning signal line 32 and the second initial signal line 42 on the substrate, and the orthographic projection of the third anode 90C on the substrate does not overlap with the orthographic projection of the first scanning signal line 31 on the substrate.

[0313] (21) Forming a pixel definition layer pattern. In an exemplary embodiment, forming a pixel definition layer pattern may include: coating a pixel definition film on a substrate formed with the aforementioned pattern, patterning the pixel definition film using a patterning process to form a pixel definition layer pattern covering the anode conductive layer pattern, wherein a plurality of pixel openings are provided on the pixel definition layer, such as Fig.16 shown.

[0314] In an exemplary embodiment, the plurality of pixel openings may include a first pixel opening 100A located in a red light emitting unit, a second pixel opening 100B located in a green light emitting unit, and a second pixel opening 100B located in a blue light emitting unit. The orthogonal projection of the first pixel opening 100A on the substrate is located within the range of the orthogonal projection of the first anode 90A on the substrate, and the pixel definition film in the first pixel opening 100A is removed to expose the surface of the first anode 90A. The orthogonal projection of the second pixel opening 100B on the substrate is located within the range of the orthogonal projection of the second anode 90B on the substrate, and the pixel definition film in the second pixel opening 100B is removed to expose the surface of the second anode 90B. The orthogonal projection of the third pixel opening 100C on the substrate is located within the range of the orthogonal projection of the third anode 90C on the substrate, and the pixel definition film in the third pixel opening 100C is removed to expose the surface of the third anode 90C.

[0315] In an exemplary embodiment, the shape of the first pixel opening 100A can be rectangular, and the corners of the rectangle can be provided with arc-shaped chamfers, the orthographic projection of the first pixel opening 100A on the substrate at least partially overlaps with the orthographic projection of the first power line 71 on the substrate, and the orthographic projection of the first pixel opening 100A on the substrate does not overlap with the orthographic projections of the data signal line 61, the anode connection line 63, the second power line 72 and the initial connection line 73 on the substrate.

[0316] In an exemplary embodiment, the orthographic projection of the first pixel opening 100A on the substrate does not overlap with the orthographic projection of the power via on the substrate, that is, there is no power via within the range of the first pixel opening 100A.

[0317] In an exemplary embodiment, an orthographic projection of the first pixel opening 100A on the substrate may be located within a range of an orthographic projection of the first power line 71 on the substrate.

[0318] In an exemplary embodiment, the orthographic projection of the first pixel opening 100A on the substrate does not overlap with the orthographic projections of the data via and the anode via on the substrate, that is, there are no data vias and anode vias within the range of the first pixel opening 100A.

[0319] In an exemplary embodiment, the orthographic projection of the second pixel opening 100B on the substrate at least partially overlaps with the orthographic projection of the first power line 71 on the substrate, and the orthographic projection of the second pixel opening 100B on the substrate does not overlap with the orthographic projections of the data signal line 61, the anode connection line 63, the second power line 72 and the initial connection line 73 on the substrate.

[0320] In an exemplary embodiment, the orthographic projection of the second pixel opening 100B on the substrate does not overlap with the orthographic projection of the power via on the substrate, that is, there is no power via within the range where the second pixel opening 100B is located.

[0321] In an exemplary embodiment, an orthographic projection of the second pixel opening 100B on the substrate may be located within a range of an orthographic projection of the first power line 71 on the substrate.

[0322] In an exemplary embodiment, the orthographic projection of the second pixel opening 100B on the substrate does not overlap with the orthographic projections of the data via and the anode via on the substrate, that is, there is no data via and anode via within the range of the third pixel opening.

[0323] In an exemplary embodiment, the orthographic projection of the third pixel opening 100C on the substrate at least partially overlaps with the orthographic projections of the data signal line 61, the anode connection line 63, the second power line 72 and the initial connection line 73 on the substrate, and the orthographic projection of the third pixel opening 100C on the substrate does not overlap with the orthographic projection of the first power line 71 on the substrate.

[0324] In an exemplary embodiment, the orthographic projection of the third pixel opening 100C on the substrate does not overlap with the orthographic projection of the power via on the substrate, that is, there is no power via within the range where the third pixel opening 100C is located.

[0325] In an exemplary embodiment, the orthographic projection of the third pixel opening 100C on the substrate does not overlap with the orthographic projections of the data via and the anode via on the substrate, that is, there is no data via and anode via within the range of the third pixel opening 100C.

[0326] In an exemplary embodiment, the first pixel opening 100A and the second pixel opening 100B overlap with the first power line, but do not overlap with the second power line 72 and the initial connection line 73, and the third pixel opening 100C overlaps with the second power line 72 and the initial connection line 73, but does not overlap with the first power line, thereby effectively ensuring the flatness and symmetry of the anode in the pixel opening.

[0327] Fig.17 FIG. 1 is a schematic diagram of the position relationship between the third pixel opening and the signal line in the embodiment of the present disclosure. Fig.17As shown, in an exemplary embodiment, the third pixel opening 100C may have an opening center line B1, which may be a straight line extending along the second direction Y and passing through the geometric center of the third pixel opening, and the opening center line B1 is a virtual line.

[0328] In an exemplary embodiment, in at least one third pixel opening 100C, in the first direction X, there is a first distance L1 between the anode connection line 63 at least partially overlapping with the third pixel opening 100C and the opening center line B1, and there is a second distance L2 between the data signal line 61 at least partially overlapping with the third pixel opening 100C and the opening center line B1, and the ratio of the first distance L1 to the second distance L2 can be approximately 0.8 to 1.2.

[0329] In an exemplary embodiment, a ratio of the first distance L1 to the second distance L2 may be approximately 0.9 to 1.1.

[0330] In an exemplary embodiment, the first distance L1 and the second distance L2 may be substantially the same, that is, the anode connection line 63 and the data signal line 61 may be substantially mirror-symmetrical with respect to the opening center line B1.

[0331] In an exemplary embodiment, the first distance L1 and the second distance L2 are both dimensions in the first direction X. The first distance L1 may be the distance between the edge of the anode connection line 63 on the side close to the opening center line B1 and the opening center line B1, or the first distance L1 may be the distance between the edge of the anode connection line 63 on the side away from the opening center line B1 and the opening center line B1. The second distance L2 may be the distance between the edge of the data signal line 61 on the side close to the opening center line B1 and the opening center line B1, or the second distance L2 may be the distance between the edge of the data signal line 61 on the side away from the opening center line B1 and the opening center line B1.

[0332] In an exemplary embodiment, in at least one third pixel opening 100C, in the first direction X, a third distance L3 is provided between the second power line 72 at least partially overlapping with the third pixel opening 100C and the opening center line B1, and a fourth distance L4 is provided between the initial connection line 73 at least partially overlapping with the third pixel opening 100C and the opening center line B1, and a ratio of the third distance L3 to the fourth distance L4 may be approximately 0.8 to 1.2.

[0333] In an exemplary embodiment, a ratio of the third distance L3 to the fourth distance L4 may be approximately 0.9 to 1.1.

[0334] In an exemplary embodiment, the third distance L3 and the fourth distance L4 may be substantially the same, that is, the second power line 72 and the initial connection line 73 may be substantially mirror-symmetrical with respect to the opening center line B1.

[0335] In an exemplary embodiment, the third distance L3 and the fourth distance L4 are both dimensions in the first direction X. The third distance L3 may be the distance between the edge of the second power line 72 on the side close to the opening center line B1 and the opening center line B1, or the third distance L3 may be the distance between the edge of the second power line 72 on the side away from the opening center line B1 and the opening center line B1. The fourth distance L4 may be the distance between the edge of the initial connection line 73 on the side close to the opening center line B1 and the opening center line B1, or the fourth distance L4 may be the distance between the edge of the initial connection line 73 on the side away from the opening center line B1 and the opening center line B1.

[0336] In an exemplary embodiment, in the second direction Y, the anode connection line 63 at least partially overlapping the third pixel opening 100C has a first extension length, the second power line 72 at least partially overlapping the third pixel opening 100C has a second extension length, the initial connection line 73 at least partially overlapping the third pixel opening 100C has a third extension length, and the data signal line 61 at least partially overlapping the third pixel opening 100C has a fourth extension length, and the first extension length, the second extension length, the third extension length and the fourth extension length may be substantially the same.

[0337] In the present disclosure, there are no power vias, data vias and anode vias within the range of the pixel opening, and the orthographic projections of the first pixel opening and the third pixel opening on the substrate are located within the range of the orthographic projection of the first power line 71 on the substrate, that is, the first pixel opening and the second pixel opening are below the entire second source and drain metal layer, and the third pixel opening is overlapped with the data signal line, the anode connection line, the second power line and the initial connection line, and the data signal line and the anode connection line are symmetrical with respect to the third pixel opening, and the second power line 72 and the initial connection line 73 are symmetrical with respect to the third pixel opening, so that the first anode, the second anode and the third anode not only have good flatness, which can effectively avoid defects such as off-screen watermarks (Mura) caused by poor anode flatness, but also have good symmetry, which can effectively improve color deviation and improve display quality.

[0338] In an exemplary embodiment, in the second direction Y, the first pixel opening 100A, the second pixel opening 100B, and the third pixel opening 100C may be disposed at a region of the corresponding circuit unit close to a next unit row.

[0339] In an exemplary embodiment, the orthographic projection of at least one first pixel opening 100A on the substrate at least partially overlaps with the orthographic projection of the power connection line 44 on the substrate, and the orthographic projection of at least one first pixel opening 100A on the substrate does not overlap with the orthographic projection of the first initial signal line 41 on the substrate.

[0340] In an exemplary embodiment, the orthographic projection of at least one first pixel opening 100A on the substrate also does not overlap with the orthographic projections of the first scan signal line 31, the second scan signal line 32, the third scan signal line 33, the light emitting signal line 34, the second initial signal line 42 and the third initial signal line 43 on the substrate.

[0341] In an exemplary embodiment, the orthographic projection of at least one second pixel opening 100B on the substrate at least partially overlaps with the orthographic projections of the first initial signal line 41, the second initial signal line 42, and the second initial signal line 43 on the substrate, and the orthographic projection of at least one second pixel opening 100B on the substrate does not overlap with the orthographic projections of the first scanning signal line 31 and the power connection line 44 on the substrate.

[0342] In an exemplary embodiment, the orthographic projection of at least one second pixel opening 100B on the substrate also at least partially overlaps with the orthographic projection of the third scanning signal line 33 on the substrate, and the orthographic projection of at least one second pixel opening 100B on the substrate also does not overlap with the orthographic projections of the second scanning signal line 32 and the light-emitting signal line 34 on the substrate.

[0343] In an exemplary embodiment, the orthographic projection of at least one third pixel opening 100C on the substrate at least partially overlaps with the orthographic projection of the second scanning signal line 32, the light emitting signal line 34, the second initial signal line 42 and the power connection line 44 on the substrate, and the orthographic projection of at least one third pixel opening 100C on the substrate does not overlap with the orthographic projection of the first scanning signal line 31 on the substrate.

[0344] In an exemplary embodiment, an orthographic projection of at least one third pixel opening 100C on the substrate also at least partially overlaps with orthographic projections of the third scan signal line 33 , the first preliminary signal line 41 , and the third preliminary signal line 43 on the substrate.

[0345] In an exemplary embodiment, the subsequent preparation process may include: first forming an organic light-emitting layer by an evaporation or inkjet printing process, then forming a cathode on the organic light-emitting layer, and then forming a packaging structure layer, the packaging structure layer may include a stacked first packaging layer, a second packaging layer and a third packaging layer, the first packaging layer and the third packaging layer may be made of inorganic materials, the second packaging layer may be made of organic materials, and the second packaging layer is arranged between the first packaging layer and the third packaging layer to ensure that external water vapor cannot enter the light-emitting structure layer.

[0346] The display substrate provided by the exemplary embodiment of the present disclosure adjusts the arrangement of the data signal line and the first power line so that there are no data vias and power vias within the range of the pixel opening, and the anode exposed by the pixel opening has good flatness, which can effectively avoid defects such as off-screen watermarks (Mura) caused by poor anode flatness, effectively improve color deviation, and enhance display quality.

[0347] In the exemplary embodiment of the present disclosure, the orthographic projections of the first pixel opening and the second pixel opening are arranged on the substrate within the range of the orthographic projection of the first power line 71 on the substrate, that is, the entire second source-drain metal layer is below the first pixel opening and the second pixel opening, and the third pixel opening is arranged to overlap with the data signal line, the anode connection line, the second power line and the initial connection line, and the data signal line and the anode connection line are symmetrical relative to the third pixel opening, and the second power line 72 and the initial connection line 73 are symmetrical relative to the third pixel opening, so that the anode exposed by the pixel opening has good symmetry, which can effectively improve color deviation and enhance display quality.

[0348] The present disclosure arranges a second power line in the second source-drain metal layer, which can, on the one hand, ensure the symmetry of the signal line below the anode and improve the flatness and symmetry of the anode; on the other hand, it can realize the VSS in pixel structure, which can greatly reduce the width of the power lead in the frame area and the frame width, thereby reducing the frame width and facilitating the realization of full-screen display.

[0349] The present disclosure sets an initial connection line in the second source-drain metal layer, which can, on the one hand, ensure the symmetry of the signal line below the anode and improve the flatness and symmetry of the anode; on the other hand, it can enable the initial signal line and the initial connection line to form a mesh-like interconnected structure for transmitting the initial signal on the display substrate, which can not only effectively reduce the resistance of the initial signal line and reduce the voltage drop of the initial signal, but also effectively improve the uniformity of the initial signal, effectively improve the display uniformity, and improve the display quality and display quality.

[0350] The present disclosure provides a power connection line extending along a first direction and a first power line extending along a second direction, and the first power line is connected to the power connection line, so that the first power line and the power connection line form a mesh-like mesh connection structure for transmitting a first power signal on a display substrate, which can not only effectively reduce the resistance of the first power signal line and reduce the voltage drop of the first power signal, but also effectively improve the uniformity of the first power signal, effectively improve the display uniformity, and improve the display quality and display quality.

[0351] The embodiment of the present disclosure sets a first initial signal line in the semiconductor layer, which can not only improve the reliable connection between the first initial signal line and the first electrode of the first transistor, but also reduce the number of vias and the space occupied by the pixel driving circuit, which is conducive to achieving high-resolution (PPI) display.

[0352] The embodiment of the present disclosure can shield the influence of the data voltage jump on the first transistor T1 and the second transistor T2 by providing a shielding electrode, thereby preventing the data voltage jump from affecting the normal operation of the pixel driving circuit and improving the display effect.

[0353] In the embodiment of the present disclosure, the first power line is provided to shield the first node N1 of the pixel driving circuit, thereby effectively preventing other signals from affecting the potential of the first node N1 of the pixel driving circuit, thereby improving the display effect.

[0354] The preparation process disclosed in the present invention is well compatible with the existing preparation process, and the process is simple to realize, easy to implement, has high production efficiency, low production cost and high yield rate.

[0355] Fig.18 Schematic diagram of another planar structure of an exemplary embodiment of the present disclosure. In an exemplary embodiment, on a plane perpendicular to the display substrate, the display substrate may include a driving structure layer disposed on a substrate and a light emitting structure layer disposed on a side of the driving structure layer away from the substrate. On a plane parallel to the display substrate, the driving structure layer includes a plurality of circuit units, and the light emitting structure layer includes a plurality of light emitting units. Figure 5 The structure of the driving structure layer including three circuit units and the light emitting structure layer including three light emitting units is illustrated. The structure of three circuit units (first circuit unit Q1, second circuit unit Q2 and third circuit unit Q3) is illustrated.

[0356] In an exemplary embodiment, the structure of the pixel driving circuit in each circuit unit of this embodiment is similar to Figure 5 The structures shown are basically the same, and the structures of the first scanning signal line 31, the second scanning signal line 32, the third scanning signal line 33, the light emitting signal line 34, the first initial signal line 41, the second initial signal line 42 and the third initial signal line 43 are the same as those shown in FIG. Figure 5 The structure shown is basically the same, and the structure of the anode and pixel opening in each light-emitting unit is the same as Figure 5 The structure shown is basically the same as Figure 5 The difference between the structures shown is the structure of the data signal line 61 and the first power line 71 .

[0357] In an exemplary embodiment, the first power line 71 of the present embodiment is provided in each circuit unit, that is, the first circuit unit Q1, the second circuit unit Q2, and the third circuit unit Q3 are each provided with a first power line 71. At least one pixel driving circuit may further include a power connection electrode, and at least one circuit unit may further include a power connection line 44, the power connection electrode is connected to the power connection line 44, and the first power line 71 may be connected to the power connection electrode in the circuit unit through the power via K1 to achieve the connection between the first power line 71 and the power connection line 44.

[0358] In an exemplary embodiment, at least one circuit unit may further include an anode connection line 63 and an initial connection line 73, and the structures of the anode connection line 63 and the initial connection line 73 are similar to those of the Figure 5 The structures shown are substantially the same. In some possible implementations, at least one circuit unit may further include a second power line, which is not limited in the present disclosure.

[0359] In an exemplary embodiment, the positions of the data signal lines 61 in the first circuit unit Q1, the second circuit unit Q2 and the third circuit unit Q3 can be substantially the same, the data signal lines 61 can all be arranged on one side of the first direction X of the first power line 71, and the data signal lines 61 are connected to the data connection electrodes in the circuit units through the data vias K2.

[0360] In an exemplary embodiment, since the relative positions of the data signal line 61 and the first power line 71 in each circuit unit are substantially the same, in order to avoid the data via being located in the pixel opening, ensure the flatness of the anode, and improve the color deviation, the present embodiment adopts a compression method to set the pixel driving circuit. In some exemplary embodiments, the compression can be achieved by setting the position of the pixel driving circuit in the first direction X, or by setting the size of the pixel driving circuit in the first direction X, or by setting the structural layout of the pixel driving circuit.

[0361] In an exemplary embodiment, the present embodiment adjusts the spacing between adjacent pixel driving circuits in the first direction X by setting the position of the pixel driving circuit in the first direction X, thereby adjusting the relative position of the data via and the pixel opening to avoid the data via being located in the pixel opening. For example, the pixel driving circuit in the second circuit unit Q2 may be arranged close to the pixel driving circuit in the first circuit unit Q1, and away from the pixel driving circuit in the third circuit unit Q3, so that the data vias in the second circuit unit Q2 and the third circuit unit Q3 avoid the third pixel opening 100C of the third light emitting unit.

[0362] In an exemplary embodiment, the first circuit unit Q1, the second circuit unit Q2, and the third circuit unit Q3 may be sequentially arranged along the first direction X, the first circuit unit Q1 may include at least a first pixel driving circuit, and a first data signal line 61-1 connected to the first pixel driving circuit through a first data via K2-1, the second circuit unit Q2 may include at least a second pixel driving circuit, and a second data signal line 61-2 connected to the second pixel driving circuit through a second data via K2-2, and the third circuit unit Q3 may include at least a third pixel driving circuit, and a third data signal line 61-3 connected to the third pixel driving circuit through a third data via K2-3. In an exemplary embodiment, the data signal line is connected to the pixel driving circuit through the data via, and the data signal line is connected to the pixel driving circuit through the data via, and the data connection electrode is connected to the first region of the fourth active layer through the via.

[0363] In an exemplary embodiment, the first data signal line 61 - 1 and the second data signal line 61 - 2 may have a first interval W1 therebetween, and the second data signal line 61 - 2 and the third data signal line 61 - 3 may have a second interval W2 therebetween, and the first interval W1 is smaller than the second interval W2.

[0364] In an exemplary embodiment, the first spacing W1 may be a distance between an edge of the first data signal line 61-1 on a side close to the second data signal line 61-2 and an edge of the second data signal line 61-2 on a side close to the first data signal line 61-1, or a distance between an edge of the first data signal line 61-1 on a side away from the second data signal line 61-2 and an edge of the second data signal line 61-2 on a side away from the first data signal line 61-1. The second spacing W2 may be a distance between an edge of the second data signal line 61-2 on a side close to the third data signal line 61-3 and an edge of the third data signal line 61-3 on a side close to the second data signal line 61-2, or a distance between an edge of the second data signal line 61-2 on a side away from the third data signal line 61-3 and an edge of the third data signal line 61-3 on a side away from the second data signal line 61-2.

[0365] In an exemplary embodiment, the first data via K2-1 and the second data via K2-2 may have a third interval W3 therebetween, the second data via K2-2 and the third data via K2-3 may have a fourth interval W4 therebetween, and the third interval W3 is smaller than the fourth interval W4.

[0366] In an exemplary embodiment, the third interval W3 may be: the distance between the edge of the first data via K2-1 close to the second data via K2-2 and the edge of the second data via K2-2 close to the first data via K2-1, or the distance between the edge of the first data via K2-1 away from the second data via K2-2 and the edge of the second data via K2-2 away from the first data via K2-1. The fourth interval W4 may be: the distance between the edge of the second data via K2-2 close to the third data via K2-3 and the edge of the third data via K2-3 close to the second data via K2-2, or the distance between the edge of the second data via K2-2 away from the third data via K2-3 and the edge of the third data via K2-3 away from the second data via K2-2.

[0367] In an exemplary embodiment, the orthographic projection of any one or more of the first pixel opening 100A, the second pixel opening 100B, and the third pixel opening 100C on the substrate does not overlap with the orthographic projection of the data vias (including the first data via K2-1, the second data via K2-2, and the third data via K2-3) on the substrate.

[0368] In an exemplary embodiment, in the second direction Y, the first data via hole K2 - 1 may be located between the first pixel opening 100A and the second pixel opening 100B.

[0369] In an exemplary embodiment, a groove may be provided on a side of the second anode 90B close to the first anode 90A, and the groove is configured to avoid the first data via K2 - 1 .

[0370] In an exemplary embodiment, the orthographic projections of the first pixel opening 100A and the second pixel opening 100B on the substrate at least partially overlap with the orthographic projection of the first data signal line 61-1 on the substrate, and the orthographic projections of the first pixel opening 100A and the second pixel opening 100B on the substrate do not overlap with the orthographic projections of the second data signal line 61-2 and the third data signal line 61-3 on the substrate.

[0371] In an exemplary embodiment, in the first direction X, the second data via hole K2 - 2 and the third data via hole K2 - 3 may be located at both sides of the third pixel opening 100C.

[0372] In an exemplary embodiment, an orthographic projection of the third pixel opening 100C on the substrate does not overlap with orthographic projections of the first data signal line 61 - 1 , the second data signal line 61 - 2 , and the third data signal line 61 - 3 on the substrate.

[0373] In an exemplary embodiment, an orthographic projection of any one or more of the first pixel opening 100A, the second pixel opening 100B, and the third pixel opening 100C on the substrate does not overlap with an orthographic projection of the power via K1 and the anode via K3 on the substrate.

[0374] In the exemplary embodiment, unlike the structure in the previous embodiment in which the first power line 71 is connected to the power connection line 44 through the power via K1, the first power line 71 of this embodiment is connected to the power connection electrode through the power via K1. Since the power connection electrode is located on one side of the second direction Y of the power connection line 44, the position of the power via K1 is lowered so that the pixel opening and the power via do not overlap. In this embodiment, the relative position of the power via and the pixel opening is adjusted by adjusting the position of the power via, so that the power via is prevented from being located in the pixel opening, the flatness of the anode is ensured, and the color deviation is improved.

[0375] In an exemplary embodiment, the power via hole K1 may be located at one side of the second pixel opening 100B in the second direction Y, or the power via hole K1 may be located at one side of the third pixel opening 100C in the second direction Y.

[0376] In an exemplary embodiment, unlike the structure of the aforementioned embodiment in which the anode and pixel opening are arranged at a lower position of the circuit unit, the anode and pixel opening of this embodiment are arranged at an upper position of the circuit unit. The relative positions of the data via and the power via and the pixel opening are adjusted by adjusting the positions of the anode and the pixel opening, thereby avoiding the power via being located in the pixel opening, ensuring the flatness of the anode, and improving the color deviation.

[0377] In an exemplary embodiment, in the second direction Y, the first pixel opening 100A, the second pixel opening 100B, and the third pixel opening 100C may be disposed at a region of the corresponding circuit unit close to a previous unit row.

[0378] In an exemplary embodiment, the orthographic projection of at least one first pixel opening 100A on the substrate at least partially overlaps with the orthographic projection of the first initial signal line 41 on the substrate, and the orthographic projection of the first pixel opening 100A on the substrate does not overlap with the orthographic projection of the power connection line 44 on the substrate.

[0379] In an exemplary embodiment, the orthographic projection of at least one second pixel opening 100B on the substrate at least partially overlaps with the orthographic projections of the first scanning signal line 31 and the power connection line 44 on the substrate, and the orthographic projection of the second pixel opening 100B on the substrate does not overlap with the orthographic projections of the first initial signal line 41, the second initial signal line 42 and the second initial signal line 43 on the substrate.

[0380] In an exemplary embodiment, the orthographic projection of at least one third pixel opening 100C on the substrate at least partially overlaps with the orthographic projections of the first scanning signal line 31 and the third scanning signal line 33 on the substrate, and the orthographic projection of the third pixel opening 100C on the substrate does not overlap with the orthographic projections of the second scanning signal line 32, the light emitting signal line 34, the power connection line 44 and the second initial signal line 42 on the substrate.

[0381] In an exemplary embodiment, taking three circuit units as an example, the preparation process of the display substrate of this embodiment may include the following operations.

[0382] (31) Forming a shielding layer pattern. In an exemplary embodiment, forming the shielding layer pattern may include: depositing a shielding film on a substrate, patterning the shielding film through a patterning process, and forming a shielding layer pattern on the substrate, such as Fig.19 shown.

[0383] In an exemplary embodiment, the shielding layer pattern of each circuit unit may include at least a shielding electrode 90, a first shielding connection bar 91, a second shielding connection bar 92, a third shielding connection bar 93, a first shielding block 94 and a second shielding block 95, and the above structure is basically the same as the previous embodiment.

[0384] In an exemplary embodiment, the shielding layer pattern in the second circuit unit Q2 is close to the shielding layer pattern in the first circuit unit Q1, and away from the shielding layer pattern in the third circuit unit Q3, that is, the distance between the shielding layer pattern in the first circuit unit Q1 and the shielding layer pattern in the second circuit unit Q2 is smaller than the distance between the shielding layer pattern in the second circuit unit Q2 and the shielding layer pattern in the third circuit unit Q3. For example, the shielding electrode 90 in the first circuit unit Q1 and the shielding electrode 90 in the second circuit unit Q2 have an eleventh spacing W11, and the shielding electrode 90 in the second circuit unit Q2 and the shielding electrode 90 in the third circuit unit Q3 have a twelfth spacing W12, and the eleventh spacing W11 is smaller than the twelfth spacing W12.

[0385] (32) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: depositing a first insulating film and a semiconductor film in sequence on the substrate on which the aforementioned pattern is formed, patterning the semiconductor film through a patterning process to form a first insulating layer covering the shielding layer, and a semiconductor layer pattern disposed on the first insulating layer, such as Fig. 20A and Fig. 20B As shown, Fig. 20B for Fig. 20A Schematic diagram of the semiconductor layer in the figure.

[0386] In an exemplary embodiment, the semiconductor layer pattern of each circuit unit may include at least first to eighth active layers 11 to 18 , and a first preliminary signal line 41 , and the above structure is substantially the same as the aforementioned embodiment.

[0387] In an exemplary embodiment, a first initial connection block 41-1 may be provided on the first initial signal line, and the first initial connection block 41-1 is configured to be connected to the subsequently formed initial connection line, so that the first initial signal line extending along the first direction and the initial connection line extending along the second direction form a meshed connection structure for transmitting the first initial signal.

[0388] In an exemplary embodiment, the semiconductor layer pattern in the second circuit unit Q2 is close to the semiconductor layer pattern in the first circuit unit Q1, and is far away from the semiconductor layer pattern in the third circuit unit Q3, that is, the distance between the semiconductor layer pattern in the first circuit unit Q1 and the semiconductor layer pattern in the second circuit unit Q2 is smaller than the distance between the semiconductor layer pattern in the second circuit unit Q2 and the semiconductor layer pattern in the third circuit unit Q3. For example, the first active layer 11 in the first circuit unit Q1 and the first active layer 11 in the second circuit unit Q2 have a twenty-first interval W21, and the first active layer 11 in the second circuit unit Q2 and the first active layer 11 in the third circuit unit Q3 have a twenty-second interval W22, and the twenty-first interval W21 is smaller than the twenty-second interval W22.

[0389] (33) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: depositing a second insulating film and a first conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the first conductive film through a patterning process to form a second insulating layer covering the semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer, such as Fig.21A and Fig.21B As shown, Fig.21B for Fig.21A Schematic plan view of the first conductive layer in FIG.

[0390] In an exemplary embodiment, the first conductive layer pattern of each circuit unit includes at least: a first gate electrode 21, a second gate electrode 22, a fourth gate electrode 24, a second scanning signal line 32, a light emitting signal line 34 and a first electrode plate 81 of a storage capacitor, and the above structure is substantially the same as the aforementioned embodiment.

[0391] In an exemplary embodiment, the first conductive layer pattern in the second circuit unit Q2 is close to the first conductive layer pattern in the first circuit unit Q1, and is far away from the first conductive layer pattern in the third circuit unit Q3, that is, the distance between the first conductive layer pattern in the first circuit unit Q1 and the first conductive layer pattern in the second circuit unit Q2 is smaller than the distance between the first conductive layer pattern in the second circuit unit Q2 and the first conductive layer pattern in the third circuit unit Q3. For example, there is a thirty-first spacing W31 between the first electrode plate 81 in the first circuit unit Q1 and the first electrode plate 81 in the second circuit unit Q2, and there is a thirty-second spacing W32 between the first electrode plate 81 in the second circuit unit Q2 and the first electrode plate 81 in the third circuit unit Q3, and the thirty-first spacing W31 is smaller than the thirty-second spacing W32.

[0392] (34) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: depositing a third insulating film and a second conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the second conductive film using a patterning process to form a third insulating layer covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer, such as Fig.22A and Fig. 22B As shown, Fig. 22B for Fig.22A Schematic plan view of the second conductive layer in FIG.

[0393] In an exemplary embodiment, the second conductive layer pattern of each circuit unit includes at least: a second plate 82 of the storage capacitor and a shielding electrode 35 , and the above structure is substantially the same as the above embodiment.

[0394] In an exemplary embodiment, the second conductive layer pattern in the second circuit unit Q2 is close to the second conductive layer pattern in the first circuit unit Q1, and is far away from the second conductive layer pattern in the third circuit unit Q3, that is, the distance between the second conductive layer pattern in the first circuit unit Q1 and the second conductive layer pattern in the second circuit unit Q2 is smaller than the distance between the second conductive layer pattern in the second circuit unit Q2 and the second conductive layer pattern in the third circuit unit Q3. For example, the second electrode plate 82 in the first circuit unit Q1 and the second electrode plate 82 in the second circuit unit Q2 have a 41st spacing W41, and the second electrode plate 82 in the second circuit unit Q2 and the second electrode plate 82 in the third circuit unit Q3 have a 42nd spacing W42, and the 41st spacing W41 is smaller than the 42nd spacing W42.

[0395] (35) Forming a fourth insulating layer pattern. In an exemplary embodiment, forming the fourth insulating layer pattern may include: depositing a fourth insulating film on the substrate on which the aforementioned pattern is formed, patterning the fourth insulating film using a patterning process to form a fourth insulating layer covering the second conductive layer, wherein a plurality of via holes are disposed on the fourth insulating layer, such as Fig.23 shown.

[0396] In an exemplary embodiment, the plurality of via holes of each circuit unit includes at least first to fourteenth via holes V1 to V14 , and the structures of the first to thirteenth via holes V1 to V13 are substantially the same as those of the aforementioned embodiment.

[0397] In an exemplary embodiment, the fourth insulating layer of at least one circuit unit may further include a fourteenth via hole V14. The orthographic projection of the fourteenth via hole V14 on the substrate is located within the range of the orthographic projection of the first initial connection block 41-1 on the substrate, the fourth insulating layer, the third insulating layer, and the second insulating layer in the fourteenth via hole V14 are etched away to expose the surface of the first initial connection block 41-1, and the fourteenth via hole V14 is configured to connect the subsequently formed sixth connection electrode to the first initial connection block 41-1 through the via hole.

[0398] (36) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer may include: depositing a third conductive film on the substrate having the aforementioned pattern, patterning the third conductive film using a patterning process, and forming a third conductive layer disposed on the fourth insulating layer, such as Fig.24A and Fig. 24B As shown, Fig. 24B for Fig.24A Schematic plan view of the third conductive layer in FIG.

[0399] In an exemplary embodiment, the third conductive layer of each circuit unit includes at least: a first scan signal line 31, a third scan signal line 33, a second initial signal line 42, a third initial signal line 43, a power connection line 44, an auxiliary scan signal line 45, a first connection electrode 51, a second connection electrode 52, a third connection electrode 53, a fourth connection electrode 54 and a fifth connection electrode 55, and the above structure is basically the same as the aforementioned embodiment.

[0400] In an exemplary embodiment, the third conductive layer of at least one circuit unit may further include a sixth connection electrode 56. The shape of the sixth connection electrode 56 may be a block shape (such as a rectangle), and the sixth connection electrode 56 is connected to the first initial connection block 41-1 through the fourteenth via hole V14. In an exemplary embodiment, the sixth connection electrode 56 is configured to connect the initial connection line formed subsequently.

[0401] In an exemplary embodiment, the third conductive layer pattern in the second circuit unit Q2 is close to the third conductive layer pattern in the first circuit unit Q1, and is far away from the third conductive layer pattern in the third circuit unit Q3, that is, the distance between the third conductive layer pattern in the first circuit unit Q1 and the third conductive layer pattern in the second circuit unit Q2 is smaller than the distance between the third conductive layer pattern in the second circuit unit Q2 and the third conductive layer pattern in the third circuit unit Q3. For example, the third connection electrode 53 in the first circuit unit Q1 and the third connection electrode 53 in the second circuit unit Q2 have a fifty-first interval W51, and the third connection electrode 53 in the second circuit unit Q2 and the third connection electrode 53 in the third circuit unit Q3 have a fifty-second interval W52, and the fifty-first interval W51 is smaller than the fifty-second interval W52.

[0402] (37) Forming a first planar layer pattern. In an exemplary embodiment, forming the first planar layer pattern may include: coating a first planar film on the substrate on which the aforementioned pattern is formed, patterning the first planar film using a patterning process to form a first planar layer covering the third conductive layer, wherein a plurality of via holes are disposed on the first planar layer, such as Fig.25 shown.

[0403] In an exemplary embodiment, the plurality of vias of each circuit unit includes at least a twenty-first via V21 , a twenty-second via V22 , and a twenty-third via V23 , and the structures of the twenty-first via V21 and the twenty-second via V22 are substantially the same as those of the previous embodiments.

[0404] In an exemplary embodiment, the orthographic projection of the twenty-third via hole V23 on the substrate is within the range of the orthographic projection of the fourth connection electrode 54 on the substrate, the first flat layer in the twenty-third via hole V23 is removed, exposing the surface of the fourth connection electrode 54, and the twenty-third via hole V23 is configured to connect a first power line formed subsequently to the fourth connection electrode 54 through the via hole. In an exemplary embodiment, the twenty-third via hole V23 may be referred to as a power via hole.

[0405] In an exemplary embodiment, the 21st via hole V21 may be used as a data via hole. Since the pixel driving circuit in the second circuit unit Q2 is close to the pixel driving circuit in the first circuit unit Q1 and far away from the pixel driving circuit in the third circuit unit Q3, the 21st via hole V21 in the second circuit unit Q2 is close to the 21st via hole V21 in the first circuit unit Q1 and far away from the 21st via hole V21 in the third circuit unit Q3.

[0406] In an exemplary embodiment, there is a third spacing W3 between the twenty-first via hole V21 (first data via hole) in the first circuit unit Q1 and the twenty-first via hole V21 (second data via hole) in the second circuit unit Q2, and there is a fourth spacing W4 between the twenty-first via hole V21 (second data via hole) in the second circuit unit Q2 and the twenty-first via hole V21 (third data via hole) in the third circuit unit Q3, and the third spacing W3 is smaller than the fourth spacing W4, so that the twenty-first via hole V21 in the second circuit unit Q2 and the third circuit unit Q3 can avoid the pixel opening formed subsequently, thereby ensuring the flatness of the anode and improving the color deviation.

[0407] In an exemplary embodiment, the third spacing W3 may be: the distance between an edge of the twenty-first via V21 in the first circuit unit Q1 that is close to the twenty-first via V21 in the second circuit unit Q2 and an edge of the twenty-first via V21 in the second circuit unit Q2 that is close to the twenty-first via V21 in the first circuit unit Q1, or, may be the distance between an edge of the twenty-first via V21 in the first circuit unit Q1 that is away from the twenty-first via V21 in the second circuit unit Q2 and an edge of the twenty-first via V21 in the second circuit unit Q2 that is away from the twenty-first via V21 in the first circuit unit Q1. The fourth spacing W4 may be: the distance between an edge of the twenty-first via V21 in the second circuit unit Q2 close to the twenty-first via V21 in the third circuit unit Q3 and an edge of the twenty-first via V21 in the third circuit unit Q3 close to the twenty-first via V21 in the second circuit unit Q2, or the distance between an edge of the twenty-first via V21 in the second circuit unit Q2 away from the twenty-first via V21 in the third circuit unit Q3 and an edge of the twenty-first via V21 in the third circuit unit Q3 away from the twenty-first via V21 in the second circuit unit Q2.

[0408] In an exemplary embodiment, the first flat layer of at least one circuit unit may further include a twenty-fourth via hole V24. The orthographic projection of the twenty-fourth via hole V24 on the substrate is located within the range of the orthographic projection of the sixth connection electrode 56 on the substrate, the first flat layer in the twenty-fourth via hole V24 is removed, and the surface of the sixth connection electrode 56 is exposed. The twenty-fourth via hole V24 is configured to allow an initial connection line formed subsequently to be connected to the sixth connection electrode 56 through the via hole.

[0409] (38) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer may include: depositing a fourth conductive film on the substrate having the aforementioned pattern, patterning the third conductive film using a patterning process, and forming a fourth conductive layer disposed on the first planar layer, such as Fig.26A and Fig.26BAs shown, Fig.26B for Fig.26A Schematic plan view of the fourth conductive layer in FIG.

[0410] In an exemplary embodiment, the fourth conductive layer of each circuit unit includes at least a data signal line 61 , an anode connection electrode 62 , and a first power line 71 .

[0411] In an exemplary embodiment, the shape of the data signal line 61 may be a straight line or a folded line extending along the second direction Y, and the data signal line 61 is connected to the third connection electrode 53 through the twenty-first via hole V21. Since the third connection electrode 53 is connected to the first region of the fourth active layer, the data signal line 61 can write the data signal to the first electrode of the fourth transistor T4.

[0412] In an exemplary embodiment, the positions of the data signal lines 61 in the first circuit unit Q1 , the second circuit unit Q2 , and the third circuit unit Q3 may be substantially the same, and the data signal lines 61 may all be located on one side of the first direction X of the first power line 71 .

[0413] In an exemplary embodiment, the fourth conductive layer pattern in the second circuit unit Q2 is close to the fourth conductive layer pattern in the first circuit unit Q1, and is far away from the fourth conductive layer pattern in the third circuit unit Q3, that is, the distance between the fourth conductive layer pattern in the first circuit unit Q1 and the fourth conductive layer pattern in the second circuit unit Q2 is smaller than the distance between the fourth conductive layer pattern in the second circuit unit Q2 and the fourth conductive layer pattern in the third circuit unit Q3. For example, the data signal line 61 in the first circuit unit Q1 and the data signal line 61 in the second circuit unit Q2 have a first spacing W1, and the data signal line 61 in the second circuit unit Q2 and the data signal line 61 in the third circuit unit Q3 have a second spacing W2, and the first spacing W1 is smaller than the second spacing W2.

[0414] In an exemplary embodiment, the first interval W1 may be a distance between an edge of the data signal line 61 in the first circuit unit Q1 close to the data signal line 61 in the second circuit unit Q2 and an edge of the data signal line 61 in the second circuit unit Q2 close to the data signal line 61 in the first circuit unit Q1, or a distance between an edge of the data signal line 61 in the first circuit unit Q1 away from the data signal line 61 in the second circuit unit Q2 and an edge of the data signal line 61 in the second circuit unit Q2 away from the data signal line 61 in the first circuit unit Q1. The second interval W2 may be a distance between an edge of the data signal line 61 in the second circuit unit Q2 close to the data signal line 61 in the third circuit unit Q3 and an edge of the data signal line 61 in the third circuit unit Q3 close to the data signal line 61 in the second circuit unit Q2, or a distance between an edge of the data signal line 61 in the second circuit unit Q2 away from the data signal line 61 in the third circuit unit Q3 and an edge of the data signal line 61 in the third circuit unit Q3 away from the data signal line 61 in the second circuit unit Q2.

[0415] In an exemplary embodiment, the shape of the anode connection electrode 62 may be a block shape (eg, a rectangular shape), and the anode connection electrode 62 is configured to be connected to an anode to be formed subsequently.

[0416] In an exemplary embodiment, the anode connection electrode 62 of the circuit unit in the first circuit unit Q1 can be arranged on the side opposite to the second direction Y of the power connection line 44 in the circuit unit, and the anode connection electrode 62 is connected to the fifth connection electrode 55 through the anode connection line 63.

[0417] In an exemplary embodiment, the fourth conductive layer of the circuit unit in the first circuit unit Q1 may also include an anode connecting line 63, and the shape of the anode connecting line 63 may be a strip shape extending along the second direction Y. The first end of the anode connecting line 63 is connected to the anode connecting electrode 62, and the second end of the anode connecting line 63 extends along the second direction Y toward the direction close to the fifth connecting electrode 55, and is connected to the fifth connecting electrode 55 through the twenty-second via hole V22.

[0418] In an exemplary embodiment, in at least one circuit unit, the anode connection electrode 62 and the anode connection line 63 may be an integral structure connected to each other.

[0419] In an exemplary embodiment, the anode connection electrode 62 of the circuit unit in the second circuit unit Q2 and the third circuit unit Q3 can be arranged on one side of the power connection line 44 in the second direction Y in the circuit unit, and the anode connection electrode 62 is connected to the fifth connection electrode 55 through the twenty-second via hole V22.

[0420] In an exemplary embodiment, the fourth conductive layer in the second circuit unit Q2 and the third circuit unit Q3 may further include an extended electrode 64, the shape of the extended electrode 64 may be a strip shape extending along the second direction Y, the first end of the extended electrode 64 is connected to the anode connecting electrode 62, the second end of the extended electrode 64 extends in the opposite direction of the second direction Y, and the extended electrode 64 is configured to improve the flatness of the anode.

[0421] In an exemplary embodiment, in at least one circuit unit, the anode connection electrode 62 and the extension electrode 64 may be an integral structure connected to each other.

[0422] In an exemplary embodiment, the shape of the first power line 71 may be a straight line or a folded line extending along the second direction Y. The first power line 71 may be provided in each circuit unit, and the first power line 71 is connected to the fourth connection electrode 54 through the twenty-third via hole V23. Since the fourth connection electrode 54 is connected to the power connection line 44, the power connection line 44 extending along the first direction X of the main body and the first power line 71 extending along the second direction Y of the main body are connected to each other, so that the first power line 71 and the power connection line 44 form a meshed connection structure for transmitting the first power signal on the display substrate, which can not only effectively reduce the resistance of the first power line 71 and reduce the voltage drop of the first power signal, but also effectively improve the uniformity of the first power signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality.

[0423] In an exemplary embodiment, unlike the structure of the aforementioned embodiment in which the first power line 71 is connected to the power connection line 44 through the twenty-third via hole V23, the first power line 71 of this embodiment is connected to the fourth connection electrode 54 serving as the power connection electrode through the twenty-third via hole V23. Since the fourth connection electrode 54 is located on one side of the second direction Y of the power connection line 44, the position of the twenty-third via hole V23 is lowered so that the pixel opening formed subsequently does not overlap with the twenty-third via hole V23.

[0424] In an exemplary embodiment, the orthographic projection of the first power line 71 on the substrate at least partially overlaps with the orthographic projection of the first connection electrode 51 on the substrate, so the constant voltage first power line 71 can effectively shield the influence of other signals in the pixel driving circuit on the first node N1.

[0425] In an exemplary embodiment, the fourth conductive layer of a part of the circuit unit may further include an initial connection line 73, the shape of the initial connection line 73 may be a straight line or a folded line extending along the second direction Y, the initial connection line 73 may be provided in the first circuit unit Q1, and the initial connection line 73 may be connected to the sixth connection electrode 56 through the twenty-fourth via hole V24. Since the sixth connection electrode 56 is connected to the first initial connection block 41-1, and the first initial connection block 41-1 is connected to the first initial signal line 41, the first initial signal line extending along the first direction X in the main part and the initial connection line extending along the second direction Y in the main part form a mesh-like mesh connection structure for transmitting the first initial signal on the display substrate, which can not only effectively reduce the resistance of the first initial signal line, reduce the voltage drop of the first initial signal, but also effectively improve the uniformity of the first initial signal, effectively improve the display uniformity, and improve the display quality and display quality.

[0426] In some possible embodiments, the initial connection line can be connected to the second initial signal line through a via, so that the second initial signal line and the initial connection line form a mesh-like network connection structure for transmitting the second initial signal on the display substrate, or the initial connection line can be connected to the third initial signal line through a via, so that the third initial signal line and the initial connection line form a mesh-like network connection structure for transmitting the third initial signal on the display substrate, and the present disclosure is not limited here.

[0427] In some possible implementations, the fourth conductive layer of at least one circuit unit may further include a second power line to form a VSS in pixel structure, which is not limited in the present disclosure.

[0428] (39) Forming a second planar layer pattern. In an exemplary embodiment, forming the second planar layer pattern may include: coating a second planar film on the substrate on which the aforementioned pattern is formed, patterning the first planar film using a patterning process to form a second planar layer covering the fourth conductive layer, and providing a plurality of via holes on the second planar layer, such as Fig. 27 shown.

[0429] In an exemplary embodiment, the plurality of vias of each circuit unit includes at least an anode via V30. The orthographic projection of the anode via V30 on the substrate is within the range of the orthographic projection of the anode connection electrode 62 on the substrate, the second flat layer in the anode via V30 is removed, exposing the surface of the anode connection electrode 62, and the anode connection electrode is configured to connect a subsequently formed anode to the anode connection electrode 62 through the via.

[0430] (40) Forming an anode conductive layer pattern. In an exemplary embodiment, forming the anode conductive layer pattern may include: depositing an anode conductive film on the substrate formed with the aforementioned pattern, patterning the anode conductive film using a patterning process to form an anode conductive layer disposed on the second flat layer, wherein the anode conductive layer includes at least a plurality of anode patterns, such as Fig.28A and Fig.28B As shown, Fig.28B for Fig.28A Schematic diagram of the plan view of the anode conductive layer.

[0431] In an exemplary embodiment, the plurality of anodes may include a first anode 90A located in a red light emitting unit, a second anode 90B located in a green light emitting unit, and a third anode 90C located in a blue light emitting unit, the first anode 90A and the second anode 90B may be arranged sequentially along the second direction Y, and the third anode 90C may be arranged on one side of the first direction X of the first anode 90A and the second anode 90B.

[0432] In an exemplary embodiment, the first anode 90A, the second anode 90B, and the third anode 90C may be connected to the anode connection electrode 62 of the corresponding circuit unit through the anode via hole V30 , respectively.

[0433] In an exemplary embodiment, at least one of the first anode 90A, the second anode 90B and the third anode 90C may include an anode body portion and an anode connecting portion connected to each other, the anode connecting portion being connected to the anode body portion on one hand and to the anode connecting electrode 62 through the anode via V30 on the other hand.

[0434] In an exemplary embodiment, the orthographic projection of the first anode body portion on the substrate does not overlap with the orthographic projection of the twenty-first via V21 as a data via and the twenty-third via V23 as a power via on the substrate, and the orthographic projection of the first anode body portion on the substrate does not overlap with the orthographic projection of the anode via V30 on the substrate.

[0435] In an exemplary embodiment, since the first anode 90A, the second anode 90B and the third anode 90C are moved upward as a whole, the orthographic projection of the first anode main body on the substrate at least partially overlaps with the orthographic projection of the first initial signal line 41 on the substrate, and the orthographic projection of the first anode main body on the substrate does not overlap with the orthographic projection of the power connection line 44 on the substrate.

[0436] In an exemplary embodiment, the second anode body may be provided with a groove 90-1. The groove 90-1 may be in a block shape (e.g., rectangular) and may be located on an edge of the second anode body close to the first anode 90A. The groove 90-1 is configured to avoid the twenty-first via hole V21, so that the orthographic projection of the second anode body on the substrate does not overlap with the orthographic projection of the twenty-first via hole V21 on the substrate as a data via hole.

[0437] In an exemplary embodiment, since the first anode 90A, the second anode 90B and the third anode 90C are moved upward as a whole, and the twenty-first via V21 serving as the power via is moved downward, the orthographic projection of the second anode body on the substrate does not overlap with the orthographic projection of the twenty-third via V23 serving as the power via on the substrate.

[0438] In an exemplary embodiment, since the first anode 90A, the second anode 90B and the third anode 90C are moved upward as a whole, the orthographic projection of the second anode body on the substrate at least partially overlaps with the orthographic projection of the first scanning signal line 31 and the power connection line 44 on the substrate, and the orthographic projection of the second anode body on the substrate does not overlap with the orthographic projection of the first initial signal line 41, the second initial signal line 42 and the second initial signal line 43 on the substrate.

[0439] In an exemplary embodiment, due to pixel compression, the distance between the data via in the second circuit unit Q2 and the data via in the third circuit unit Q3 is increased, so that the twenty-first via V21 in the second circuit unit Q2 and the twenty-first via V21 in the third circuit unit Q3 are respectively located on both sides of the first direction X of the third anode body, and the distance between the twenty-first via V21 in the second circuit unit Q2 and the twenty-first via V21 in the third circuit unit Q3 is greater than the width of the third anode body in the first direction X, so that the orthographic projection of the third anode body on the substrate does not overlap with the orthographic projection of the twenty-first via V21 serving as the data via on the substrate.

[0440] In an exemplary embodiment, since the first anode 90A, the second anode 90B and the third anode 90C are moved upward as a whole, and the twenty-first via V21 serving as the power via is moved downward, the orthographic projection of the third anode body on the substrate does not overlap with the orthographic projection of the twenty-third via V23 serving as the power via on the substrate.

[0441] In an exemplary embodiment, since the first anode 90A, the second anode 90B and the third anode 90C are moved upward as a whole, the orthographic projection of the third anode body on the substrate at least partially overlaps with the orthographic projections of the first scanning signal line 31 and the third scanning signal line 33 on the substrate, and the orthographic projection of the third anode body on the substrate does not overlap with the orthographic projections of the second scanning signal line 32, the light-emitting signal line 34, the power connection line 44 and the second initial signal line 42 on the substrate.

[0442] (41) Forming a pixel definition layer pattern. In an exemplary embodiment, forming the pixel definition layer pattern may include: coating a pixel definition film on a substrate formed with the aforementioned pattern, patterning the pixel definition film using a patterning process to form a pixel definition layer pattern covering the anode conductive layer pattern, wherein a plurality of pixel openings are provided on the pixel definition layer, such as Fig.29 shown.

[0443] In an exemplary embodiment, the plurality of pixel openings may be a first pixel opening 100A, a second pixel opening 100B, and a third pixel opening 100C, and the structure is substantially the same as that of the aforementioned embodiment.

[0444] In an exemplary embodiment, any one or more of the first pixel opening 100A, the second pixel opening 100B and the third pixel opening 100C have an orthographic projection on the substrate that does not overlap with an orthographic projection of the twenty-first via hole V21 on the substrate as a data via hole, have an orthographic projection on the substrate that does not overlap with an orthographic projection of the twenty-first via hole V21 on the substrate as a power via hole, and have an orthographic projection on the substrate that does not overlap with an orthographic projection of the anode via hole on the substrate.

[0445] In an exemplary embodiment, in the second direction Y, the first pixel opening 100A, the second pixel opening 100B, and the third pixel opening 100C may be disposed at a region of the corresponding circuit unit close to a previous unit row.

[0446] In an exemplary embodiment, the orthographic projection of at least one first pixel opening 100A on the substrate at least partially overlaps with the orthographic projection of the first initial signal line 41 on the substrate, and the orthographic projection of the first pixel opening 100A on the substrate does not overlap with the orthographic projection of the power connection line 44 on the substrate.

[0447] In an exemplary embodiment, the orthographic projection of at least one first pixel opening 100A on the substrate also at least partially overlaps with the orthographic projection of the third initial signal line 43 on the substrate, and the orthographic projection of at least one first pixel opening 100A on the substrate also does not overlap with the orthographic projections of the first scanning signal line 31, the second scanning signal line 32, the third scanning signal line 33, the light-emitting signal line 34 and the second initial signal line 42 on the substrate.

[0448] In an exemplary embodiment, the orthographic projection of at least one second pixel opening 100B on the substrate at least partially overlaps with the orthographic projections of the first scanning signal line 31 and the power connection line 44 on the substrate, and the orthographic projection of the second pixel opening 100B on the substrate does not overlap with the orthographic projections of the first initial signal line 41, the second initial signal line 42 and the second initial signal line 43 on the substrate.

[0449] In an exemplary embodiment, the orthographic projection of the at least one second pixel opening 100B on the substrate also does not overlap with the orthographic projections of the second scan signal line 32 , the third scan signal line 33 , and the light emitting signal line 34 on the substrate.

[0450] In an exemplary embodiment, the orthographic projection of at least one third pixel opening 100C on the substrate at least partially overlaps with the orthographic projections of the first scanning signal line 31 and the third scanning signal line 33 on the substrate, and the orthographic projection of the third pixel opening 100C on the substrate does not overlap with the orthographic projections of the second scanning signal line 32, the light emitting signal line 34, the power connection line 44 and the second initial signal line 42 on the substrate.

[0451] In an exemplary embodiment, an orthographic projection of the at least one third pixel opening 100C on the substrate also at least partially overlaps with orthographic projections of the first preliminary signal line 41 and the third preliminary signal line 43 on the substrate.

[0452] In an exemplary embodiment, the subsequent preparation process may include forming an organic light emitting layer, a cathode and an encapsulation structure layer, and the above structures are substantially the same as those in the previous embodiment.

[0453] The display substrate provided by the exemplary embodiments of the present disclosure has the technical effects of the aforementioned embodiments, and by adopting technical means such as pixel compression to adjust the spacing between data vias, moving the anode upward as a whole, and moving the power via downward, there are no data vias and power vias within the range of the pixel opening, and the anode exposed by the pixel opening has good flatness, which can effectively avoid defects such as screen-off watermarks caused by poor anode flatness, can effectively improve color deviation, and improve display quality.

[0454] The structure and preparation process shown above in the present disclosure are merely exemplary. In an exemplary embodiment, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs, and the present disclosure does not limit this.

[0455] In an exemplary embodiment, the display substrate of the present disclosure can be applied to a display device having a pixel driving circuit, such as OLED, quantum dot display (QLED), light emitting diode display (Micro LED or Mini LED) or quantum dot light emitting diode display (QDLED), etc., which is not limited in the present disclosure.

[0456] The present disclosure also provides a method for preparing a display substrate to manufacture the display substrate provided in the above embodiment. In an exemplary embodiment, the preparation method may include:

[0457] A driving structure layer is formed on a substrate, wherein the driving structure layer includes a plurality of circuit units, at least one of which includes a pixel driving circuit, a power connection line extending along a first direction, and a first power line extending along a second direction, wherein the first direction intersects the second direction, the pixel driving circuit includes at least a power connection electrode, the power connection electrode is connected to the power connection line, and the first power line is connected to the power connection line or the power connection electrode through a power via;

[0458] A light-emitting structure layer is formed on the driving structure layer; the light-emitting structure layer includes a plurality of light-emitting units, at least one of the light-emitting units includes an anode and a pixel definition layer arranged on a side of the anode away from the substrate, the anode is connected to a pixel driving circuit of a corresponding circuit unit, the pixel definition layer is provided with a pixel opening exposing the anode, and the orthographic projection of at least one pixel opening on the substrate does not overlap with the orthographic projection of the power via on the substrate.

[0459] The present disclosure also provides a display device, which includes the aforementioned display substrate. The display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc., but the embodiments of the present invention are not limited thereto.

[0460] Although the embodiments disclosed in the present disclosure are as above, it should be noted that the above embodiments are merely exemplary and not restrictive. Therefore, the present disclosure is not limited to the contents specifically shown and described herein. Various modifications, substitutions or omissions may be made to the forms and details of the implementation without departing from the scope of the present disclosure.

Claims

1. A display substrate, characterized in that: It includes a driving structure layer arranged on a substrate and a light-emitting structure layer arranged on a side of the driving structure layer away from the substrate; on a plane parallel to the display substrate, the driving structure layer includes a plurality of circuit units, at least one circuit unit includes a pixel driving circuit, a power connection line extending along a first direction, and a first power line extending along a second direction, the first direction and the second direction intersect, the pixel driving circuit at least includes a power connection electrode, the power connection electrode is connected to the power connection line, and the first power line is connected to the power connection line or the power connection electrode through a power via; the light-emitting structure layer includes a plurality of light-emitting units, at least one light-emitting unit includes an anode and a pixel definition layer arranged on a side of the anode away from the substrate, the anode is connected to the pixel driving circuit of the corresponding circuit unit, the pixel definition layer is provided with a pixel opening exposing the anode, and the orthographic projection of at least one pixel opening on the substrate does not overlap with the orthographic projection of the power via on the substrate.

2. The display substrate according to claim 1, characterized in that: The plurality of light-emitting units at least include a first light-emitting unit emitting a first color light, a second light-emitting unit emitting a second color light, and a third light-emitting unit emitting a third color light, wherein the first light-emitting unit at least includes a first anode and a first pixel opening exposing the first anode, the second light-emitting unit at least includes a second anode and a second pixel opening exposing the second anode, and the third light-emitting unit at least includes a third anode and a third pixel opening exposing the third anode; The second anode is arranged on one side of the first anode in the second direction, and the third anode is arranged on one side of the first anode in the first direction; the orthographic projections of the first pixel opening and the second pixel opening on the substrate at least partially overlap with the orthographic projection of the first power line on the substrate, and the orthographic projection of the third pixel opening on the substrate does not overlap with the orthographic projection of the first power line on the substrate.

3. The display substrate according to claim 2, characterized in that: The orthographic projections of the first pixel opening and the second pixel opening on the substrate are located within a range of the orthographic projection of the first power line on the substrate.

4. The display substrate according to claim 2, characterized in that: In at least one circuit unit and a circuit unit adjacent to the first direction, the first power lines in the two circuit units are an integrated structure connected to each other.

5. The display substrate according to claim 2, characterized in that: At least one circuit unit also includes a data signal line. In at least one circuit unit and the circuit units adjacent to each other in the first direction, the data signal line in one circuit unit is arranged on the side of the first power line in the opposite direction of the first direction, and the data signal line in another circuit unit is arranged on the side of the first power line in the first direction; the orthographic projections of the first pixel opening and the second pixel opening on the substrate do not overlap with the orthographic projections of the data signal line on the substrate, and the orthographic projection of the third pixel opening on the substrate at least partially overlaps with the orthographic projection of the data signal line on the substrate.

6. The display substrate according to claim 5, characterized in that: The pixel driving circuit also includes a fourth transistor and a data connection electrode, the fourth transistor includes at least a fourth active layer, and the data signal line is connected to the data connection electrode through a data via; in at least one circuit unit and the circuit units adjacent in the first direction, the data connection electrode in one circuit unit is connected to the first area of ​​the fourth active layer through a via, and the data connection electrode in another circuit unit is connected to the first area of ​​the fourth active layer through a data connection line.

7. The display substrate according to claim 6, characterized in that: The pixel driving circuit also includes a shielding electrode and a second transistor with a dual-gate structure, the shielding electrode is connected to the first power line, the orthographic projection of the shielding electrode on the substrate at least partially overlaps with the orthographic projection of the second active layer between the two gate electrodes of the second transistor on the substrate, and the orthographic projection of the shielding electrode on the substrate at least partially overlaps with the orthographic projection of the data connection line on the substrate.

8. The display substrate according to claim 5, characterized in that: The pixel driving circuit also includes a fourth node electrode and an anode connecting electrode, and the anode in at least one light-emitting unit is connected to the anode connecting electrode through an anode via hole; in at least one circuit unit and the circuit units adjacent in the first direction, the anode connecting electrode in one circuit unit is connected to the fourth node electrode through a via hole, and the anode connecting electrode in another circuit unit is connected to the fourth node electrode through an anode connecting line; the orthographic projections of the first pixel opening and the second pixel opening on the substrate do not overlap with the orthographic projections of the anode connecting line on the substrate, and the orthographic projections of the third pixel opening on the substrate at least partially overlap with the orthographic projections of the anode connecting line on the substrate.

9. The display substrate according to claim 8, characterized in that: The third pixel opening has an opening center line, which is a straight line extending along the second direction and passing through the geometric center of the third pixel opening; in at least one third pixel opening, the anode connection line has a first distance from the opening center line, and the data signal line has a second distance from the opening center line, and the ratio of the first distance to the second distance is 0.8 to 1.

2.

10. The display substrate according to claim 2, characterized in that: At least one circuit unit also includes at least one initial signal line extending along the first direction, and a second power line and an initial connection line extending along the second direction, the initial connection line is connected to the initial signal line, the orthographic projections of the first pixel opening and the second pixel opening on the substrate do not overlap with the orthographic projections of the second power line and the initial connection line on the substrate, and the orthographic projection of the third pixel opening on the substrate at least partially overlaps with the orthographic projections of the second power line and the initial connection line on the substrate.

11. The display substrate according to claim 10, characterized in that: The third pixel opening has an opening center line, which is a straight line extending along the second direction and passing through the geometric center of the third pixel opening; in at least one third pixel opening, a third distance exists between the second power line and the opening center line, and a fourth distance exists between the initial connection line and the opening center line, and a ratio of the third distance to the fourth distance is 0.8 to 1.

2.

12. The display substrate according to claim 2, characterized in that: The pixel driving circuit also includes a storage capacitor, and at least one circuit unit also includes a first scanning signal line, a second scanning signal line, a third scanning signal line, a light-emitting signal line, a first initial signal line, a second initial signal line and a third initial signal line extending along the first direction and connected to the pixel driving circuit, the first scanning signal line is arranged on a side of the storage capacitor in the opposite direction of the second direction, the third scanning signal line is arranged on a side of the first scanning signal line away from the storage capacitor, the first initial signal line is arranged on a side of the third scanning signal line away from the storage capacitor, the light-emitting signal line is arranged on a side of the storage capacitor in the second direction, and the second scanning signal line is arranged on a side of the light-emitting signal line away from the storage capacitor on one side, the second initial signal line is arranged on the side of the second scanning signal line away from the storage capacitor, and the third initial signal line is arranged on the side of the second initial signal line away from the storage capacitor; the orthographic projection of at least one first pixel opening on the substrate at least partially overlaps with the orthographic projection of the power connection line on the substrate, the orthographic projection of at least one second pixel opening on the substrate at least partially overlaps with the orthographic projections of the first initial signal line, the second initial signal line and the third initial signal line on the substrate, and the orthographic projection of at least one third pixel opening on the substrate at least partially overlaps with the orthographic projections of the second scanning signal line, the light-emitting signal line, the second initial signal line and the power connection line on the substrate.

13. The display substrate according to claim 12, characterized in that: The orthographic projection of at least one first pixel opening on the substrate does not overlap with the orthographic projection of the first initial signal line on the substrate, the orthographic projection of at least one second pixel opening on the substrate does not overlap with the orthographic projection of the first scanning signal line and the power connection line on the substrate, and the orthographic projection of at least one third pixel opening on the substrate does not overlap with the orthographic projection of the first scanning signal line and the third scanning signal line on the substrate.

14. The display substrate according to claim 1, characterized in that: The plurality of light-emitting units at least include a first light-emitting unit emitting a first color light, a second light-emitting unit emitting a second color light, and a third light-emitting unit emitting a third color light, wherein the first light-emitting unit at least includes a first anode and a first pixel opening exposing the first anode, the second light-emitting unit at least includes a second anode and a second pixel opening exposing the second anode, and the third light-emitting unit at least includes a third anode and a third pixel opening exposing the third anode; The second anode is arranged on one side of the first anode in the second direction, and the third anode is arranged on one side of the first anode in the first direction; the pixel driving circuit further comprises a data connection electrode, and at least one circuit unit further comprises a data signal line, and the data signal line is connected to the data connection electrode through a data via hole; The orthographic projections of the first pixel opening, the second pixel opening, and the third pixel opening on the substrate do not overlap with the orthographic projection of the data via on the substrate.

15. The display substrate according to claim 14, characterized in that: The multiple circuit units at least include a first circuit unit, a second circuit unit and a third circuit unit which are sequentially arranged along the first direction, the first circuit unit at least includes a first pixel driving circuit and a first data signal line connected to a data connection electrode in the first pixel driving circuit through a first data via, the second circuit unit at least includes a second pixel driving circuit and a second data signal line connected to a data connection electrode in the second pixel driving circuit through a second data via, the third circuit unit at least includes a third pixel driving circuit and a third data signal line connected to a data connection electrode in the third pixel driving circuit through a third data via; the orthographic projections of the first pixel opening and the second pixel opening on the substrate at least partially overlap with the orthographic projections of the first data signal line on the substrate, and the orthographic projections of the third pixel opening on the substrate do not overlap with the orthographic projections of the first data signal line, the second data signal line and the third data signal line on the substrate.

16. The display substrate according to claim 15, characterized in that: In the first direction, the spacing between the first data signal line and the second data signal line is smaller than the spacing between the second data signal line and the third data signal line, and the spacing between the first data via and the second data via is smaller than the spacing between the second data via and the third data via.

17. The display substrate according to claim 15, characterized in that: In the first direction, the second data via hole and the third data via hole are arranged at both sides of the third pixel opening, and in the second direction, the first data via hole is arranged between the first pixel opening and the second pixel opening.

18. The display substrate according to claim 14, characterized in that: The pixel driving circuit at least includes a storage capacitor, and at least one circuit unit also includes a first scanning signal line, a second scanning signal line, a third scanning signal line, a light-emitting signal line, a first initial signal line, a second initial signal line and a third initial signal line extending along the first direction and connected to the pixel driving circuit, the first scanning signal line is arranged on a side of the storage capacitor in the opposite direction of the second direction, the third scanning signal line is arranged on a side of the first scanning signal line away from the storage capacitor, the first initial signal line is arranged on a side of the third scanning signal line away from the storage capacitor, the light-emitting signal line is arranged on one side of the storage capacitor in the second direction, and the second scanning signal line is arranged on the The light-emitting signal line is arranged on a side away from the storage capacitor, the second initial signal line is arranged on a side away from the storage capacitor of the second scanning signal line, and the third initial signal line is arranged on a side away from the storage capacitor of the second initial signal line; the orthographic projection of at least one first pixel opening on the substrate at least partially overlaps with the orthographic projection of the first initial signal line on the substrate, the orthographic projection of at least one second pixel opening on the substrate at least partially overlaps with the orthographic projections of the first scanning signal line and the power connection line on the substrate, and the orthographic projection of at least one third pixel opening on the substrate at least partially overlaps with the orthographic projections of the first scanning signal line and the third scanning signal line on the substrate.

19. The display substrate according to claim 18, characterized in that: The orthographic projection of at least one first pixel opening on the substrate does not overlap with the orthographic projection of the power connection line on the substrate, the orthographic projection of at least one second pixel opening on the substrate does not overlap with the orthographic projections of the first initial signal line, the second initial signal line and the third initial signal line on the substrate, and the orthographic projection of at least one third pixel opening on the substrate does not overlap with the orthographic projections of the second scanning signal line, the light-emitting signal line, the power connection line and the second initial signal line on the substrate.

20. A display device, characterized in that: The display substrate comprises the display substrate as claimed in any one of claims 1 to 19.

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