Soft start circuit and switching power supply
By designing current source, resistance selection, clock and frequency multiplication control circuits in switching power supplies, an accurate soft start circuit is realized, which solves the problem of low accuracy of traditional soft start circuits and improves system stability and power supply life.
Patent Information
- Application Number
- CN202420627261.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-27
- Publication Date
- 2024-12-13
- Estimated Expiration
- 2034-03-27
AI Technical Summary
Traditional soft-start circuits are difficult to achieve accurate voltage soft start, resulting in waste of inrush current and energy during the startup process of switching power supply, affecting system stability and reliability.
A soft start circuit including a current source circuit, a resistor selection circuit, a clock circuit, a frequency multiplier control circuit and a switch selection circuit are designed. By replacing the reference voltage with a clock cycle frequency multiplier and a rising voltage, the output voltage rise of the error amplifier is accurately controlled. , avoid inrush current.
It achieves soft start with high accuracy and high stability, reduces the damage to the circuit by inrush current, extends the service life of the switching power supply, and reduces the design cost.
Smart Images
Figure CN222169619U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of switching power supplies, in particular to a soft starting circuit and a switching power supply. Background Art
[0002] During the startup of the switching power supply, refer to Figure 1 , because the loop control of the switching power supply has a delay, the reference voltage vref connected to the same-direction input of the error amplifier EA is established before the feedback voltage vfb connected to its reverse input, so that the output of the error amplifier EA is in a high-level state. At this time, the power switch tube is working in the maximum duty cycle state, which in turn generates a peak surge current, causing circuit overvoltage or circuit overheating, and even damage to circuit components. Therefore, it is necessary to use soft start technology to slow down the output mutation of the error amplifier EA and limit the working proportion of the power switch tube to ensure that the output voltage vout has sufficient time to start normally, so as to prevent the surge current and output voltage overcharging from damaging the circuit, reduce energy waste during startup, extend battery life, and improve system stability and reliability.
[0003] However, the traditional soft-start circuit uses a current to control the charging of the capacitor, so that the reference voltage vref of the inverting input of the error amplifier EA rises slowly from zero to the required reference voltage value at a fixed slope during the soft-start phase through the charging time of the fixed reference voltage difference across the capacitor. Assuming that a longer soft-start time is to be set, a large capacitor or a small current is required. If the current is too small, the error is too large and the anti-interference ability is poor. On the other hand, a large capacitor requires a large area inside the chip, with low integration, and external integration requires the addition of current output pins, resulting in high costs. In addition, assuming that the output voltage vout requires different output voltages, it is necessary to set the corresponding reference voltage to control the different charging times for the capacitor under the same charging current and capacitance. In this process, the application environment changes, the temperature process changes, and the power-on rate of the switching power supply changes with changes in temperature and process, resulting in large deviations in the soft-start time and low accuracy. Utility Model Content
[0004] The main purpose of the utility model is to provide a soft start circuit and a switching power supply, aiming to solve the problem that the traditional soft start circuit is difficult to achieve accurate voltage soft start technology.
[0005] The utility model provides a soft start circuit, which is applied to a switching power supply. The switching power supply includes an error amplifier. The soft start circuit includes: a current source circuit; a resistor selection circuit; a clock circuit, wherein the enable end of the clock circuit is used to access an enable signal; the clock circuit is used to output a clock signal according to the enable signal; a frequency multiplication control circuit, wherein the input end of the frequency multiplication control circuit is connected to the output end of the clock circuit, and the output end of the frequency multiplication control circuit is connected to the controlled end of the resistor selection circuit; the frequency multiplication control circuit is used to perform frequency multiplication processing on the period of the clock signal and output the clock frequency multiplication signal to the resistor selection circuit; a switch selection circuit, wherein the enable end of the switch selection circuit is used to access an enable signal. An enable signal is received, a first input terminal of the switch selection circuit is connected to an output terminal of the current source circuit, a second input terminal of the switch selection circuit is used to access a reference voltage, a first output terminal of the switch selection circuit is connected to an input terminal of the resistance selection circuit, and a second output terminal of the switch selection circuit is connected to an input terminal of the error amplifier; the switch selection circuit is used to connect a path between the current source circuit and the resistance selection circuit according to the enable signal so as to output a voltage output from the current source circuit to the resistance selection circuit to the error amplifier, or to disconnect a path between the current source circuit and the resistance selection circuit according to the enable signal so as to output the reference voltage to the error amplifier.
[0006] Optionally, the clock circuit includes: a first switch circuit, a second switch circuit, a charge and discharge circuit, a drive circuit, a control circuit and an output circuit; the input end of the first switch circuit is used to connect to the power supply end, the output end of the first switch circuit is respectively connected to the input end of the second switch circuit, the input end of the control circuit and the input end of the drive circuit, and the connection point between the first switch circuit and the second switch circuit is connected to the input end of the output circuit; the controlled end of the control circuit is connected to the output end of the output circuit, the output end of the control circuit is connected to the input end of the second switch circuit, and the control end of the control circuit is respectively connected to the controlled end of the drive circuit and the controlled end of the charge and discharge circuit; the output end of the drive circuit is connected to the input end of the second switch circuit; the output end of the second switch circuit is used to connect to the ground end; the control circuit is used to turn on / off the path between the first switch circuit and the charge and discharge circuit according to the level signal of the output circuit to control the charge / discharge of the charge and discharge circuit; the drive circuit is used to drive the first switch circuit to output a corresponding level signal to the output circuit according to the voltage of the charge and discharge circuit.
[0007] Optionally, the first switch circuit includes: a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube and an eighth PMOS tube; the input end of the first PMOS tube is used to connect to the power supply end, the controlled end of the first PMOS tube is used to access the enable signal, and the output end of the first PMOS tube is connected to the input end of the control circuit; the input end of the second PMOS tube is used to connect to the power supply end, the controlled end of the second PMOS tube is used to access the enable signal, and the output end of the second PMOS tube is connected to the input end of the control circuit; the input end of the third PMOS tube is used to connect to the power supply end, the controlled end of the third PMOS tube is used to access the enable signal, and the output end of the third PMOS tube is connected to the input end of the drive circuit; the input end of the fourth PMOS tube is used to connect to the power supply end, and the controlled end of the fourth PMOS tube is connected to the input end of the control circuit, The output end of the fourth PMOS tube is connected to the input end of the driving circuit; the input end of the fifth PMOS tube is used to connect to the power supply end, the controlled end of the fifth PMOS tube is connected to the input end of the control circuit, and the output end of the fifth PMOS tube is connected to the input end of the second switch circuit; the input end of the sixth PMOS tube is used to connect to the power supply end, the controlled end of the sixth PMOS tube is connected to the output end of the fourth PMOS tube, and the output end of the sixth PMOS tube is connected to the input end of the second switch circuit; the input end of the seventh PMOS tube is used to connect to the power supply end, the controlled end of the seventh PMOS tube is connected to the output end of the sixth PMOS tube, and the output end of the seventh PMOS tube is connected to the input end of the second switch circuit; the input end of the eighth PMOS tube is used to connect to the power supply end, the controlled end of the eighth PMOS tube is connected to the input end of the control circuit, and the output end of the eighth PMOS tube is connected to the input end of the control circuit.
[0008] Optionally, the second switch circuit includes: a first inverter, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube and a fifth NMOS tube; the controlled end of the first NMOS tube is connected to the output end of the first inverter, the input end of the first NMOS tube is connected to the output end of the control circuit, and the output end of the first NMOS tube is used to connect to the ground end; the controlled end of the second NMOS tube is connected to the output end of the first inverter, the input end of the second NMOS tube is connected to the control end of the control circuit, and the output end of the second NMOS tube is used to connect to the ground end; the controlled end of the third NMOS tube is connected to the output end of the first NMOS The input end of the third NMOS tube is connected to the output end of the control circuit, and the output end of the third NMOS tube is connected to the controlled end of the second NMOS tube; the controlled end of the fourth NMOS tube is connected to the output end of the fifth PMOS tube, the input end of the fourth NMOS tube is connected to the output end of the sixth PMOS tube, and the output end of the fourth NMOS tube is used to connect to the ground end; the controlled end of the fifth NMOS tube is respectively connected to the output end of the sixth PMOS tube and the controlled end of the seventh PMOS tube, and the input end of the fifth NMOS tube is respectively connected to the output end of the seventh PMOS tube.
[0009] Optionally, the driving circuit includes a first switch tube, a fourth switch tube, and a clamp tube, and the control circuit includes a second switch tube and a third switch tube; the input end of the first switch tube is connected to the output end of the first switch circuit, the output end of the first switch tube is connected to the input end of the clamp tube, the output end of the clamp tube is connected to the output end of the fourth switch tube, and their mutual connection point is used to connect to the ground end; the controlled end of the second switch tube is connected to the controlled end of the third switch tube, and their mutual connection point is connected to the input end of the output circuit; the output end of the second switch tube is connected to the input end of the third switch tube, and their mutual connection point is respectively connected to the input end of the charge and discharge circuit, the controlled end of the first switch tube, and the controlled end of the fourth switch tube, and the input end of the fourth switch tube is connected to the output end of the first switch circuit; the output end of the charge and discharge circuit is used to connect to the ground end; the input end of the second switch tube is connected to the output end of the first switch circuit; the output end of the third switch tube is used to connect to the ground end.
[0010] Optionally, the frequency multiplication control circuit includes: a trigger module, the trigger module includes a plurality of triggers, and the plurality of triggers are sequentially connected in series to the output end of the clock circuit.
[0011] Optionally, the resistor selection circuit includes: a resistor module, the resistor module includes multiple resistors, and the multiple resistors are connected in series in sequence to the first output end of the switch selection circuit; a switch tube module, the switch tube module includes multiple switch tubes, the number of the multiple resistors is consistent with the number of the multiple switch tubes, each switch tube is connected in parallel with each resistor, and the controlled end of each switch tube is used to access the clock multiplication signal; the switch tube module is used to turn on / off the path between the switch selection circuit and the resistor module according to the clock multiplication signal.
[0012] Optionally, the switch selection circuit includes: a fourth switch tube, a fifth switch tube and a sixth switch tube; the input end of the fourth switch tube is used to access the reference voltage, and the output end of the fourth switch tube is connected to the input end of the error amplifier; the input end of the fifth switch tube is connected to the output end of the current source circuit, the output end of the fifth switch tube is respectively connected to the input end of the sixth switch tube and the input end of the resistance selection circuit, and the output end of the sixth switch tube is connected to the input end of the error amplifier.
[0013] Optionally, the current source circuit comprises: a current source module, the current source module comprises a plurality of current source switches, and the plurality of current source switches are sequentially connected in parallel to the first input terminal of the switch selection circuit.
[0014] The utility model also provides a switching power supply, which includes an error amplifier and the soft start circuit as described above.
[0015] The utility model proposes a soft start circuit and a switching power supply, wherein the switching power supply includes an error amplifier, and the soft start circuit includes a current source circuit, a resistor selection circuit, a clock circuit, a frequency multiplication control circuit and a switch selection circuit. The clock circuit outputs a clock signal according to an enable signal; the frequency multiplication control circuit performs frequency multiplication processing on the period of the clock signal, and outputs the clock frequency multiplication signal to the resistor selection circuit, so that the resistor selection circuit conducts the path between multiple resistors and the switch selection circuit; the switch selection circuit outputs the current source circuit to the resistor selection circuit voltage according to the enable signal, and outputs it to the error amplifier as a rising voltage, or outputs the reference voltage to the error amplifier according to the enable signal. The utility model uses a rising voltage instead of a reference voltage to access the positive terminal of the error amplifier, so that the output voltage rises slowly, avoiding the surge current generated when the switching power supply is powered on to damage the circuit, and has the characteristics of high precision and high stability. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] In order to more clearly illustrate the embodiments of the utility model or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the utility model. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying creative work.
[0017] Figure 1 A circuit flow chart of the switching power supply described in the background technology;
[0018] Figure 2 It is a circuit flow chart of the soft start circuit and the switching power supply of the utility model;
[0019] Figure 3 This is a circuit structure diagram of the soft start circuit of the utility model;
[0020] Figure 4 It is a circuit structure diagram of the clock circuit of the utility model;
[0021] Figure 5 This is a circuit structure diagram of the frequency multiplication control circuit of the utility model;
[0022] Figure 6 It is a circuit structure diagram of the resistance selection circuit of the utility model;
[0023] Figure 7 This is a circuit structure diagram of the switch selection circuit and the current source circuit of the utility model.
[0024] The realization of the purpose, functional features and advantages of the utility model will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION
[0025] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.
[0026] It should be noted that if the embodiments of the present invention involve directional indications (such as up, down, left, right, front, back...), the directional indications are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.
[0027] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the utility model, the descriptions of "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, if the meaning of "and / or" appearing in the full text is to include three parallel schemes, taking "A and / or B" as an example, it includes scheme A, or scheme B, or a scheme that satisfies both A and B. In addition, the technical solutions between the various embodiments can be combined with each other, but it must be based on the ability of ordinary technicians in this field to implement. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the utility model.
[0028] The traditional soft start circuit uses a current to control the charging of the capacitor. The charging time of the fixed reference voltage difference across the capacitor is used to make the reference voltage vref of the inverting input of the error amplifier EA rise slowly from zero to the required reference voltage value at a fixed slope during the soft start phase. If a longer soft start time is to be set, a large capacitor or a small current is required. If the current is too small, the error is too large and the anti-interference ability is poor. On the other hand, a large capacitor requires a large area inside the chip and has low integration. External integration requires the addition of current output pins, resulting in high costs. In addition, if the output voltage vout requires different output voltages, the corresponding reference voltage needs to be set to control the different charging times for the capacitor under the same charging current and capacitance. In this process, the application environment changes, the temperature process changes, and the power-on rate of the switching power supply changes with temperature and process changes, resulting in large deviations in the soft start time and low accuracy.
[0029] Therefore, in order to realize the precise voltage soft start technology, the utility model proposes a soft start circuit, which is applied to a switching power supply. The switching power supply includes an error amplifier. Figure 2 and Figure 3 , the soft start circuit comprises:
[0030] Current source circuit 500;
[0031] Resistance selection circuit 300;
[0032] A clock circuit 100, wherein the enable terminal of the clock circuit 100 is used to receive an enable signal; the clock circuit 100 is used to output a clock signal according to the enable signal;
[0033] A frequency multiplication control circuit 200, wherein the input end of the frequency multiplication control circuit 200 is connected to the output end of the clock circuit 100, and the output end of the frequency multiplication control circuit 200 is connected to the controlled end of the resistance selection circuit 300; the frequency multiplication control circuit 200 is used to perform frequency multiplication processing on the period of the clock signal and output the clock frequency multiplication signal to the resistance selection circuit 300;
[0034] A switch selection circuit 400, wherein an enable terminal of the switch selection circuit 400 is used to access an enable signal, a first input terminal of the switch selection circuit 400 is connected to an output terminal of the current source circuit 500, a second input terminal of the switch selection circuit 400 is used to access a reference voltage, a first output terminal of the switch selection circuit 400 is connected to an input terminal of the resistor selection circuit 300, and a second output terminal of the switch selection circuit 400 is connected to an input terminal of the error amplifier;
[0035] The switch selection circuit 400 is used to turn on the path between the current source circuit 500 and the resistor selection circuit 300 according to the enable signal so as to output the voltage output from the current source circuit 500 to the resistor selection circuit 300 to the error amplifier, or to disconnect the path between the current source circuit 500 and the resistor selection circuit 300 according to the enable signal so as to output the reference voltage to the error amplifier.
[0036] It is understandable that, referring to Figure 2 The utility model adds a soft start circuit for controlling the soft start period of the reference voltage, replaces the reference voltage vref with a rising voltage vrss and connects to the positive terminal of the error amplifier EA, so that the output voltage vout rises gradually and gradually, avoiding the circuit damage caused by the surge current during the power-on process. Specifically, the utility model proposes a soft start circuit that accurately controls the soft start time through the clock cycle, so that the output voltage vout maintains a high-precision soft start time under different output application conditions. At the same time, before and after the soft start process starts, the voltage of the switching power supply is guaranteed to switch smoothly, thereby improving the voltage stability of the switching power supply. In addition, the soft start circuit of the utility model is smaller in size and easier to integrate, saving the design cost of the switching power supply.
[0037] In this embodiment, refer to Figure 2 , the switching power supply includes an error amplifier EA and a feedback circuit. Figure 3During the soft start process, the enable signal controls the switch selection circuit 400 to conduct the path between the current source circuit 500 and the resistor selection circuit 300, and at the same time controls the switch selection circuit 400 to conduct the path between the current source circuit 500 and the positive terminal of the error amplifier EA, so that the voltage vs of the current source circuit 500 is in an increased state after the resistor selection processing of the resistor selection circuit 300, and outputs the increased voltage vrss to the positive terminal of the error amplifier EA. The error amplifier EA compares the increased voltage vrss with the feedback voltage vfb output by the feedback circuit, and generates a comp1 signal according to the comparison result to control the conduction and shutdown of the power tube during the soft start process, thereby realizing a stable soft start process with a period of T. Reference Figure 3 , when the step voltage vs of the current source circuit 500 rises to the same level as the reference voltage vref, the enable signal controls the switch selection circuit 400 to disconnect the path between the current source circuit 500 and the resistor selection circuit 300, and at the same time controls the switch selection circuit 400 to disconnect the path between the current source circuit 500 and the positive terminal of the error amplifier EA, and conducts the path between the reference voltage vref and the positive terminal of the error amplifier EA, so as to cut off the output of the step voltage vs, and output the reference voltage vref to the positive terminal of the error amplifier EA. The error amplifier EA compares the reference voltage vref with the feedback voltage vfb output by the feedback circuit, and generates a comp2 signal according to the comparison result. At this time, the PWM comparator is controlled to work normally through the loop regulation of the switching power supply itself, and the soft start circuit no longer participates in the switching power supply loop, which reduces the chip power consumption, prolongs the service life of the switching power supply, improves the integration, accuracy and stability of the soft start circuit, and ensures the smooth voltage switching of the switching power supply.
[0038] The utility model provides a soft start circuit and a switching power supply, the switching power supply includes an error amplifier, and the soft start circuit includes a current source circuit 500, a resistor selection circuit 300, a clock circuit 100, a frequency multiplication control circuit 200 and a switch selection circuit 400. Among them, the enable end of the clock circuit 100 is used to access the enable signal; the input end of the frequency multiplication control circuit 200 is connected to the output end of the clock circuit 100, and the output end of the frequency multiplication control circuit 200 is connected to the controlled end of the resistor selection circuit 300; the enable end of the switch selection circuit 400 is used to access the enable signal, the first input end of the switch selection circuit 400 is connected to the output end of the current source circuit 500, the second input end of the switch selection circuit 400 is used to access the reference voltage, the first output end of the switch selection circuit 400 is connected to the input end of the resistor selection circuit 300, and the second output end of the switch selection circuit 400 is connected to the input end of the error amplifier. In practical applications, the enable end of the clock circuit 100 is connected to the enable signal, and the clock signal is output according to the enable signal; the frequency multiplication control circuit 200 multiplies the period of the clock signal, and outputs the clock frequency multiplication signal to the resistor selection circuit 300, so that the resistor selection circuit 300 conducts the path between multiple resistors connected in series and the switch selection circuit 400; the switch selection circuit 400 conducts the path between the current source circuit 500 and the resistor selection circuit 300 and the path between the current source circuit 500 and the error amplifier according to the enable signal, so as to output the voltage of the current source circuit 500 to the resistor selection circuit 300 as a rising voltage to the error amplifier, or disconnects the path between the current source circuit 500 and the resistor selection circuit 300 and the path between the current source circuit 500 and the error amplifier according to the enable signal, and conducts the path between the reference voltage and the error amplifier, so as to output the reference voltage to the error amplifier. The utility model uses a rising voltage instead of a reference voltage to connect to the positive end of the error amplifier, so that the output voltage rises gradually, thereby avoiding circuit damage caused by surge current during power-on. Compared with the traditional soft start circuit, the soft start circuit of the utility model has higher accuracy and stability.
[0039] In one embodiment, referring to Figure 4 , the clock circuit 100 includes: a first switch circuit 10, a second switch circuit 20, a charge and discharge circuit 60, a drive circuit 40, a control circuit 30 and an output circuit 50;
[0040] The input end of the first switch circuit 10 is used to connect to the power supply end, the output end of the first switch circuit 10 is respectively connected to the input end of the second switch circuit 20, the input end of the control circuit 30, and the input end of the drive circuit 40, and the connection point between the first switch circuit 10 and the second switch circuit 20 is connected to the input end of the output circuit 50; the controlled end of the control circuit 30 is connected to the output end of the output circuit 50, the output end of the control circuit 30 is connected to the input end of the second switch circuit 20, and the control end of the control circuit 30 is respectively connected to the controlled end of the drive circuit 40 and the controlled end of the charge and discharge circuit 60; the output end of the drive circuit 40 is connected to the input end of the second switch circuit 20; the output end of the second switch circuit 20 is used to connect to the ground end;
[0041] The control circuit 30 is used to turn on / off the path between the first switch circuit 10 and the charge / discharge circuit 60 according to the level signal of the output circuit 50, so as to control the charge / discharge of the charge / discharge circuit 60;
[0042] The driving circuit 40 is used to drive the first switch circuit 10 to output a corresponding level signal to the output circuit 50 according to the voltage of the charging and discharging circuit 60 .
[0043] It is understandable that, referring to Figure 4 In this embodiment, the driving circuit includes a first switch tube Q1, a fourth switch tube Q4, and a clamp tube M6. The charge and discharge state is determined by the sum of the voltage threshold of the first switch tube Q1 and the voltage threshold of M6 (the first preset voltage), and the voltage threshold of the fourth switch tube Q4 (the second preset voltage), thereby generating oscillation; the first switch circuit includes a plurality of PMOS tubes, and the second switch circuit includes a plurality of NMOS tubes. The first switch circuit is also used to access an enable signal, and the enable signal includes a high level signal / a low level signal, which is used to control the clock circuit 100 to be in a working state / a non-working state.
[0044] When the enable signal connected to the clock circuit 100 jumps to a high-level signal, the input end of the output circuit 50 first maintains a high-level signal, that is, the input end of the second inverter D2 in the output circuit 50 is connected to a high-level signal, and a low-level signal is output to the control circuit 30 after inversion processing. The control circuit 30 receives the low-level signal and turns on the path between the first switch circuit 10 and the charge-discharge circuit 60 to output the current mirrored by the eighth PMOS tube P8 to the charge-discharge circuit 60 through the second switch tube Q2, so that the charge-discharge circuit 60 is in a charging state. When the charging voltage of the charge-discharge circuit 60 reaches the second preset voltage first, the fourth switch tube Q4 is turned on first, the first switch tube Q1 is turned off, and the output circuit 50 maintains the previous state; the charging continues until the charging voltage of the charge-discharge circuit 60 reaches the first preset voltage, and the first switch tube Q1 in the drive circuit 40 is turned on, so that the first switch circuit 10 outputs a low-level signal to the second switch circuit 20 and the output circuit 50. At this time, the input end of the output circuit 50 receives a low-level signal, and the low-level signal still outputs a low-level signal after being inverted by the second inverter D2 and the third inverter D3. It can be understood that the clock signal output by the output circuit 50 flips from logic 1 to logic 0. Since the input end of the second inverter D2 in the output circuit 50 is connected to the low-level signal, a high-level signal is output to the control circuit 30 after inversion processing. The control circuit 30 receives the high-level signal, that is, disconnects the path between the first switch circuit 10 and the charge-discharge circuit 60, and conducts the path between the second switch circuit 20 and the charge-discharge circuit 60, so that the charge stored in the capacitor in the charge-discharge circuit 60 is discharged to the ground through the third NMOS tube M3 in the second switch circuit 20, so that the charge-discharge circuit 60 is in a discharge state. When the discharge voltage on the charge and discharge circuit 60 drops below the first preset voltage (VgsQ1+VgsM6), the first switch tube Q1 is disconnected first, the fourth switch tube Q4 remains in the open state, and the output circuit 50 maintains the previous state; the discharge continues until the discharge voltage of the charge and discharge circuit 60 reaches the second preset voltage, and the fourth switch tube Q4 in the drive circuit 40 is disconnected, so that the first switch circuit 10 outputs a high-level signal to the second switch circuit 20 and the output circuit 50. At this time, the input end of the output circuit 50 changes back to a high-level signal due to the low-level signal, and the high-level signal still outputs a high-level signal after being inverted by the second inverter D2 and the third inverter D3. It can be understood that the clock signal output by the output circuit 50 flips from logic 0 to logic 1.
[0045] With such an arrangement, the clock signal output by the clock circuit 100 is flipped from a high potential to a low potential, or from a low potential to a high potential, thereby achieving oscillation.
[0046] In one embodiment, referring to Figure 4The first switch circuit 10 includes: a first PMOS tube P1, a second PMOS tube P2, a third PMOS tube P3, a fourth PMOS tube P4, a fifth PMOS tube P5, a sixth PMOS tube P6, a seventh PMOS tube P7 and an eighth PMOS tube P8; the input end of the first PMOS tube P1 is used to connect to the power supply end, the controlled end of the first PMOS tube P1 is used to access the enable signal, and the output end of the first PMOS tube P1 is connected to the input end of the control circuit; the input end of the second PMOS tube P2 is used to connect to the power supply end, the controlled end of the second PMOS tube P2 is used to access the enable signal, and the output end of the second PMOS tube P2 is connected to the input end of the control circuit; the input end of the third PMOS tube P3 is used to connect to the power supply end, the controlled end of the third PMOS tube P3 is used to access the enable signal, and the output end of the third PMOS tube P3 is connected to the input end of the driving circuit; the input end of the fourth PMOS tube P4 is used to connect to the power supply end, the controlled end of the fourth PMOS tube P4 is connected to the input end of the control circuit The output end of the fourth PMOS tube P4 is connected to the input end of the driving circuit; the input end of the fifth PMOS tube P5 is used to connect to the power supply end, the controlled end of the fifth PMOS tube P5 is connected to the input end of the control circuit, and the output end of the fifth PMOS tube P5 is connected to the input end of the second switch circuit; the input end of the sixth PMOS tube P6 is used to connect to the power supply end, the controlled end of the sixth PMOS tube P6 is connected to the output end of the fourth PMOS tube P4, and the output end of the sixth PMOS tube P6 is connected to the input end of the second switch circuit; the input end of the seventh PMOS tube P7 is used to connect to the power supply end, the controlled end of the seventh PMOS tube P7 is connected to the output end of the sixth PMOS tube P6, and the output end of the seventh PMOS tube P7 is connected to the input end of the second switch circuit; the input end of the eighth PMOS tube P8 is used to connect to the power supply end, the controlled end of the eighth PMOS tube is connected to the input end of the control circuit, and the output end of the eighth PMOS tube P8 is connected to the input end of the control circuit.
[0047] The second switch circuit 20 includes: a first inverter, a first NMOS tube M1, a second NMOS tube M2, a third NMOS tube M3, a fourth NMOS tube M4 and a fifth NMOS tube M5; the controlled end of the first NMOS tube M1 is connected to the output end of the first inverter D1, the input end of the first NMOS tube M1 is connected to the output end of the control circuit, and the output end of the first NMOS tube M1 is used to connect to the ground end; the controlled end of the second NMOS tube M2 is connected to the output end of the first inverter D1, the input end of the second NMOS tube M2 is connected to the control end of the control circuit, and the output end of the second NMOS tube M2 is used to connect to the ground end; the controlled end of the third NMOS tube M3 is connected to the output end of the first NMOS tube M1 The input ends of the third NMOS tube M3 are connected, and the interconnection point is used to connect the power supply terminal VDD. The input end of the third NMOS tube M3 is connected to the output end of the control circuit 30, and the output end of the third NMOS tube M3 is connected to the controlled end of the second NMOS M2 tube; the controlled end of the fourth NMOS tube M4 is connected to the output end of the fifth PMOS tube P5, the input end of the fourth NMOS tube M4 is connected to the output end of the sixth PMOS tube P6, and the output end of the fourth NMOS tube M4 is used to connect to the ground end; the controlled end of the fifth NMOS tube M5 is respectively connected to the output end of the sixth PMOS tube P6 and the controlled end of the seventh PMOS tube P7, and the input end of the fifth NMOS tube M5 is respectively connected to the output end of the seventh PMOS tube P7.
[0048] Reference Figure 4 The driving circuit 40 includes a first switch tube Q1, a fourth switch tube Q4, and a clamp tube M6, and the control circuit 30 includes a second switch tube Q2 and a third switch tube Q3; the input end of the first switch tube Q1 is connected to the output end of the first switch circuit 10, the output end of the first switch tube Q1 is connected to the input end of the clamp tube M6, the output end of the clamp tube M6 is connected to the output end of the fourth switch tube Q4, and the mutual connection point is used to connect the ground end; the controlled end of the second switch tube Q2 is connected to the controlled end of the third switch tube Q3, and the mutual connection point is connected to the The output end of the second switch tube Q2 is connected to the input end of the third switch tube Q3, and their interconnection points are respectively connected to the input end of the charge and discharge circuit 60, the controlled end of the first switch tube Q1, and the controlled end of the fourth switch tube Q4, and the input end of the fourth switch tube Q4 is connected to the output end of the first switch circuit 10; the output end of the charge and discharge circuit 60 is used to connect to the ground end; the input end of the second switch tube Q2 is connected to the output end of the first switch circuit 10; the output end of the third switch tube Q3 is used to connect to the ground end.
[0049] It can be understood that, in this embodiment, referring to Figure 4 , the clock circuit 100 also includes a first inverter D1, a second inverter D2 and a third inverter D3. Specifically, after the power supply VDD and the current ib are ready, when the enable signal en is a low-level signal, the second PMOS tube P2 is turned on, the third PMOS tube P3 is turned on, the second NMOS tube M2 is turned on, and the first switch tube Q1 is turned off. Since the first switch tube Q1 is turned off, the fourth NMOS tube M4 is turned on, the sixth PMOS tube P6 is turned off, the seventh PMOS tube P7 is turned on, and the fifth NMOS tube M5 is turned off. At this time, the clock signal output by the clock circuit 100 is a high-level signal, and the clock circuit 100 is in an abnormal working state. When the enable signal en is a high-level signal, the first PMOS tube P1 is turned off, the second PMOS tube P2 is turned off, and the third PMOS tube P3 is turned off. The enable signal en outputs a low level signal to the first NMOS transistor M1 after passing through the first inverter D1 , and the first NMOS transistor M1 is turned off, and the second NMOS transistor M2 is turned off. At this time, the clock circuit 100 enters a normal working state.
[0050] When the clock circuit 100 just enters the normal working state, the clock signal output by the clock circuit 100 is a high-level signal, the third switch tube Q3 is turned off, and the second switch tube Q2 is turned on, and the first capacitor in the charge-discharge circuit starts to be charged. When charging starts, the fourth PMOS tube P4 is turned on, so that the sixth PMOS tube P6 is turned off. The fourth switch tube Q4 is turned on before the first switch tube Q1, and the input of the first inverter D1 maintains a high potential. The clock signal output by the clock circuit 100 maintains a high-level state. Until the charging voltage of the first capacitor in the charge-discharge circuit increases to a peak value (a first preset voltage), the first switch tube Q1 is turned on, thereby turning on the sixth PMOS tube P6, turning on the fifth NMOS tube M5, and turning off the seventh PMOS tube P7, so that the potential of the input end of the second inverter D2 is flipped from a high potential to a low potential, and the clock signal is flipped from a high potential to a low potential. At this time, the potential of the input end of the third inverter D3 flips from a low potential to a high potential, so that the second switch tube Q2 is turned off, the third switch tube Q3 is turned on, and the first capacitor in the charge-discharge circuit begins to discharge. The first switch tube Q1 is turned off first, the sixth PMOS tube P6 is turned off immediately, the fourth switch tube Q4 remains turned on, and the fourth NMOS tube M4 is turned off, so that the clock signal is maintained at a low potential state. Until the discharge voltage of the first capacitor in the charge-discharge circuit drops to the second preset voltage, the fourth switch tube Q4 is turned off, thereby turning on the fourth NMOS tube M4, and the sixth PMOS tube P6 remains turned off, thereby turning on the seventh PMOS tube P7 and turning off the fifth NMOS tube M5, so that the clock signal flips from a low potential to a high potential. At this time, the potential of the input end of the third inverter D3 flips from a high potential to a low potential, turning on the second switch tube Q2 and turning off the third switch tube Q3. The first capacitor in the charge and discharge circuit enters the charging state again, and continues a new round of charge and discharge cycle. The corresponding charge and discharge current value and capacitance value are selected to form a fixed 1us clock signal.
[0051] It should be understood that only one of the sixth PMOS tube P6 and the fourth NMOS tube M4 is turned on at the moment of clock flipping, and both remain in the off state at other times, which greatly saves current waste and reduces circuit power consumption. On the other hand, the oscillation waveform on the first capacitor can have an oscillation range between the VGS end of the fourth switch tube and the sum of the VGS of the first switch tube Q1 and the VGS of the clamp tube M6. The first switch tube Q1 and the fourth switch tube Q4 are equal in size, and the VG ends of the two are connected to the same potential, so that the clock flip is realized by using an oscillating voltage signal with a small amplitude, which not only achieves the purpose of fast and agile, but also saves the area of the first capacitor, improves the circuit integration, and saves production costs.
[0052] In one embodiment, referring to Figure 5The frequency multiplication control circuit 200 includes: a trigger module, the trigger module includes a plurality of triggers, and the plurality of triggers are sequentially connected in series to the output end of the clock circuit 100.
[0053] It can be understood that, in this embodiment, each trigger includes an SN terminal, a D terminal, a CK terminal, a Q terminal and a QN terminal. Among them, the SN terminal is used to access the enable signal. When the enable signal en_cnt is a low-level signal, the QN terminal outputs a low-level signal, and the Q terminal outputs a high-level signal opposite thereto; when the enable signal en_cnt is a high-level signal and a rising edge arrives at the CK terminal, the Q terminal outputs a signal of the same level as the D terminal, and maintains it until the next rising edge of the CK terminal arrives.
[0054] It should be understood that the SN terminals of all triggers are connected to the same enable signal en_cnt, the CK terminal of the first trigger df1 is connected to the clock signal, the D terminal of the trigger df1 is connected to the QN terminal of the trigger df1, the output signal of the Q terminal of the trigger df1 is connected to a buffer buf1 to generate a T1 signal with a period of 2*T0, the T1 signal is used as the input signal of the CK terminal of the second trigger df2, and the T1 signal is also output to the resistor selection circuit 300. Further, the D terminal of the trigger df2 is connected to the QN terminal of the trigger df2, the output signal of the Q terminal of the trigger df2 is connected to a buffer buf2 to generate a T2 signal with a period of 2*T1, the T2 signal is used as the input signal of the CK terminal of the third trigger df3, and the T2 signal is also output to the resistor selection circuit 300.
[0055] Similarly, the Q output signal of the trigger dfN-1 is connected to the CK terminal of the trigger dfN as the input signal of the Nth trigger. The D terminal of the trigger dfN is connected to the QN terminal of the trigger dfN. The Q terminal of the trigger dfN is connected to a buffer bufN to generate a cycle of 2. n-1 *T0 TN signal, and the TN signal is also output to the resistor selection circuit 300; the Q-end output signal of the trigger dfN is connected to the CK end of the trigger dfN+1 as the input signal of the N+1th trigger, the D end of the trigger dfN+1 is connected to the QN end of the trigger dfN+1, and the Q end of the trigger dfN+1 is connected to a buffer bufN+1 to generate a cycle of 2 n *T0 TN+1 signal. The frequency multiplication control circuit 200 in this embodiment further includes a NOT gate nad1, a NOT gate nad2 and a fourth inverter D4. The TN+1 signal and the enable signal en_cn are used as input terminals of a latch composed of two NAND gates nad1 and nad2. The output terminal of the latch is connected to the fourth inverter D4 to generate an end signal end as a signal of the end of the soft start and output to the resistor selection circuit 300.
[0056] For example, the frequency multiplication control circuit 200 is composed of 7 (N=6) cascaded triggers (df1~dfN+1) as an example for explanation. Specifically, when the enable signal en_cnt is a low-level signal, the frequency multiplication control circuit 200 cannot work normally, and the TN signal (N=1, 2...6) at the Q end of each trigger outputs a high-level signal. When the soft start circuit needs to be started, the enable signal en_cnt is a high-level signal. After the clock signal and power signal of the clock circuit 100 are ready, each trigger dfN doubles the period of the clock signal TN-1 connected to the CK end, so that its Q end outputs an extended period clock signal TN signal = 2*TN-1, and outputs each TN signal to the resistor selection circuit 300 until the trigger df6 doubles the period T0 signal of the clock signal. 6 *T0 is frequency-multiplied to obtain a clock frequency-multiplied signal of T6 signal = 1.024ms, and T6 signal is the soft-start cycle time. The last trigger dfN+1, that is, the output TN+1 signal of the trigger df7 = T7 signal = 2*T6 = 2.048ms, and the trigger df7 first flips from high potential to low potential at 1 / 2*T7 = T6 = 1.024ms, which is the soft-start cycle time. The TN+1 signal and the enable signal en_cnt are sent to the latch, and then connected to the fourth inverter D4. After counting to the completion of the soft-start cycle time of 1.024ms, that is, when the first falling edge of the T7 signal flips, the end signal end is output, and the end signal end jumps from low potential to high potential and is in a latched state, and the soft-start ends at this time. At the same time, the output end of the frequency-multiplied control circuit 200 is also connected to the input end of the switch selection circuit 400, and the end signal end is sent to the switch selection circuit 400 as an enable signal to control the switch selection circuit 400.
[0057] In another embodiment, by increasing the number of triggers, different soft start times can be flexibly controlled, thereby improving the flexibility of the switching power supply.
[0058] In one embodiment, referring to Figure 6 , the resistance selection circuit 300 comprises:
[0059] A resistor module, the resistor module includes a plurality of resistors, and the plurality of resistors are sequentially connected in series to the first output end of the switch selection circuit 400;
[0060] A switch tube module, wherein the switch tube module comprises a plurality of switch tubes, the number of the plurality of resistors is consistent with the number of the plurality of switch tubes, each of the switch tubes is connected in parallel with each of the resistors, and a controlled end of each of the switch tubes is used to access the clock multiplication signal;
[0061] The switch tube module is used to turn on / off the path between the switch selection circuit 400 and the resistance module according to the clock multiplication signal.
[0062] It can be understood that in this embodiment, the resistor module includes resistors RN (N=1...n), and the switch tube module includes switch tubes MsN (N=1...n). The resistors RN (N=1...n) are connected in series, and the resistors RN (N=1...n) and the switch tubes MsN (N=1...n) are connected in parallel. The TN (N=1...n) signal output by the frequency multiplication control circuit 200 is used as the switch selection signal of the switch tube MsN (N=1...n).
[0063] In practical applications, according to the parallel shunt principle, when the TN (N = 1 ... n) signal input is a low-level signal, the switch tube MsN (N = 1 ... n) is turned off, and the current flows through the resistor RN (N = 1 ... n) in sequence; when the TN (N = 1 ... n) signal input is a high-level signal, the current passes through the switch tube MsN (N = 1 ... n), which is equivalent to the resistor RN (N = 1 ... n) not being connected to the series circuit. It should be understood that each resistor RN (N = 1 ... n) is composed of a resistor with a positive temperature coefficient R + N (N = 1 ... n) and a resistor with a negative temperature coefficient RN (N = 1 ... n) in series, wherein the ratio of the positive temperature coefficient resistor R + 1 to the negative temperature coefficient resistor R - 1 of the resistor R1 is obtained according to the inverse proportion of the temperature coefficient of the positive temperature coefficient resistor R + 1 and the negative temperature coefficient resistor R - 1, so as to obtain a resistor with a temperature coefficient close to 0 in series to compensate for the temperature. The filter resistor Rc and the filter capacitor Cc form a low-pass filter to weaken the circuit jitter and enhance the circuit stability.
[0064] For example, the resistor module includes a resistor RN (N=6), and the switch tube module includes a switch tube MsN (N=6) as an example for explanation. Among them, during soft start, the end signal end output by the frequency multiplication control circuit 200 is sent to the switch selection circuit 400 as an enable signal for controlling the switch selection circuit 400. The end signal end at a low potential controls the fifth switch tube s0 to be turned on, the sixth switch tube s2 to be turned on, and the fourth switch tube s1 to be turned off, and controls the current source switch si in the current source circuit 500 to be turned on according to the voltage formula vs=vref=i*R to configure a suitable injection current, and selects the corresponding switch tube MsN (N=1, 2...6) to be turned on according to the TN (N=1, 2...6) signal output by the frequency multiplication control circuit 200, that is, the clock frequency multiplication signal output by the frequency multiplication control circuit 200 is used as the soft start cycle time to select the corresponding switch tube MsN (N=1, 2...6) to be turned on to control the corresponding resistance value.
[0065] It is important to understand that referring to Figure 6, the resistance values of resistors R1 to R6 are doubled in sequence, R1=r, R2=2*r, R3=4*r...R6=32*r. When the TN (N=1, 2...6) signal is high, the switch tube MsN (N=1, 2...6) is turned on, and the current does not flow through the resistor RN; when the frequency multiplication control circuit 200 starts timing work, and the TN (N=1, 2...6) signal jumps to a low potential, the switch tube MsN (N=1, 2...6) is turned off, and the resistor RN is connected to the current path. For example, when the T1 signal jumps to a low potential, the resistor R1 is connected to the current path, and when the resistor T2 signal jumps to a low potential, the resistor R1 is connected in series with the resistor R2 to the current path, and so on, until the resistor T6 signal jumps to a low potential, and the resistors R1 to R6 are connected in series to the current path in sequence.
[0066] Since the current is fixed, the resistors R1 to R6 rise in steps with the resistance value r, so that the voltage vs is output to the error amplifier in the form of a rising voltage vrss, and finally the voltage vs rises to a voltage consistent with the reference voltage vref in 1.024ms. Among them, each rising step is maintained for 16us. In this embodiment, according to the formula vs = vref = i*R, it can be seen that the absolute value of the current i and the resistor R can be flexibly changed, and the current has a switch selection function, and different current gears can be set. By regulating the high gear of the current, the circuit is adapted to reference voltages of different values, thereby improving the scope of application of the circuit; by regulating the low gear of the current, the circuit is adjusted to adjust the error, thereby improving the accuracy of the circuit.
[0067] In one embodiment, referring to Figure 7 , the switch selection circuit 400 includes: a fourth switch tube s1, a fifth switch tube s0 and a sixth switch tube s2;
[0068] The input end of the fourth switch tube s1 is used to access the reference voltage, and the output end of the fourth switch tube s1 is connected to the input end of the error amplifier;
[0069] The input end of the fifth switch tube s0 is connected to the output end of the current source circuit 500, the output end of the fifth switch tube s0 is respectively connected to the input end of the sixth switch tube s2 and the input end of the resistance selection circuit 300, and the output end of the sixth switch tube s2 is connected to the input end of the error amplifier.
[0070] It can be understood that, during the soft start process, the end signal end output by the frequency multiplication control circuit 200 is used as an enable signal for the control switch selection circuit 400, so as to control the voltage vs to be output to the positive terminal of the error amplifier EA in the form of a rising voltage vrss. The error amplifier EA compares the rising voltage vrss with the feedback voltage vfb of the feedback circuit, and generates a comp1 signal to control the on and off of the power tube during the soft start process, thereby realizing a stable soft start process with a period of T. When the voltage vs rises to be consistent with the reference voltage vref, the potential of the end signal end jumps to a high potential, thereby controlling the fifth switch tube s0 and the sixth switch tube s2 to be disconnected, and the fourth switch tube s1 to be turned on, cutting off the output of the voltage vs, and connecting the reference voltage vref to the positive terminal of the error amplifier EA. The error amplifier EA compares the reference voltage vref with the feedback voltage vfb of the feedback circuit, and generates a comp2 signal. After completion, the soft start module is turned off to save current.
[0071] In one embodiment, referring to Figure 7 , the current source circuit 500 comprises:
[0072] A current source module, wherein the current source module comprises a plurality of current source switches, and the plurality of current source switches are sequentially connected in parallel to the first input terminal of the switch selection circuit 400 .
[0073] It can be understood that, in this embodiment, the current source module includes a current source switch siN (N=1...n). During the soft start process, in conjunction with the current source circuit 500 and the switch selection circuit 400, the end signal end output by the frequency multiplication control circuit 200 is used as an enable signal of the switch selection circuit 400 to control the switch selection circuit 400 to select the corresponding switch tube to turn on, and control the corresponding current source switch siN (N=1...n) to open according to the requirement of the voltage formula vs=vref=i*R to configure a suitable injection current.
[0074] The utility model also provides a switching power supply, which includes an error amplifier and the soft start circuit as described above.
[0075] It can be understood that, in this embodiment, referring to Figure 2 The switching power supply also includes a feedback circuit, an input voltage Vin, an output voltage Vout, a driver logic (drive circuit) and a PWM comparator. In practical applications, the soft start circuit uses a rising voltage instead of a reference voltage to access the positive terminal of the error amplifier, so that the output voltage gradually rises, avoiding circuit damage caused by surge current during the power-on process. Compared with the traditional soft start circuit, the soft start circuit of the utility model has higher accuracy and stability.
[0076] The above embodiments are only preferred embodiments of the present invention, and do not limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made by using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.
Claims
1. A soft start circuit, applied to a switching power supply, the switching power supply comprising an error amplifier, It is characterized in that The soft start circuit comprises: Current source circuit; Resistor selection circuit; A clock circuit, wherein an enable terminal of the clock circuit is used to receive an enable signal; the clock circuit is used to output a clock signal according to the enable signal; A frequency multiplication control circuit, wherein the input end of the frequency multiplication control circuit is connected to the output end of the clock circuit, and the output end of the frequency multiplication control circuit is connected to the controlled end of the resistance selection circuit; the frequency multiplication control circuit is used to perform frequency multiplication processing on the period of the clock signal and output the clock frequency multiplication signal to the resistance selection circuit; A switch selection circuit, wherein an enable terminal of the switch selection circuit is used to access an enable signal, a first input terminal of the switch selection circuit is connected to an output terminal of the current source circuit, a second input terminal of the switch selection circuit is used to access a reference voltage, a first output terminal of the switch selection circuit is connected to an input terminal of the resistance selection circuit, and a second output terminal of the switch selection circuit is connected to an input terminal of the error amplifier; The switch selection circuit is used to connect the path between the current source circuit and the resistor selection circuit according to the enable signal so as to output the voltage output from the current source circuit to the resistor selection circuit to the error amplifier, or to disconnect the path between the current source circuit and the resistor selection circuit according to the enable signal so as to output the reference voltage to the error amplifier.
2. The soft start circuit as claimed in claim 1, It is characterized in that The clock circuit includes: a first switch circuit, a second switch circuit, a charge and discharge circuit, a drive circuit, a control circuit and an output circuit; The input end of the first switch circuit is used to connect to the power supply end, the output end of the first switch circuit is respectively connected to the input end of the second switch circuit, the input end of the control circuit, and the input end of the drive circuit, and the connection point between the first switch circuit and the second switch circuit is connected to the input end of the output circuit; the controlled end of the control circuit is connected to the output end of the output circuit, the output end of the control circuit is connected to the input end of the second switch circuit, and the control end of the control circuit is respectively connected to the controlled end of the drive circuit and the controlled end of the charge and discharge circuit; the output end of the drive circuit is connected to the input end of the second switch circuit; the output end of the second switch circuit is used to connect to the ground end; The control circuit is used to turn on / off the path between the first switch circuit and the charge / discharge circuit according to the level signal of the output circuit, so as to control the charge / discharge of the charge / discharge circuit; The driving circuit is used to drive the first switch circuit to output a corresponding level signal to the output circuit according to the voltage of the charging and discharging circuit.
3. The soft start circuit as claimed in claim 2, It is characterized in that The first switch circuit includes: a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube and an eighth PMOS tube; The input end of the first PMOS tube is used to connect to the power supply end, the controlled end of the first PMOS tube is used to access the enable signal, and the output end of the first PMOS tube is connected to the input end of the control circuit; The input end of the second PMOS tube is used to connect to the power supply end, the controlled end of the second PMOS tube is used to access the enable signal, and the output end of the second PMOS tube is connected to the input end of the control circuit; The input end of the third PMOS tube is used to connect to the power supply end, the controlled end of the third PMOS tube is used to access the enable signal, and the output end of the third PMOS tube is connected to the input end of the driving circuit; The input end of the fourth PMOS tube is used to connect to the power supply end, the controlled end of the fourth PMOS tube is connected to the input end of the control circuit, and the output end of the fourth PMOS tube is connected to the input end of the driving circuit; The input end of the fifth PMOS tube is used to connect to the power supply end, the controlled end of the fifth PMOS tube is connected to the input end of the control circuit, and the output end of the fifth PMOS tube is connected to the input end of the second switch circuit; The input end of the sixth PMOS tube is used to connect to the power supply end, the controlled end of the sixth PMOS tube is connected to the output end of the fourth PMOS tube, and the output end of the sixth PMOS tube is connected to the input end of the second switch circuit; The input end of the seventh PMOS tube is used to connect to the power supply end, the controlled end of the seventh PMOS tube is connected to the output end of the sixth PMOS tube, and the output end of the seventh PMOS tube is connected to the input end of the second switch circuit; The input end of the eighth PMOS tube is used to connect to the power supply end, the controlled end of the eighth PMOS tube is connected to the input end of the control circuit, and the output end of the eighth PMOS tube is connected to the input end of the control circuit.
4. The soft start circuit as claimed in claim 3, It is characterized in that The second switch circuit includes: a first inverter, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor and a fifth NMOS transistor; The controlled end of the first NMOS tube is connected to the output end of the first inverter, the input end of the first NMOS tube is connected to the output end of the control circuit, and the output end of the first NMOS tube is used to connect to the ground end; The controlled end of the second NMOS tube is connected to the output end of the first inverter, the input end of the second NMOS tube is connected to the control end of the control circuit, and the output end of the second NMOS tube is used to connect to the ground end; The controlled end of the third NMOS tube is connected to the input end of the first NMOS tube, and the mutual connection point is used to connect the power supply end, the input end of the third NMOS tube is connected to the output end of the control circuit, and the output end of the third NMOS tube is connected to the controlled end of the second NMOS tube; The controlled end of the fourth NMOS tube is connected to the output end of the fifth PMOS tube, the input end of the fourth NMOS tube is connected to the output end of the sixth PMOS tube, and the output end of the fourth NMOS tube is used to connect to the ground end; The controlled end of the fifth NMOS tube is respectively connected to the output end of the sixth PMOS tube and the controlled end of the seventh PMOS tube, and the input end of the fifth NMOS tube is respectively connected to the output end of the seventh PMOS tube.
5. The soft start circuit as claimed in claim 2, It is characterized in that The driving circuit includes a first switch tube, a fourth switch tube, and a clamp tube, and the control circuit includes a second switch tube and a third switch tube; The input end of the first switch tube is connected to the output end of the first switch circuit, the output end of the first switch tube is connected to the input end of the clamp tube, the output end of the clamp tube is connected to the output end of the fourth switch tube, and their mutual connection point is used to connect to the ground end; the controlled end of the second switch tube is connected to the controlled end of the third switch tube, and their mutual connection point is connected to the input end of the output circuit; the output end of the second switch tube is connected to the input end of the third switch tube, and their mutual connection point is respectively connected to the input end of the charge and discharge circuit, the controlled end of the first switch tube, and the controlled end of the fourth switch tube, and the input end of the fourth switch tube is connected to the output end of the first switch circuit; the output end of the charge and discharge circuit is used to connect to the ground end; the input end of the second switch tube is connected to the output end of the first switch circuit; the output end of the third switch tube is used to connect to the ground end.
6. The soft start circuit as claimed in claim 1, It is characterized in that The frequency multiplication control circuit comprises: A trigger module, wherein the trigger module comprises a plurality of triggers, and the plurality of triggers are sequentially connected in series to the output end of the clock circuit.
7. The soft start circuit as claimed in claim 1, It is characterized in that The resistance selection circuit comprises: A resistor module, the resistor module comprising a plurality of resistors, wherein the plurality of resistors are sequentially connected in series to the first output end of the switch selection circuit; A switch tube module, wherein the switch tube module comprises a plurality of switch tubes, the number of the plurality of resistors is consistent with the number of the plurality of switch tubes, each of the switch tubes is connected in parallel with each of the resistors, and a controlled end of each of the switch tubes is used to access the clock multiplication signal; The switch tube module is used to turn on / off the path between the switch selection circuit and the resistance module according to the clock multiplication signal.
8. The soft start circuit as claimed in claim 1, It is characterized in that The switch selection circuit includes: a fourth switch tube, a fifth switch tube and a sixth switch tube; The input end of the fourth switch tube is used to access the reference voltage, and the output end of the fourth switch tube is connected to the input end of the error amplifier; The input end of the fifth switch tube is connected to the output end of the current source circuit, the output end of the fifth switch tube is respectively connected to the input end of the sixth switch tube and the input end of the resistance selection circuit, and the output end of the sixth switch tube is connected to the input end of the error amplifier.
9. The soft start circuit as claimed in claim 1, It is characterized in that The current source circuit comprises: A current source module, wherein the current source module comprises a plurality of current source switches, and the plurality of current source switches are sequentially connected in parallel to the first input end of the switch selection circuit.
10. A switching power supply, It is characterized in that The invention comprises an error amplifier and a soft start circuit as claimed in any one of claims 1 to 9.