Multilayer ceramic capacitor

Abstract

The utility model provides a laminated ceramic capacitor which has high reliability while realizing miniaturization and large capacitance. The laminated ceramic capacitor is provided with a laminated body (2); and external electrodes (3) respectively disposed on both end surfaces on both sides in the longitudinal direction of the laminated body, the laminated body being provided with: an inner layer section (11) in which dielectric layers (14) and internal electrode layers (15) are alternately laminated; an outer layer section (12) that forms two main surfaces (A) on both sides in the stacking direction (Z) of the inner layer section; and a side edge section (13) that forms two side surfaces (B) on both sides in the width direction (Y) of the inner layer section, and satisfies the following relational expressions (1) and (2), where W1 is the thickness of the side edge section in the width direction, and T1 is the thickness of the dielectric layer in the stacking direction. 60 [mu] m < = W1 < = 80 [mu] m (1) 1.5 < = T1 / W1 * 100 < = 2.5 (2).

Description

Technical Field

[0001] The utility model relates to a stacked ceramic capacitor. Background Art

[0002] In the past, stacked ceramic capacitors widely used in electronic devices such as portable phones and portable music players include: an inner layer portion, in which multiple dielectric layers and multiple internal electrode layers made of ceramic materials are stacked to form an electrostatic capacitor; an outer layer portion, which is arranged on both sides of the stacking direction of the inner layer portion; and a side edge portion, which is arranged on both sides of the width direction of the inner layer portion.

[0003] Moreover, with the miniaturization and high performance of electronic devices in recent years, multilayer ceramic capacitors are also required to be miniaturized and have a larger capacitance. In order to achieve miniaturization and large capacitance in multilayer ceramic capacitors, it is possible to consider reducing the thickness of the side edge portion and increasing the area of ​​the internal electrode layer. However, if the thickness of the side edge portion is reduced, the resistance (i.e., moisture resistance) of the internal electrode layer to moisture that penetrates from the side of the stack and the external electrode and reaches the end surface of the stack is reduced, and as a result, it is considered that the reliability is reduced.

[0004] Furthermore, when manufacturing a laminated ceramic capacitor by stacking a plurality of ceramic green sheets on which a pattern of an internal electrode layer is printed, if the internal electrode layer is printed thinner in order to achieve miniaturization and high capacitance of the laminated ceramic capacitor, the following situation may occur: structural defects may occur in the internal electrode layer, and the capacitor may not fully function.

[0005] Therefore, there is a demand for the development of a multilayer ceramic capacitor that is compact and has a large capacitance while having high reliability.

[0006] Prior Art Literature

[0007] Patent Literature

[0008] Patent Document 1: Japanese Patent Application Publication No. 2014-150240 Utility Model Content

[0009] Problems to be solved by utility models

[0010] An object of the present invention is to provide a multilayer ceramic capacitor that is compact and has a large capacitance while having high reliability.

[0011] Technical solutions to solve problems

[0012] The inventors of the utility model discovered the following fact and finally completed the utility model, namely, in a stacked ceramic capacitor having an inner layer portion in which dielectric layers and internal electrode layers are alternately stacked, an outer layer portion arranged on both sides in the stacking direction of the inner layer portion, and a side edge portion arranged on both sides in the width direction of the inner layer portion, if the thickness W1 of the side edge portion in the width direction is made greater than 60 μm and less than 80 μm, and the thickness W1 of the side edge portion in the width direction and the thickness T1 of the dielectric layer in the stacking direction are formed to satisfy a given relationship, a stacked ceramic capacitor having high reliability while increasing electrostatic capacitance can be provided.

[0013] That is, the utility model is a laminated ceramic capacitor including a laminate and external electrodes.

[0014] The laminated body comprises:

[0015] An inner layer portion having dielectric layers and internal electrode layers alternately stacked;

[0016] An outer layer portion having two main surfaces on both sides of the inner layer portion in the stacking direction and formed opposite to each other in the stacking direction; and

[0017] The side edge portion is formed on both sides of the inner layer portion in the width direction intersecting the stacking direction to form two side surfaces opposite to each other in the width direction.

[0018] The external electrodes are respectively arranged on two opposite end surfaces formed on both sides of the stacked body in a length direction intersecting the stacking direction and the width direction.

[0019] When the thickness of the side edge portion in the width direction is W1 and the thickness of the dielectric layer in the stacking direction is T1, the following relational expressions (1) and (2) are satisfied.

[0020] 60μm≤W1≤80μm…(1)

[0021] 1.5≤T1 / W1×100≤2.5…(2)

[0022] Utility Model Effect

[0023] According to the present invention, it is possible to provide a multilayer ceramic capacitor that is compact and has a large capacitance while having high reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 1 is a diagram showing the appearance of the multilayer ceramic capacitor 1 .

[0025] Figure 2 It is along Figure 1FIG. 1 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line II-II.

[0026] Figure 3 It is along Figure 1 FIG. 1 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line III-III.

[0027] Figure 4 It is along Figure 2 FIG. 1 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line IV-IV.

[0028] Figure 5(a) to Figure 5(d) The diagrams are for explaining the manufacturing process of the multilayer ceramic capacitor 1 .

[0029] Description of Reference Numerals

[0030] A: Main side;

[0031] B: side view;

[0032] C: end face;

[0033] 1: Multilayer ceramic capacitor;

[0034] 2: laminate;

[0035] 3: External electrode;

[0036] 11: inner layer;

[0037] 12: outer layer;

[0038] 13: lateral edge;

[0039] 14: dielectric layer;

[0040] 15: internal electrode layer;

[0041] 30: base electrode layer;

[0042] 31: Plating layer. DETAILED DESCRIPTION

[0043] Hereinafter, a multilayer ceramic capacitor 1 is described as an embodiment of the present invention, but the present invention is not limited thereto. In addition, in order to explain the contents of the utility model, the drawings are sometimes simplified and drawn schematically, and sometimes the ratio of the dimensions of the drawn components or components is inconsistent with the ratio of these dimensions described in the specification. In addition, there are cases where the components described in the specification are omitted in the drawings or the number of components is omitted and drawn.

[0044] Figure 1 It is a schematic perspective view of the multilayer ceramic capacitor 1 . Figure 2 is a multilayer ceramic capacitor 1 along Figure 1Cross-sectional view along line II-II. Figure 3 is a multilayer ceramic capacitor 1 along Figure 1 Cross-sectional view along line III-III. Figure 4 is a multilayer ceramic capacitor 1 along Figure 2 In addition, sometimes Figure 2 The cross section shown is called the XZ cross section. Figure 3 The section shown is called the YZ section. Figure 4 The cross section shown is called an XY cross section.

[0045] The multilayer ceramic capacitor 1 is substantially in the shape of a rectangular parallelepiped and includes a multilayer body 2 and a pair of external electrodes 3 provided at both ends of the multilayer body 2. The multilayer body 2 includes an inner layer portion 11 in which a plurality of dielectric layers 14 and internal electrode layers 15 are stacked.

[0046] In the following description, as terms indicating the orientation of the multilayer ceramic capacitor 1, in the multilayer ceramic capacitor 1, the direction in which the pair of external electrodes 3 are provided is referred to as the length direction X. The direction in which the dielectric layer 14 and the internal electrode layer 15 are stacked is referred to as the stacking direction Z. The direction intersecting both the length direction X and the stacking direction Z is referred to as the width direction Y. In the embodiment, the width direction Y is orthogonal to both the length direction X and the stacking direction Z.

[0047] (Outer surface of laminate 2)

[0048] In addition, among the six outer surfaces of the stacked body 2, a pair of outer surfaces opposite to each other in the stacking direction Z are referred to as the first main surface A1 and the second main surface A2, a pair of outer surfaces opposite to each other in the width direction Y are referred to as the first side surface B1 and the second side surface B2, and a pair of outer surfaces opposite to each other in the length direction X are referred to as the first end surface C1 and the second end surface C2. In addition, when it is not necessary to distinguish the first main surface A1 and the second main surface A2 in particular, they are collectively referred to as the main surface A in the description, when it is not necessary to distinguish the first side surface B1 and the second side surface B2 in the description, they are collectively referred to as the side surface B in the description, and when it is not necessary to distinguish the first end surface C1 and the second end surface C2 in particular, they are collectively referred to as the end surface C in the description.

[0049] The laminate 2 preferably has rounded edges R1 including corners. The edge R1 is a portion where two surfaces of the laminate 2 (i.e., the main surface A and the side surface B, the main surface A and the end surface C, or the side surface B and the end surface C) intersect.

[0050] (Laminate 2)

[0051] The laminate 2 includes an inner layer portion 11 forming an electrostatic capacitor, outer layer portions 12 arranged on both sides of the inner layer portion 11 in a lamination direction Z, and side edge portions 13 arranged on both sides of the inner layer portion 11 in a width direction Y.

[0052] (Inner layer portion 11)

[0053] The inner layer portion 11 includes a plurality of dielectric layers 14 and internal electrode layers 15 alternately stacked along the stacking direction Z.

[0054] (Dielectric layer 14)

[0055] The dielectric layer 14 is made of a ceramic material. As the ceramic material, for example, a dielectric ceramic containing BaTiO 3 as a main component can be used.

[0056] (Internal Electrode Layer 15)

[0057] The internal electrode layer 15 includes a plurality of first internal electrode layers 15a and a plurality of second internal electrode layers 15b. The first internal electrode layers 15a and the second internal electrode layers 15b are arranged alternately. The first internal electrode layer 15a includes a first opposing portion 152a opposed to the second internal electrode layer 15b and a first lead portion 151a led from the first opposing portion 152a to the first end surface C1. The end of the first lead portion 151a is exposed at the first end surface C1 and is electrically connected to the first external electrode 3a described later. The second internal electrode layer 15b includes a second opposing portion 152b opposed to the first internal electrode layer 15a and a second lead portion 151b led from the second opposing portion 152b to the second end surface C2. The end of the second lead portion 151b is electrically connected to the second external electrode 3b described later. Electric charges are accumulated in the first opposing portion 152a of the first internal electrode layer 15a and the second opposing portion 152b of the second internal electrode layer 15b.

[0058] The internal electrode layer 15 is preferably formed of a metal material represented by, for example, nickel (Ni), copper (Cu), silver (Ag), palladium (Pd), a silver-palladium (Ag-Pd) alloy, gold (Au), or the like.

[0059] (Outer layer 12)

[0060] The outer layer portion 12 includes a first outer layer portion 12a and a second outer layer portion 12b arranged to sandwich the inner layer portion 11 from the stacking direction Z. The first outer layer portion 12a forms the first main surface A1 of the multilayer ceramic capacitor 1 , and the second outer layer portion 12b forms the second main surface A2 of the multilayer ceramic capacitor 1 .

[0061] The outer layer portion 12 can be formed of the same material as the dielectric layer 14 of the inner layer portion 11 .

[0062] (Side edge portion 13)

[0063] The side edge portion 13 includes a first side edge portion 13a and a second side edge portion 13b which are arranged to sandwich the inner layer portion 11 from the width direction Y. The first side edge portion 13a forms a first side surface B1 of the multilayer ceramic capacitor 1, and the second side edge portion 13b forms a second side surface B2 of the multilayer ceramic capacitor 1. The side edge portion 13 can be formed of the same material as the dielectric layer 14.

[0064] (External electrode 3)

[0065] The external electrode 3 includes a first external electrode 3a provided on the first end surface C1 and a second external electrode 3b provided on the second end surface C2. The external electrode 3 covers not only the end surface C but also a part of the main surface A and the side surface B which are continuous with the end surface C.

[0066] As described above, the end of the first lead portion 151a of the first internal electrode layer 15a is exposed at the first end surface C1 and is electrically connected to the first external electrode 3a. In addition, the end of the second lead portion 151b of the second internal electrode layer 15b is exposed at the second end surface C2 and is electrically connected to the second external electrode 3b. Thus, a structure in which a plurality of capacitor elements are electrically connected in parallel is formed between the first external electrode 3a and the second external electrode 3b.

[0067] In addition, the external electrode 3 includes, for example, a base electrode layer 30 and a plating layer 31. In addition, the external electrode 3 does not necessarily have to have such a layered structure.

[0068] The base electrode layer 30 is formed by, for example, applying and baking a conductive paste containing copper (Cu). Alternatively, the base electrode layer 30 may contain glass.

[0069] The plating layer 31 includes a nickel (Ni) plating layer 31a disposed on the surface of the base electrode layer 30 and a tin (Sn) plating layer 31b disposed on the surface of the nickel (Ni) plating layer 31a. The structure of the plating layer 31 is not limited thereto.

[0070] When the thickness of the side edge portion 13 in the width direction Y is W1 and the thickness of the dielectric layer 14 in the stacking direction Z is T1, the multilayer ceramic capacitor 1 satisfies the following relational expressions (1) and (2).

[0071] 60μm≤W1≤80μm…(1)

[0072] 1.5≤T1 / W1×100≤2.5…(2)

[0073] Thus, the number of stacked internal electrode layers 15 can be increased while maintaining high reliability, and thus the electrostatic capacitance can be increased.

[0074] Furthermore, when the length of the internal electrode layer 15 in the width direction Y is represented by We, the multilayer ceramic capacitor 1 preferably satisfies the following relational expression (3).

[0075] 7.0≤W1 / We×100≤9.0…(3)

[0076] By making the thickness W1 of the side edge portion 13 in the width direction Y and the length We of the internal electrode layer 15 in the width direction Y satisfy the relational expression (3), the inner layer portion 11 forming the electrostatic capacitor can be enlarged while maintaining moisture resistance, thereby achieving high reliability.

[0077] Furthermore, when the length of the internal electrode layer 15 in the longitudinal direction X is denoted as Le, it is preferable that the following relational expression (4) is satisfied.

[0078] 0.45≤We / Le≤0.65…(4)

[0079] By making the length We of the internal electrode layer 15 in the width direction Y and the length Le of the internal electrode layer 15 in the longitudinal direction X satisfy the relational expression (4), the surface area of ​​the internal electrode layer 15 required for increasing the electrostatic capacitance can be obtained.

[0080] (Method for Manufacturing Multilayer Ceramic Capacitor 1)

[0081] use Figure 5(a) to Figure 5(d) A method for manufacturing the multilayer ceramic capacitor 1 will be described.

[0082] A ceramic slurry containing ceramic powder, a binder and a solvent is formed into a sheet on the surface of a carrier film by a die coater, a gravure coater, a micro gravure coater or the like, thereby producing a laminated ceramic green sheet 101 to be the dielectric layer 14. Next, a conductor paste is printed in a strip shape on the laminated ceramic green sheet 101 by screen printing, inkjet printing, gravure printing or the like, and a conductive pattern 102 to be the internal electrode layer 15 is printed on the surface of the laminated ceramic green sheet 101, thereby producing a raw material sheet 103.

[0083] Next, as shown in FIG5(a), a plurality of green sheets 103 are stacked so that the conductive patterns 102 face the same direction and the conductive patterns 102 are staggered by half a pitch in the length direction between adjacent green sheets 103. Furthermore, ceramic green sheets 112 for the outer layer portion, which will become the outer layer portion 12, are stacked on both sides of the stacked green sheets 103.

[0084] The stacked plurality of raw material sheets 103 and the outer layer ceramic green sheets 112 are bonded by thermal compression to produce a mother block 110 as shown in FIG. 5( b ).

[0085] Next, the mother block 110 is cut along the cutting line x shown in FIG. 5( b ) and the cutting line y intersecting the cutting line x, thereby manufacturing a plurality of laminated bodies 2 shown in FIG. 5( c ).

[0086] According to the above process, the outer layer portion 12 and the side edge portion 13 can be formed at the same time as the laminate 2 is formed. However, the inner layer portion 11 with the ends of the internal electrode layer 15 in the width direction Y exposed on both sides can be first formed by cutting from the mother block member, and then the side edge portions 13 are adhered to both sides of the inner layer portion 11 so as to cover the exposed ends of the internal electrode layer 15, thereby forming the laminate 2. In this case, the adhered side edge portions 13 can use the same dielectric ceramic material as the dielectric layer 14. In addition, the side edge portions 13 can also be formed by applying ceramic paste on both sides of the inner layer portion 11.

[0087] Next, a conductive paste containing copper (Cu) is applied and sintered on the end faces C of the stack 2, thereby forming a base electrode layer 30. The base electrode layer 30 is formed to not only cover the end faces C on both sides of the stack 2, but also to extend to the main surface A and the side surface B of the stack 2 and cover a portion of the end face C side of the main surface A.

[0088] Next, a nickel (Ni) plating layer 31 a is formed on the surface of the base electrode layer 30 , and a tin (Sn) plating layer 31 b is formed on the nickel (Ni) plating layer 31 a , thereby manufacturing the multilayer ceramic capacitor 1 shown in FIG. 5( d ) .

[0089] As mentioned above, although embodiment of this invention was described, this invention is not limited to embodiment, It can implement in various forms within the range which does not deviate from the summary of this invention.

Claims

1. A laminated ceramic capacitor, characterized in that: comprising a laminate and external electrodes, The laminated body comprises: An inner layer portion having dielectric layers and internal electrode layers alternately stacked; An outer layer portion having two main surfaces on both sides of the inner layer portion in the stacking direction and formed opposite to each other in the stacking direction; and The side edge portion is formed on both sides of the inner layer portion in the width direction intersecting the stacking direction to form two side surfaces opposite to each other in the width direction. The external electrodes are respectively arranged on two opposite end surfaces formed on both sides of the stacked body in a length direction intersecting the stacking direction and the width direction. When the thickness of the side edge portion in the width direction is W1 and the thickness of the dielectric layer in the stacking direction is T1, the following relations (1) and (2) are satisfied: 60μm≤W1≤80μm …(1) 1.5≤T1 / W1×100≤2.5 …(2).

2. The multilayer ceramic capacitor according to claim 1, wherein: When the length of the internal electrode layer in the width direction is We, the following relational expression (3) is satisfied: 7.0≤W1 / We×100≤9.0…(3).

3. The multilayer ceramic capacitor according to claim 2, wherein: When the length of the internal electrode layer in the longitudinal direction is Le, the following relational expression (4) is satisfied: 0.45≤We / Le≤0.65…(4).

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