Protection circuit and three-phase PFC circuit dual-DSP system
By designing a protection circuit, using the driving circuit and the latch circuit to handle the fault signal, ensuring that the input level of the IGBT driving unit is pulled down, solving the problem of high-impedance state instability in the dual DSP system of three-phase PFC circuit, and improving the reliability of the system.
Patent Information
- Application Number
- CN202420156365.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-01-22
- Publication Date
- 2024-12-17
- Estimated Expiration
- 2034-01-22
AI Technical Summary
In the three-phase PFC circuit, there is a delay in the communication and transmission of the dual DSP chip, and there is a time difference during the fault transmission, resulting in the high-impedance state of the buffer, affecting the IGBT driving unit, which may lead to a direct-through tube blowout, causing risks to the system. .
A protection circuit is designed to pull down the input driving signal level of the IGBT driving unit to a low level through the driving circuit, and use the latch circuit and filter circuit to process the fault signal to ensure that the input of the IGBT driving unit remains at low power during the failure. Flat state to avoid unstable output in high-impedance state.
It effectively avoids the risk of IGBT driving unit passing through the pipe, improves the reliability of the three-phase PFC circuit dual DSP system, and ensures the stable operation of the system in the event of a fault.
Smart Images
Figure CN222192140U_ABST
Abstract
Description
Technical Field
[0001] The present application belongs to the field of power electronics technology and relates to a protection circuit, and in particular to a protection circuit and a three-phase PFC circuit dual DSP system. Background Art
[0002] With the development and maturity of power electronics technology, the HVAC (Heating Ventilation and Air Conditioning) market continues to expand, and the application of variable frequency drives is becoming more and more extensive. With the increase of harmonic pollution of load equipment to the power grid and the increase in the proportion of three-phase high-power devices in the power grid, the requirements for performance indicators are gradually increasing. APFC (Active Power Factor Correction) three-phase high power factor active correction technology has become a hot issue in the field of power electronics and research at home and abroad. At the same time, with the gradual replacement of R32 (difluoromethane) refrigerant and the promotion of high back electromotive force compressors, the requirements for the output voltage of the driver are further improved. However, the traditional three-phase topology driver has limited performance in driving new high-reverse compressors because it does not have a Boost boost function, and cannot exert the full performance of the compressor.
[0003] In the context of the performance requirements of high output voltage of the inverter, the three-phase APFC boost circuit has also been developing. The mainstream topology circuits mainly include the traditional three-phase two-level PFC circuit and the three-phase three-level Vienna circuit. The former has a small input current THD (Total Harmonic Distortion) and high power factor and efficiency, while the latter has small tube stress and no dead zone direct-through problem.
[0004] In the three-phase two-level bridgeless PFC circuit, considering the DSP control resources and PCB layout issues of the boost and inverter output parts, a dual DSP chip control solution is adopted in some technical solutions. One DSP controls the boost and related sampling protection of the three-phase input part, and the other DSP controls the inverter output drive compressor and related sampling protection. The two are connected through uart (Universal Asynchronous Receiver / Transmitter) communication data to achieve complete control. At the same time, considering the reliability design of the circuit, the control method adopts dual protection of software overcurrent and overvoltage and hardware overcurrent buffer.
[0005] Due to the delay in the communication transmission of the dual DSP chips in the three-phase PFC circuit dual DSP system, there is a time difference in the process from fault transmission to the final shutdown processing. When the input boost part of the three-phase PFC circuit dual DSP system is shut down due to overcurrent, the buffer output of the input boost part will switch to a high-impedance state through software overcurrent and overvoltage and hardware overcurrent buffer latch protection, but the output inverter part is still operating normally. At this time, the high-impedance state of the buffer is a greater risk source. The high-impedance state of the buffer in the three-phase PFC circuit dual DSP system is more sensitive to noise sources. When the inverter part does not shut down, the DV / DT noise brought by the power device switch of the inverter output part will affect the buffer chip. The high-voltage noise will be coupled to the buffer chip through the parasitic capacitance between the board layers, resulting in an unstable high-impedance output state. The abnormal high level will cause the upper and lower bridge arms IGBT (Insulated Gate Bipolar Transistor) to directly explode, causing a greater risk to the three-phase PFC circuit dual DSP system. Utility Model Content
[0006] The purpose of the present application is to provide a protection circuit for controlling the input drive signal of an IGBT drive unit and providing circuit protection for a three-phase PFC circuit dual DSP system.
[0007] In a first aspect, the present application provides a protection circuit, which includes a driving circuit; a first end of the driving circuit is connected to an output end of a first buffer control unit and an input end of an IGBT driving unit, and is used to pull down the level of an input driving signal of the IGBT driving unit to keep it in a low level state.
[0008] In an implementation of the first aspect, the protection circuit also includes a latch circuit; the output end of the latch circuit is connected to the second end of the drive circuit and the enable end of the first buffer control unit; the latch circuit outputs a high level and latches after receiving a fault signal; the drive circuit receives the high level and pulls down the level of the input drive signal of the IGBT drive unit.
[0009] In an implementation of the first aspect, the driving circuit includes a driving transistor and a pull-up resistor; the base of the driving transistor is connected to the output end of the latch circuit; the emitter of the driving transistor is grounded; the first end of the pull-up resistor is connected to the collector of the driving transistor; and the second end of the pull-up resistor is connected to the input end of the IGBT driving unit.
[0010] In an implementation of the first aspect, the driving circuit also includes a first current limiting resistor and a bias resistor; the base of the driving transistor is connected to the output end of the latch circuit through the first current limiting resistor; the first end of the bias resistor is connected to the base of the driving transistor; the second end of the bias resistor is connected to the emitter of the driving transistor and is grounded.
[0011] In an implementation of the first aspect, the latch circuit includes a trigger and a conversion circuit; the conversion circuit is used to convert the fault signal into a low level; the preset signal input terminal of the trigger is used to input the low level; and the output terminal of the trigger is used to output the high level when the preset signal is the low level.
[0012] In an implementation of the first aspect, the latch circuit further includes a filter circuit; the filter circuit is used to filter the reset enable signal and input the filtered signal to the clock signal terminal of the trigger.
[0013] In an implementation of the first aspect, the filtering circuit includes a second current limiting resistor and a filtering capacitor; the first end of the second current limiting resistor is used to input the reset enable signal; the second end of the second current limiting resistor is connected to the first end of the filtering capacitor and the clock signal end of the trigger; and the second end of the filtering capacitor is grounded.
[0014] In an implementation of the first aspect, the latch circuit also includes a power supply decoupling capacitor; the first end of the power supply decoupling capacitor is connected to the reset end of the trigger, the power supply end of the trigger and the power supply; the second end of the power supply decoupling capacitor is connected to the ground end of the trigger and is grounded.
[0015] In an implementation manner of the first aspect, the fault signal includes a bus overvoltage signal, an input overcurrent signal, and an input over- or undervoltage signal.
[0016] In the second aspect, the present application provides a three-phase PFC circuit dual DSP system, which includes: a DSP input unit, a DSP inverter unit, the protection circuit described in any one of the above, a first fault detection unit, a second fault detection unit, a first buffer control unit, a second buffer control unit, an IGBT drive unit, a DC bus rectifier unit, a PIM inverter control unit and a compressor drive unit.
[0017] As described above, the protection circuit and three-phase PFC circuit dual DSP system described in this application have the following beneficial effects:
[0018] In the present application, the protection circuit pulls down the level of the input drive signal of the IGBT drive unit in the three-phase PFC circuit dual DSP system to a low level state through the drive circuit, thereby realizing effective control of the input drive signal of the IGBT drive unit. When a fault signal appears in the three-phase PFC circuit dual DSP system, the protection circuit can prevent the IGBT drive unit from directly blowing up due to the unstable high-impedance output of the first buffer control unit, thereby providing circuit protection for the three-phase PFC circuit dual DSP system. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] Figure 1 Shown is a schematic diagram of the structure of the protection circuit described in an embodiment of the present application.
[0020] Figure 2 Shown is a circuit diagram of a driving circuit described in an embodiment of the present application.
[0021] Figure 3 Shown is a schematic diagram of the structure of the latch circuit described in an embodiment of the present application.
[0022] Figure 4 Shown is a circuit diagram of the trigger and filter circuit described in the embodiment of the present application.
[0023] Figure 5 Shown is a circuit diagram of the protection circuit described in an embodiment of the present application.
[0024] Figure 6 Shown is a structural schematic diagram of the three-phase PFC circuit dual DSP system described in an embodiment of the present application.
[0025] Component number description
[0026] 4 Three-phase PFC circuit dual DSP system
[0027] 401 DSP input unit
[0028] 402 DSP inverter unit
[0029] 403 First fault detection unit
[0030] 404 Second fault detection unit
[0031] 405 First buffer control unit
[0032] 406 Second buffer control unit
[0033] 407 Protection Circuit
[0034] 408 IGBT driver unit
[0035] 409 DC bus rectifier unit
[0036] 410 PIM inverter control unit
[0037] 411 Compressor drive unit
[0038] 1 Protection circuit
[0039] 11. Driving Circuit
[0040] a1 Driver circuit first terminal
[0041] a2 The second terminal of the driving circuit
[0042] 111 driving transistor
[0043] R1 pull-up resistor
[0044] R2 First current limiting resistor
[0045] R3 Bias resistor
[0046] 12 Latch Circuit
[0047] 121 Conversion circuit
[0048] 122 Trigger
[0049] 123 Filter Circuit
[0050] R4 Second current limiting resistor
[0051] C1 filter capacitor
[0052] C2 Power supply decoupling capacitor
[0053] 2 First buffer control unit
[0054] 3 IGBT driver unit
[0055] Input IGBT drive unit input
[0056] Output1 The first buffer control unit output
[0057] Output2 Latch circuit output
[0058] Enable the first buffer control unit enable terminal DETAILED DESCRIPTION
[0059] The following describes the embodiments of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.
[0060] It should be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application, and thus the drawings only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed at will, and the component layout may also be more complicated.
[0061] With the development and maturity of power electronics technology, the HVAC (Heating Ventilation and Air Conditioning) market continues to expand, and the application of variable frequency drives is becoming more and more extensive. With the increase of harmonic pollution of load equipment to the power grid and the increase in the proportion of three-phase high-power devices in the power grid, the requirements for performance indicators are gradually increasing. APFC (Active Power Factor Correction) three-phase high power factor active correction technology has become a hot issue in the field of power electronics and research at home and abroad. At the same time, with the gradual replacement of R32 (difluoromethane) refrigerant and the promotion of high back electromotive force compressors, the requirements for the output voltage of the driver are further improved. However, the traditional three-phase topology driver has limited performance in driving new high-reverse compressors because it does not have a Boost boost function, and cannot exert the full performance of the compressor.
[0062] In the context of the performance requirements of high output voltage of the inverter, the three-phase APFC boost circuit has also been developing. The mainstream topology circuits mainly include the traditional three-phase two-level PFC circuit and the three-phase three-level Vienna circuit. The former has a small input current THD (Total Harmonic Distortion) and high power factor and efficiency, while the latter has small tube stress and no dead zone direct-through problem.
[0063] In the three-phase two-level bridgeless PFC circuit, considering the DSP control resources and PCB layout issues of the boost and inverter output parts, a dual DSP chip control solution is adopted in some technical solutions. One DSP controls the boost and related sampling protection of the three-phase input part, and the other DSP controls the inverter output drive compressor and related sampling protection. The two are connected through uart (Universal Asynchronous Receiver / Transmitter) communication data to achieve complete control. At the same time, considering the reliability design of the circuit, the control method adopts dual protection of software overcurrent and overvoltage and hardware overcurrent buffer.
[0064] Due to the delay in the communication transmission of the dual DSP chips in the three-phase PFC circuit dual DSP system, there is a time difference in the process from fault transmission to the final shutdown processing. When the input boost part of the three-phase PFC circuit dual DSP system is shut down due to overcurrent, the buffer output of the input boost part will switch to a high-impedance state through software overcurrent and overvoltage and hardware overcurrent buffer latch protection, but the output inverter part is still operating normally. At this time, the high-impedance state of the buffer is a greater risk source. The high-impedance state of the buffer in the three-phase PFC circuit dual DSP system is more sensitive to noise sources. When the inverter part does not shut down, the DV / DT noise brought by the power device switch of the inverter output part will affect the buffer chip. The high-voltage noise will be coupled to the buffer chip through the parasitic capacitance between the board layers, resulting in an unstable high-impedance output state. The abnormal high level will cause the upper and lower bridge arms IGBT (Insulated Gate Bipolar Transistor) to directly explode, causing a greater risk to the three-phase PFC circuit dual DSP system.
[0065] At least to address the above-mentioned problems, the following embodiments of the present application provide a protection circuit for controlling the input drive signal of the IGBT drive unit to provide circuit protection for the three-phase PFC circuit dual DSP system.
[0066] The principle and implementation of a protection circuit of this embodiment will be described in detail below in conjunction with the accompanying drawings so that those skilled in the art can understand the protection circuit of this embodiment without creative work.
[0067] Figure 1 The diagram shows a schematic diagram of the structure of a protection circuit in one embodiment of the present application. Figure 1 As shown, the protection circuit 1 includes a driving circuit 11. The first terminal a1 of the driving circuit 11 is connected to the output terminal Output1 of the first buffer control unit 2 and the input terminal Input of the IGBT driving unit 3, and is used to pull down the level of the input driving signal of the IGBT driving unit 3 to keep it in a low level state.
[0068] In an embodiment of the present application, the first buffer control unit 2 includes a buffer chip. The IGBT driving unit 3 includes a driving IC (integrated circuit) for driving a subsequent IGBT circuit.
[0069] Exemplarily, the buffer chip is 74HCT541D, and the driver IC is 1ED3122MU12H.
[0070] Please continue reading Figure 1 In one embodiment of the present application, the protection circuit 1 may further include a latch circuit 12. The output terminal Output2 of the latch circuit 12 is connected to the second terminal a2 of the drive circuit 11 and the enable terminal Enable of the first buffer control unit 2. After receiving the fault signal, the latch circuit 12 outputs a high level and latches it. The drive circuit 11 receives the high level and pulls down the level of the input drive signal of the IGBT drive unit 3.
[0071] The enable terminal Enable of the first buffer control unit 2 is effective at a low level. The output state of the output terminal Output1 of the first buffer control unit 2 includes a high level, a low level and a high impedance state. When the enable terminal Enable of the first buffer control unit 2 is a low level, the output state is a high impedance state. The input and output states of the buffer in the first buffer control unit 2 can be referred to in the following Table 1:
[0072] Table 1. Buffer truth table
[0073]
[0074] Among them, H represents high level, L represents low level, Z represents high impedance, X represents no effect, OE1 and OE2 represent the enable terminals of the buffer, An represents the input terminal of the buffer, and Yn represents the output terminal of the buffer.
[0075] In one embodiment of the present application, the fault signal includes a bus overvoltage signal, an input overcurrent signal, and an input over- or undervoltage signal.
[0076] In one embodiment of the present application, after receiving the fault signal, the latch circuit 12 latches the output in a high level state, the enable terminal Enable of the first buffer control unit 2 is invalid, and the output of the first buffer control unit 2 remains in a high impedance state. At this time, the level of the input drive signal of the IGBT drive unit 3 is high, and the drive circuit 11 can pull the level of the input drive signal of the IGBT drive unit 3 down to a low level state.
[0077] Figure 2 The circuit diagram of the driving circuit in one embodiment of the present application is shown. Figure 2 As shown, the driving circuit 11 includes a driving transistor 111 and a pull-up resistor R1. The base of the driving transistor 111 is connected to the output end of the latch circuit 12. The emitter of the driving transistor 111 is grounded. The first end of the pull-up resistor R1 is connected to the collector of the driving transistor 111. The second end of the pull-up resistor R1 is connected to the input end of the IGBT driving unit 3.
[0078] Please continue reading Figure 2 , the driving circuit 11 may further include a first current limiting resistor R2 and a bias resistor R3. The base of the driving transistor 111 is connected to the output end of the latch circuit 12 through the first current limiting resistor R2. The first end of the bias resistor R3 is connected to the base of the driving transistor 111. The second end of the bias resistor R3 is connected to the emitter of the driving transistor 111 and is grounded.
[0079] The first current limiting resistor R2 is connected to the output end of the latch circuit 12 and can limit the current flowing into the driving transistor 111 , thereby preventing the driving transistor 111 from being burned due to excessive base current.
[0080] The two ends of the bias resistor R3 are connected to the base and emitter of the driving transistor 111, providing a bias voltage and a bias current for the base of the driving transistor 111, which can amplify the low-frequency signal and avoid signal distortion.
[0081] Figure 3 The structure diagram of the latch circuit in one embodiment of the present application is shown. Figure 3 As shown, the latch circuit 12 includes a conversion circuit 121, a trigger 122, and a filter circuit 123. The conversion circuit 121 is used to convert the fault signal into a low level. The trigger 122 receives the low level sent by the conversion circuit 121. The filter circuit 123 sends the filtered signal to the trigger 122.
[0082] In an embodiment of the present application, the conversion circuit 121 can be constructed based on an upper and lower threshold comparator loop.
[0083] Figure 4 The circuit diagram of the trigger and filter circuit in one embodiment of the present application is shown. Figure 6 As shown, Figure 4 As shown, the preset signal input terminal PRE of the trigger 122 is used to input the low level. The in-phase output terminal of the trigger 122 is used to output the high level when the preset signal is the low level. The clock signal terminal CLK of the trigger 122 is connected to the filter circuit for receiving the clock signal. The D pin of the trigger 122 is connected to the ground terminal of the DSP input unit. The anti-phase output pin of the trigger 122 is suspended. The power supply terminal, reset terminal CLR and ground terminal of the trigger 122 are connected to the power supply circuit 124. The reset terminal of the trigger 122 is set to a high level.
[0084] In one embodiment of the present application, the preset signal input terminal 7 of the trigger 122 is a high level input when there is no abnormality.
[0085] In one embodiment of the present application, when the clock signal terminal EN_DRIVE of the flip-flop 122 does not provide a rising edge reset signal, the output of the in-phase output terminal of the flip-flop 122 will always be latched in a high level state.
[0086] In one embodiment of the present application, when a rising edge reset clock signal is input to the clock signal terminal of the trigger 122, the in-phase output terminal of the trigger 122 outputs a low level, so that the enable terminal Enable of the first buffer control unit 2 is effective and can normally output a high level and a low level. At this time, the driving transistor 111 is not turned on, the collector of the driving transistor 111 remains in an open circuit state, and the first buffer control unit 2 outputs a PWM control signal.
[0087] The filter circuit 123 includes a second current limiting resistor R4 and a filter capacitor C1. The first end of the second current limiting resistor R4 is used to input the reset enable signal. The second end of the second current limiting resistor R4 is connected to the first end of the filter capacitor C1 and the clock signal end of the trigger 122. The second end of the filter capacitor C1 is grounded.
[0088] The preset signal input terminal PRE of the trigger 122 is connected to the conversion circuit 121. The conversion circuit 121 generates a low level after receiving the fault signal, and inputs the low level to the preset signal input terminal PRE. The filter circuit 123 is used to filter the reset enable signal EN_DRIVE, and input the filtered signal to the clock signal terminal CLK of the trigger 122. The first end of the power supply decoupling capacitor C2 is connected to the reset terminal CLR of the trigger 122, the power supply terminal of the trigger 122 and the power supply. The second end of the power supply decoupling capacitor C2 is connected to the ground terminal of the trigger 122 and is grounded.
[0089] In one embodiment of the present application, the power supply is 3.3V.
[0090] Figure 5 Shown is a circuit diagram of a protection circuit in one embodiment of the present application. Figure 5 As shown, the output end of the trigger 122 in the latch circuit 12 is connected to the base of the driving transistor 111 and the enable end of the first buffer control unit 2. When the output end of the trigger 122 outputs a high level, the enable end is invalid, the output of the first buffer control unit 2 is in a high impedance state, the base and emitter of the driving transistor 111 are turned on, and the collector of the driving transistor 111 is connected to the input end of the IGBT driving unit 3 through the pull-up resistor R1, so that the level of the input driving signal at the input end of the IGBT driving unit 3 is pulled down. The noise energy of the coupling interference of the first buffer control unit 2 is discharged to the signal ground through the pull-up resistor R1, so that the gate-level driving signal level of the driving IC in the IGBT driving unit 3 is maintained at the saturation conduction voltage of the driving transistor 111, that is, the input of the driving IC is maintained at a low level state, avoiding the mis-conduction of the driving IC, and realizing effective latching of the driving IC.
[0091] Exemplarily, the saturation conduction voltage of the driving transistor 111 is 0.25V.
[0092] Exemplarily, the high level threshold voltage of the 1ED3122MU12H is 2.5V, and the low level threshold voltage is 1.1V.
[0093] In one embodiment of the present application, when the inverter does not shut down due to a single fault and the input current still exists, the first buffer control unit 2 introduces a continuous voltage noise of more than 3V after outputting a high-impedance state, which is much higher than the on-voltage of the driver IC. If there is no control of the driver circuit, the upper and lower bridges of the subsequent IGBT circuit will be misconnected and the tube will explode.
[0094] In one embodiment of the present application, after a fault occurs, the drive circuit 11 pulls down the level of the input drive signal of the IGBT drive unit 3 to below 0.5V, which is much lower than the turn-on voltage of the drive IC, thereby avoiding the problem of mis-conduction and protecting the power devices of the input part of the three-phase PFC circuit dual DSP system to a greater extent.
[0095] In summary, the embodiment of the present application provides a protection circuit. The protection circuit can pull down the level of the input drive signal of the IGBT drive unit to a low level state when a fault signal occurs, and effectively latch the drive IC, thereby avoiding the loss caused by the subsequent IGBT directly blowing up the tube and improving the reliability of the circuit.
[0096] Figure 6 The structure diagram of the three-phase PFC circuit dual DSP system in one embodiment of the present application is shown. Figure 6 As shown, the three-phase PFC circuit dual DSP system 4 includes: a DSP input unit 401, a DSP inverter unit 402, a protection circuit 407 described in any embodiment of the present application, a first fault detection unit 403, a second fault detection unit 404, a first buffer control unit 405, a second buffer control unit 406, an IGBT drive unit 408, a DC bus rectifier unit 409, a PIM inverter control unit 410 and a compressor drive unit 411.
[0097] The DSP input unit 401 is connected to the DSP inverter unit 402 for communication. The DSP input unit 401 is connected to the IGBT drive unit 408 through the first buffer control unit 405. The first fault detection unit 403 is connected to the protection circuit 407, and the protection circuit 407 is respectively connected to the first buffer control unit 405 and the IGBT drive unit 408. The IGBT drive unit 408 is connected to the PIM inverter control unit 410 through the DC bus rectifier unit 409. The second fault detection unit 404 is connected to the second buffer control unit 406. The DSP inverter unit 402 is connected to the PIM inverter control unit 410 through the second buffer control unit 406. The PIM inverter control unit 410 is connected to the compressor drive unit 411 for driving the compressor.
[0098] In one embodiment of the present application, in the three-phase PFC circuit dual DSP system 4, due to the problem of boost communication transparent transmission time between the DSP input unit 401 and the DSP inverter unit 402, when the output of the first buffer control unit 405 remains in a high impedance state, if the DSP inverter unit 402 is not shut down and is still running, the DV / DT effect brought by the PIM device of the high-speed switch in the PIM inverter control unit 410 will cause a large voltage spike signal interference to the input end of the IGBT drive unit 408 through the parasitic capacitance between the board layers. The protection circuit 407 can continuously pull down the voltage at the input end of the IGBT drive unit 408, and discharge the noise energy of the coupled interference to the signal ground, so that the input of the IGBT drive unit 408 is kept in a low level state, avoiding the direct conduction of the upper and lower bridge arms of the subsequent IGBT, until the DSP input unit 401 sends the fault signal to the DSP inverter unit 402 through the communication transparent transmission, and both sides are shut down for protection.
[0099] In summary, the embodiment of the present application provides a three-phase PFC circuit dual DSP system. The three-phase PFC circuit dual DSP system can realize abnormal protection of high-impedance state in DSP input and DSP inverter output driver IC, improve the abnormal timeliness problem of high-impedance state of the three-phase PFC circuit dual DSP system, and greatly improve the reliability of the entire system.
[0100] The descriptions of the processes or structures corresponding to the above-mentioned figures have different emphases. For parts that are not described in detail in a certain process or structure, please refer to the relevant descriptions of other processes or structures.
[0101] The above embodiments are merely illustrative of the principles and effects of the present application and are not intended to limit the present application. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed in the present application shall still be covered by the claims of the present application.
Claims
1. A protection circuit, characterized in that: The protection circuit includes a driving circuit; The first end of the driving circuit is connected to the output end of the first buffer control unit and the input end of the IGBT driving unit, and is used to pull down the level of the input driving signal of the IGBT driving unit to keep it in a low level state.
2. The protection circuit according to claim 1, characterized in that: The protection circuit also includes a latch circuit; The output end of the latch circuit is connected to the second end of the drive circuit and the enable end of the first buffer control unit; After receiving the fault signal, the latch circuit outputs a high level and latches; The driving circuit receives the high level and pulls down the level of the input driving signal of the IGBT driving unit.
3. The protection circuit according to claim 2, characterized in that: The driving circuit includes a driving transistor and a pull-up resistor; The base of the driving transistor is connected to the output end of the latch circuit; The emitter of the driving transistor is grounded; The first end of the pull-up resistor is connected to the collector of the driving transistor; The second end of the pull-up resistor is connected to the input end of the IGBT driving unit.
4. The protection circuit according to claim 3, characterized in that: The driving circuit also includes a first current limiting resistor and a bias resistor; The base of the driving transistor is connected to the output end of the latch circuit through the first current limiting resistor; The first end of the bias resistor is connected to the base of the driving transistor; The second end of the bias resistor is connected to the emitter of the driving transistor and is grounded.
5. The protection circuit according to claim 2, characterized in that: The latch circuit includes a trigger and a conversion circuit; The conversion circuit is used to convert the fault signal into a low level; The preset signal input terminal of the trigger is used to input the low level; The output end of the trigger is used to output the high level when the preset signal is the low level.
6. The protection circuit according to claim 5, characterized in that: The latch circuit also includes a filter circuit; The filtering circuit is used to filter the reset enable signal and input the filtered signal to the clock signal terminal of the trigger.
7. The protection circuit according to claim 6, characterized in that: The filtering circuit includes a second current limiting resistor and a filtering capacitor; The first end of the second current limiting resistor is used to input the reset enable signal; The second end of the second current limiting resistor is connected to the first end of the filter capacitor and the clock signal end of the trigger; The second end of the filter capacitor is grounded.
8. The protection circuit according to claim 5, characterized in that: The latch circuit also includes a power supply decoupling capacitor; The first end of the power supply decoupling capacitor is connected to the reset end of the trigger, the power end of the trigger and the power supply; The second end of the power supply decoupling capacitor is connected to the ground end of the trigger and is grounded.
9. The protection circuit according to claim 2, characterized in that: The fault signals include bus overvoltage signals, input overcurrent signals and input over-voltage or under-voltage signals.
10. A three-phase PFC circuit dual DSP system, characterized in that: The three-phase PFC circuit dual DSP system includes: a DSP input unit, a DSP inverter unit, a protection circuit according to any one of claims 1 to 9, a first fault detection unit, a second fault detection unit, a first buffer control unit, a second buffer control unit, an IGBT drive unit, a DC bus rectifier unit, a PIM inverter control unit and a compressor drive unit.